阅读说明：本技术 半导体封装结构和半导体封装结构的制备方法 (Semiconductor packaging structure and preparation method thereof ) 是由 何正鸿 徐玉鹏 钟磊 李利 于 2021-10-29 设计创作，主要内容包括：本发明提供了一种半导体封装结构和半导体封装结构的制备方法,涉及半导体封装技术领域,本发明在转接板的上侧直接设置堆叠焊盘,从而避免了直接在塑封体上激光开口漏出基板焊盘的操作,避免了基板被烧坏的情况,同时也提升了产品的自主分配性。同时在转接板的下侧设置凹槽,封装芯片局部容置在该凹槽内,从而使得转接板与封装基板之间的间距得以减小,进而降低了转接板的贴装高度,使得封装尺寸得以减小,有利于产品的微型化。同时,由于转接板与封装基板之间的间距得以减小,使得导电引脚的尺寸得以降低,可以选用更小的导电引脚进行焊接,从而使得相邻的导电引脚之间的间隙更大,从而避免了基板翘曲时导电引脚之间发生桥接或虚焊现象。(The invention provides a semiconductor packaging structure and a preparation method thereof, and relates to the technical field of semiconductor packaging. Meanwhile, the lower side of the adapter plate is provided with the groove, and the local packaging chip is accommodated in the groove, so that the distance between the adapter plate and the packaging substrate is reduced, the mounting height of the adapter plate is reduced, the packaging size is reduced, and the miniaturization of a product is facilitated. Meanwhile, the distance between the adapter plate and the packaging substrate is reduced, so that the size of the conductive pins is reduced, smaller conductive pins can be selected for welding, the gap between adjacent conductive pins is larger, and the bridging or false welding phenomenon between the conductive pins when the substrate is warped is avoided.)

1. A semiconductor package structure, comprising:

a package substrate;

a package chip disposed on the package substrate;

the conductive pins are arranged on the packaging substrate and surround the packaging chip;

the adapter plate is arranged on the conductive pins and covers the packaged chip;

the upper side of the adapter plate is provided with a stacking pad, the lower side of the adapter plate is provided with a conductive pad, the conductive pad is connected with the conductive pins and is electrically connected with the packaging substrate through the conductive pins, a groove corresponding to the packaging chip is further formed in the lower side of the adapter plate, and the packaging chip is locally accommodated in the groove.

2. The semiconductor package structure according to claim 1, wherein an adhesive layer is further disposed on an upper side of the package chip, the adhesive layer is attached to the groove, and the package chip is connected to the interposer through the adhesive layer.

3. The semiconductor package structure of claim 1, further comprising a first molding compound layer disposed on the package substrate and encapsulating the conductive pins and the package chip, wherein the first molding compound layer is bonded to the underside of the interposer.

4. The semiconductor package structure according to claim 1, wherein the groove penetrates through to an upper side of the interposer, a first molding compound is disposed on an upper side of the package chip, and at least a portion of a surface of the first molding compound is exposed to the interposer.

5. The semiconductor package structure according to claim 4, wherein a heat dissipation plate is further attached to an upper side of the interposer, and the heat dissipation plate covers the groove and is attached to the surface of the first plastic package body.

6. The semiconductor package structure according to claim 5, wherein a package module is further stacked on the interposer, and the package module is connected to the conductive pads and attached to an upper surface of the heat dissipation plate.

7. The semiconductor package structure according to claim 6, wherein the package module comprises a stacked substrate, a first stacked chip, a second plastic package, and a second plastic package layer, the first stacked chip is attached to the stacked substrate, the second stacked chip is stacked on the lower side of the stacked substrate, the stacked substrate is connected to the stacked pad, the second plastic package layer is disposed on the upper side of the stacked substrate and covers the first stacked chip, the second plastic package is disposed on the lower side of the stacked substrate and covers the second stacked chip, and the second plastic package is attached to the upper surface of the heat dissipation plate.

8. The semiconductor package structure according to claim 4, wherein an electrically conductive heat dissipation wire is disposed on an upper side of the interposer, and two ends of the electrically conductive heat dissipation wire are respectively connected to the stacked pads located on two sides of the groove.

9. The semiconductor package structure according to claim 8, wherein a heat dissipation adhesive layer is disposed on the upper side of the interposer, the heat dissipation adhesive layer covers the conductive heat dissipation line and covers the groove, and the heat dissipation adhesive layer is attached to the surface of the first plastic package body.

10. A method for manufacturing a semiconductor packaging structure is characterized by comprising the following steps:

mounting a packaging chip on a packaging substrate;

arranging conductive pins surrounding the packaging chip on the packaging substrate;

mounting an adapter plate covering the packaging chip on the conductive pins;

the upper side of the adapter plate is provided with a stacking pad, the lower side of the adapter plate is provided with a conductive pad, the conductive pad is connected with the conductive pins and is electrically connected with the packaging substrate through the conductive pins, a groove corresponding to the packaging chip is further formed in the lower side of the adapter plate, and the packaging chip is locally accommodated in the groove.

Technical Field

The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure and a preparation method of the semiconductor packaging structure.

Background

With the rapid development of the semiconductor industry, electronic products are increasingly high-density and miniaturized, and communication products need to meet high-bandwidth performance, so that the electronic products are widely applied to the semiconductor industry through a POP (package on package) stacking structure, a memory chip and a processor chip are packaged together to meet the high-bandwidth performance, and the miniaturization is realized. Due to the requirement of the customer to customize the product, the upper layer structure needs to be stacked again in the POP stack structure to realize the size of the freely distributed memory chip, so that the detachability needs to be satisfied. Traditional POP stacked structure adopts laser trompil to spill the substrate surface pad behind the plastic-sealed body trompil usually, leads to the substrate pad to burn out easily, and then leads to the welding of upper stack dress structure to become invalid, can't realize the independently distributability of product simultaneously.

In addition, in the POP package in the prior art, different materials are used between different packages and the laminate structure, and CTE coefficients between the materials are different, so that product warpage is easily caused in a product reflow soldering process, and bridging/insufficient soldering between solder balls is easily caused during product warpage due to large size and small interval of the solder balls, and the product size is also large, which is not favorable for product miniaturization.

Disclosure of Invention

The present invention provides a semiconductor package structure and a method for manufacturing the same, which can avoid the substrate pad burning caused by laser, and can realize the independent dispensability of the product, and can avoid the bridging between solder balls, thereby improving the reliability of the product.

Embodiments of the invention may be implemented as follows:

in a first aspect, the present invention provides a semiconductor package structure, including:

a package substrate;

a package chip disposed on the package substrate;

the conductive pins are arranged on the packaging substrate and surround the packaging chip;

the adapter plate is arranged on the conductive pins and covers the packaged chip;

the upper side of the adapter plate is provided with a stacking pad, the lower side of the adapter plate is provided with a conductive pad, the conductive pad is connected with the conductive pins and is electrically connected with the packaging substrate through the conductive pins, a groove corresponding to the packaging chip is further formed in the lower side of the adapter plate, and the packaging chip is locally accommodated in the groove.

In an optional embodiment, the upside of the packaged chip is further provided with an adhesive layer, the adhesive layer is attached to the inside of the groove, and the packaged chip is connected with the adapter plate through the adhesive layer.

In an optional embodiment, the semiconductor package structure further includes a first molding compound layer, the first molding compound layer is disposed on the package substrate and wraps the conductive pins and the package chip, and the first molding compound layer is bonded to the lower side of the interposer.

In an optional embodiment, the groove penetrates through the upper side of the interposer, a first plastic package body is disposed on the upper side of the package chip, and at least a part of the surface of the first plastic package body is exposed from the interposer.

In an optional embodiment, a heat dissipation plate is further attached to the upper side of the adapter plate, and the heat dissipation plate is covered on the groove and attached to the surface of the first plastic package body.

In an optional embodiment, a package module is further stacked on the interposer, and the package module is connected to the conductive pad and attached to the upper surface of the heat dissipation plate.

In an optional embodiment, the package module includes a stack substrate, a first stack chip, a second plastic package body and a second plastic package layer, the first stack chip is attached to the upper side of the stack substrate, the second stack chip is stacked on the lower side of the stack substrate, the stack substrate is connected to the stack pad, the second plastic package layer is disposed on the upper side of the stack substrate and is wrapped outside the first stack chip, the second plastic package body is disposed on the lower side of the stack substrate and is wrapped outside the second stack chip, and the second plastic package body is attached to the upper side surface of the heat dissipation plate.

In an optional embodiment, an electrically conductive heat dissipation line is disposed on the upper side of the interposer, and two ends of the electrically conductive heat dissipation line are respectively connected to the stacking pads located on two sides of the groove.

In an optional implementation mode, a heat dissipation glue layer is arranged on the upper side of the adapter plate, covers the conductive heat dissipation line and is attached to the surface of the first plastic package body.

In a second aspect, the present invention provides a method for manufacturing a semiconductor package structure, including:

mounting a packaging chip on a packaging substrate;

arranging conductive pins surrounding the packaging chip on the packaging substrate;

mounting an adapter plate covering the packaging chip on the conductive pins;

the upper side of the adapter plate is provided with a stacking pad, the lower side of the adapter plate is provided with a conductive pad, the conductive pad is connected with the conductive pins and is electrically connected with the packaging substrate through the conductive pins, a groove corresponding to the packaging chip is further formed in the lower side of the adapter plate, and the packaging chip is locally accommodated in the groove.

The beneficial effects of the embodiment of the invention include, for example:

the semiconductor packaging structure provided by the invention is characterized in that a packaging chip is arranged on a packaging substrate, an adapter plate is arranged on the packaging chip, a stacking pad is arranged on the upper side of the adapter plate, a conductive pad is arranged on the lower side of the adapter plate, the conductive pad is connected with a conductive pin and is electrically connected with the packaging substrate through the conductive pin, a groove corresponding to the packaging chip is also arranged on the lower side of the adapter plate, and the packaging chip is partially accommodated in the groove. Due to the adoption of the adapter plate and the direct arrangement of the stacking bonding pads on the upper side of the adapter plate, the operation that the bonding pads of the substrate are exposed from the laser opening on the plastic package body directly is avoided, the condition that the substrate is burnt out is avoided, and the automatic distribution performance of the product is improved. Meanwhile, the lower side of the adapter plate is provided with the groove, and the local packaging chip is accommodated in the groove, so that the distance between the adapter plate and the packaging substrate is reduced, the mounting height of the adapter plate is reduced, the packaging size is reduced, and the miniaturization of a product is facilitated. Meanwhile, the distance between the adapter plate and the packaging substrate is reduced, so that the size of the conductive pins is reduced, smaller conductive pins can be selected for welding, the gap between adjacent conductive pins is larger, and the bridging or false welding phenomenon between the conductive pins when the substrate is warped is avoided. And because the conductive pin is smaller in size, the design freedom degree is higher, and more conductive bonding pads can be designed. Compared with the prior art, the semiconductor packaging structure provided by the invention can avoid the condition that the substrate bonding pad is burnt out due to laser, can realize the independent distributability of the product, can avoid bridging among the solder balls, and improves the reliability of the product.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 is a schematic view of a semiconductor package structure according to a first embodiment of the invention;

fig. 2 is a schematic view of a semiconductor package structure according to a second embodiment of the invention;

fig. 3 is a schematic view of a semiconductor package structure according to a third embodiment of the invention;

fig. 4 is a schematic view of a semiconductor package structure according to a fourth embodiment of the invention;

fig. 5 is a schematic view of a semiconductor package structure according to a fifth embodiment of the present invention;

fig. 6 is a schematic view of a semiconductor package structure according to a sixth embodiment of the invention;

fig. 7 is a block diagram illustrating a method for fabricating a semiconductor package according to a seventh embodiment of the present invention;

fig. 8 to 11 are process flow diagrams of a method for manufacturing a semiconductor package structure according to a seventh embodiment of the invention.

Icon: 100-a semiconductor package structure; 110-a package substrate; 111-substrate pads; 120-packaging the chip; 121-an adhesive layer; 123-a first plastic package body; 130-conductive pins; 140-an adapter plate; 141-stack pads; 143-conductive pads; 145-grooves; 150-a first molding compound layer; 160-heat sink plate; 170-packaging the module; 171-stacked substrates; 173 — first stacked chip; 175-a second molding layer; 177-a second stacked chip; 179-second plastic package body; 180-conductive heat dissipation wires; 181-heat dissipation glue layer.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.

Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

As disclosed in the background, the conventional POP stack package structure typically uses laser opening to open the molding body to expose the pad on the surface of the substrate, and then forms a metal pillar in the opening to realize the stack. However, the substrate is easily broken when the laser is drilled by the process, the pad on the surface of the substrate is burnt, and the welding failure of the upper-layer stacked structure is further caused. Meanwhile, in the existing POP package, different materials are used for different packages, and CTE coefficients among the materials are different, so that product warpage is easily caused in a reflow soldering process of a product, bridging/insufficient soldering between solder balls (middle layer solder balls and bottom substrate solder balls) is caused, product quality is affected, and reliability of the product is reduced.

In order to solve the above problems, the present invention provides a semiconductor package structure and a method for manufacturing the semiconductor package structure, which can avoid the substrate pad burning caused by laser, and can simultaneously realize the autonomous dispensability of the product, and can avoid the bridging between solder balls, thereby improving the reliability of the product. It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.

First embodiment

Referring to fig. 1, the present embodiment provides a semiconductor package structure 100, which uses an interposer 140 as a base of a stacked structure, so as to avoid burning out of a substrate pad 111 due to laser drilling, achieve independent dispensability of a product, avoid bridging between solder balls, and improve reliability of the product.

The semiconductor package structure 100 provided by this embodiment includes a package substrate 110, a package chip 120, a plurality of conductive pins 130 and an interposer 140, wherein the package chip 120 is disposed on the package substrate 110, the plurality of conductive pins 130 surround the package chip 120, the interposer 140 is disposed on the conductive pins 130 and covers the package chip 120, a stacking pad 141 is disposed on an upper side of the interposer 140, a conductive pad 143 is disposed on a lower side of the interposer 140, the conductive pad 143 is connected to the conductive pins 130 and electrically connected to the package substrate 110 through the conductive pins 130, a groove 145 corresponding to the package chip 120 is further disposed on the lower side of the interposer 140, and the package chip 120 is partially accommodated in the groove 145.

In this embodiment, a circuit layer is disposed in the interposer 140, and the circuit layer is connected to the stacking pads 141 and the conductive pads 143, respectively, so that the interposer 140 functions as a middle conductive interface, and other package modules 170, such as package chips 120 or stack modules, can be stacked on the upper side of the interposer 140, and different interposer 140 can be adopted for different stacking requirements, and the positions and the number of the stacking pads 141 can be reasonably set, thereby improving the self-distribution of products, and facilitating the stacking of products.

It should be noted that the groove 145 in this embodiment may not be provided with a circuit layer, so as to avoid the influence of the grooving on the circuit layer.

In this embodiment, the package substrate 110 is provided with a plurality of substrate pads 111 on an upper side thereof, a plurality of external pads on a lower side thereof, and a plurality of conductive pins 130 are correspondingly disposed on the plurality of substrate pads 111, wherein the conductive pins 130 are solder balls, that is, each substrate pad 111 is provided with a solder ball, and the substrate pads 111 and the conductive pads 143 are electrically connected by the solder balls. Meanwhile, a plurality of solder balls are also formed by ball-planting on a plurality of external pads on the lower side of the package substrate 110, so as to realize the external connection or grounding function.

In the embodiment, the interposer 140 is adopted, and the stacking pad 141 is directly arranged on the upper side of the interposer 140, so that the operation that the substrate pad 111 is exposed from a laser opening on the plastic package body directly is avoided, the substrate is prevented from being burned out, and the autonomous distribution of products is improved. Meanwhile, the groove 145 is formed in the lower side of the interposer 140, and the package chip 120 is partially accommodated in the groove 145, so that the distance between the interposer 140 and the package substrate 110 is reduced, the mounting height of the interposer 140 is reduced, the package size is reduced, and the miniaturization of the product is facilitated. Meanwhile, the distance between the interposer 140 and the package substrate 110 is reduced, so that the size of the conductive pins 130 is reduced, and smaller conductive pins 130 can be selected for welding, so that the gap between adjacent conductive pins 130 is larger, and the bridging or cold joint phenomenon between the conductive pins 130 is avoided when the substrate is warped. And since the conductive pin 130 has a smaller size, the design freedom is higher, and more conductive pads 143 can be designed.

In the embodiment, the packaged chip 120 is flip-chip mounted on the package substrate 110, and the depth of the groove 145 is smaller than the package height of the packaged chip 120, so that the packaged chip 120 is partially accommodated in the groove 145, the shape of the groove 145 is matched with the packaged chip 120, and the size of the groove 145 is slightly larger than the size of the packaged chip 120, so that the packaged chip 120 can be fitted in the groove 145. It should be noted that in the present embodiment, one package chip 120 is disposed on the package substrate 110, and a groove 145 is correspondingly formed on the interposer 140, but of course, a plurality of package chips 120 may also be disposed on the package substrate 110, and a plurality of grooves 145 are correspondingly formed on the interposer 140, so as to accommodate a plurality of package substrates 110.

It should be further noted that, in the embodiment, the interposer 140 may adopt a board-level design, positions of the plurality of package substrates 110 on the whole package substrate 110 are designed on one interposer 140, and finally, the package substrates are separated into single products after being cut by using a cutting process, wherein the interposer 140 adopts a whole board design, and a size of the whole board is consistent with a size of the whole board of the package substrate 110, so that a warpage of the package substrate 110 in a packaging process can be greatly reduced, and the package efficiency can be improved by one-time mounting and covering.

In this embodiment, an adhesive layer 121 is further disposed on the upper side of the package chip 120, the adhesive layer 121 is attached to the groove 145, and the package chip 120 is connected to the interposer 140 through the adhesive layer 121. Specifically, during actual manufacturing, glue may be coated in the groove 145, and then the interposer 140 is attached to the conductive pin 130, where the groove 145 corresponds to the packaged chip 120, the packaged chip 120 contacts with the glue in the groove 145, and the adhesive layer 121 is formed after curing. The adhesive layer 121 may be coated only on the bottom of the groove 145, or may be coated on the bottom wall and the side wall of the groove 145 at the same time, so as to ensure good adhesion. Of course, in the actual manufacturing process, the glue may be directly applied to the upper surface of the packaged chip 120, and then the interposer 140 is mounted, so that the bonding between the packaged chip 120 and the interposer 140 can be achieved. Here adhesive layer 121 not only plays the bonding effect, and adhesive layer 121 still plays buffering and heat dissipation effect simultaneously, and wherein adhesive layer 121 adopts the heat dissipation to glue, can be with the heat transfer that packaged chip 120 produced to keysets 140, realizes the heat dissipation, also makes simultaneously have buffer space between keysets 140 and packaged chip 120, avoids stress impact to lead to packaged chip 120 impaired.

It should be noted that the thickness of the adhesive layer 121 is much smaller than the thickness of the interposer 140 or the height of the packaged chip 120, and the influence on the package height is negligible.

In this embodiment, the semiconductor package structure 100 further includes a first molding compound layer 150, the first molding compound layer 150 is disposed on the package substrate 110 and covers the conductive pins 130 and the package chip 120, and the first molding compound layer 150 is bonded to the lower side of the interposer 140. Specifically, after the mounting of the interposer 140 is completed, a plastic package material is filled between the interposer 140 and the package substrate 110, the plastic package material covers the plurality of conductive pins 130 and the package chip 120 at the same time, and after curing, a first plastic package layer 150 is formed, and by providing the first plastic package layer 150, the conductive pins 130 and the package chip 120 can be protected, and meanwhile, the fixing effect of the bonding plate is further achieved, and the interposer 140 is prevented from falling off from the package chip 120.

In summary, the present embodiment provides a semiconductor package structure 100, which employs an interposer 140, and a stack pad 141 is directly disposed on an upper side of the interposer 140, so as to avoid an operation of directly exposing a substrate pad 111 through a laser opening on a molding compound, avoid a situation that a substrate is burned out, and improve an autonomous distribution of products. Meanwhile, the groove 145 is formed in the lower side of the interposer 140, and the package chip 120 is partially accommodated in the groove 145, so that the distance between the interposer 140 and the package substrate 110 is reduced, the mounting height of the interposer 140 is reduced, the package size is reduced, and the miniaturization of the product is facilitated. Meanwhile, the distance between the interposer 140 and the package substrate 110 is reduced, so that the size of the conductive pins 130 is reduced, and smaller conductive pins 130 can be selected for welding, so that the gap between adjacent conductive pins 130 is larger, and the bridging or cold joint phenomenon between the conductive pins 130 is avoided when the substrate is warped. And since the conductive pin 130 has a smaller size, the design freedom is higher, and more conductive pads 143 can be designed.

Second embodiment

Referring to fig. 2, the basic structure and principle of the semiconductor package structure 100 and the technical effects thereof are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents of the first embodiment without reference to the parts of the embodiment.

In this embodiment, the semiconductor package structure 100 includes a package substrate 110, a package chip 120, a plurality of conductive pins 130 and an interposer 140, wherein the package chip 120 is disposed on the package substrate 110, the plurality of conductive pins 130 surround the package chip 120, the interposer 140 is disposed on the conductive pins 130 and covers the package chip 120, a stacking pad 141 is disposed on an upper side of the interposer 140, a conductive pad 143 is disposed on a lower side of the interposer 140, the conductive pad 143 is connected to the conductive pins 130 and electrically connected to the package substrate 110 through the conductive pins 130, a groove 145 corresponding to the package chip 120 is further disposed on the lower side of the interposer 140, and the package chip 120 is partially accommodated in the groove 145.

In the embodiment, the groove 145 penetrates to the upper side of the interposer 140, the first molding compound 123 is disposed on the upper side of the package chip 120, and at least a part of the surface of the first molding compound 123 is exposed out of the interposer 140. Specifically, a groove is formed in the interposer 140 and penetrates through the interposer 140, so as to form a through-hole-shaped groove 145 structure, the first plastic package body 123 is disposed around the packaged chip 120, and the upper surface of the first plastic package body 123 is exposed out of the interposer 140, so that the chip can be better cooled.

It should be noted that, here, the first plastic package body 123 may be a plastic package structure of the package chip 120 itself, or may be an additionally arranged plastic package structure, where an upper side surface of the first plastic package body 123 is flush with an upper side surface of the interposer 140, so that the package height of the interposer 140 can be further reduced, and the package size can be reduced.

In the semiconductor package structure 100 provided in this embodiment, the groove 145 penetrating through the interposer 140 is disposed, so that the first molding compound 123 on the upper side of the package substrate 110 is exposed out of the interposer 140, thereby improving the heat dissipation performance of the packaged chip 120, further reducing the package size, and facilitating the miniaturization of the product.

Third embodiment

Referring to fig. 3, the basic structure and principle of the semiconductor package structure 100 and the technical effects thereof are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents of the first embodiment without reference to the parts of the embodiment.

The semiconductor package structure 100 provided by this embodiment includes a package substrate 110, a package chip 120, a plurality of conductive pins 130 and an interposer 140, wherein the package chip 120 is disposed on the package substrate 110, the plurality of conductive pins 130 surround the package chip 120, the interposer 140 is disposed on the conductive pins 130 and covers the package chip 120, a stacking pad 141 is disposed on an upper side of the interposer 140, a conductive pad 143 is disposed on a lower side of the interposer 140, the conductive pad 143 is connected to the conductive pins 130 and electrically connected to the package substrate 110 through the conductive pins 130, a groove 145 corresponding to the package chip 120 is further disposed on the lower side of the interposer 140, and the package chip 120 is partially accommodated in the groove 145.

In the embodiment, the groove 145 penetrates to the upper side of the interposer 140, the first molding compound 123 is disposed on the upper side of the package chip 120, and at least a part of the surface of the first molding compound 123 is exposed out of the interposer 140. And the heat dissipation plate 160 is attached to the upper side of the interposer 140, and the heat dissipation plate 160 covers the groove 145 and is attached to the surface of the first plastic package body 123. Specifically, a groove is formed in the interposer 140 and penetrates through the interposer 140, so as to form a through-hole-shaped groove 145 structure, the first plastic package body 123 is disposed around the package chip 120, the upper surface of the first plastic package body 123 is exposed out of the interposer 140, the heat dissipation plate 160 is further attached to the upper side of the groove 145, and the heat dissipation plate 160 is attached to the surface of the first plastic package body 123, so that the heat dissipation effect on the package substrate 110 can be further improved.

The semiconductor package structure 100 provided by this embodiment is through setting up the recess 145 that link up the interposer 140 to set up the heating panel 160 on the upper side, the heating panel 160 directly laminates with the first plastic-sealed body 123, and on the one hand the heating panel 160 can promote the heat dissipation effect to the encapsulation chip 120, and on the other hand the heating panel 160 also can play the heat conduction effect to the upper stacked structure bottom, makes the heat dissipation efficiency of whole stacked structure can strengthen.

Fourth embodiment

Referring to fig. 4, the basic structure and principle of the semiconductor package structure 100 and the technical effects thereof are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents of the first embodiment without reference to the parts of the embodiment.

The semiconductor package structure 100 includes a package substrate 110, a package chip 120, a plurality of conductive pins 130 and an interposer 140, wherein the package chip 120 is disposed on the package substrate 110, the plurality of conductive pins 130 surround the package chip 120, the interposer 140 is disposed on the conductive pins 130 and covers the package chip 120, a stacking pad 141 is disposed on an upper side of the interposer 140, a conductive pad 143 is disposed on a lower side of the interposer 140, the conductive pad 143 is connected to the conductive pins 130 and electrically connected to the package substrate 110 through the conductive pins 130, a groove 145 corresponding to the package chip 120 is further disposed on the lower side of the interposer 140, and the package chip 120 is partially accommodated in the groove 145.

In the embodiment, the groove 145 penetrates to the upper side of the interposer 140, the first molding compound 123 is disposed on the upper side of the package chip 120, and at least a part of the surface of the first molding compound 123 is exposed out of the interposer 140. And the heat dissipation plate 160 is attached to the upper side of the interposer 140, and the heat dissipation plate 160 covers the groove 145 and is attached to the surface of the first plastic package body 123. In addition, the interposer 140 is stacked with a package module 170, and the package module 170 is connected to the conductive pads 143 and attached to the upper surface of the heat dissipation plate 160.

In the present embodiment, the package module 170 includes a stacked substrate 171, a first stacked chip 173 and a second molding layer 175, the first stacked chip 173 is attached to the upper side of the stacked substrate 171, the lower side of the stacked substrate 171 is attached to the heat dissipation plate 160, and the position of the heat dissipation plate 160 corresponds to the position of the first stacked chip 173, so as to achieve the heat dissipation effect on the upper first stacked chip 173. The stacked substrate 171 and the interposer 140 are also electrically connected by solder balls.

In the semiconductor package structure 100 provided by this embodiment, the lower side of the heat dissipation plate 160 is attached to the first plastic package body 123, and the upper side of the heat dissipation plate 160 is attached to the stacked substrate 171, where the heat dissipation plate 160 plays a role of heat dissipation for the upper and lower structures at the same time, so as to further improve the heat dissipation effect of the semiconductor package structure 100.

Fifth embodiment

Referring to fig. 5, the basic structure and principle of the semiconductor package structure 100 and the technical effects thereof are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents of the first embodiment without reference to the parts of the embodiment.

The semiconductor package structure 100 includes a package substrate 110, a package chip 120, a plurality of conductive pins 130, an interposer 140 and a package module 170, wherein the package chip 120 is disposed on the package substrate 110, the plurality of conductive pins 130 surround the package chip 120, the interposer 140 is disposed on the conductive pins 130 and covers the package chip 120, a stack pad 141 is disposed on an upper side of the interposer 140, a conductive pad 143 is disposed on a lower side of the interposer 140, the conductive pad 143 is connected to the conductive pins 130 and electrically connected to the package substrate 110 through the conductive pins 130, a groove 145 corresponding to the package chip 120 is further disposed on the lower side of the interposer 140, and the package chip 120 is partially accommodated in the groove 145. The package modules 170 are stacked on the interposer 140 and connected to the stack pads 141 of the interposer 140 by solder balls to realize electrical connection.

In the present embodiment, the package module 170 includes a stacked substrate 171, a first stacked chip 173, a second stacked chip 177, a second molding compound 179 and a second molding compound 175, the first stacked chip 173 is attached to the upper side of the stacked substrate 171, the second stacked chip 177 is stacked on the lower side of the stacked substrate 171, the stacked substrate 171 is connected to the stacked pad 141, the second molding compound 175 is disposed on the upper side of the stacked substrate 171 and covers the first stacked chip 173, the second molding compound 179 is disposed on the lower side of the stacked substrate 171 and covers the second stacked chip 177, and the second molding compound 179 is attached to the upper surface of the heat sink 160. Specifically, be provided with first stacked chip 173 and second stacked chip 177 in the encapsulation module 170, promoted whole packaging structure's chip and piled up the quantity, heat dissipation plate 160 simultaneously with the laminating of first plastic-sealed body 123 and second plastic-sealed body 179, can directly realize piling up the radiating effect of chip 177 and encapsulated chip 120 to the second.

Sixth embodiment

Referring to fig. 6, the basic structure and principle of the semiconductor package structure 100 and the technical effects thereof are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents of the first embodiment without reference to the parts of the embodiment.

The semiconductor package structure 100 provided by this embodiment includes a package substrate 110, a package chip 120, a plurality of conductive pins 130 and an interposer 140, wherein the package chip 120 is disposed on the package substrate 110, the plurality of conductive pins 130 surround the package chip 120, the interposer 140 is disposed on the conductive pins 130 and covers the package chip 120, a stacking pad 141 is disposed on an upper side of the interposer 140, a conductive pad 143 is disposed on a lower side of the interposer 140, the conductive pad 143 is connected to the conductive pins 130 and electrically connected to the package substrate 110 through the conductive pins 130, a groove 145 corresponding to the package chip 120 is further disposed on the lower side of the interposer 140, and the package chip 120 is partially accommodated in the groove 145.

In the present embodiment, the upper side of the interposer 140 is provided with a conductive heat dissipation wire 180, and two ends of the conductive heat dissipation wire 180 are respectively connected to the stacking pads 141 located at two sides of the groove 145. Specifically, a circuit layer is arranged in the adapter plate 140, the circuit layer and the groove 145 yield, the circuit layers on two sides of the groove 145 can be electrically connected through the conductive heat dissipation wire 180, and wiring of the circuit layer is reduced.

It should be noted that the groove 145 penetrates through the upper side of the interposer 140, the first molding compound 123 is disposed on the upper side of the package chip 120, and at least a part of the surface of the first molding compound 123 is exposed out of the interposer 140.

In this embodiment, the upper side of the interposer 140 is provided with a heat dissipation adhesive layer 181, the heat dissipation adhesive layer 181 covers the conductive heat dissipation line 180 and covers the groove 145, and the heat dissipation adhesive layer 181 is attached to the surface of the first plastic package body 123. Specifically, the heat dissipation glue layer 181 is attached to the first plastic package body 123, so that the heat dissipation effect on the packaged chip 120 is achieved.

Seventh embodiment

Referring to fig. 7, the present embodiment provides a method for manufacturing a semiconductor package structure, which is used to manufacture the semiconductor package structure 100 provided in the first, second, third, fourth, fifth, sixth or seventh embodiment.

The preparation method of the semiconductor packaging structure provided by the embodiment comprises the following steps:

s1: the package chip 120 is mounted on the package substrate 110.

Referring to fig. 8 in combination, specifically, a package substrate 110 is taken, a plurality of substrate pads 111 and flip pads are designed on the package substrate 110, wherein the flip pads are disposed in a mounting area of the package substrate 110, a package chip 120 is mounted on the flip pads in the mounting area, the flip of the package chip 120 is realized through a reflow curing method, and the package chip 120 is electrically connected to the package substrate 110 through the flip pads.

S2: conductive leads 130 are disposed on the package substrate 110 around the package chip 120.

Referring to fig. 9, specifically, a ball-mounting process is performed on the substrate pads 111 on the package substrate 110 to form a plurality of conductive pins 130, where the conductive pins 130 are solder balls, and the solder balls are formed on the plurality of substrate pads 111 and surround the package chip 120.

It should be noted that the ball-mounting process and the flip-chip mounting of the package chip 120 have no obvious sequential relationship, and the package chip 120 may be flip-chip mounted after the conductive pins 130 are formed by ball-mounting on the substrate pads 111.

S3: an interposer 140 is mounted over the conductive leads 130 and over the packaged chip 120.

Referring to fig. 10, specifically, after the ball mounting process is completed, the interposer 140 is mounted, wherein the interposer 140 is designed in advance, the stacking pads 141 are disposed on the upper side of the interposer 140, the conductive pads 143 are disposed on the lower side of the interposer 140, and the mounted interposer 140 is formed by connecting the conductive pads 143 with the conductive pins 130 and electrically connecting the conductive pins 130 with the package substrate 110. And the lower side of the interposer 140 is further provided with a groove 145 corresponding to the packaged chip 120, and the packaged chip 120 is partially accommodated in the groove 145.

Before the interposer 140 is mounted, glue may be applied in the groove 145, and the adhesive layer 121 may be formed on the upper side of the package chip 120 after mounting and curing. By arranging the groove 145, the mounting height of the adapter plate 140 can be greatly reduced, so that the welding size of the conductive pins 130 is reduced, the solder ball with smaller size can be selected for welding, bridging among the solder balls is avoided, and more solder ball pads can be designed after the solder balls are smaller in size, so that the freedom degree of design is improved.

It should be noted that, in this embodiment, the interposer 140 may adopt a board-level design, positions of the plurality of package substrates 110 on the whole package substrate 110 are designed on one interposer 140, and finally, the package substrates are separated into a single product after being cut by using a cutting process, where the interposer 140 adopts a whole board design, and a size of the whole board is consistent with a size of the whole board of the package substrate 110, so that a warpage of the package substrate 110 in a packaging process can be greatly reduced, and the package efficiency can be improved by one-time mounting and covering.

Referring to fig. 11, after the interposer 140 is mounted, the stacked structure is plastic-packaged by a plastic packaging process, a plastic packaging material is filled in the intermediate layer, and finally, solder balls are formed on the back surface of the package substrate 110 by ball mounting, and then the product is cut into individual pieces by a cutting process.

According to the preparation method of the semiconductor packaging structure provided by the invention, the packaging chip 120 is arranged on the packaging substrate 110, the adapter plate 140 is arranged on the packaging chip 120, the stacking bonding pad 141 is arranged on the upper side of the adapter plate 140, the conductive bonding pad 143 is arranged on the lower side of the adapter plate 140, the conductive bonding pad 143 is connected with the conductive pin 130 and is electrically connected with the packaging substrate 110 through the conductive pin 130, the groove 145 corresponding to the packaging chip 120 is also arranged on the lower side of the adapter plate 140, and the packaging chip 120 is partially accommodated in the groove 145. Due to the adoption of the adapter plate 140 and the direct arrangement of the stacking bonding pad 141 on the upper side of the adapter plate 140, the operation that the substrate bonding pad 111 is exposed from a laser opening on the plastic package body directly is avoided, the substrate is prevented from being burnt out, and meanwhile, the autonomous distribution of products is also improved. Meanwhile, the groove 145 is formed in the lower side of the interposer 140, and the package chip 120 is partially accommodated in the groove 145, so that the distance between the interposer 140 and the package substrate 110 is reduced, the mounting height of the interposer 140 is reduced, the package size is reduced, and the miniaturization of the product is facilitated. Meanwhile, the distance between the interposer 140 and the package substrate 110 is reduced, so that the size of the conductive pins 130 is reduced, and smaller conductive pins 130 can be selected for welding, so that the gap between adjacent conductive pins 130 is larger, and the bridging or cold joint phenomenon between the conductive pins 130 is avoided when the substrate is warped. And since the conductive pin 130 has a smaller size, the design freedom is higher, and more conductive pads 143 can be designed.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.