阅读说明：本技术 半导体结构及其制备方法 (Semiconductor structure and preparation method thereof ) 是由 蒋维 杨展悌 叶甜春 罗军 赵杰 于 2021-08-20 设计创作，主要内容包括：本发明涉及一种一种半导体结构,包括：衬底,所述衬底内形成有阱区；浮栅晶体管结构,位于所述衬底上,且覆盖部分所述阱区；体偏压结构,位于所述衬底中,且位于所述晶体管结构的一侧,所述体偏压结构与所述阱区电连接。上述半导体结构,可通过体偏压结构直接向阱区施加正向偏压,以将浮栅中电子吸附至阱区,实现擦除动作；或通过体偏压结构直接向阱区施加负向偏压,以向浮栅中增加电子,实现写入动作。简化了半导体结构,在擦除和写入时更加便捷。(The invention relates to a semiconductor structure, comprising: the semiconductor device comprises a substrate, wherein a well region is formed in the substrate; the floating gate transistor structure is positioned on the substrate and covers part of the well region; and the body bias structure is positioned in the substrate and positioned on one side of the transistor structure, and the body bias structure is electrically connected with the well region. The semiconductor structure can directly apply forward bias to the well region through the body bias structure so as to absorb electrons in the floating gate to the well region and realize erasing action; or a body bias structure directly applies negative bias to the well region to increase electrons in the floating gate, thereby realizing writing action. The semiconductor structure is simplified, and the erasing and writing are more convenient.)

1. A semiconductor structure, comprising:

the semiconductor device comprises a substrate, wherein a well region is formed in the substrate;

the floating gate transistor structure is positioned on the substrate and covers part of the well region;

and the body bias structure is positioned in the substrate and positioned on one side of the transistor structure, and the body bias structure is electrically connected with the well region.

2. The semiconductor structure of claim 1, wherein the body biasing structure is electrically connected to the voltage generator.

3. The semiconductor structure of claim 2, wherein the floating gate transistor structure comprises a gate, a source and a drain, the source and the drain being located on opposite sides of the gate; the semiconductor structure further includes:

the substrate dielectric layer is positioned on the upper surface of the substrate; the grid electrode, the source electrode and the drain electrode are all positioned on the substrate dielectric layer.

4. The semiconductor structure of claim 3, further comprising a fully depleted channel layer between the gate and the substrate dielectric layer and between the source and drain.

5. The semiconductor structure of claim 3, wherein the gate comprises:

the grid laminated structure is positioned on the upper surface of the fully depleted channel layer; the grid laminated structure comprises a tunneling dielectric layer, a floating gate, a control dielectric layer and a control grid which are sequentially overlapped from bottom to top;

and the grid side walls are positioned at two opposite sides of the grid laminated structure.

6. The semiconductor structure of claim 3, further comprising shallow channel isolation structures on both sides of the floating gate transistor structure separating the floating gate transistor structure from the body bias structure.

7. The semiconductor structure of claim 2, wherein the floating gate transistor structure comprises a gate, a source, and a drain; the semiconductor structure also comprises a substrate dielectric layer and a fully depleted channel layer, wherein the substrate dielectric layer is positioned on the upper surface of the substrate, and the fully depleted channel layer is positioned on the upper surface of the substrate dielectric layer;

the grid, the source and the drain are all located on the upper surface of the fully depleted channel layer, and the source and the drain are located on two opposite sides of the grid respectively.

8. The semiconductor structure of any of claims 1-7, wherein the substrate dielectric layer comprises a buried oxide layer; the tunneling dielectric layer comprises an oxide layer, and the control dielectric layer comprises a first oxide layer, a nitride layer and a second oxide layer which are sequentially overlapped from bottom to top; the floating gate and the control gate each comprise a polysilicon gate.

9. A method for fabricating a semiconductor structure, comprising:

providing a substrate, wherein a well region is formed in the substrate;

forming a floating gate transistor structure on the substrate, and forming a body bias structure in the substrate; the floating gate transistor structure covers a portion of the well region; the body bias structure is located on one side of the floating gate transistor structure and electrically connected with the well region.

10. The method of claim 9, further comprising:

providing a voltage generator electrically connected to the body biasing structure.

Technical Field

The present invention relates generally to integrated circuit fabrication, and more particularly to a semiconductor structure and a method of fabricating the same.

Background

A non-volatile memory (NVM) can hold existing data when the chip is completely powered off, read out the data when the chip is powered back next time, and continue to use the data.

NVM formed by Floating Gate (FG) technology is currently the most commonly used one. Floating gate implementations, whether stand-alone or embedded NOR flash, are now the most common.

The floating gate transistor is the biggest difference compared to a normal transistor in that an additional electrically insulated floating gate is added between the gate and the channel. Since the floating gate is electrically isolated, electrons that reach the floating gate are trapped even after the voltage is removed, and do not run off as the voltage is removed. This is the principle of flash non-volatility. However, when the conventional floating gate transistor is erased or written, voltages need to be applied to the well region or the control gate respectively, the circuit structure is complex, and the conventional floating gate transistor is not convenient enough when the voltages are applied, so that the calculation speed is affected.

Disclosure of Invention

In view of the above, it is desirable to provide a semiconductor structure and a method for fabricating the same.

A semiconductor structure, comprising: the semiconductor device comprises a substrate, wherein a well region is formed in the substrate; the floating gate transistor structure is positioned on the substrate and covers part of the well region; and the body bias structure is positioned in the substrate and positioned on one side of the transistor structure, and the body bias structure is electrically connected with the well region.

The semiconductor structure can directly apply forward bias to the well region through the body bias structure so as to absorb electrons in the floating gate to the well region and realize erasing action; or a body bias structure directly applies negative bias to the well region to increase electrons in the floating gate, thereby realizing writing action. The semiconductor structure is simplified, and the erasing and writing are more convenient.

In one embodiment, the body biasing structure is electrically connected to the voltage generator. The body bias arrangement is provided with a positive bias or a negative bias by a voltage generator.

In one embodiment, the floating gate transistor structure comprises a gate, a source and a drain, wherein the source and the drain are respectively positioned at two opposite sides of the gate; the semiconductor structure further includes: the substrate dielectric layer is positioned on the upper surface of the substrate; the grid electrode, the source electrode and the drain electrode are all positioned on the substrate dielectric layer. The substrate dielectric layer can greatly reduce the parasitic capacitance between the source electrode and the drain electrode, can effectively inhibit electrons from flowing from the source electrode to the drain electrode through the well region, and reduces the leakage current of the semiconductor structure.

In one embodiment, the fully depleted channel layer is located between the gate and the substrate dielectric layer and between the source and the drain. The fully depleted channel layer can significantly reduce short channel effects, and has good scaling characteristics and near-ideal subthreshold swing. Compared with the traditional floating gate semiconductor structure, the semiconductor structure has the advantages of better electrostatic controllability, smaller variability, higher speed and lower power consumption.

In one embodiment, the gate includes: the grid laminated structure is positioned on the upper surface of the fully depleted channel layer; the grid laminated structure comprises a tunneling dielectric layer, a floating gate, a control dielectric layer and a control grid which are sequentially overlapped from bottom to top; and the grid side walls are positioned at two opposite sides of the grid laminated structure.

In one embodiment, the semiconductor structure further comprises shallow trench isolation structures on both sides of the transistor structure, separating the transistor structure from the body bias structure.

In one embodiment, a transistor structure includes a gate, a source, and a drain; the semiconductor structure also comprises a substrate dielectric layer and a fully depleted channel layer, wherein the substrate dielectric layer is positioned on the upper surface of the substrate, and the fully depleted channel layer is positioned on the upper surface of the substrate dielectric layer; the grid, the source and the drain are all located on the upper surface of the fully depleted channel layer, and the source and the drain are located on two opposite sides of the grid respectively.

In one embodiment, the substrate dielectric layer comprises a buried oxide layer; the tunneling dielectric layer comprises an oxide layer, and the control dielectric layer comprises a first oxide layer, a nitride layer and a second oxide layer which are sequentially overlapped from bottom to top; the floating gate and the control gate each comprise a polysilicon gate.

A method of fabricating a semiconductor structure, comprising: providing a substrate, wherein a well region is formed in the substrate; forming a floating gate transistor structure on the substrate, and forming a body bias structure in the substrate; the floating gate transistor structure covers a portion of the well region; the body bias structure is located on one side of the floating gate transistor structure and electrically connected with the well region.

In one embodiment, the method for manufacturing a semiconductor structure further includes: providing a voltage generator electrically connected to the body biasing structure.

The semiconductor structure prepared by the method can directly apply forward bias to the well region through the body bias structure so as to adsorb electrons in the floating gate to the well region and realize erasing action; or a body bias structure directly applies negative bias to the well region to increase electrons in the floating gate, thereby realizing writing action. The semiconductor structure is simplified, and the erasing operation and the writing operation are more convenient.

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain drawings of other embodiments based on these drawings without any creative effort.

Fig. 1 is a schematic cross-sectional view of a conventional floating gate NOR flash memory cell.

Fig. 2 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present application.

Fig. 3 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present application.

FIG. 4 is a cross-sectional structure of a semiconductor structure according to yet another embodiment of the present application.

Fig. 5 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

The reference numbers illustrate: 11. a substrate; 12. a substrate dielectric layer; 13. a fully depleted channel layer; 2. a gate electrode; 21. tunneling through the dielectric layer; 22. a floating gate; 23. a control dielectric layer; 231. a first oxide layer; 232. a nitride layer; 233. a second oxide layer; 24. a control gate; 25. a gate side wall; 3. a source electrode; 4. a drain electrode; 5. a body biasing structure; 61. a first shallow trench isolation structure; 62. a second shallow trench isolation structure; 63. and a third shallow trench isolation structure.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing, the regions illustrated in the figures being schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.

The application of non-volatile memory (NVM) is becoming more and more popular, and two non-volatile flash technologies currently in use on the market are NOR flash technology and NAND flash technology. In the NOR flash memory technology, the floating gate NOR flash memory cell has been widely used, and the schematic cross-sectional structure of the conventional floating gate NOR flash memory cell is shown in fig. 1. The semiconductor structure of the present application may be an improvement over conventional floating gate NOR flash memory cells.

In a conventional floating gate NOR flash memory cell, the floating gate 22 is used to trap, store and release electrons. Wherein the trapped electrons and the released electrons correspond to a write operation and an erase operation of the NOR flash memory cell, respectively.

Specifically, when a NOR flash memory cell is erased, a high positive voltage may be applied to the well region to attract most of the electrons stored in the floating gate 22 into the well region, resulting in a transistor that is almost identical to a normal transistor. At this time, the first voltage VDD is applied to the control gate 24, and when the value of the first voltage VDD is greater than a threshold voltage vt (threshold voltage), the NOR flash memory cell is turned on, and a saturation current is generated between the source 3 and the drain 4. At this time, the read value of the NOR flash memory cell is 1.

When a write operation is performed on a NOR flash memory cell, a suitable positive voltage is first applied to the control gate 24 to attract a portion of the electrons from the well region into the floating gate 22. Since the floating gate 22 is provided with insulating layers above and below, this portion of electrons is latched into the floating gate 22, forming a negative pressure region. When the first voltage VDD is applied to the control gate 24, the negative pressure region formed by electrons in the floating gate 22 can counteract a portion of the first voltage VDD, so that the actual voltage on the gate structure is less than the threshold voltage Vt, and thus a current path cannot be formed between the source 3 and the drain 4, and a saturation current cannot be generated. At this time, the read value of the NOR flash memory cell is 0.

However, the conventional floating gate NOR flash memory cell requires a positive voltage to be applied to the well region by means of an additional circuit structure when performing an erase operation, and the circuit structure is complicated, the speed is limited by the response time of the circuit, and it is disadvantageous to reduce the volume of the semiconductor structure. In order to increase the speed of erasing and pumping the NOR flash memory cell, simplify the semiconductor structure, and reduce the volume, an embodiment of the present application proposes a semiconductor structure, as shown in fig. 2, including: a substrate 11, wherein a well region is formed in the substrate 11; the floating gate transistor structure is positioned on the substrate 11 and covers part of the well region; and the body bias structure 5 is positioned in the substrate 11 and positioned at one side of the transistor structure, and the body bias structure 5 is electrically connected with the well region.

As an example, the semiconductor structure shown in fig. 2 is exemplified as a floating gate NOR flash memory cell. Well regions are formed in various portions of substrate 11. In the erase operation, a forward bias voltage is applied to the well region by the body bias structure 5 connected to the well region, so that electrons in the floating gate 22 are absorbed into the well region to obtain a transistor almost identical to a normal transistor. When the first voltage VDD is applied to the control gate 24 and is greater than the threshold voltage Vt, the NOR flash memory cell is turned on, and a saturation current is generated between the source 3 and the drain 4. At this time, the read value of the NOR flash memory cell is 1.

During a write operation, a negative bias is applied to the well region through the body bias structure 5 to repel electrons in the well region to the floating gate 22, and a part of the electrons enter the floating gate through a tunneling effect and are locked in the floating gate 22 to form a negative pressure region. When the first voltage VDD is applied to the control gate 24 and is greater than the threshold voltage Vt, the negative pressure region at the floating gate 22 will cancel part of the first voltage VDD, so that the actual voltage on the gate 2 structure is less than the threshold voltage Vt, and thus a current channel cannot be formed between the source 3 and the drain 4, and a saturation current cannot be generated. At this time, the read value of the NOR flash memory cell is 0.

In summary, in the semiconductor structure of the present embodiment, the body bias structure 5 electrically connected to the well region applies a positive bias or a negative bias to the well region to complete erasing or writing of the semiconductor structure, so that the structure of the NOR flash memory cell is simplified, the volume of the NOR flash memory cell structure is reduced, and the response speed of the NOR flash memory cell is improved.

In one embodiment, the body biasing structure 5 is electrically connected to the voltage generator. The body biasing structure 5 is provided with a positive bias or a negative bias by a voltage generator.

In one embodiment, as shown in fig. 2, the floating gate transistor structure includes a gate 2, a source 3 and a drain 4, wherein the source 3 and the drain 4 are respectively located at two opposite sides of the gate 2; the semiconductor structure further includes: a substrate dielectric layer 12 located on the upper surface of the substrate 11; the grid 2, the source 3 and the drain 4 are all positioned on the substrate dielectric layer 12.

The substrate dielectric layer 12 completely separates the floating gate transistor structure from the substrate 11, and can effectively inhibit electrons of the source 3 from moving to the drain 4 through the well region when the transistor is turned off, so that leakage current is reduced, and system power consumption is reduced. In addition, the substrate dielectric layer 12 can greatly reduce the parasitic capacitance between the source electrode 3 and the drain electrode 4. By way of example, the substrate dielectric layer 12 may be a buried oxide layer.

In one embodiment, as shown in fig. 2, the semiconductor structure further includes a fully depleted channel layer 13. The fully depleted channel layer 13 is located between the gate 2 and the substrate dielectric layer 12, and between the source 3 and the drain 4.

By disposing the fully depleted channel layer 13 between the source 3 and the drain 4, short channel effects can be significantly reduced, resulting in a semiconductor structure with good scaling down characteristics and near ideal subthreshold swing. Compared with the traditional floating gate 22 semiconductor structure, the semiconductor structure in the embodiment has better electrostatic controllability, smaller variability, higher speed and lower power consumption.

In one embodiment, with continued reference to fig. 2, the gate 2 includes: a gate 2 stacked structure on an upper surface of the fully depleted channel layer 13; the gate 2 laminated structure comprises a tunneling dielectric layer 21, a floating gate 22, a control dielectric layer 23 and a control gate 24 which are sequentially laminated from bottom to top; and the grid side walls 25 are positioned at two opposite sides of the laminated structure of the grid 2.

The tunnel dielectric layer 21 may include an oxide layer, and the floating gate 22 and the control gate 24 may include polysilicon layers, for example, the floating gate 22 and the control gate 24 may be polysilicon gates 2. The control dielectric layer 23 may be an oxide layer, or an ONO layer composed of a first oxide layer 231, a nitride layer 232, and a second oxide layer 233 stacked in sequence from bottom to top, as shown in fig. 3. By arranging the oxide layer or the ONO layer above and below the floating gate 22, the floating gate 22 is isolated from other conductive layers, so that electrons cannot be easily lost after tunneling from the well region of the substrate 11 to the floating gate 22, but are latched into the floating gate 22, thereby forming a negative pressure region.

In one embodiment, as shown in fig. 2, the semiconductor structure further comprises shallow trench isolation structures on both sides of the floating gate transistor structure, separating the transistor structure from the body bias structure 5.

As an example, the semiconductor structure includes a first shallow trench isolation structure 61, a second shallow trench isolation structure 62, and a third shallow trench isolation structure 63. The floating gate transistor structure and the substrate dielectric layer 12 are located between the first shallow trench isolation structure 61 and the second shallow trench isolation structure 62, and the body bias structure 5 is located between the second shallow trench isolation structure 62 and the third shallow trench isolation structure 63. The second shallow trench isolation structure 62 separates the floating gate transistor structure from the body bias structure 5, the body bias structure 5 being electrically connected to the well region below the floating gate transistor structure.

In one embodiment, as shown in fig. 4, a floating gate transistor structure in a semiconductor structure includes a gate 2, a source 3, and a drain 4, and the semiconductor structure further includes a substrate dielectric layer 12 and a fully depleted channel layer 13, wherein the substrate dielectric layer 12 is located on the upper surface of the substrate 11, and the fully depleted channel layer 13 is located on the upper surface of the substrate dielectric layer 12; the gate 2, the source 3, and the drain 4 are all located on the upper surface of the fully depleted channel layer 13, and the source 3 and the drain 4 are located on two opposite sides of the gate 2, respectively.

In the present embodiment, the source electrode 3 and the drain electrode 4 are disposed on the upper surface of the fully depleted channel layer 13. Specifically, the source electrode 3 and the drain electrode 4 may be fabricated by an epitaxial process, which aims to increase the saturation current. With the continuous shrinkage of semiconductor structures, the volumes of the source electrode 3 and the drain electrode 4 in the structure shown in fig. 2 are also continuously reduced, so that the saturation current is continuously reduced, and the switching speed of the semiconductor device is reduced. In the semiconductor structure in this embodiment, the source electrode 3 and the drain electrode 4 are arranged in an epitaxial manner, so that the volumes of the source electrode 3 and the drain electrode 4 are not limited by the thickness of the fully depleted channel layer 13, the volumes of the source electrode 3 and the drain electrode 4 can be properly enlarged above the fully depleted channel layer 13, the number of carriers passing through the fully depleted channel layer 13 when a transistor is turned on is increased, the saturation current is increased, and the switching speed of a semiconductor device is increased. In addition, the erasing or writing is performed by applying positive and negative bias voltages to the well region through the body bias structure 5, in this embodiment

An embodiment of the present application further discloses a method for manufacturing a semiconductor structure, as shown in fig. 5, including:

s11: providing a substrate 11, wherein a well region is formed in the substrate 11;

s12: forming a floating gate transistor structure on the substrate 11, and forming a body bias structure 5 in the substrate 11; the floating gate transistor structure covers a portion of the well region; the body bias structure 5 is located at one side of the floating gate transistor structure and is electrically connected to the well region.

In step S11, the well region may be distributed in each portion of the substrate 11, or may be distributed in a concentrated manner in a portion of the substrate 11 corresponding to the floating gate transistor structure, i.e., located right below the floating gate transistor structure, and at least corresponding to the gate 2 of the floating gate transistor structure. By compressing the area of the well region, the electron concentration in the well region can be increased, the corresponding relationship between the well region and the gate 2 can be enhanced, the difficulty of providing electrons from the well region to the floating gate 22 is reduced, that is, the low negative bias voltage is applied to the well region, so that the electrons can tunnel to the floating gate 22.

In step S12, before forming the floating gate transistor structure, the method further includes: a substrate dielectric layer 12 is formed over the substrate 11. The substrate dielectric layer 12 serves to completely separate the floating gate transistor structure from the substrate 11 to reduce leakage current and to reduce parasitic capacitance between the source 3 and the drain 4. By way of example, the substrate dielectric layer 12 may be a buried oxide layer.

The step of forming the floating gate transistor structure comprises: forming a source electrode 3 and a drain electrode 4 on the upper surface of the substrate medium layer 12, wherein the source electrode 3 and the drain electrode 4 are connected through a fully depleted channel layer 13; a gate 2 is formed over the fully depleted channel layer 13. Specifically, the gate 2 comprises a gate 2 laminated structure and a gate sidewall 25, wherein the gate 2 laminated structure comprises a tunneling dielectric layer 21, a floating gate 22, a control dielectric layer 23 and a control gate 24 which are sequentially laminated from bottom to top; the gate spacers 25 are located on opposite sides of the stacked structure of the gate 2.

The body bias structure 5 is formed in the substrate 11 and separated from the floating gate transistor structure by a front channel isolation structure. Wherein the body bias structure 5 is electrically connected to the well region. As an example, the connection between the body bias structure 5 and the well region may be through a metal line, or through another conductive material layer.

In one embodiment, the body biasing structure 5 is connected to a voltage generator. The voltage generator is used for providing a voltage, and the voltage is applied to the body bias structure 5, and the voltage provided by the voltage generator can act on the well region because the body bias structure 5 is electrically connected with the well region. For example, the voltage generator may generate a negative bias to repel electrons in the well region toward the floating gate 22, entering the floating gate 22 by tunneling; alternatively, the voltage generator may generate a forward bias voltage to attract electrons in the floating gate 22 into the well region.

As an example, the floating gate NOR flash memory cell may be prepared by the above method to improve the erase and write speed of the NOR flash memory cell and simplify the structure of the NOR flash memory cell.

The semiconductor structure prepared by the method can apply positive bias or negative bias to the well region through the body bias structure 5 so as to realize erasing or writing operation. Compared with the traditional voltage applying circuit, the body bias structure 5 and the well region are electrically connected or the body bias structure 5 and the well region are electrically connected, so that positive pressure or negative pressure is conveniently and quickly provided for the well region, the semiconductor structure is simplified, and the erasing and writing speed of the semiconductor structure is improved.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.