阅读说明：本技术 集成电路的电源管理方法以及对应的集成电路 (Power management method for integrated circuit and corresponding integrated circuit ) 是由 T·茹阿诺 于 2021-05-20 设计创作，主要内容包括：本公开涉及集成电路的电源管理方法以及对应的集成电路。例如,一种集成电路包括：第一节点,用于在第一电压下偏置；第二节点,用于在第二电压下偏置并且与第一节点具有不可忽略的电容耦合。电源管理设备包括电压提升器,其被配置为提高电源电压并且包括被配置为在中间节点上生成中间电压的升压级。兼容性检测电路被配置为检测中间电压之一和第二电压之间的兼容性,并且如果第二电压与中间电压兼容,则将至少一个第二节点耦合到兼容中间节点。(The present disclosure relates to a power management method for an integrated circuit and a corresponding integrated circuit. For example, an integrated circuit includes: a first node for biasing at a first voltage; a second node for biasing at a second voltage and having a non-negligible capacitive coupling with the first node. The power management device includes a voltage booster configured to boost a power supply voltage and including a boost stage configured to generate an intermediate voltage on an intermediate node. The compatibility detection circuit is configured to detect compatibility between one of the intermediate voltages and the second voltage and couple at least one second node to the compatible intermediate node if the second voltage is compatible with the intermediate voltage.)

1. A method, comprising:

distributing a first voltage on at least one first node;

distributing a second voltage on at least one second node having a capacitance coupled to the at least one first node;

boosting the supply voltage using a boost stage having an intermediate voltage on an intermediate node;

detecting compatibility between at least one of the intermediate voltages and the second voltage; and

coupling at least one second node to a compatible intermediate node having a compatible intermediate voltage in response to at least one of the intermediate voltages being compatible with the second voltage.

2. The method of claim 1, wherein the first and second light sources are selected from the group consisting of,

wherein dividing the second voltage comprises regulating the second voltage by a second regulator circuit; and is

Wherein the method further comprises disconnecting the at least one second node and the second regulator circuit.

3. The method of claim 1, wherein the coupling of the at least one second node to the compatible intermediate node is performed prior to a charging phase of the first node, the charging phase comprising increasing a voltage on the first node to a level of the first voltage.

4. The method of claim 1, wherein the detecting of the compatibility is performed on a digital control signal that controls a value of at least one of the intermediate voltages and a value of the second voltage.

5. The method of claim 4, wherein allocating the first voltage comprises a first adjustment, allocating the second voltage comprises a second adjustment, and the digital control signal comprises at least one of: a signal to control a voltage boost, a signal to control the first conditioning, or a signal to control the second conditioning.

6. The method of claim 4, wherein the coupling of the at least one second node to the compatible intermediate node is delayed by a delay that allows the at least one second node to be charged to the second voltage.

7. The method of claim 1, wherein detecting the compatibility comprises an analog comparison of an instantaneous measurement of a voltage present on a node of an integrated circuit.

8. The method of claim 7, wherein the transient measurements comprise at least one of: a voltage present on at least one of the intermediate nodes, a voltage present on the at least one first node, or a voltage present on the at least one second node.

9. An integrated circuit, comprising:

at least one first node configured to be biased at a first voltage;

at least one second node having a capacitance coupled to the at least one first node and configured to be biased at a second voltage;

a voltage boost circuit configured to boost a supply voltage and comprising a boost stage configured to generate an intermediate voltage on an intermediate node; and

a compatibility detection circuit configured to:

detecting compatibility between at least one of the intermediate voltages and the second voltage; and

coupling at least one second node to a compatible intermediate node having a compatible intermediate voltage in response to at least one of the intermediate voltages being compatible with the second voltage.

10. The integrated circuit of claim 9, further comprising a second regulator circuit configured to regulate the second voltage, wherein the compatibility detection circuit is configured to disconnect the at least one second node from the second regulator circuit.

11. The integrated circuit of claim 9, wherein the compatibility detection circuit is configured to couple the at least one second node to the compatible intermediate node prior to a charging phase of the first node, wherein the charging phase comprises increasing a voltage on the first node to a level of the first voltage.

12. The integrated circuit of claim 9, wherein the compatibility detection circuit is configured to detect the compatibility of digital control signals that control a value of at least one of the intermediate voltages and a value of the second voltage.

13. The integrated circuit of claim 12, wherein the digital control signal comprises at least one of: a signal to control the voltage boost circuit; a signal to control a first regulator circuit configured to regulate the first voltage; or a signal controlling a second regulator circuit configured to regulate the second voltage.

14. The integrated circuit of claim 12, wherein the compatibility detection circuit is configured to: coupling the at least one second node to the compatible intermediate node after a delay that allows the at least one second node to be charged to the second voltage.

15. The integrated circuit according to claim 9, wherein the compatibility detection circuit is configured to detect compatibility between at least one of the intermediate voltages and the second voltage by measuring instantaneous values of voltages present on nodes of the integrated circuit and by comparing the measured instantaneous values.

16. The integrated circuit of claim 15, wherein the compatibility detection circuit is configured to measure instantaneous values of at least one of: a voltage present on at least one of the intermediate nodes, a voltage present on the at least one first node, or a voltage present on the at least one second node.

17. A method, comprising:

distributing a first voltage on a first node;

distributing a second voltage on a second node having a capacitance coupled to the first node;

boosting the supply voltage using a boost stage having an intermediate voltage on an intermediate node;

detecting a compatibility between the second voltage and a compatible intermediate voltage; and

coupling the second node to a compatible intermediate node having the compatible intermediate voltage in response to the second voltage being compatible with the compatible intermediate voltage.

18. The method of claim 17, wherein the first and second light sources are selected from the group consisting of,

wherein dividing the second voltage comprises regulating the second voltage by a second regulator circuit; and is

Wherein the method further comprises disconnecting the second node from the second regulator circuit.

19. The method of claim 17, wherein coupling of the second node to the compatible intermediate node is performed prior to a charging phase of the first node, the charging phase comprising increasing a voltage on the first node to a level of the first voltage.

20. The method of claim 17, wherein the detecting of the compatibility is performed on a digital control signal that controls a value of the second voltage and a value of the intermediate voltage.

Technical Field

Embodiments and implementations relate generally to integrated circuits and related methods, and more particularly, to management of integrated circuit power supplies.

Background

Some nodes in an integrated circuit may reach high voltages (e.g., above 10V (volts)) while other nodes remain at a constant lower voltage.

However, these nodes may have large capacitive coupling, so that when the voltage in the node reaching the high voltage rises, parasitic current is injected into the node at a constant low voltage by the capacitive effect.

In particular, the parasitic current is simply discharged to ground and is therefore lost.

This type of parasitic current flow is particularly likely to occur in large network structures such as memory planes or pixel arrays, where the nodes that can reach high voltages or remain at a lower constant voltage can be numerous and variable depending on the use of the circuit.

Disclosure of Invention

Structurally adapting the architecture of an integrated circuit in order to limit the capacitive coupling between nodes is often very limited, for example in terms of congestion.

In general, it is desirable to avoid energy losses, such as the leakage of the parasitic capacitive currents mentioned above, especially in devices with low energy consumption, for example devices of the "contactless" type, such as devices using RFID ("radio frequency identification") or NFC ("near field communication") technologies associated with standards well known to those skilled in the art.

According to one aspect, there is provided a method for managing power supply to an integrated circuit, the method comprising: distributing a first voltage on at least one first node; distributing a second voltage on at least one second node having a capacitive coupling with the at least one first node; and boosting the supply voltage using a boost stage having an intermediate voltage on an intermediate node. The method further comprises the following steps: detecting a compatibility between the second voltage and the at least one intermediate voltage; and coupling the at least one second node to an intermediate node having a compatible intermediate voltage if the second voltage is compatible with the at least one intermediate voltage.

For example, the second voltage being compatible with the intermediate voltage means that the value of the second voltage is equal to or close to 5% of the value of the intermediate voltage. More broadly, a second voltage and an intermediate voltage may be considered compatible if any difference between them does not impair the functionality of the circuitry on the second node nor the functionality of the circuitry on the intermediate node.

In other words, it is proposed to reintroduce the parasitic capacitance current into the voltage boosting circuit to supply the voltage boosting circuit with the parasitic capacitance current flowing from the first node to the second node.

In one aspect, the compatibility of detecting the voltages on one of the intermediate nodes and the second node allows flexibility in selecting the second node in the architecture of the integrated circuit and selecting the intermediate node in the voltage boost stage.

Thus, energy recovery by reintroducing the parasitic capacitance current into the boost circuit may be optimized in terms of the number of events that generate the capacitive parasitic current to be reintroduced and the efficiency of energy recovery.

Indeed, the choice of the second node can multiply the parasitic current reintroduction, and the choice of the intermediate node allows to optimize the level of the intermediate stage.

Since boosting the supply voltage is typically implemented by a charge pump type boost circuit, the higher the level of the intermediate stage, the greater the energy gain on the supply.

The boost circuit may be configured to boost a power supply voltage (e.g., between 1V and 3V (volts)) to a level of the first voltage (e.g., greater than 10V).

According to one embodiment, the distribution of the second voltage comprises regulating the second voltage by a second regulator circuit, and if the second voltage is compatible with the at least one intermediate voltage, the method comprises disconnecting the connection between the at least one second node and the second regulator circuit.

This allows, in particular, to avoid conflicts with the parasitic currents flowing between the ground terminal and the intermediate node of the regulator circuit.

According to one embodiment, the coupling of the at least one second node to the intermediate node is performed before a charging phase of the first node, the charging phase comprising an increase of the voltage on the first node to a level of the first voltage.

According to one embodiment, the detection of the compatibility is performed on a digital control signal controlling the value of the second voltage and the value of the at least one intermediate voltage.

In fact, the compatibility detection can be programmed to detect a parameterization of the integrated circuit on the digital control signal, wherein the value of the second voltage will be compatible with at least one intermediate voltage, for example an operation specific to the architecture of the integrated circuit and its function.

For example, the distribution of the first voltage includes a first adjustment, the distribution of the second voltage includes a second adjustment, and the digital control signal includes at least one of: a signal to control boost, a signal to control first regulation, a signal to control second regulation.

Advantageously, the coupling of the at least one second node to the intermediate node is delayed by a delay allowing the at least one second node to be charged to the second voltage when compatibility is detected.

In fact, the voltages generated by analog devices (such as regulators and boosters) often have reaction times with respect to their digital control. Thus, the delay added before the effective coupling of the second node to the intermediate node allows no sudden voltage drop caused by the transient voltage on the second node to be applied to the intermediate node from a level lower than the level of the intermediate voltage.

According to another embodiment, detecting compatibility includes analog comparison of instantaneous measurements of voltages present on nodes of the integrated circuit.

The advantage of this embodiment is that the true signal is measured and therefore very reliable in return for the analog design, which is usually more cumbersome than the digital design.

For example, the instantaneous measurement includes at least one of the following voltages: a voltage present on at least one intermediate node; a voltage present on the at least one first node; a voltage present on the at least one second node.

According to another aspect, there is provided an integrated circuit comprising: at least one first node for biasing at a first voltage; at least one second node for biasing at a second voltage and having a capacitive coupling with the at least one first node; and a power management device comprising a voltage boost circuit configured to boost a supply voltage and comprising a boost stage configured to generate an intermediate voltage on an intermediate node. The power management device also includes a compatibility detection circuit configured to detect compatibility between the at least one intermediate voltage and the second voltage and, if the at least one intermediate voltage is compatible with the second voltage, couple the at least one second node to an intermediate node having a compatible intermediate voltage.

According to one embodiment, the integrated circuit includes a second regulator circuit configured to regulate the second voltage and, if the second voltage is compatible with the at least one intermediate voltage, the power management device is configured to disconnect the at least one second node from the regulator circuit.

According to one embodiment, the power management device is configured to couple the at least one second node to the intermediate node prior to a charging phase of the first node, wherein the charging phase of the first node comprises an increase of the voltage on the first node to a level of the first voltage.

According to one embodiment, the power management device is configured to detect compatibility of a digital control signal controlling a value of the second voltage and a value of the at least one intermediate voltage.

For example, the digital control signal includes at least one of: a signal to control the voltage boost circuit; a signal to control a first regulator circuit configured to regulate a first voltage; controlling a signal of a second regulator circuit configured to regulate the second voltage.

Advantageously, the power management device is configured to: upon detecting compatibility, coupling the at least one second node to the intermediate node after a delay that allows the at least one second node to be charged to the second voltage.

According to one embodiment, the power management device is configured to detect the compatibility between the second voltage and the at least one intermediate voltage by measuring an instantaneous value of a voltage present on a node of the integrated circuit and by comparing the measured values.

For example, the power management device is configured to measure the instantaneous value of at least one of the following voltages: a voltage present on at least one intermediate node; a voltage present on the at least one first node; a voltage present on the at least one second node.

Drawings

Further advantages and features of the invention will become apparent upon examination of the detailed description of embodiments and non-limiting embodiments, namely the accompanying drawings, wherein:

FIG. 1 shows an integrated circuit in an initial mode, including a voltage booster and a compatibility detection circuit;

FIG. 2 illustrates an integrated circuit in an energy recovery mode, including a voltage booster and a compatibility detection circuit;

FIG. 3 shows plots of voltage and parasitic current as a function of time for the first and second nodes;

FIG. 4 illustrates an integrated circuit having a compatibility detection circuit capable of selecting an intermediate node compatible with a second voltage; and

fig. 5 shows an integrated circuit with a compatibility detection circuit configured to read a digital control signal in order to detect a compatibility between the second voltage and the at least one intermediate voltage.

Detailed Description

Fig. 1 and 2 show an integrated circuit CI comprising in particular a voltage booster ELV and a compatibility detection circuit CMPTB configured to reintroduce to the voltage booster ELV a parasitic capacitance current Ip flowing from a first node N1 to a second node N2.

Fig. 3 shows curves G1, G2, G3, which show the development of the voltages V1, V2 and the parasitic current Ip on the first and second nodes N1, N2 as a function of time t, in particular with respect to the times t0, t1, t2 defined below.

Fig. 1 shows the integrated circuit CI in the initial mode (or normal mode) between times t0 and t1, while fig. 2 shows the integrated circuit CI in the energy recovery mode between times t1 and t 2.

In particular, fig. 1, 2 and 3 will be described in relation to each other in order to illustrate a method for managing a power supply of an integrated circuit CI, wherein a parasitic capacitance current Ip flowing from a first node N1 to a second node N2 is reintroduced into a voltage boosting circuit ELV.

Reintroducing the parasitic current Ip into the booster circuit ELV allows reducing the power consumption of the integrated circuit CI, which is advantageous in itself.

This allows in particular to relieve the stress of the power supply stage ALM of the integrated circuit CI, which may have limited energy resources, for example in the case of "contactless" powering of the integrated circuit, as defined for example in standards associated with technologies known as RFID and NFC (respectively for "radio frequency identification" and "near field communication" associated with standards well known to those skilled in the art).

For example, the first node N1 and the second node N2 of the integrated circuit CI belong to a device ARY comprising a matrix array of relatively large size, such as a storage plane of a typical non-volatile memory or a matrix of light-sensitive or photo-emitter pixels.

In fact, this type of matrix array ARY device usually has parasitic capacitive coupling between the nodes of the circuit, which is also difficult to avoid in terms of structural architecture.

The first node N1 and the second node N2 are selected to have, for example, a non-zero capacitive coupling Cp.

Advantageously, the first node N1 and the second node N2 are selected to have a non-negligible capacitive coupling Cp, that is to say the capacitive coupling Cp may cause a significant current leakage (with respect to the values of the first voltage V1 and the second voltage V2 which belong to the normal use conditions of the integrated circuit CI) with respect to the output current of the voltage boosting circuit ELV. For example, "significant" means "at least of the same order of magnitude.

The booster circuit ELV is configured to boost the power supply voltage supplied by the power supply ALM to a higher level (referred to as a high voltage HV).

For example, power supply ALM provides a low power supply voltage (e.g., 1V to 3V (volts)), while boost circuit ELV provides a high voltage HV (e.g., on the order of 10V).

The voltage boosting circuit ELV is, for example, of the charge pump type and comprises a series of voltage boosting stages STG1, STG2, STG3, STG4, STG5, each configured to boost the input voltage from a basic level. Thus, the output of each stage STG1-STG5 is at a respective intermediate voltage on a respective intermediate node, particularly the intermediate voltage V3 on node N3 at the output of stage STG 3.

Each boost stage STG1-STG5 cannot produce power and the input current I2 (for stage STG3) is necessarily higher than the output current I3 (for stage STG 3).

According to a simplified operating principle, if each voltage boosting stage STGk (1 ≦ k ≦ 5) is capable of providing at the output a current Ik equal to half the current Ik-1 received at the input, the currents I0-I5 decrease quadratically with the number of voltage boosting stages.

The input and output currents I0, I1, I2, I3, I4 of each voltage boosting stage are shown by arrows whose size is proportional to the intensity of the respective current.

For example, the current I0 supplied by the power supply ALM to the voltage boost circuit ELV is budgeted to 0.9 mA.

For example, the first voltage V1 is distributed across the first node N1 via a first regulator circuit REG1, which is configured to regulate the high voltage HV exiting the boost circuit ELV 1. For example, the first voltage V1 leaving the regulator REG1 is regulated to the same level as the high voltage HV, e.g. 10V.

For example, the second voltage V2 is distributed to the second node N2 via a second regulator circuit REG2, which is configured to regulate the high voltage HV exiting the boost circuit ELV 2. The second voltage V2 leaving the regulator REG2 is regulated to a level lower than that of the first voltage V1, for example, a level between 5V and 7V.

Alternatively, the second voltage V2 may be distributed by the second regulator circuit REG2 from another node than the output HV of the voltage boost circuit ELV (e.g., from the intermediate node or the first node N1 of the voltage boost circuit).

In the initial mode t0-t1 shown in fig. 1, the second node N2 is coupled to the output of the regulator REG2 through a switch SW2 that is controlled to be turned on (i.e., closed) by the compatibility detection circuit CMPTB.

Also, in the initial mode t0-t1, the other switch SW1 connected between the second node N2 and the intermediate node N3 of the voltage boosting circuit ELV is controlled to be turned off (i.e., turned on) by the compatibility detection circuit CMPTB.

Refer to fig. 3 and 1.

At time t0 when the integrated circuit is operating, the distribution of the first voltage V1 at level HV and the second voltage V2 at level LV is controlled. The control comes from conventional control circuitry such as a microcontroller or automaton commonly referred to as a state machine.

The first voltage V1 and the second voltage V2 do not immediately rise to the respective stable levels HV, LV, but have a charging time during which the voltages V1, V2 gradually increase before reaching the controlled levels HV, LV.

As shown in the graph G2, the second voltage V2 reaches the level LV at the time t 1; and as shown in the graph G1, the first voltage V1 reaches the level HV at a time t2 after t 1.

The charging time (t2-t0) of the first voltage V1 and the charging time (t1-t0) of the second voltage V2 depend, inter alia, on the analog function of the voltage-boosting circuit ELV and the regulator circuits REG1, REG 2.

In this example, the shape of the slopes of the first voltage V1 and the second voltage V2 is the same between times t0 and t1, in particular because the first voltage V1 and the second voltage V2 come from regulators REG1, REG2, while regulators REG1, REG2 are supplied by the same voltage HV from the boost stage ELV. The shape of the slopes of the first voltage V1 and the second voltage V2 may also result from the fact that the output of the voltage boost circuit ELV is current limited.

Thus, as shown in the graph G3, the difference Δ V (Δ V — V1-V2) between the first voltage V1 and the second voltage V2 is zero between the times t0 and t 1.

Therefore, according to the equation Ip ═ C × dV/dt (C is the capacitance value of the parasitic capacitance Cp and dV/dt is the variance of Δ V) is zero between times t0 and t 1.

On the other hand, from the time t1 to the time t2, the second voltage V2 stabilizes at the level LV, while the first voltage V1 continues to rise to the level HV.

The difference Δ V follows a linear variation and between times t1 and t2 a constant parasitic capacitance current Ip has flowed from the first node N1 to the second node N2.

After the time t2, the first voltage V1 remains constant at the controlled level HV, the difference Δ V also remains constant, and the parasitic current Ip is zero.

When the parasitic current Ip has flowed, i.e. between times t1 and t2, the parasitic current Ip will be evacuated to the ground GND of the integrated circuit through the second regulator REG2 if the power management device PWM is kept in the mode shown in fig. 1.

However, as mentioned above, the compatibility detection circuit CMPTB is configured to reintroduce the parasitic capacitance current Ip into the voltage boosting circuit ELV.

In this regard, reference is made to fig. 2 and 3.

Fig. 2 shows the integrated circuit CI in energy recovery mode between times t1 and t2, i.e. when a parasitic capacitance current Ip is generated between the nodes N1, N2 of the integrated circuit CI.

The compatibility detection circuit CMPTB is configured to detect compatibility between the second voltage V2 and at least one intermediate voltage of the voltage boosting circuit ELV. An example where a single intermediate voltage V3 leaves the penultimate stage (before the penultimate stage) the boosting stage STG3 on the intermediate node N3 will be considered.

And, if the actual value of the second voltage V2 is detected to be compatible with the intermediate voltage V3, the compatibility detection circuit CMPTB is configured to couple the at least one second node N2 to the intermediate node N3. Advantageously, the compatibility detection circuit CMPTB is configured to simultaneously disconnect the second node N2 from the output of the regulator REG 2.

In this regard, the compatibility detection circuit CMPTB controls the switch SW1 to be turned on (closed) and advantageously controls the switch SW2 to be turned off (open).

In order to be compatible with the intermediate voltage V3, the second voltage V2, which is stabilized at the controlled level LV, must be similar to, that is to say substantially equal, for example equal to 5%, to the intermediate voltage V3. Of course, the similarity threshold between the second voltage and the intermediate voltage will depend on the architecture of the integrated circuit and the function of the signals on nodes N2, N3, as the case may be. The skilled person will know how to determine the similarity threshold accordingly.

In fact, on the one hand, the second voltage V2 must not interfere with the function of the voltage boost circuit ELV, for example, a second voltage V2 that is too low may cause the voltage at the intermediate node N3 to drop, and on the other hand, the intermediate voltage V3 does not interfere with the function of the circuit ARY comprising the second node N2.

Therefore, the selection of the second node N2 will advantageously take into account this parameter, i.e. the compatibility with the at least one intermediate node N3 of the boost circuit.

In the example of fig. 1 and 2, the compatibility detection circuit CMPTB comprises a first analog input IANA2 coupled to the output node (N2) of the regulator REG2 and a second analog input IANA3 coupled to the intermediate node N3.

In this exemplary embodiment and implementation, in order to evaluate the compatibility between the second voltage V2 and the intermediate voltage V3, the compatibility detection circuit CMPTB is configured to measure the instantaneous values of the voltages present on the nodes of the integrated circuit CI, in particular the second voltage V2 present on the second node N2, the intermediate voltage V3 present on the intermediate node N3, and optionally the first voltage V1 present on the first node N1.

The compatibility detection circuit CMPTB is configured to compare the measured values in order to identify equality or similarity of the voltage values.

In this example, the compatibility detection circuit CMPTB includes a comparator circuit (e.g., of a typical operational amplifier type) configured to perform an all-or-nothing type of comparison of the level of the second voltage V2 on the input IANA2 with the level of the intermediate voltage V3 on the input IANA 3. Thus, the digital output signals of the comparators may control the switches SW2, SW1 in opposite directions from each other.

Alternatively, the compatibility detection circuit CMPTB may comprise a dynamic comparator circuit based on a conventional function of comparing samples, which is more energy efficient.

Analog comparator technology, while traditionally relatively power hungry, has the advantage of being reliable because it is based on measuring the voltage that is actually present on an integrated circuit IC node.

Therefore, the compatibility detection circuit CMPTB is able to detect the time t1 at which the second voltage V2 is compatible with the intermediate voltage V3 of the voltage boost circuit ELV, thereby placing the power management device PWM in the energy recovery mode t1-t 2.

In the energy recovery mode t1-t2, as shown in FIG. 2, a parasitic capacitance current Ip is injected into the intermediate node N3 via the switch SW3 in the on state.

The currents I0, I1, I2, I3, I4 and Ip present in the booster circuit ELV are again indicated by arrows, the size of which is proportional to the intensity of the respective currents.

The current Ip thus injected into the intermediate node N3 is added to the current I3b leaving the stage STG3, and the upper stage STG4 benefits from a current of strength I3b + Ip. Thus, the stage STG3 provides a current I3b that is lower than the current I3 of the conventional mode shown in fig. 1 (I3b — I3-Ip). Thus, the current I2b generated by the lower-stage STG2 consumed by the stage STG3 at its input is lower (I2b < I2) compared to the conventional mode. Similarly, the lower stage STG2 consumes a lower current I1b generated by the first stage STG1 compared to the conventional mode (I1b < I1), and the first stage STG1 also consumes a current I0b, which is lower than the current I0 provided by the power supply ALM in the conventional mode.

Each reduction in current I3b-I1b at the output of each boost stage STG3-STG1 is amplified by the gain at the input due to the two-fold reduction in current consumption explained above.

In other words, the difference between the current I2b and the conventional current I2 is greater than the difference I3b-I3, I2b-I2> I3b-I3, similarly, I1b-I1> I2b-I2, and thus I0b-I0> I1 b-I1. Therefore, the gain of the current I0b provided by the power supply ALM is much greater than the total intensity of the parasitic current Ip re-injected into the booster circuit ELV (I0b-I0> > Ip).

For example, a parasitic current Ip of approximately 13 μ A (microamperes) injected back into the output of the second stage of the three stage boost circuit reflects a gain on the power source ALM of 150 μ A. For a budget of 0.9mA, a gain of 150 μ A represents more than 15% of the budget.

The higher the parasitic current Ip is re-injected into the intermediate node N3 of the series of boost stages STG1-STG5, the greater the gain of the power supply ALM.

The selection of the second node will therefore advantageously take into account this parameter, i.e. be able to have a voltage level corresponding to the high intermediate node of the voltage boosting circuit ELV.

In general, the choice of the second node N2 will take into account the various parameters described above, that is to say have a capacitive coupling with the first node capable of generating the parasitic current of interest and compatibility with the at least one intermediate node N3 of the booster circuit, and is advantageously as high as possible.

Refer to fig. 4.

Fig. 4 shows an embodiment corresponding to the integrated circuit described above with reference to fig. 1 and 2, wherein the compatibility detection circuit CMPTB is capable of selecting an intermediate node among the plurality of intermediate nodes N3, N4 of the voltage boost circuit ELV that is compatible with the second voltage V2.

In the example of fig. 4, two intermediate nodes may be selected, one being node N3 at the output of the second to last (second from last) boosting stage STG4, and the other being node N4 at the output of the third to last (before last) boosting stage STG 4. In another example, other intermediate nodes may be selected, such as all of the intermediate nodes of the boost circuit ELV.

This allows for a multiplication example, wherein the parasitic current Ip is generated according to different levels of the second voltage V2, thereby being able to be re-injected into different intermediate nodes N3, N4 of the voltage boost circuit ELV.

In this embodiment, the compatibility detection circuit CMPTB comprises an additional analog input IANA4 coupled to an additional intermediate node N4 (in this example at the output of the penultimate boosting stage STG 4).

The additional switch SW4 connected between the second node N2 and the additional intermediate node N4 is controlled to be in an on or off state according to whether compatibility between the second voltage V2 and the voltage on the additional intermediate node N4 is detected.

In this example, the compatibility check is performed by comparison with the simulation previously described with reference to fig. 1 and 2.

Of course, in case other intermediate nodes (nodes other than the illustrated nodes N3 and N4) may be selected, the compatibility detection circuit CMPTB is able to couple another intermediate node compatible with the second voltage V2 through other additional switches coupled between the respective other intermediate node and the second node N2.

Multiplying the number of analog inputs IANA3, IANA4 by the number of analog comparator circuits within the compatibility detection circuit CMPTB may be cumbersome and power consuming. Therefore, a limited number of intermediate nodes will advantageously be selected which are as high as possible in a series of boosting stages of the boosting circuit ELV (such as the output nodes of the penultimate and third-to-last boosting stages SGT4, SGT 3).

Fig. 5 shows a preferred embodiment, wherein the compatibility detection circuit CMPTB is configured to read the digital control signals DC1, DC11-DC15, DC2 in order to detect the compatibility of the second voltage V2 with the at least one intermediate voltage V3, V4 of the voltage booster circuit ELV.

The integrated circuit CI has an example of the architecture described above with reference to fig. 1 to 3, with the exception of the function of the compatibility detection circuit CMPTB, and like elements have like reference numerals and are not described in detail here.

For example, the compatibility detection circuit CMPTB is incorporated in a control and management circuit of the device ARY, such as a state machine or a microcontroller (such as a programmer).

The first regulator REG1 receives the first digital control signal DC1, for example defining the stable level HV of the first voltage V1, and the second regulator REG2 receives the second digital control signal DC2, for example defining the stable level LV of the second voltage V2.

Furthermore, in this example, to define the level of the high voltage HV, it is considered that the first digital control signal DC1 is also received by the voltage boost circuit ELV.

The voltage boost stages STG1-STG5 are typically provided with an internal regulation loop from which an internal digital regulation signal DC11-DC15 representing the voltage level at the respective intermediate node (in particular N3, N4) is output.

In fact, when the voltage boost circuit ELV includes the regulation intermediate nodes N3, N4, it is generally considered that there are digital signals DC13, DC14 on the intermediate nodes N3, N4 that control the level of the regulated intermediate voltage.

For example, internal conditioning digital signals DC11-DC15 are of the "on/off" type, that is, when the output node of the boost stage STG1-STG5 reaches the target voltage, the stage stops pumping (its internal clock is switched off). This stage does not resume pumping until the output voltage drops below the threshold.

Also, knowing the function of the routines of the integrated circuit CI and the control (or setting) of the voltage boost circuit ELV and the regulators REG1, REG2, it is possible to know when the second node N2 and one of the intermediate nodes N3, N4 are equal without making any analog measurements.

In this example, the known regulator REG2 controls the second voltage V2 (refer to fig. 3) under the following conditions:

condition 1: when V1< LV, V2 ═ V1;

condition 2: when V1> LV, V2 ═ LV (∼ V3).

Condition 2 may be detected by simply observing the digital control signals DC1, DC2 from regulators REG1, REG2, and the digital internal regulation signals DC11-DC15 from stages STG1-STG5 of the voltage boost circuit ELV.

In this example, the compatibility detection circuit CMPTB comprises, in this case, a first input INUM1 receiving the digital control signal DC1 and the digital internal regulation signals DC11-DC15, and a second input INUM2 receiving the digital control signal DC2 of the second regulator REG 2.

In fact, condition 2 is recognized if the digitally controlled DC1 of the first regulator REG1 controls the first voltage V1 to be greater than the intermediate voltage LV on the intermediate node N3 (controlled by the digital internal regulation signal DC 13).

Then, the compatibility detection circuit CMPTB may connect the second node N2 to the corresponding intermediate node N3 and disconnect the second node N2 from the output of the second regulator REG 2.

Of course, in the context of a different routine of the function of the integrated circuit or of the selection of the second node N2 in another position of the device ARY, the compatibility detection device CMPTB is configured to connect the second node N2 with another intermediate node N4, in particular to detect its compatibility with the second voltage V2 by means of a corresponding digital internal regulation signal DC 14.

However, since analog circuits such as regulators and boosters may require time to react to digital control, a delay may be added between the detection of conditions made with respect to digital signals and the effective connection of the second node N2 and the intermediate nodes N3, N4 (the voltage of which is compatible with the second node V2).

Thus, the compatibility detection circuit CMPTB is advantageously configured to connect the second node N2 to the compatible intermediate node N3 after a delay t1-t0 (fig. 3) of detecting the compatibility condition t 0. The delay t1-t0 is determined so as to allow charging of the at least one second node N2 to the second voltage V2 at a stable Level (LV).

Furthermore, and in a general manner applicable to the embodiments and implementations described with reference to fig. 1-4 and 5, at a time t1 marked as the beginning of the charging phase t2-t1 of the first node N1, the compatibility detection circuit CMPTB is configured to couple the second node N2 to the intermediate node N3 detected as compatible. The charging phase of the first node N1 includes increasing the voltage on the first node N1 to a level of the first voltage V1(HV), while the second voltage V2 is stable (LV). In fact, during the charging phase t2-t1, the potential difference Δ V between the first node N1 and the second node N2 varies, generating a parasitic capacitance current Ip.

In summary, the above-described embodiments and implementations are advantageously associated with low voltage (e.g., less than 3V) powered integrated circuits, while some internal functions (such as non-volatile memory or image sensors) require high internal voltages. To generate a high internal voltage, a voltage boosting circuit divided into a plurality of stages (such as charge pumps) is used. However, these circuits, which may consume large amounts of current, may present problems for low energy applications such as contactless products, internet of things products, and the like. In applications including storage networks or image sensors, nodes that are controlled to perform the functions for which the network is intended often have significant parasitic coupling due to the size of the network.

The above described embodiments and implementations allow for energy savings by utilizing the current caused by parasitic coupling. This parasitic capacitance current is reinjected into the intermediate stage of the appropriate boost circuit through the compatibility detection circuit when possible and useful. Thus, the lower stage of the boost circuit requires less input current to maintain the voltage of the upper intermediate stage, which reduces overall power consumption.

While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description of the invention. It is therefore intended that the appended claims encompass any such modifications or embodiments.