阅读说明：本技术 抢占式页故障处理 (Preemptive page fault handling ) 是由 M·拉马多斯 V·韦姆拉帕利 N·库雷 W·B·萨德勒 J·D·皮亚尔斯 M·A·彼得 于 2020-02-10 设计创作，主要内容包括：涉及预测性页故障处理的方法和设备。在示例中,一种设备包括处理器,所述处理器用于：接收触发了计算进程的页故障的虚拟地址；检查用于虚拟存储器分配的虚拟存储器空间,所述虚拟存储器分配针对触发了所述页故障的所述计算进程；以及根据以下项之一来管理所述页故障：第一协议,所述第一协议响应于确定触发了所述页故障的所述虚拟地址是针对所述计算进程的所述虚拟存储器分配中的最后页,或者第二协议,所述第二协议响应于确定触发了所述页故障的所述虚拟地址不是针对所述计算进程的所述虚拟存储器分配中的最后页。还公开并要求保护其它实施例。(To methods and apparatus for predictive page fault handling. In an example, an apparatus includes a processor to: receiving a virtual address that triggered a page fault of a computing process; checking virtual memory space for a virtual memory allocation, the virtual memory allocation being for the computing process that triggered the page fault; and managing the page fault according to one of: a first protocol in response to determining that the virtual address that triggered the page fault is the last page in the virtual memory allocation for the computing process, or a second protocol in response to determining that the virtual address that triggered the page fault is not the last page in the virtual memory allocation for the computing process. Other embodiments are also disclosed and claimed.)

1. An apparatus comprising a processor configured to:

receiving a virtual address that triggered a page fault of a computing process;

checking virtual memory space for a virtual memory allocation, the virtual memory allocation being for the computing process that triggered the page fault; and

managing the page fault according to one of:

a first protocol responsive to determining that the virtual address that triggered the page fault is a last page in the virtual memory allocation for the computing process, or

A second protocol responsive to determining that the virtual address that triggered the page fault is not a last page in the virtual memory allocation for the computing process.

2. The apparatus of claim 1, the processor to:

allocating and mapping a predetermined number of pages in the virtual memory space for the computing process that triggered the page fault.

3. The apparatus of claim 2, wherein the predetermined number of pages starts from the virtual address that triggered the page fault.

4. The apparatus of claim 3, the processor to:

updating a page table in the virtual memory space.

5. The apparatus of claim 4, the processor to:

storing in memory a page fault event data record, the page fault event data record including a process identifier, a virtual memory address, and a timestamp.

6. The apparatus of claim 5, the processor to:

constructing a time series dataset from a series of page fault event data records stored in memory;

generating a predicted page fault based on an analysis of the time series data; and

preemptively retrieving data into virtual memory based on the predicted page fault.

7. The device of claim 1, wherein the processor is embedded in a memory management unit.

8. A method, comprising:

receiving a virtual address that triggered a page fault of a computing process;

checking virtual memory space for a virtual memory allocation, the virtual memory allocation being for the computing process that triggered the page fault; and

managing the page fault according to one of:

a first protocol responsive to determining that the virtual address that triggered the page fault is a last page in the virtual memory allocation for the computing process, or

A second protocol responsive to determining that the virtual address that triggered the page fault is not a last page in the virtual memory allocation for the computing process.

9. The method of claim 8, further comprising:

allocating and mapping a predetermined number of pages in the virtual memory space for the computing process that triggered the page fault.

10. The method of claim 9, wherein the predetermined number of pages starts from the virtual address that triggered the page fault.

11. The method of claim 10, further comprising:

updating a page table in the virtual memory space.

12. The method of claim 11, further comprising:

storing in memory a page fault event data record, the page fault event data record including a process identifier, a virtual memory address, and a timestamp.

13. The method of claim 12, further comprising:

constructing a time series dataset from a series of page fault event data records stored in memory;

generating a predicted page fault based on an analysis of the time series data; and

preemptively retrieving data into virtual memory based on the predicted page fault.

14. The method of claim 8, wherein the processor is embedded in a memory management unit.

15. One or more non-transitory computer-readable media comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to:

receiving a virtual address that triggered a page fault of a computing process;

checking virtual memory space for a virtual memory allocation, the virtual memory allocation being for the computing process that triggered the page fault; and

managing the page fault according to one of:

a first protocol responsive to determining that the virtual address that triggered the page fault is a last page in the virtual memory allocation for the computing process, or

A second protocol responsive to determining that the virtual address that triggered the page fault is not a last page in the virtual memory allocation for the computing process.

16. The computer-readable medium of claim 15, comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:

allocating and mapping a predetermined number of pages in the virtual memory space for the computing process that triggered the page fault.

17. The computer-readable medium of claim 16, wherein the predetermined number of pages starts from the virtual address that triggered the page fault.

18. The computer-readable medium of claim 17, comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:

updating a page table in the virtual memory space.

19. The computer-readable medium of claim 18, comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:

storing in memory a page fault event data record, the page fault event data record including a process identifier, a virtual memory address, and a timestamp.

20. The computer-readable medium of claim 19, comprising one or more instructions that when executed on the at least one processor configure the at least one processor to:

constructing a time series dataset from a series of page fault event data records stored in memory;

generating a predicted page fault based on an analysis of the time series data; and

preemptively retrieving data into virtual memory based on the predicted page fault.

21. The computer-readable medium of claim 15, wherein the processor is embedded in a memory management unit.

Technical Field

The present disclosure relates generally to the field of electronics. More particularly, some embodiments relate to preemptive page fault handling in a data processing system (e.g., a graphics processor).

Background

Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, and so forth. Traditionally, graphics processors have used fixed-function computational units to process graphics data; more recently, however, some graphics processors have been made programmable to enable such processors to support a wide variety of operations for processing vertex and fragment data.

To further improve performance, graphics processors often implement processing techniques, such as pipelining, that attempt to process as much graphics data as possible in parallel throughout different portions of the graphics pipeline. Parallel graphics processors with single instruction multi-thread (SIMT) architectures are designed to maximize parallel throughput in the graphics pipeline. In the SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as often as possible to improve processing efficiency. A general overview of software and hardware for the SIMT architecture can be found in Shane CookCUDA ProgrammingChapter 3, pages 37-51 (2013).

The phrase "page fault" refers to a type of exception caused by computer hardware when a running program accesses a memory page that is not currently mapped by a Memory Management Unit (MMU) to the virtual address space of a process executing on the computer hardware. Typically, the MMU detects a page fault, and the page fault handler is part of the operating system kernel. When dealing with a page fault, the operating system attempts to make the needed page accessible at a location in physical memory. If this cannot be done, the process may be terminated due to an illegal memory access. Page faults consume processing resources and introduce latency into the process.

Thus, techniques for managing page faults may find utility in, for example, a data processing system including a graphics processing system.

Drawings

So that the manner in which the above recited features of the embodiments of the present invention can be understood in detail, a more particular description of the embodiments briefly summarized above may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments and are therefore not to be considered limiting of its scope.

FIG. 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein;

2A-2D illustrate parallel processor components according to embodiments;

3A-3C are block diagrams of graphics multiprocessor and multiprocessor-based GPUs, according to embodiments;

4A-4F illustrate exemplary architectures in which multiple GPUs are communicatively coupled to multiple multi-core processors;

FIG. 5 illustrates a graphics processing pipeline according to an embodiment;

FIG. 6 illustrates a machine learning software stack according to an embodiment;

FIG. 7 illustrates a general purpose graphics processing unit in accordance with an embodiment;

FIG. 8 illustrates a multi-GPU computing system according to an embodiment;

9A-9B illustrate layers of an exemplary deep neural network;

FIG. 10 illustrates an exemplary recurrent neural network;

FIG. 11 illustrates training and deployment of a deep neural network;

FIG. 12 is a block diagram illustrating distributed learning;

FIG. 13 illustrates an exemplary inference System On Chip (SOC) adapted for performing inference using a trained model;

FIG. 14 is a flowchart illustrating operations in a method for preemptive page fault handling in a graphics processing apparatus according to an embodiment;

FIG. 15 is a flowchart illustrating operations in a method for preemptive page fault handling in a graphics processing apparatus according to an embodiment;

FIG. 16 is a schematic block diagram of a processing environment suitable for implementing preemptive page fault handling according to an embodiment;

fig. 17 is a block diagram of a processing system according to an embodiment;

FIG. 18 is a block diagram of a processor according to an embodiment;

FIG. 19 is a block diagram of a graphics processor according to an embodiment;

FIG. 20 is a block diagram of a graphics processing engine of a graphics processor, according to some embodiments;

FIG. 21 is a block diagram of hardware logic of a graphics processor core according to some embodiments described herein;

22A-22B illustrate thread execution logic including an array of processing elements employed in a graphics processor core in accordance with embodiments described herein;

FIG. 23 is a block diagram illustrating a graphics processor instruction format, according to some embodiments;

FIG. 24 is a block diagram of a graphics processor, according to another embodiment;

25A-25B illustrate graphics processor command formats and command sequences, according to some embodiments;

FIG. 26 illustrates an exemplary graphics software architecture for a data processing system according to some embodiments;

fig. 27A is a block diagram illustrating an IP core development system according to an embodiment;

fig. 27B shows a cross-sectional side view of an integrated circuit package assembly according to some embodiments described herein;

FIG. 28 is a block diagram illustrating an exemplary system on a chip integrated circuit according to an embodiment; and

29A-29B are block diagrams illustrating exemplary graphics processors for use within a SoC according to embodiments described herein.

Detailed Description

In some embodiments, a Graphics Processing Unit (GPU) is communicatively coupled to a host/processor core to accelerate graphics operations, machine learning operations, pattern (pattern) analysis operations, and various general purpose GPU (gpgpu) functions. The GPU may be communicatively coupled to the host processor/core via a bus or another interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core through an internal processor bus/interconnect (i.e., internal to the package or chip). Regardless of the manner in which the GPU is connected, the processor core may allocate work to the GPU in the form of a sequence of commands/instructions contained in a work descriptor. The GPU then uses dedicated circuitry/logic for efficient processing of these commands/instructions.

In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the details of the embodiments of the present invention.

Overview of the System

FIG. 1 is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101, the processing subsystem 101 having one or more processors 102 and a system memory 104, the one or more processors 102 and the system memory 104 communicating via an interconnect path that may include a memory hub (hub) 105. The memory hub 105 may be a separate component within a chipset component or may be integrated within the one or more processors 102. The memory hub 105 is coupled with the I/O subsystem 111 via a communication link 106. The I/O subsystem 111 includes an I/O hub 107, which I/O hub 107 may enable the computing system 100 to receive input from one or more input devices 108. Additionally, the I/O hub 107 may enable a display controller, which may be included in the one or more processors 102, to provide output to one or more display devices 110A. In one embodiment, the one or more display devices 110A coupled to I/O hub 107 may include local, internal, or embedded display devices.

In one embodiment, the processing subsystem 101 includes one or more parallel processors 112, the parallel processors 112 coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 may be one of any number of standards-based communication link technologies or protocols (such as, but not limited to, PCI express), or may be a vendor-specific communication interface or communication fabric. In one embodiment, the one or more parallel processors 112 form a computationally intensive parallel or vector processing system, which may include a large number of processing cores and/or processing clusters (such as integrated many-core (MIC) processors). In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of the one or more display devices 110A coupled via the I/O hub 107. The one or more parallel processors 112 may also include a display controller and display interface (not shown) to enable direct connection with one or more display devices 110B.

Within I/O subsystem 111, system memory unit 114 may be connected to I/O hub 107 to provide a storage mechanism for computing system 100. The I/O switch 116 may be used to provide an interface mechanism to enable connection between the I/O hub 107 and other components, such as a network adapter 118 and/or a wireless network adapter 119, which may be integrated into a platform, as well as various other devices that may be added via one or more add-in devices 120. The network adapter 118 may be an ethernet adapter or another wired network adapter. The wireless network adapter 119 may include one or more of the following: Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network device that includes one or more wireless radios.

Computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like, which may also be connected to I/O hub 107. The communication paths interconnecting the various components in fig. 1 may be implemented using any suitable protocol, such as a PCI (peripheral component interconnect) based protocol (e.g., PCI express) or any other bus or point-to-point communication interface and/or protocol, such as an NV-Link high speed interconnect, or interconnect protocol known in the art.

In one embodiment, the one or more parallel processors 112 incorporate circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a Graphics Processing Unit (GPU). In another embodiment, the one or more parallel processors 112 incorporate circuitry optimized for general purpose processing while maintaining the underlying computing architecture described in more detail herein. In yet another embodiment, components of computing system 100 may be integrated together with one or more other system elements on a single integrated circuit. For example, the one or more parallel processors 112, memory hub 105, processor(s) 102, and I/O hub 107 may be integrated into a system on a chip (SoC) integrated circuit. Alternatively, components of computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of computing system 100 may be integrated into a multi-chip module (MCM) that may be interconnected into a modular computing system along with other multi-chip modules.

It will be appreciated that the computing system 100 shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processor(s) 102, and the number of parallel processor(s) 112, may be modified as desired. For example, in some embodiments, the system memory 104 is connected to the processor(s) 102 directly rather than through a bridge, while other devices communicate with the system memory 104 and the processor(s) 102 via the memory hub 105. In other alternative topologies, the parallel processor(s) 112 are connected to the I/O hub 107 or directly to one of the one or more processors 102 rather than to the memory hub 105. In other embodiments, the I/O hub 107 and the memory hub 105 may be integrated into a single chip. Some embodiments may include two or more sets of processors 102 attached via multiple sockets, which may be coupled with two or more instances of parallel processor(s) 112.

Some of the specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. Further, some architectures may use different terminology for components similar to those shown in fig. 1. For example, in some architectures memory hub 105 may be referred to as a north bridge, while I/O hub 107 may be referred to as a south bridge.

FIG. 2A illustrates a parallel processor 200 according to an embodiment. Various components of parallel processor 200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an Application Specific Integrated Circuit (ASIC), or a Field Programmable Gate Array (FPGA). According to an embodiment, the parallel processor 200 shown is a variation of one or more of the parallel processors 112 shown in FIG. 1.

In one embodiment, parallel processor 200 includes parallel processing unit 202. The parallel processing unit includes an I/O unit 204, the I/O unit 204 enabling communication with other devices, including other instances of the parallel processing unit 202. The I/O unit 204 may be directly connected to other devices. In one embodiment, the I/O unit 204 interfaces with other devices via the use of a hub or switch interface, such as the memory hub 105. The connection between the memory hub 105 and the I/O unit 204 forms a communication link 113. Within parallel processing unit 202, I/O unit 204 is connected to host interface 206 and memory crossbar 216, where host interface 206 receives commands for performing processing operations and memory crossbar 216 receives commands for performing memory operations.

When the host interface 206 receives the command buffers via the I/O unit 204, the host interface 206 may direct the work operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled to a scheduler 210, the scheduler 210 configured to distribute commands or other work items to a processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is properly configured and in a valid state before tasks are distributed to the processing clusters of processing cluster array 212. In one embodiment, scheduler 210 is implemented via firmware logic executing on a microcontroller. The microcontroller-implemented scheduler 210 may be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, enabling context switching and fast preemption (rapid preemption) of threads executing on the processing array 212. In one embodiment, the host software may verify that a workload is scheduled on the processing array 212 via one of a plurality of graphics processing doorbells (doorbell). The workload may then be automatically distributed across processing array 212 by scheduler 210 logic within the scheduler microcontroller.

Processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each cluster 214A-214N of processing cluster array 212 may execute a large number of concurrent threads. Scheduler 210 may assign work to clusters 214A-214N of processing cluster array 212 using various scheduling and/or work distribution algorithms, which may vary depending on the workload generated for each type of program or computation. Scheduling may be handled dynamically by scheduler 210 or may be assisted in part by compiler logic during compilation of program logic configured for execution by processing cluster array 212. In one embodiment, different clusters 214A-214N of processing cluster array 212 may be allocated for processing different types of programs, or for performing different types of computations.

Processing cluster array 212 may be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general purpose parallel computing operations. For example, the processing cluster array 212 may include logic to perform processing tasks including filtering video and/or audio data, performing modeling operations (including physical operations), and performing data transformations.

In one embodiment, processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments in which parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic to support the performance of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. Additionally, processing cluster array 212 may be configured to execute graphics processing-related shader (shader) programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may transfer data from system memory for processing via I/O unit 204. During processing, the transferred data may be stored to an on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 may be configured to divide the processing workload into approximately equal sized tasks to better enable distribution of graphics processing operations to the multiple clusters 214A-214N of the processing cluster array 212. In some embodiments, the partial processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometric shading, and a third portion may be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data generated by one or more of the clusters 214A-214N may be stored in a buffer to allow the intermediate data to be transferred between the clusters 214A-214N for further processing.

During operation, processing cluster array 212 may receive processing tasks to be executed via scheduler 210, which receives commands defining the processing tasks from front end 208. For graphics processing operations, a processing task may include command and state parameters that define how data is to be processed (e.g., what program is to be executed) and an index of the data to be processed, e.g., surface (patch) data, primitive data (critical data), vertex data, and/or pixel data. Scheduler 210 may be configured to extract the index corresponding to the task or may receive the index from front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to a valid state prior to initiating a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.).

Each of the one or more instances of parallel processing unit 202 may be coupled with parallel processor memory 222. The parallel processor memory 222 may be accessed via a memory crossbar 216, and the memory crossbar 216 may receive memory requests from the processing cluster array 212 and the I/O unit 204. Memory crossbar 216 may access parallel processor memory 222 via memory interface 218. Memory interface 218 may include a plurality of partition units (e.g., partition unit 220A, partition unit 220B, up to partition unit 220N), which may each be coupled to a portion (e.g., memory unit) of parallel processor memory 222. In one implementation, the number of partition units 220A-220N is configured to equal the number of memory units, such that a first partition unit 220A has a corresponding first memory unit 224A, a second partition unit 220B has a corresponding memory unit 224B, and an Nth partition unit 220N has a corresponding Nth memory unit 224N. In other embodiments, the number of partition units 220A-220N may not equal the number of memory devices.

In various embodiments, memory units 224A-224N may comprise various types of memory devices, including Dynamic Random Access Memory (DRAM) or graphics random access memory, such as Synchronous Graphics Random Access Memory (SGRAM), including Graphics Double Data Rate (GDDR) memory. In one embodiment, memory units 224A-224N may also comprise 3D stacked memory, including but not limited to High Bandwidth Memory (HBM). Those skilled in the art will recognize that the particular implementation of memory cells 224A-224N may vary and may be selected from one of a variety of conventional designs. Render targets, such as frame buffers or texture maps (texture maps), may be stored across the memory units 224A-224N, allowing the partition units 220A-220N to write portions of each render target in parallel to efficiently use the available bandwidth of the parallel processor memory 222. In some embodiments, local instances of the parallel processor memory 222 may be eliminated to facilitate a unified memory design that utilizes system memory along with local cache memory.

In one embodiment, any of the clusters 214A-214N of the processing cluster array 212 may process data to be written to any of the memory units 224A-224N within the parallel processor memory 222. The memory crossbar 216 may be configured to transfer the output of each cluster 214A-214N to any partition unit 220A-220N or another cluster 214A-214N, which may perform additional processing operations on the output. Each cluster 214A-214N may communicate with a memory interface 218 through a memory crossbar 216 to read from or write to various external memory devices. In one embodiment, memory crossbar 216 has a connection to memory interface 218 to communicate with I/O unit 204 and a connection to a local instance of parallel processor memory 222, thereby enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory not local to parallel processing unit 202. In one embodiment, the memory crossbar 216 may use virtual channels to separate traffic flows between the clusters 214A-214N and the partition units 220A-220N.

Although a single instance of parallel processing unit 202 is shown within parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of parallel processing unit 202 may be configured to: even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and/or other configuration differences. For example, in one embodiment, some instances of parallel processing unit 202 may include a higher precision floating point unit relative to other instances. A system incorporating one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in a variety of configurations and form factors (form factors), including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and/or embedded systems.

Fig. 2B is a block diagram of a partition unit 220 according to an embodiment. In one embodiment, partition unit 220 is an example of one of partition units 220A-220N of FIG. 2A. As shown, partition unit 220 includes L2 cache 221, frame buffer interface 225, and ROP 226 (raster operations unit). L2 cache 221 is a read/write cache configured to perform load and store operations received from memory crossbar 216 and ROP 226. Read miss (read miss) and urgent writeback requests are output by L2 cache 221 to frame buffer interface 225 for processing. Updates may also be sent to the frame buffer for processing via frame buffer interface 225. In one embodiment, frame buffer interface 225 interfaces with one of the memory units in parallel processor memory, such as memory units 224A-224N of FIG. 2A (e.g., within parallel processor memory 222).

In graphics applications, ROP 226 is a processing unit that performs raster operations such as stencil printing (tencel), z-testing, blending, and the like. ROP 226 then outputs the processed graphics data stored in graphics memory. In some embodiments, ROP 226 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. The compression logic may be lossless compression logic that utilizes one or more of a plurality of compression algorithms. The type of compression performed by ROP 226 may vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta color compression is performed on the depth and color data on a tile-by-tile basis.

In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A-214N of FIG. 2A) instead of partition unit 220. In such embodiments, read and write requests for pixel data, rather than pixel fragment data, are communicated through memory crossbar 216. The processed graphics data may be displayed on a display device (e.g., one or more display devices 110 of fig. 1), routed for further processing by processor(s) 102, or routed for further processing by one of the processing entities within parallel processor 200 of fig. 2A.

FIG. 2C is a block diagram of processing cluster 214 within a parallel processing unit, according to an embodiment. In one embodiment, a processing cluster is an instance of one of processing clusters 214A-214N of FIG. 2A. Processing cluster 214 may be configured to execute a number of threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In some embodiments, Single Instruction Multiple Data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single-instruction, multi-threading (SIMT) techniques are used to support parallel execution of a large number of generally simultaneous threads using a common instruction unit configured to issue instructions to a set of processing engines within each of the processing clusters. Unlike the SIMD execution regime (in which all processing engines typically execute the same instructions), SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will appreciate that the SIMD processing regime represents a functional subset of the SIMT processing regime.

The operation of the processing clusters 214 may be controlled via a pipeline manager 232 that distributes processing tasks to SIMT parallel processors. Pipeline manager 232 receives instructions from scheduler 210 of FIG. 2A and manages the execution of those instructions via graphics multiprocessor 234 and/or texture unit 236. The graphics multiprocessor 234 shown is an illustrative example of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures may be included within processing cluster 214. One or more instances of graphics multiprocessor 234 may be included within processing cluster 214. The graphics multiprocessor 234 may process data, and the data crossbar 240 may be used to distribute the processed data to one of a plurality of possible destinations (including other shader units). Pipeline manager 232 may facilitate distributing processed data by specifying destinations for the processed data to be distributed via data crossbar 240.

Each graphics multiprocessor 234 within processing cluster 214 may include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). The function execution logic can be configured in a pipelined manner in which a new instruction can be issued before a previous instruction completes. The function execution logic supports various operations including integer and floating point arithmetic, compare operations, Boolean operations, bit shifting, and computation of various algebraic functions. In one embodiment, different operations may be performed by the same functional unit hardware, and any combination of functional units may be present.

The instructions delivered to processing cluster 214 constitute a thread. A set of threads executing across a set of parallel processing engines is a thread group. The thread group executes the same program on different input data. Each thread within the thread group may be assigned to a different processing engine within graphics multiprocessor 234. The thread group may include fewer threads than the number of processing engines within graphics multiprocessor 234. When the thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycles in which the thread group is being processed. The thread group may also include a greater number of threads than the number of processing engines within graphics multiprocessor 234. When the thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing may be performed by successive clock cycles. In one embodiment, multiple thread groups may be concurrently executing on graphics multiprocessor 234.

In one embodiment, graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, graphics multiprocessor 234 may relinquish internal caching and use cache memory within processing cluster 214 (e.g., L1 cache 248). Each graphics multiprocessor 234 also has access to the L2 cache within a partition unit (e.g., partition units 220A-220N of FIG. 2A) that may be used to transfer data between threads and that is shared among all processing clusters 214. The graphics multiprocessor 234 may also have access to off-chip global memory, which may include one or more of local parallel processor memory and/or system memory. Any memory external to parallel processing unit 202 may be used as global memory. Embodiments (where processing cluster 214 includes multiple instances of graphics multiprocessor 234) may share common instructions and data, which may be stored in L1 cache 248.

Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses into physical addresses. In other embodiments, one or more instances of MMU 245 may reside within memory interface 218 of FIG. 2A. MMU 245 includes: a set of Page Table Entries (PTEs) for mapping virtual addresses to physical addresses of a tile; and optionally a cache line index. MMU 245 may comprise an address Translation Lookaside Buffer (TLB) or cache that may reside within graphics multiprocessor 234 or L1 cache or processing cluster 214. The physical addresses are processed to distribute surface data access locality, allowing efficient request interleaving among partition units. The cache line index may be used to determine whether a request for a cache line is a hit or a miss.

In graphics and computing applications, processing cluster 214 may be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within graphics multiprocessor 234, and is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. Each graphics multiprocessor 234 outputs the processed tasks to data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in L2 cache, local parallel processor memory, or system memory via memory crossbar 216. The preROP 242 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 234, direct data to ROP units, which may be located with partition units (e.g., partition units 220A-220N of FIG. 2A) as described herein. The preROP 242 unit may perform optimizations for color mixing, organize pixel color data, and perform address translation.

It will be appreciated that the core architecture described herein is illustrative and that variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, preROP 242, etc.) may be included within processing cluster 214. Further, although only one processing cluster 214 is shown, a parallel processing unit as described herein may include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, and the like.

FIG. 2D illustrates a graphics multiprocessor 234 according to one embodiment. In such embodiments, graphics multiprocessor 234 is coupled with pipeline manager 232 of processing cluster 214. Graphics multiprocessor 234 has an execution pipeline including, but not limited to: instruction cache 252, instruction unit 254, address mapping unit 256, register file (file) 258, one or more General Purpose Graphics Processing Unit (GPGPU) cores 262, and one or more load/store units 266. GPGPU core 262 and load/store unit 266 are coupled with cache memory 272 and shared memory 270 via memory and cache interconnect 268. In one embodiment, the graphics multiprocessor 234 additionally includes a tensor and/or ray tracing core 263 that includes hardware logic to accelerate matrix and/or ray tracing operations.

In one embodiment, instruction cache 252 receives a stream of instructions to be executed from pipeline manager 232. The instructions are cached in instruction cache 252 and dispatched for execution by instruction unit 254. Instruction unit 254 may dispatch instructions as a group of threads (e.g., a bundle of threads (warp)), where each thread of the group of threads is assigned to a different execution unit within GPGPU core 262. An instruction may access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 may be used to translate addresses in the unified address space into different memory addresses that may be accessed by the load/store unit 266.

Register file 258 provides a set of registers for the functional units of graphics multiprocessor 234. Register file 258 provides temporary storage for operands of the datapath connected to the functional units of graphics multiprocessor 234 (e.g., GPGPU core 262, load/store unit 266). In one embodiment, register file 258 is divided among each of the functional units such that each functional unit is assigned a dedicated portion of register file 258. In one embodiment, the register file 258 is divided among the different thread bundles executed by the graphics multiprocessor 234.

GPGPU cores 262 may each include a Floating Point Unit (FPU) and/or an integer Arithmetic Logic Unit (ALU) that are used to execute instructions of graphics multiprocessor 234. Depending on the embodiment, GPGPU core 262 may be architecturally similar, or may be architecturally different. For example and in one embodiment, a first portion of the GPGPU core 262 includes single precision FPUs and integer ALUs, while a second portion of the GPGPU core includes double precision FPUs. In one embodiment, the FPU may implement the IEEE 754-. Graphics multiprocessor 234 may additionally include one or more fixed-function or special-function units to perform specific functions (such as copying rectangles or pixel blending operations). In one embodiment, one or more of the GPGPU cores may also include fixed or special function logic.

In one embodiment, GPGPU core 262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, GPGPU core 262 may physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. SIMD instructions for a GPGPU core may be generated by a shader compiler at compile time, or may be generated automatically when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. Multiple threads of a program configured for the SIMT execution model may be executed via a single SIMD instruction. For example and in one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logic unit.

Memory and cache interconnect 268 is an interconnection network that connects each of the functional units of graphics multiprocessor 234 to register file 258 and to shared memory 270. In one embodiment, memory and cache interconnect 268 is a crossbar interconnect that allows load/store unit 266 to implement load and store operations between shared memory 270 and register file 258. The register file 258 may operate at the same frequency as the GPGPU core 262, thus data transfers between the GPGPU core 262 and the register file 258 are very low latency. Shared memory 270 may be used to enable communication between threads executing on functional units within graphics multiprocessor 234. Cache memory 272 may function as, for example, a data cache to cache texture data passed between functional units and texture units 236. Shared memory 270 may also be used as a cache for program management. Threads executing on GPGPU core 262 may programmatically store data in shared memory in addition to the automatically cached data stored in cache memory 272.

3A-3C illustrate additional graphics multiprocessors according to embodiments. Fig. 3A-3B illustrate graphics multiprocessors 325, 350, which are variations of graphics multiprocessor 234 of fig. 2C. FIG. 3C illustrates a Graphics Processing Unit (GPU) 380 that includes a dedicated set of graphics processing resources arranged into multi-core groups 365A-365N. The illustrated graphics multiprocessors 325, 350 and multi-core groups 365A-365N may be Streaming Multiprocessors (SMs) capable of executing a large number of threads of execution simultaneously.

FIG. 3A illustrates a graphics multiprocessor 325, according to an additional embodiment. Graphics multiprocessor 325 includes a number of additional instances of execution resource units related to graphics multiprocessor 234 of FIG. 2D. For example, graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and texture unit(s) 344A-344B. Graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A-336B, tensor cores 337A-337B, ray trace cores 338A-338B) and multiple sets of load/store units 340A-340B. In one embodiment, the execution resource units have a common instruction cache 330, texture and/or data cache memory 342, and a shared memory 346.

The various components may communicate via an interconnect fabric 327. In one embodiment, the interconnect fabric 327 includes one or more crossbar switches (crossbar switches) to enable communication between the various components of the graphics multiprocessor 325. In one embodiment, interconnect fabric 327 is a separate high-speed network fabric layer on which each component of graphics multiprocessor 325 is stacked. Components of graphics multiprocessor 325 communicate with remote components via interconnect fabric 327. For example, GPGPU cores 336A-336B, 337A-337B, and 338A-338B may each communicate with shared memory 346 via interconnect fabric 327. The interconnect fabric 327 may arbitrate communication within the graphics multiprocessor 325 to ensure fair bandwidth allocation among the components.

FIG. 3B illustrates a graphics multiprocessor 350, according to an additional embodiment. The graphics processor includes multiple sets of execution resources 356A-356D, where each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load store units, as shown in FIG. 2D and FIG. 3A. Execution resources 356A-356D may work in concert with texture unit(s) 360A-360D for texture operations, while sharing instruction cache 354 and shared memory 353. In one embodiment, execution resources 356A-356D may share instruction cache 354 and shared memory 353, as well as multiple instances of texture and/or data cache memory 358A-358B. Various components may communicate via an interconnect fabric 352 similar to the interconnect fabric 327 of fig. 3A.

Those skilled in the art will appreciate that the architectures depicted in FIGS. 1, 2A-2D, and 3A-3B are illustrative and not limiting with respect to the scope of the present embodiments. Thus, the techniques described herein may be implemented on any properly configured processing unit, including but not limited to one or more mobile application processors, one or more desktop or server Central Processing Units (CPUs), including multi-core CPUs, one or more parallel processing units, such as parallel processing unit 202 of fig. 2A, and one or more graphics processors or application-specific processing units, without departing from the scope of the embodiments described herein.

In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host/processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various General Purpose Gpu (GPGPU) functions. The GPU may be communicatively coupled to the host processor/core by a bus or other interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core through an internal processor bus/interconnect (i.e., internal to the package or chip). Regardless of the manner in which the GPU is connected, the processor core may allocate work to the GPU in the form of a sequence of commands/instructions contained in a work descriptor. The GPU then uses specialized circuitry/logic for efficiently processing these commands/instructions.

FIG. 3C illustrates a Graphics Processing Unit (GPU) 380, the graphics processing unit 380 containing a specialized set of graphics processing resources arranged into multi-core groups 365A-N. While only the details of a single multi-core group 365A are provided, it will be appreciated that other multi-core groups 365B-365N may be equipped with the same or similar sets of graphics processing resources.

As shown, the multi-core group 365A may include a set of graphics cores 370, a set of tensor cores 371, and a set of ray tracing cores 372. Scheduler/dispatcher 368 schedules and dispatches graphics threads for execution on the various cores 370, 371, 372. A set of register files 369 store operand values for use by cores 370, 371, 372 when executing a graphics thread. For example, these may include integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and/or floating point data elements), and tile registers for storing tensor/matrix values. In one embodiment, the tile registers are implemented as a combined set of vector registers.

One or more combined level 1 (L1) cache and shared memory units 373 store graphics data, such as texture data, vertex data, pixel data, ray data, bounding volume data, and the like, locally within each multi-core group 365A. One or more texture units 374 may also be used to perform texture operations, such as texture mapping and sampling. The level 2 (L2) cache 375 shared by all or a subset of the multi-core groups 365A-365N stores graphics data and/or instructions for multiple concurrent graphics threads. As shown, L2 cache 375 may be shared across multiple multi-core groups 365A-365N. One or more memory controllers 367 couple GPU 380 to memory 366, where memory 366 may be system memory (e.g., DRAM) and/or dedicated graphics memory (e.g., GDDR6 memory).

Input/output (I/O) circuits 363 couple GPU 380 to one or more I/O devices 362, such as a Digital Signal Processor (DSP), network controller, or user input device. On-chip interconnects may be used to couple I/O devices 362 to GPU 380 and memory 366. One or more I/O memory management units (IOMMU) 364 of I/O circuitry 3195 couples I/O device 362 directly to system memory 366. In one embodiment, the IOMMU 364 manages multiple sets of page tables to map virtual addresses to physical addresses in the system memory 366. In this embodiment, I/O device 362, CPU(s) 361, and GPU(s) 380 may share the same virtual address space.

In one implementation, the IOMMU 364 supports virtualization. In this case, it may manage a first set of page tables to map guest/graphics virtual addresses to guest/graphics physical addresses and a second set of page tables to map guest/graphics physical addresses to system/host physical addresses (e.g., in system memory 366). The base address of each of the first and second sets of page tables may be stored in a control register and swapped out on a context switch (e.g., to provide access to the relevant set of page tables for the new context). Although not shown in FIG. 3C, each of the cores 370, 371, 372 and/or multi-core groups 365A-365N may include a Translation Lookaside Buffer (TLB) for caching guest virtual to guest physical translations, guest physical to host physical translations, and guest virtual to host physical translations.

In one embodiment, CPU 361, GPU 380, and I/O device 362 are integrated on a single semiconductor chip and/or chip package. The illustrated memory 366 may be integrated on the same chip or may be coupled to the memory controller 367 via an off-chip interface. In one implementation, memory 366 includes GDDR6 memory, which shares the same virtual address space with other physical system-level memory, although the underlying principles of the invention are not limited to this particular implementation.

In one embodiment, the tensor core 371 includes multiple execution units specifically designed to perform matrix operations, which are the basic computational operations for performing deep learning operations. For example, simultaneous matrix multiplication operations may be used for neural network training and reasoning. The tensor core 371 may perform matrix processing using a variety of operand precisions, including single precision floating point (e.g., 32 bits), half precision floating point (e.g., 16 bits), integer word (16 bits), byte (8 bits), and nibble (4 bits). In one embodiment, a neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames, to construct a high quality final image.

In a deep learning implementation, the parallel matrix multiplication work may be arranged for execution on the tensor core 371. Training of neural networks in particular requires a large number of matrix dot-product operations. To process the inner product formula of an nxnxnxn matrix multiplication, the tensor core 371 may contain at least N dot product processing elements. Before the start of the matrix multiplication, a complete matrix is loaded into the tile register, and for each of the N cycles, at least one column of the second matrix is loaded. For each cycle, N dot products are processed.

Depending on the particular implementation, matrix elements may be stored with different precisions, including 16-bit words, 8-bit bytes (e.g., INT 8), and 4-bit nibbles (e.g., INT 4). Different precision modes can be specified for the tensor core 371 to ensure that the most efficient precision is used for different workloads (e.g., inference workloads such as can tolerate quantization to bytes and nibbles).

In one embodiment, ray tracing core 372 speeds up ray tracing operations for both real-time ray tracing and non-real-time ray tracing implementations. In particular, ray tracing core 372 includes ray traversal/intersection circuitry to perform ray traversal using a Bounding Volume Hierarchy (BVH) and identify intersections between rays and primitives enclosed within the BVH volume. Ray tracing core 372 may also include circuitry for performing depth testing and sorting (e.g., using a Z buffer or similar arrangement). In one implementation, the ray tracing kernel 372 performs traversal and intersection operations in cooperation with the image denoising techniques described herein, at least a portion of which may be performed on the tensor kernel 371. For example, in one embodiment, tensor core 371 implements a deep learning neural network to perform denoising of frames generated by ray tracing core 372. However, CPU(s) 361, graphics kernel 370, and/or ray tracing kernel 372 may also implement all or part of the denoising and/or depth learning algorithms.

Additionally, as described above, a distributed approach may be employed to denoise, where the GPU 380 is located in a computing device that is coupled to other computing devices over a network or high-speed interconnect. In this embodiment, interconnected computing devices share neural network learning/training data to increase the speed at which the overall system learns to perform denoising for different types of image frames and/or different graphics applications.

In one embodiment, ray tracing core 372 handles all BVH traversals and ray-primitive intersections, avoiding overloading the graphics core 370 with thousands of instructions per ray. In one embodiment, each ray tracing core 372 includes a first set of dedicated circuitry for performing bounding box tests (e.g., for traversal operations) and a second set of dedicated circuitry for performing ray-triangle intersection tests (e.g., traversed intersected rays). Thus, in one embodiment, multi-core group 365A may simply initiate ray detection and ray tracing core 372 independently perform ray traversals and intersections and return hit data (e.g., hit, no hit, multiple hits, etc.) to the thread context. The other cores 370, 371 are freed to perform other graphics or computational work, while the ray tracing core 372 performs traversal and intersection operations.

In one embodiment, each ray tracing core 372 includes a traversal unit to perform BVH test operations and an intersection unit to perform ray primitive intersection tests. The intersection unit generates a "hit", "miss", or "multiple hit" response and provides it to the appropriate thread. During traversal and intersection operations, execution resources of other cores (e.g., graphics core 370 and tensor core 371) are freed to perform other forms of graphics work.

In one particular embodiment described below, a hybrid rasterization/ray tracing approach is used in which work is distributed between a graphics core 370 and a ray tracing core 372.

In one embodiment, the ray tracing core 372 (and/or other cores 370, 371) includes hardware support for a ray tracing instruction set, such as microsoft's DirectX ray tracing (DXR), which includes a DispatchRays command along with ray generation, recent hits, any hits, and miss shaders, which enable assigning a unique set of shaders and textures to each object. Another ray tracing platform that ray tracing core 372, graph core 370, and tensor core 371 may support is Vulkan 1.1.85. It should be noted, however, that the underlying principles of the invention are not limited to any particular ray tracing ISA.

In general, the various cores 372, 371, 370 may support a ray tracing instruction set that includes instructions/functions for ray generation, recent hits, any hits, ray-primitive intersections, per-primitive and hierarchical bounding box constructions, misses, accesses, and exceptions. More specifically, one embodiment includes ray tracing instructions to perform the following functions:

ray generationRay generation instructions may be executed for each pixel, sample, or other user-defined job assignment.

Recent hitThe nearest hit instruction may be executed to locate the nearest intersection of the ray and the primitive within the scene.

Any hitAny hit instruction identifies multiple intersections between the ray and the primitive within the scene, so as to potentially identify a new nearest intersection point.

Intersect each other-the intersection instruction performs a ray-primitive intersection test and outputs the result.

Per primitive bounding box constructionThe instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other accelerated data structure).

MissIndicating that the ray missed all the geometries within the scene or a specified region of the scene.

AccessIndicating the sub-volume that the ray will traverse.

Abnormality (S)Including various types of exception handlers (e.g., invoked for various error conditions).

Techniques for GPU and host processor interconnection

FIG. 4A illustrates an exemplary architecture in which multiple GPUs 410 and 413 are communicatively coupled to multiple multicore processors 405 and 406 via high-speed links 440A-440D (e.g., buses, point-to-point interconnects, etc.). In one embodiment, depending on the implementation, high speed links 440A-440D support communication throughputs of 4GB/s, 30GB/s, 80GB/s or higher. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the invention are not limited to any particular communication protocol or throughput.

Additionally, in one embodiment, two or more of GPUs 410 and 413 are interconnected by high speed links 442A-442B, which may be implemented using the same or different protocols/links than those used for high speed links 440A-440D. Similarly, two or more of the multi-core processors 405-406 may be connected by a high-speed link 443, which may be a Symmetric Multiprocessor (SMP) bus operating at 20GB/s, 30GB/s, 120GB/s, or higher. Alternatively, all communications between the various system components shown in fig. 4A may be implemented using the same protocol/link (e.g., over a common interconnect fabric). As mentioned, however, the underlying principles of the invention are not limited to any particular type of interconnect technology.

In one embodiment, each of the multicore processors 405 and 406 is communicatively coupled to the processor memories 401 and 402 via the memory interconnects 430A-430B, respectively, and each of the GPUs 410 and 413 is communicatively coupled to the GPU memory 420 and 423 via the GPU memory interconnects 450A-450D, respectively. Memory interconnects 430A-430B and 450A-450D may utilize the same or different memory access technologies. By way of example and not limitation, processor memory 401 and GPU memory 420 and 423 may be volatile memories such as Dynamic Random Access Memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR 6), or High Bandwidth Memory (HBM), and/or may be non-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2 LM) hierarchy).

As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to the specific memories 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed among all of the various physical memories. For example, processor memories 401-402 may each comprise 64GB of system memory address space, and GPU memories 420-423 may each comprise 32GB of system memory address space (yielding a total of 256GB of addressable memory in this example).

FIG. 4B shows additional details of the interconnection between the multi-core processor 407 and the graphics acceleration module 446, according to one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on line cards coupled to the processor 407 via a high speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

The illustrated processor 407 includes multiple cores 460A-460D each having a translation look-aside buffer 461A-461D and one or more caches 462A-462D. The core may include various other components for executing instructions and processing data (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.), which are not shown to avoid obscuring the underlying principles of the invention. Caches 462A-462D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 456 may be included in the cache hierarchy and shared by multiple sets of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores each having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In the present embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and the graphics accelerator integration module 446 are coupled to a system memory 441, which system memory 441 may include processor memory 401 and 402.

Coherency is maintained for data and instructions stored in the various caches 462A-462D, 456 and system memory 441 via inter-core communication through a coherency bus 464. For example, each cache may have cache coherency logic/circuitry associated therewith to communicate over the coherency bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snoop protocol is implemented over coherency bus 464 to snoop cache accesses. Cache snooping/coherency techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the underlying principles of the invention.

In one embodiment, the proxy circuitry 425 communicatively couples the graphics acceleration module 446 to the coherency bus 464, allowing the graphics acceleration module 446 to join a cache coherency protocol as a peer of a core. In particular, interface 435 provides connectivity to the proxy circuit 425 through a high-speed link 440 (e.g., PCIe bus, NVLink, etc.), and interface 437 connects the graphics acceleration module 446 to the high-speed link 440.

In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines 431, 432, N of the graphics acceleration module 446. Graphics processing engines 431, 432, N may each comprise a separate Graphics Processing Unit (GPU). Alternatively, graphics processing engines 431, 432, N may include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders/decoders), samplers, and bit block transfer engines. In other words, the graphics acceleration module may be a GPU with multiple graphics processing engines 431- > 432, N, or the graphics processing engines 431- > 432, N may be individual GPUs integrated on a common package, line card, or chip.

In one embodiment, the accelerator integrated circuit 436 includes a Memory Management Unit (MMU) 439 for performing various memory management functions, such as virtual-to-physical memory translation (also referred to as effective-to-real memory translation) and memory access protocols for accessing the system memory 441. The MMU 439 can also include a Translation Lookaside Buffer (TLB) (not shown) for caching virtual/valid-to-physical/real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431 and 432, N. In one embodiment, the data stored in cache 438 and graphics memory 433 and 434, M is coherent with core caches 462A-462D, 456 and system memory 411. As mentioned, this may be accomplished via proxy circuitry 425, which proxy circuitry 425 participates in cache coherency mechanisms on behalf of cache 438 and memories 433 and 434, M (e.g., sending updates to cache 438 (in connection with modification/access of cache lines on processor caches 462A-462D, 456), and receiving updates from cache 438).

A set of registers 445 stores context data for threads executed by the graphics processing engines 431-432, N, and a context management circuit 448 manages thread contexts. For example, the context management circuitry 448 may perform save and restore operations during a context switch to save and restore the context of various threads (e.g., where a first thread is saved and a second thread is stored such that the second thread may be executed by the graphics processing engine). For example, at context switch, the context management circuitry 448 may store the current register value to an assigned region in memory (e.g., identified by a context pointer). It may then restore the register values upon returning to the context. In one embodiment, interrupt management circuit 447 receives and processes interrupts received from system devices.

In one implementation, virtual/effective addresses from graphics processing engine 431 are translated to real/physical addresses in system memory 411 by MMU 439. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and/or other accelerator devices. The graphics accelerator module 446 may be dedicated to a single application executing on the processor 407 or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of graphics processing engine 431- > 432, N are shared with multiple applications or Virtual Machines (VMs). The resources may be subdivided into "slices" that are assigned to different VMs and/or applications based on processing requirements and priorities associated with the VMs and/or applications.

Thus, the accelerator integrated circuit acts as a bridge to the system for the graphics acceleration module 446 and provides address translation and system memory caching services. Additionally, accelerator integrated circuit 436 may provide a virtualization facility for a host processor to manage virtualization of graphics processing engines, interrupts, and memory management.

Because the hardware resources of graphics processing engine 431-432, N are explicitly mapped to the real address space seen by host processor 407, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, N, such that they appear to the system as independent units.

As mentioned, in the illustrated embodiment, one or more graphics memories 433- < - > 434, M are coupled to each of the graphics processing engines 431- < - > 432, N, respectively. Graphics memories 433-. Graphics memories 433-434, M may be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR 6), or HBM, and/or may be non-volatile memories such as 3D XPoint or Nano-Ram.

In one embodiment, to reduce data traffic on high speed link 440, a biasing technique is used to ensure that the data stored in graphics memory 433-. Similarly, the biasing mechanism attempts to save the data required by the core (and preferably not graphics processing engine 431-432, N) within system memory 411 and the core's caches 462A-462D, 456.

Fig. 4C shows another embodiment in which accelerator integrated circuit 436 is integrated within processor 407. In the present embodiment, graphics processing engines 431-432, N communicate directly with accelerator integrated circuit 436 through high speed link 440 via interface 437 and interface 435 (which again may utilize any form of bus or interface protocol). The accelerator integrated circuit 436 may perform the same operations as those described for fig. 4B, but potentially at higher throughput in view of its close proximity to the coherency bus 464 and caches 462A-462D, 456.

One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). Which may include a programming model controlled by the accelerator integrated circuit 436 and a programming model controlled by the graphics acceleration module 446.

In one embodiment of the dedicated process model, the graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. A single application can aggregate (channel) other application requests to graphics engine 431- > 432, N, providing virtualization within the VM/partition.

In the dedicated process programming model, the graphics processing engine 431-432, N may be shared by multiple VM/application partitions. The shared model requires a hypervisor to virtualize the graphics processing engines 431- > 432, N to allow access by each operating system. For a single partition system without a hypervisor, graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system may virtualize the graphics processing engine 431- > 432, N to provide access to each process or application.

For the shared programming model, the graphics acceleration module 446 or the individual graphics processing engines 431- > 432, N use a process handle (process handle) to select a process element (process element). In one embodiment, the process elements are stored in system memory 441 and are addressable using the effective-to-real address translation techniques described herein. The process handle may be an implementation-specific value that is provided to the host process when its context (that is, invoking the system software to add a process element to the process element linked list) is registered with the graphics processing engine 431-432, N. The lower 16 bits of the process handle may be the offset of the process element within the linked list of process elements.

Fig. 4D shows an exemplary accelerator integration slice 490. As used herein, a "slice" includes a designated portion of the processing resources of accelerator integrated circuit 436. An application effective address space 482 within system memory 441 stores a process element 483. In one embodiment, the process element 483 is stored in response to a GPU call (invocation) 481 from an application 480 executing on the processor 407. The process element 483 contains the process state of the corresponding application 480. Work Descriptor (WD) 484 included in process element 483 may be a single job requested by an application or may include a pointer to a job queue. In the latter case, WD 484 is a pointer to a queue of job requests in application's address space 482.

The graphics acceleration module 446 and/or the individual graphics processing engines 431-432, N may be shared by all or a subset of the processes in the system. Embodiments of the present invention include infrastructure for setting a process state and sending WD 484 to graphics acceleration module 446 to begin a job in a virtualized environment.

In one implementation, the dedicated process programming model is implementation specific. In this model, a single process owns either the graphics acceleration module 446 or the individual graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, at the time the graphics acceleration module 446 is dispatched, the hypervisor initializes the accelerator integrated circuits 436 for the owned partitions and the operating system initializes the accelerator integrated circuits 436 for the owned processes.

In operation, WD fetch unit 491 in accelerator integration slice 490 fetches a next WD 484, which next WD 484 includes an indication of work to be done by one of the graphics processing engines of graphics acceleration module 446. Data from WD 484 may be stored in registers 445 and used by MMU 439, interrupt management circuitry 447, and/or context management circuitry 448 as shown. For example, one embodiment of MMU 439 includes a segment/page walk circuit (walk circuit) for accessing segment/page tables 486 within OS virtual address space 485. The interrupt manager circuit 447 may process interrupt events 492 received from the graphics acceleration module 446. When performing graphics operations, the effective addresses 493 generated by graphics processing engines 431- + 432, N are translated to real addresses by MMU 439.

In one embodiment, the same set of registers 445 is replicated for each graphics processing engine 431- & 432, N and/or graphics acceleration module 446, and the set of registers 445 may be initialized by a hypervisor or operating system. Each of these copied registers may be included in the accelerator integration slice 490. Exemplary registers that may be initialized by the hypervisor are shown in table 1.

TABLE 1 hypervisor initialized registers

1	Slice control register
		2	Process area pointer for Real Address (RA) scheduling
3	Permission mask override register
		4	Interrupt vector table entry offset
5	Interrupt vector table entry restriction
		6	Status register
7	Logical partition ID
		8	Real Address (RA) hypervisor accelerator utilizing record pointers
9	Storage description register

Exemplary registers that may be initialized by the operating system are shown in table 2.

TABLE 2 registers for operating System initialization

1	Process and thread identification
		2	Effective Address (EA) context save/restore pointer
3	Virtual Address (VA) accelerator utilizing record pointers
		4	Virtual Address (VA) storage segment table pointer
5	Authority masking
		6	Work descriptor

In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and/or graphics processing engine 431-. It contains all the information required by the graphics processing engine 431-432, N to complete its work, or it may be a pointer to the memory location of the command queue where the application has set up the work to be completed.

FIG. 4E illustrates additional details for one embodiment of the sharing model. The present embodiment includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496, which hypervisor 496 virtualizes the graphics acceleration module engine for the operating system 495.

The shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time slice sharing and graphics directed sharing.

In this model, hypervisor 496 owns graphics acceleration module 446 and makes its functionality available to all operating systems 495. For graphics acceleration module 446 to support virtualization by hypervisor 496, graphics acceleration module 446 may comply with the following requirements: 1) the application's job requests must be autonomous (that is, no state needs to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The job requests of the application (including any translation faults) are guaranteed to complete within a specified amount of time by the graphics acceleration module 446, or the graphics acceleration module 446 provides the ability to preempt processing of the job. 3) When operating in the directed sharing programming model, graphics acceleration module 446 must ensure fairness between processes.

In one embodiment, for the shared model, the application 480 is required to make operating system 495 system calls with a graphics acceleration module 446 type, a Work Descriptor (WD), an Authority Mask Register (AMR) value, and a context save/restore area pointer (CSRP). Graphics acceleration module 446 types describe targeted acceleration functionality for system calls. The graphics acceleration module 446 type may be a system specific value. WD is formatted specifically for graphics acceleration module 446 and may take the form of: the graphics acceleration module 446 commands, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure for describing work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state to be used for the current process. The values passed to the operating system are similar to the application setting AMR. If the accelerator integrated circuit 436 and graphics acceleration module 446 implementation do not support a User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing AMR in the hypervisor call. Optionally, the hypervisor 496 may apply a current permission mask override register (AMOR) value before placing AMR into the process element 483. In one embodiment, CSRP is one of registers 445 that contains the effective address of a region in the application's address space 482 for use in causing graphics acceleration module 446 to save and restore context state. This pointer is optional if it is not required to save state between jobs or when a job is preempted. The context save/restore area may be fixed (pined) system memory.

Upon receiving the system call, the operating system 495 may verify that the application 480 is registered and has been given the right to use the graphics acceleration module 446. Operating system 495 then calls hypervisor 496 with the information shown in table 3.

TABLE 3-OS to hypervisor Call parameters

1	Work Descriptor (WD)
		2	Permission mask register (AMR) value (potentially masked)
3	Effective Address (EA) context save/restore area pointer (CSRP)
		4	Process ID (PID) and optional Thread ID (TID)
5	Virtual Address (VA) accelerator utilizing a record pointer (AURP)
		6	Virtual address Storing Segment Table Pointer (SSTP)
7	Logic Interruption Service Number (LISN)

Upon receiving the hypervisor call, hypervisor 496 verifies that operating system 495 is registered and has been given authority to use graphics acceleration module 446. Hypervisor 496 then places process element 483 into the linked list of process elements for the corresponding graphics acceleration module 446 type. The process elements may include the information shown in table 4.

Table 4-Process element information

1	Work Descriptor (WD)
		2	Permission mask register (AMR) value (potentially masked)
3	Effective Address (EA) context save/restore area pointer（CSRP）
		4	Process ID (PID) and optional Thread ID (TID)
5	Virtual Address (VA) accelerator utilizing a record pointer (AURP)
		6	Virtual address Storing Segment Table Pointer (SSTP)
7	Logic Interruption Service Number (LISN)
		8	Interrupt vector table derived from hypervisor call parameters
9	Status Register (SR) value
		10	Logical Partition ID (LPID)
11	Real Address (RA) hypervisor accelerator utilizing record pointers
		12	Storage Descriptor Register (SDR)

In one embodiment, the hypervisor initializes the plurality of accelerator integration slices 490 registers 445.

As shown in FIG. 4F, one embodiment of the invention employs unified memory addressable via a common virtual memory address space for accessing physical processor memory 401 and GPU memory 420 and 423. In such an implementation, the operations performed on the GPUs 410 and 413 utilize the same virtual/effective memory address space to access the processor memories 401 and 402 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual/effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. The entire virtual/effective memory space (sometimes referred to as the effective address space) is thus distributed across each of the processor memory 401 and the GPU memory 402 and 423, allowing any processor or GPU to access any physical memory (with virtual addresses mapped to that memory).

In one embodiment, the bias/coherency management circuits 494A-494E within one or more of the MMUs 439A-439E ensure cache coherency between the host processor (e.g., 405) and the caches of the GPUs 410 and 413 and implement a biasing technique that indicates the physical memory in which certain types of data should be stored. Although multiple instances of bias/coherency management circuits 494A-494E are shown in FIG. 4F, the bias/coherency circuits may be implemented within one or more MMUs of host processor 405 and/or within accelerator integrated circuit 436.

One embodiment allows the GPU-attached memory 420 to be accessed and mapped 423 as part of system memory using a Shared Virtual Memory (SVM) technique without suffering from the typical performance drawbacks associated with full system cache coherency. The ability of the GPU attached memory 420-423 to be accessed as system memory without heavy cache coherency overhead provides a beneficial operating environment for GPU offloading. This arrangement allows the host processor 405 software to set operands and access computational results without the overhead of conventional I/O DMA data copying. Such traditional copying involves driver calls, interrupts, and memory mapped I/o (mmio) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access GPU-attached memory 420-423 without cache coherency overhead can be critical to the execution time of the computations being offloaded. With substantial streaming write memory traffic, for example, the cache coherency overhead can significantly reduce the effective write bandwidth seen by the GPU 410 and 413. The efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computations all play a role in determining the effectiveness of GPU offload.

In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table may be used, which may be a page granularity structure (i.e., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU attached memory page. The bias table may be implemented in a stolen (stolen) memory range of one or more GPU-attached memories 420-423 with or without a bias cache (e.g., a frequently/recently used entry for caching the bias table) in GPU 410-413. Alternatively, the entire bias table may be maintained within the GPU.

In one implementation, the bias table entries associated with each access to the GPU attached memory 420 and 423 are accessed prior to actual access to the GPU memory, causing the following operations. First, the local requests from the GPUs 410 and 413 to find their pages in GPU offsets are forwarded directly to the corresponding GPU memories 420 and 423. Local requests from the GPU to find their pages in the host bias are forwarded to the processor 405 (e.g., over a high speed link as discussed above). In one embodiment, a request from the processor 405 to find the requested page in the host processor bias completes the request like a normal memory read. Alternatively, the request for GPU-biased pages may be forwarded to GPU 410 and 413. Then, if the GPU is not currently using the page, the GPU may transition the page to host processor bias.

The bias state of a page may be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or a purely hardware-based mechanism for a limited set of situations.

One mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn calls the device driver of the GPU, which in turn sends a message (or enqueue command descriptor) to the GPU instructing it to change the bias state and perform a cache flush (flushing) operation in the host for some transitions. Cache flush operations are needed for the transition from host processor 405 bias to GPU bias, but not for the reverse transition.

In one embodiment, cache coherency is maintained by temporarily rendering GPU offset pages that are not cacheable by the host processor 405. To access these pages, the processor 405 may request access from the GPU 410, which may or may not grant access immediately (depending on the implementation). Thus, to reduce communication between the host processor 405 and the GPU 410, it is advantageous to ensure that GPU offset pages are those pages that are required by the GPU but not the host processor 405 (and vice versa).

Graphics processing pipeline

FIG. 5 illustrates a graphics processing pipeline 500 according to an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included within a parallel processing subsystem as described herein, such as parallel processor 200 of fig. 2A, which in one embodiment is a variation of parallel processor(s) 112 of fig. 1. Various parallel processing systems may implement graphics processing pipeline 500 via one or more instances of a parallel processing unit as described herein (e.g., parallel processing unit 202 of fig. 2A). For example, a shader unit (e.g., graphics multiprocessor 234 of fig. 2C) may be configured to perform the functions of one or more of vertex processing unit 504, tessellation control processing unit 508, tessellation evaluation processing unit 512, geometry processing unit 516, and fragment/pixel processing unit 524. The functions of data assembler 502, primitive assemblers (506, 514, 518), tessellation unit 510, rasterizer 522, and raster operations unit 526 may also be performed by other processing engines and corresponding partition units (e.g., partition units 220A-220N of FIG. 2A) within a processing cluster (e.g., processing cluster 214 of FIG. 2A). Graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of graphics processing pipeline 500 may be executed by parallel processing logic within a general purpose processor (e.g., a CPU). In one embodiment, one or more portions of graphics processing pipeline 500 may access on-chip memory (e.g., parallel processor memory 222 as in FIG. 2A) via memory interface 528, which memory interface 528 may be an example of memory interface 218 of FIG. 2A.

In one embodiment, data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. Data populator 502 then outputs vertex data, including the vertex attributes, to vertex processing unit 504. Vertex processing unit 504 is a programmable execution unit that executes vertex shader programs, illuminating (lighting) and transforming vertex data as specified by the vertex shader programs. Vertex processing unit 504 reads data stored in cache, local, or system memory for use in processing the vertex data, and vertex processing unit 504 may be programmed to transform the vertex data from an object-based coordinate representation to world space coordinate space or normalized device coordinate space.

A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches (patches), and so forth as supported by various graphics processing Application Programming Interfaces (APIs).

The tessellation control processing unit 508 treats the input vertices as control points for the geometric patches. The control points are transformed from an input representation from the patches (e.g., the basis of the patches) to a representation suitable for use in surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometric patches. The tessellation factor is applied to a single edge and the view-dependent level of detail associated with that edge is quantified. Tessellation unit 510 is configured to receive tessellation factors for edges of a patch and tessellate the patch into a plurality of geometric primitives, such as line, triangle, or quadrilateral primitives, which are passed to tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patches to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

A second instance of primitive assembler 514 receives the vertex attributes from tessellation evaluation processing unit 512 (which reads the stored vertex attributes as needed), and constructs the graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform graphics primitives received from primitive assembler 514 as specified by the geometry shader program. In one embodiment, geometry processing unit 516 is programmed to subdivide a graphics primitive into one or more new graphics primitives and to compute parameters for rasterizing the new graphics primitives.

In some embodiments, geometry processing unit 516 may add or delete elements in the geometry stream. Geometry processing unit 516 outputs parameters and vertices that specify new graphics primitives to primitive assembler 518. Primitive assembler 518 receives the parameters and vertices from geometry processing unit 516 and constructs graphics primitives for processing by viewport scale, sort, and clip unit 520. Geometry processing unit 516 reads data stored in parallel processor memory or system memory for use in processing geometry data. Viewport scale, cull, and clip unit 520 performs clipping, culling, and viewport scaling and outputs processed graphics primitives to rasterizer 522.

Rasterizer 522 may perform depth culling and other depth-based optimizations. Rasterizer 522 also performs scan conversion on the new graphics primitives to generate fragments and outputs those fragments and associated coverage data to fragment/pixel processing unit 524. Fragment/pixel processing unit 524 is a programmable execution unit configured to execute fragment shader programs or pixel shader programs. Fragment/pixel processing unit 524 transforms the fragments or pixels received from rasterizer 522 as specified by a fragment or pixel shader program. For example, the fragment/pixel processing unit 524 may be programmed to perform operations including, but not limited to, texture mapping, shading, blending, texture correction, and perspective correction to generate shaded fragments or pixels that are output to the raster operations unit 526. Fragment/pixel processing unit 524 may read data stored in a parallel processor memory or a system memory for use in processing fragment data. Fragment or pixel shader programs may be configured to color at sample, pixel, tile, or other granularity, depending on the sampling rate configured for the processing unit.

Raster operations unit 526 is a processing unit that performs raster operations including, but not limited to, stencil printing, z-testing, blending, and the like, and outputs pixel data as processed graphics data for storage in graphics memory (e.g., parallel processor memory 222 as in fig. 2A and/or system memory 104 as in fig. 1) for display on the one or more display devices 110 or for further processing by one of parallel processor(s) 112 or processor(s) 102. In some embodiments, raster operations unit 526 is configured to compress z or color data written to memory and decompress z or color data read from memory.

Machine learning overview

The architecture described above can be applied to perform training and reasoning operations using machine learning models. Machine learning has successfully solved a variety of tasks. The computations that occur when training and using machine learning algorithms (e.g., neural networks) are naturally amenable to efficient parallel implementation. Therefore, parallel processors such as general purpose graphics processing units (gpgpgpu) have played an important role in the practical implementation of deep neural networks. Parallel graphics processors with single instruction multi-thread (SIMT) architectures are designed to maximize parallel throughput in the graphics pipeline. In the SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as often as possible to improve processing efficiency. The efficiency provided by parallel machine learning algorithm implementations allows for the use of high capacity networks and enables those networks to be trained on larger data sets.

Machine learning algorithms are algorithms that can learn based on a data set. Embodiments of machine learning algorithms can be designed to model high-level abstractions within a data set. For example, an image recognition algorithm may be used to determine to which of several categories a given input belongs; given an input, a regression algorithm may output a value; and pattern recognition algorithms may be used to generate converted text or perform text-to-speech and/or speech recognition.

An exemplary type of machine learning algorithm is a neural network. There are many types of neural networks; a simple type of neural network is a feed-forward network. The feed-forward network may be implemented as an acyclic graph (acyclic graph) in which nodes are arranged in layers. Typically, a feed-forward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer transforms input received by the input layer into a representation that is useful for generating output in the output layer. Network nodes are fully connected via edges to nodes in adjacent layers, but there are no edges between nodes within each layer. Data received at nodes of the input layer of the feed-forward network is propagated (i.e., "fed forward") to nodes of the output layer via an activation function that computes the state of the nodes of each successive layer in the network based on coefficients ("weights") respectively associated with each of the edges of the connected layers. The output from the neural network algorithm may take various forms depending on the particular model represented by the algorithm being executed.

The training data set is used to train the algorithm before the machine learning algorithm can be used to model a particular problem. Training a neural network involves selecting a network topology, using a set of training data representing the problem being modeled by the network, and adjusting weights until the network model executes with minimal error on all instances of the training data set. For example, during a supervised learning training process for a neural network, the output produced by the network in response to an instance in a set of training data is compared to a "correct" labeled output for that instance, an error signal representing the difference between the output and the labeled output is calculated, and weights associated with the connections are adjusted to minimize the error as it propagates back through the network layers. The network is considered "trained" when the error is minimized for each of the outputs generated from the instances of the training data set.

The accuracy of a machine learning algorithm can be significantly affected by the quality of the data set used to train the algorithm. The training process may be computationally intensive and may require a significant amount of time on a conventional general purpose processor. Thus, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, since the computations performed in adapting the coefficients in the neural network make them very natural to facilitate parallel implementation. In particular, many machine learning algorithms and software applications have been adapted to take advantage of parallel processing hardware within general purpose graphics processing devices.

Fig. 6 is a general diagram of a machine learning software stack 600. The machine learning application 602 may be configured to train a neural network using a training data set or implement machine intelligence using a trained deep neural network. The machine learning application 602 may include training and reasoning functionality for the neural network and/or dedicated software that may be used to train the neural network prior to deployment. The machine learning application 602 may implement any type of machine intelligence including, but not limited to, image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

Hardware acceleration for the machine learning application 602 may be enabled via the machine learning framework 604. The machine learning framework 604 can provide a library of machine learning primitives. Machine learning primitives are the basic operations that machine learning algorithms commonly perform. Without the machine learning framework 604, a developer of the machine learning algorithm would be required to create and optimize the main computational logic associated with the machine learning algorithm, and then re-optimize the computational logic as new parallel processors are developed. Alternatively, the machine learning application may be configured to perform the necessary computations using the primitives provided by the machine learning framework 604. Exemplary primitives include tensor convolution, activation functions, and pooling (posing), which are computational operations performed in training a Convolutional Neural Network (CNN). The machine learning framework 604 may also provide primitives to implement basic linear algebraic subroutines performed by many machine learning algorithms, such as matrix and vector operations.

The machine learning framework 604 can process input data received from the machine learning application 602 and generate suitable input to the computing framework 606. The compute framework 606 may extract the underlying instructions provided to the GPGPU driver 608 to enable the machine learning framework 604 to take advantage of hardware acceleration via the GPGPU hardware 610 without requiring the machine learning framework 604 to have an in-depth knowledge of the architecture of the GPGPU hardware 610. Additionally, the computing framework 606 may implement hardware acceleration for the machine learning framework 604 across various types and generations of GPGPU hardware 610.

GPGPU machine learning acceleration

FIG. 7 illustrates a general purpose graphics processing unit 700, according to an embodiment. In one embodiment, a general purpose processing unit (GPGPU) 700 may be configured to be particularly efficient at processing the type of computational workload associated with training a deep neural network. Additionally, the GPGPU 700 may link directly to other instances of the GPGPU to create multiple GPU clusters to increase training speed for a particular deep neural network.

The GPGPU 700 includes a host interface 702 for enabling connection to a host processor. In one embodiment, host interface 702 is a PCI express interface. However, the host interface may also be a vendor-specific communication interface or communication fabric. The GPGPU 700 receives commands from host processors and uses the global scheduler 704 to distribute the execution threads associated with those commands to a set of compute clusters 706A-706H. The compute clusters 706A-706H share a cache memory 708. The cache memory 708 may act as a higher-level cache for cache memories within the compute clusters 706A-706H.

The GPGPU 700 includes memories 714A-B coupled with the compute clusters 706A-H via a set of memory controllers 712A-712B. In various embodiments, memories 714A-714B may comprise various types of memory devices, including Dynamic Random Access Memory (DRAM) or graphics random access memory, such as Synchronous Graphics Random Access Memory (SGRAM), including Graphics Double Data Rate (GDDR) memory. In one embodiment, memory units 714A-714N may also include 3D stacked memory, including but not limited to High Bandwidth Memory (HBM).

In one embodiment, each compute cluster 706A-706H includes a set of graphics multiprocessors, such as graphics multiprocessor 400 of FIG. 4A. The graphics multiprocessor of a compute cluster includes various types of integer and floating point logic units that can perform computational operations at a range of precision, including those suitable for machine learning computations. For example, and in one embodiment, at least a subset of the floating point units in each of the compute clusters 706A-H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units may be configured to perform 64-bit floating point operations.

Multiple instances of the GPGPU 700 may be configured to operate as a compute cluster. The communication mechanism used by the computing cluster for synchronization and data exchange varies from embodiment to embodiment. In one embodiment, multiple instances of the GPGPU 700 communicate through the host interface 702. In one embodiment, the GPGPU 700 includes an I/O hub 709 that couples the GPGPU 700 with a GPU link 710, which GPU link 710 enables direct connections to other instances of the GPGPU. In one embodiment, GPU link 710 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 700. In one embodiment, GPU link 710 is coupled with a high speed interconnect to transmit data to and receive data from other GPGPUs or parallel processors. In one embodiment, multiple instances of the GPGPU 700 are located in separate data processing systems and communicate via a network device that is accessible via the host interface 702. In one embodiment, GPU link 710 may be configured to enable a connection with a host processor in addition to or as an alternative to host interface 702.

While the configuration of the illustrated GPGPU 700 may be configured to train a neural network, one embodiment provides an alternative configuration of the GPGPU 700 that may be configured for deployment within a high performance or low power inference platform. In the inference configuration, the GPGPU 700 includes fewer computing clusters 706A-706H relative to the training configuration. Additionally, the memory technology associated with memories 714A-714B may differ between inference and training configurations. In one embodiment, the inference configuration of the GPGPU 700 may support inference-specific instructions. For example, the inference configuration may provide support for one or more 8-bit integer dot-product instructions that are typically used during inference operations with the deployed neural network.

Fig. 8 illustrates a multi-GPU computing system 800 according to an embodiment. The multi-GPU computing system 800 can include a processor 802 coupled to a plurality of GPGPUs 806A-806D via a host interface switch 804. In one embodiment, the host interface switch 804 is a PCI express switching device that couples the processor 802 to a PCI express bus through which the processor 802 may communicate with a set of GPGPUs 806A-806D. Each of the multiple GPGPUs 806A-806D may be an example of the GPGPU 700 of FIG. 7. GPGPGPUs 806A-806D may be interconnected via a set of high speed point-to-point GPU-to-GPU links 816. The high-speed GPU-to-GPU link may be connected to each of the GPGPUs 806A-806D via a dedicated GPU link (such as GPU link 710 in FIG. 7). P2P GPU link 816 enables direct communication between each of the GPGPGPUs 806A-806D without requiring communication on the host interface bus to which processor 802 is connected. With GPU-to-GPU traffic directed to the P2P GPU link, the host interface bus is still available for system memory access or communication with other instances of the multi-GPU computing system 800, e.g., via one or more network devices. Although in the illustrated embodiment, GPGPGPUs 806A-D are connected to processor 802 via host interface switch 804, in one embodiment, processor 802 includes direct support for P2P GPU link 816 and may be directly connected to GPGPGPUs 806A-806D.

Machine learning neural network implementation

The computing architecture provided by the embodiments described herein may be configured to perform parallel processing of the type particularly suited to training and deploying neural networks for machine learning. The neural network can be generalized to a network having a function of graph relationship (graph relationship). As is well known in the art, there are many types of neural network implementations used in machine learning. One exemplary type of neural network is a feed-forward network, as previously described.

A second exemplary type of neural network is a Convolutional Neural Network (CNN). CNN is a specialized feed-forward neural network for processing data with a known mesh-like topology, such as image data. CNNs are therefore commonly used in computational vision and image recognition applications, but they can also be used for other types of pattern recognition, such as speech and language processing. The nodes in the CNN input layer are organized into a set of "filters" (feature detectors inspired by the receptive field found in the retina), and the output of each set of filters is propagated to nodes in successive layers of the network. The calculation for CNN includes applying a convolution mathematical operation to each filter to produce the output of that filter. Convolution is a specialized mathematical operation performed by two functions to produce a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function to convolution may be referred to as the input, and the second function may be referred to as the convolution kernel. The output may be referred to as a feature map. For example, the input to the convolutional layer may be data defining a multi-dimensional array of various color components of the input image. The convolution kernel may be a parameter of the multi-dimensional array, wherein the parameters are adapted for the neural network by the training process.

A Recurrent Neural Network (RNN) is a series of feed-forward neural networks that include feedback connections between layers. The RNN enables modeling of sequential (sequential) data by sharing parameter data across different parts of the neural network. The architecture of the RNN includes loops. The loop represents the effect of the current value of the variable on its own value at a future time, since at least a portion of the output data from the RNN is used as feedback for processing subsequent inputs in the sequence. This feature makes RNNs particularly useful for linguistic processing due to the nature of variables in which linguistic data may be composed.

The diagrams described below present exemplary feed-forward, CNN, and RNN networks, as well as describe a general process for training and deploying each of those types of networks separately. It will be understood that these descriptions are exemplary and non-limiting with respect to any particular embodiment described herein and that the illustrated concepts may be applied to deep neural networks and machine learning techniques in general.

The exemplary neural networks described above may be used to perform deep learning. Deep learning is machine learning using a deep neural network. A deep neural network used in deep learning is an artificial neural network composed of a plurality of hidden layers, as opposed to a shallow neural network including only a single hidden layer. Deeper neural networks are typically more computationally intensive to train. However, the additional hidden layer of the network enables multi-step pattern recognition, which results in reduced output errors relative to shallow machine learning techniques.

Deep neural networks used in deep learning typically include a front-end network coupled to a back-end network for performing feature recognition, the back-end network representing a mathematical model that may perform operations (e.g., object classification, speech recognition, etc.) based on a feature representation provided to the model. Deep learning enables machine learning to be performed without the need to perform manual feature engineering on the model. Alternatively, the deep neural network may learn features based on statistical structures or correlations within the input data. The learned features can be provided to a mathematical model, which can map the detected features to an output. The mathematical model used by the network is generally specific to the particular task to be performed, and different models will be used to perform different tasks.

Once the neural network is constructed, a learning model may be applied to the network to train the network to perform a particular task. The learning model describes how to adjust the weights within the model to reduce the output error of the network. Error back-propagation is a common method for training neural networks. The input vectors are presented to the network for processing. The output of the network is compared to a desired output using a loss function and an error value is calculated for each of the neurons in the output layer. The error values are then propagated back until each neuron has an associated error value that approximately represents its contribution to the original output. The network may then learn from those errors using an algorithm (such as a random gradient descent algorithm) to update the weights of the neural network.

Fig. 9A-9B illustrate exemplary convolutional neural networks. Fig. 9A shows various layers within a CNN. As shown in fig. 9A, an exemplary CNN for modeling image processing may receive an input 902 describing red, green, and blue (RGB) components of an input image. Input 902 may be processed by multiple convolutional layers (e.g., convolutional layer 904, convolutional layer 906). The output from the plurality of convolutional layers may optionally be processed by a set of fully-connected layers 908. Neurons in a fully connected layer have a full connection to all activations in a previous layer, as described previously for the feed forward network. The output from the fully connected layer 908 may be used to generate output results from the network. Activations within fully connected layer 908 may be computed using matrix multiplication rather than convolution. Not all CNN implementations utilize a fully connected layer 908. For example, in some implementations, convolutional layer 906 can generate an output for CNN.

Convolutional layers are sparsely connected, unlike conventional neural network configurations found in fully connected layer 908. The traditional neural network layers are fully connected such that each output unit interacts with each input unit. However, as shown, the convolutional layers are sparsely connected because the output of the convolution of the field is an input to the nodes of the subsequent layer (rather than the respective state values of each of the nodes in the field). The kernel associated with the convolutional layer performs a convolution operation, the output of which is sent to the next layer. The dimensionality reduction performed within the convolution layer is one aspect of enabling the CNN to scale to handle large images.

Fig. 9B shows exemplary computation stages within the convolutional layer of CNN. Inputs to convolutional layer 912 of CNN may be processed in three stages of convolutional layer 914. These three stages may include a convolution stage 916, a detector stage 918, and a pooling stage 920. Convolutional layers 914 may then output data to the continuous convolutional layers. The last convolutional layer of the network may generate output profile data or provide input to the fully-connected layer, e.g., to generate a classification value for the input to the CNN.

In the convolution stage 916, several convolutions are performed in parallel to produce a set of linear activations. Convolution stage 916 may include an affine transform, which is any transform that may be specified as a linear transform plus a translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage computes the output of a function (e.g., a neuron) connected to a particular region in the input, which may be determined as a local region associated with the neuron. The neuron calculates a dot product between the weight of the neuron and the region in the local input to which the neuron is connected. The output from convolution stage 916 defines a set of linear activations that are processed by successive stages of convolutional layer 914.

The linear activation may be processed by the detector stage 918. In the detector stage 918, each linear activation is processed by a nonlinear activation function. The nonlinear activation function increases the nonlinear properties of the overall network without affecting the corresponding field of the convolutional layer. Several types of non-linear activation functions may be used. One particular type is the rectifying Linear Unit (ReLU), the use of which is defined asSuch that the activation threshold is zero.

The pooling stage 920 uses a pooling function that replaces the output of the convolutional layer 906 with the summary statistics of nearby outputs. The pooling function may be used to introduce translation invariance into the neural network such that small translations to the input do not change the pooled output. Invariance to local translation may be useful in scenarios where the presence of features in the input data is more important than the precise location of the features. Various types of pooling functions may be used during the pooling stage 920, including maximum pooling, average pooling, and l2 norm pooling. Additionally, some CNN implementations do not include a pooling stage. Instead, such an implementation replaces an additional convolution stage with an increased step size relative to the previous convolution stage.

The output from convolutional layer 914 may then be processed by the next layer 922. The next layer 922 may be one of an additional convolutional layer or a fully connected layer 908. For example, first convolutional layer 904 of FIG. 9A may be output to second convolutional layer 906, and the second convolutional layer may be output to the first layer of fully-connected layer 908.

Fig. 10 illustrates an exemplary recurrent neural network 1000. In a Recurrent Neural Network (RNN), a previous state of the network affects the output of the current state of the network. The RNN may be constructed in various ways using various functions. The use of RNNs generally revolves around the use of mathematical models to predict the future based on a priori sequences of inputs. For example, given a sequence of previous words, the RNN may be used to perform statistical language modeling to predict upcoming words. The illustrated RNN 1000 may be described as having an input layer 1002 that receives input vectors, a hidden layer 1004 that implements a recursive function, a feedback mechanism 1005 that enables 'remembering' of previous states, and an output layer 1006 that outputs results. The RNN 1000 operates on a time step basis. The state of the RNN at a given time step is affected based on previous time steps via the feedback mechanism 1005. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input of the current time step. Initial input at first time step (x)₁) May be processed by the hidden layer 1004. Second input (x)₂) Can be used by the hidden layer 1004 at the initial input (x)₁) Is processed during the processing of (1). The given state may be calculated asWhereinUAndWis a parameter matrix. Function(s)fGenerally non-linear, e.g. hyperbolic tangent function (Tanh) or rectification functionA variant of (1). However, the particular mathematical function used in the hidden layer 1004 may vary depending on the particular implementation details of the RNN 1000.

Changes on these networks may be enabled in addition to the basic CNN and RNN networks described. One example RNN variant is the Long Short Term Memory (LSTM) RNN. The LSTM RNN is able to learn long-term dependencies, which are necessary to handle longer language sequences. A variation on CNN is a convolutional deep belief network, which has a similar structure and is trained in a similar manner as CNN. A Deep Belief Network (DBN) is a generative neural network that consists of layers of probabilistic (random) variables. The DBN may be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining an optimal initial set of weights for the neural network.

Fig. 11 illustrates training and deployment of a deep neural network. Once a given network has been constructed for a task, the neural network is trained using the training data set 1102. Various training frameworks 1104 have been developed to enable hardware acceleration of the training process. For example, the machine learning framework 604 of fig. 6 may be configured as a training framework 604. The training framework 604 may hook (hook into) an untrained neural network 1106 and enable the untrained neural network to be trained using parallel processing resources described herein to generate a trained neural network 1108.

To begin the training process, the initial weights may be selected randomly or by pre-training using a deep belief network. The training cycle is then performed in a supervised or unsupervised manner.

Supervised learning is a learning method in which training is performed as a mediated operation, such as when the training data set 1102 includes inputs paired with desired outputs of the inputs, or where the training data set includes inputs having known outputs and the outputs of the neural network are manually ranked. The network processes the inputs and compares the resulting outputs to a set of expected or expected outputs. The error is then propagated backwards through the system. The training framework 1104 may be adapted to adjust the weights that control the untrained neural network 1106. The training framework 1104 may provide tools to monitor how well the untrained neural network 1106 converges to a model suitable for generating a correct response based on known input data. The training process recurs as the weights of the network are adjusted to improve the output generated by the neural network. The training process may continue until the neural network reaches a statistically desired accuracy associated with the trained neural network 1108. The trained neural network 1108 may then be deployed to implement any number of machine learning operations to generate inference results 1114 based on the input of new data 1112.

Unsupervised learning is a learning method in which the network attempts to train itself using unlabeled data. Thus, for unsupervised learning, the training data set 1102 will include input data without any associated output data. The untrained neural network 1106 can learn the groupings within the unlabeled input and can determine how the individual inputs relate to the overall data set. Unsupervised training may be used to generate a self-organizing map, which is a type of trained neural network 1108 that is capable of performing operations useful in the dimensionality reduction of data. Unsupervised training may also be used to perform anomaly detection, which allows for identification of data points in the input data set that deviate from the normal pattern of data.

Variations on supervised and unsupervised training may also be employed. Semi-supervised learning is a technique in which the training data set 1102 includes a mixture of identically distributed labeled and unlabeled data. Incremental learning is a variation of supervised learning in which input data is continuously used to further train the model. Incremental learning enables the trained neural network 1108 to adapt to new data 1112 without forgetting knowledge instilled within the network during initial training.

The training process for deep neural networks in particular, whether supervised or unsupervised, may be too computationally intensive for a single compute node. Instead of using a single compute node, a distributed network of compute nodes may be used to accelerate the training process.

Fig. 12 is a block diagram illustrating distributed learning. Distributed learning is a training model that uses a plurality of distributed computing nodes to perform supervised or unsupervised training of a neural network. The distributed computing nodes may each include one or more host processors and one or more of the general purpose processing nodes, such as highly parallel general purpose graphics processing unit 700 as in fig. 7. As shown, distributed learning can be model parallel structure 1202, data parallel structure 1204, or a combination of model and data parallel structure 1204 that are performed.

In model parallel structure 1202, different compute nodes in a distributed system may perform training computations on different portions of a single network. For example, each layer of the neural network may be trained by a different processing node of the distributed system. Benefits of model parallel architecture include the ability to scale to especially large models. Splitting the computations associated with different layers of the neural network enables training of such a very large neural network in which the weights of all layers would not fit into the memory of a single compute node. In some instances, the model parallel architecture may be particularly useful in performing unsupervised training of large neural networks.

In the data parallel structure 1204, different nodes of the distributed network have complete instances of the model and each node receives a different portion of the data. The results from the different nodes are then combined. While different approaches are possible for data parallel structures, data parallel training approaches all require techniques to combine results and synchronize model parameters between each node. Exemplary methods of combining data include parameter averaging and update-based data parallel structures. The parameter average trains each node on the training data subset and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server, which maintains parameter data. The update-based data parallel structure is similar to parameter averaging, except that updates to the model are transmitted instead of transmitting parameters from the nodes to the parameter server. Additionally, the update-based data parallel structure may be performed in a decentralized manner, where updates are compressed and transmitted between nodes.

The combined model and data parallel structure 1206 may be implemented, for example, in a distributed system in which each compute node includes multiple GPUs. Each node may have a complete instance of the model, with a separate GPU within each node being used to train different portions of the model.

Distributed training has increased overhead relative to training on a single machine. However, the parallel processors and gpgpgpu described herein may each implement various techniques to reduce the overhead of distributed training, including techniques to implement high-bandwidth GPU-to-GPU data transfers and to accelerate remote data synchronization.

Exemplary machine learning application

Machine learning may be applied to solve a variety of technical problems including, but not limited to, computer vision, autonomous driving and navigation, speech recognition, and language processing. Traditionally, computer vision has been one of the most active research areas for machine learning applications. Applications of computer vision range from rendering human visual capabilities (e.g., recognizing faces) to creating new categories of visual capabilities. For example, a computer vision application may be configured to identify sound waves from vibrations induced in objects visible in a video. Parallel processor accelerated machine learning enables computer vision applications to be trained using significantly larger training data sets than previously possible and inference systems to be deployed using low power parallel processors.

Parallel processor accelerated machine learning has autonomous driving applications including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques may be used to train driving models based on data sets that define appropriate responses to particular training inputs. The parallel processors described herein may enable fast training of increasingly complex neural networks for autonomous driving solutions and enable deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

Parallel processor accelerated deep neural networks enable machine learning methods for Automatic Speech Recognition (ASR). ASR involves creating a function that: given the input acoustic sequence, the most likely language sequence is calculated. Accelerated machine learning using deep neural networks has enabled the replacement of Hidden Markov Models (HMMs) and Gaussian Mixture Models (GMMs) previously used for ASR.

Parallel processor accelerated machine learning may also be used to accelerate natural language processing. The automatic learning procedure may utilize statistical inference algorithms to generate models that are robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. The training platform is generally highly parallel and includes optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include the general purpose graphics processing unit 700 of FIG. 7 and the multi-GPU computing system 800 of FIG. 8. In contrast, deployed machine learning platforms generally include lower power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

FIG. 13 illustrates an exemplary inference System On Chip (SOC) 1300 suitable for performing inference using a trained model. SOC 1300 may integrate processing components including media processor 1302, vision processor 1304, GPGPU 1306, and multicore processor 1308. The SOC 1300 may additionally include on-chip memory 1305, which may implement a shared on-chip data pool accessible to each of the processing components. The processing component may optimize low power operation to enable deployment to various machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of SOC 1300 may be used as part of a master control system of an autonomous vehicle. Where the SOC 1300 is configured for use with an autonomous vehicle, the SOC is designed and configured to comply with deployment-governed, related functional safety standards.

During operation, the media processor 1302 and the vision processor 1304 may work together (in concert) to accelerate computer vision operations. The media processor 1302 may implement low latency decoding of multiple high resolution (e.g., 4K, 8K) video streams. The decoded video stream may be written to a buffer in the on-chip memory 1305. The vision processor 1304 may then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation for processing the frames using the trained image recognition model. For example, the vision processor 1304 may accelerate convolution operations for CNN used to perform image recognition on high-resolution video data, while back-end model calculations are performed by the GPGPU 1306.

The multi-core processor 1308 may include control logic to facilitate the sequencing and synchronization of data transfers and shared memory operations performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also act as an application processor to execute software applications that may utilize the speculative computing capabilities of the GPGPU 1306. For example, at least a portion of the navigation and driving logic may be implemented in software executing on the multi-core processor 1308. Such software may issue computational workloads directly to the GPGPU 1306 or may issue computational workloads to the multi-core processor 1308, which multi-core processor 1308 may offload at least a portion of those operations to the GPGPU 1306.

The GPGPU 1306 may include a low power configuration of compute clusters, such as compute clusters 706A-706H within the general purpose graphics processing unit 700. The compute clusters within the GPGPU 1306 may support instructions that are specifically optimized to perform inference computations on a trained neural network. For example, the GPGPU 1306 may support instructions that perform low precision computations, such as 8-bit and 4-bit integer vector operations.

Page fault handling

The foregoing description and drawings are to be regarded in an illustrative rather than a restrictive sense. It will be appreciated by persons skilled in the art that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the invention as set forth in the appended claims. As described above, page fault handling consumes processing resources and introduces latency into the process. To address these and other problems, the techniques described herein enable a processing system (e.g., a graphics processing system and device as described herein) to handle page faults.

In some examples, the processing system may perform operations to implement a preemptive page fault handling algorithm. In some examples, the operations depicted in fig. 14 may be implemented in a page fault handler, which in turn may be implemented in hardware or by a general purpose processor executing logical instructions (e.g., software). As an example, in some embodiments, the operations depicted in fig. 15 may be implemented in a microcontroller communicatively coupled to one or more Memory Management Units (MMUs) associated with or communicatively coupled to a graphics processor.

Referring to FIG. 14, at operation 1410, a page fault virtual address is received. As an example, a memory management unit associated with a processor executing a process may detect a page fault when the process accesses a memory page that is not mapped into a virtual address space associated with the process. In some examples, the page associated with the virtual address may be present in memory, but may not have been flagged by the memory management unit (i.e., a soft page fault). In other examples, the memory page associated with the virtual address may not be loaded in memory (i.e., a hard page fault), in which case memory space must be created for the memory page by expanding memory dedicated to the process or by evicting the contents of some portion of memory to create free space for the memory page.

At operation 1415, the virtual address allocation for the process is checked to determine the page location of the virtual address received in operation 1410 within the virtual address space allocated for the process. At operation 1420, if the virtual address received in operation 1410 does not represent the last page of the memory allocation for the process, then control passes to operation 1425 and memory is allocated in the page table. In some examples, memory is mapped starting with the page fault virtual address received in operation 1410 and an additional number of pages (indicated by N) are mapped in the page table, and control passes to operation 1430. In some examples, the number of pages may be determined in part by the amount of available memory. In contrast, at operation 1420, if the virtual address received in operation 1410 represents the last page of the memory allocation for the process, then control passes to operation 1430.

At operation 1430, the page table is updated in virtual memory to reflect the allocation of memory. At operation 1435, information associated with the page fault is stored in memory. For example, a page fault data record including at least a process identifier, a virtual memory address, and a timestamp may be stored in memory. In addition, the page fault data record may include a memory allocation parameter, a memory capacity parameter, and a thread count parameter for the process. When the memory management unit detects a page fault, the operations of FIG. 14 may be repeated to manage the allocation of pages in the page table. Further, the repeated execution of operation 1435 builds a data table of page fault data records in memory.

In some examples, the page fault data records stored in memory in operation 1435 may be used to generate page fault predictions, which in turn may be used to preemptively retrieve data in an attempt to avoid predicted page faults. Referring to FIG. 15, at operation 1510, page fault information stored in the data records via repeated execution of operation 1435 is retrieved from memory, and at operation 1515, a time series data set is constructed from the page fault data stored in operation 1435. In some examples, the time series dataset may collate data records for one or more processes and build correlations between one or more parameters in the data records and page fault events.

At operation 1520, the time series dataset can be used to predict a page fault event for one or more processes. In response to the prediction of the page fault event, data may be preemptively retrieved from memory in order to avoid the page fault(s) predicted in operation 1520.

FIG. 16 is a schematic block diagram of an environment 1600 suitable for implementing preemptive page fault handling, according to an embodiment. Referring to fig. 16, in some examples, an environment includes a plurality of memory management units 1610 communicatively coupled to a microcontroller 1620. The microcontroller 1620 is communicatively coupled to the direct memory access controller 1630 and the memory 1640. In some examples, page fault handling algorithms (such as those described with reference to fig. 14 and 15) may be implemented in a local microcontroller 1620, the local microcontroller 1620 communicatively coupled to the memory management unit 1610. Microcontroller 1620 may also manage page faults, schedule handles (clocks), and update page tables. Hardware-based embodiments using page fault handlers may reduce latency associated with page fault handling.

Additional exemplary graphics processing System

Details of the above-described embodiments may be incorporated into the graphics processing systems and devices described below. The graphics processing systems and devices of fig. 17-29 illustrate alternative systems and graphics processing hardware that can implement any and all of the techniques described above.

Overview of the System

Fig. 17 is a block diagram of a processing system 1700 according to an embodiment. The system 1700 may be used in a single processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 1702 or processor cores 1707. In one embodiment, system 1700 is a processing platform incorporated within a system on a chip (SoC) integrated circuit for use with a mobile device, handheld device, or embedded device within an internet of things (IoT) device, such as having a wired or wireless connection to a local area network or a wide area network.

In one embodiment, system 1700 may include, be coupled with, or integrated within: a server-based game platform; game consoles, including games and media consoles; a mobile game console, a handheld game console, or an online game console. In some embodiments, system 1700 is part of a mobile phone, smart phone, tablet computing device, or mobile internet connected device (such as a laptop device with low internal storage capabilities). The processing system 1700 may also include, be coupled with, or be integrated within: wearable devices, such as smart watch wearable devices; smart glasses (eyewear) or apparel augmented with Augmented Reality (AR) or Virtual Reality (VR) features to provide visual, auditory, or haptic output to supplement the real world visual, auditory, or haptic experience, or to otherwise provide text, audio, graphics, video, holographic images or video, or haptic feedback; other Augmented Reality (AR) devices; or other Virtual Reality (VR) device. In some embodiments, processing system 1700 includes or is part of a television or set-top box device.

In some embodiments, system 1700 may include, be coupled with, or integrated within: an autonomous vehicle such as a bus, tractor trailer, automobile, motorcycle or electric bicycle, airplane or glider (or any combination thereof). Autonomous vehicles may use system 1700 to address the environment sensed around the vehicle.

In some embodiments, the one or more processors 1702 each include one or more processor cores 1707 for processing instructions that, when executed, perform operations for system and user software. In some embodiments, at least one of the one or more processor cores 1707 is configured to process a particular instruction set 1709. In some embodiments, the instruction set 1709 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via Very Long Instruction Words (VLIW). One or more processor cores 1707 may process a different instruction set 1709, which may include instructions to facilitate emulation of other instruction sets. Processor core 1707 may also include other processing devices, such as a Digital Signal Processor (DSP).

In some embodiments, the processor 1702 includes a cache memory 1704. Depending on the architecture, the processor 1702 may have a single internal cache or multiple levels of internal cache. In some embodiments, cache memory is shared among various components of the processor 1702. In some embodiments, the processor 1702 also uses an external cache (e.g., a level 3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among the processor cores 1707 using known cache coherency techniques. The register file 1706 is additionally included in the processor 1702 and may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers while other registers may be specific to the design of the processor 1702.

In some embodiments, one or more processors 1702 are coupled with one or more interface buses 1710 to transmit communication signals (such as address, data, or control signals) between the processors 1702 and other components in the system 1700. In one embodiment, the interface bus 1710 may be a processor bus, such as a version of a Direct Media Interface (DMI) bus. However, the processor bus is not limited to a DMI bus, but may include one or more peripheral component interconnect buses (e.g., PCI express), a memory bus, or other types of interface buses. In one embodiment, the processor(s) 1702 include an integrated memory controller 1716 and a platform controller hub 1730. The memory controller 1716 facilitates communication between the memory devices and other components of the system 1700, while the platform controller hub (ICH) 1730 provides a connection to I/O devices via a local I/O bus.

Memory device 1720 may be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable capabilities to function as a process memory. In one embodiment, the memory device 1720 may operate as a system memory for the system 1700 to store data 1722 and instructions 1721 for use when the one or more processors 1702 execute an application or process. The memory controller 1716 is also coupled to an optional external graphics processor 1718, which may communicate with one or more graphics processors 1708 in the processor 1702 to perform graphics and media operations. In some embodiments, graphics, media, and computing operations may be facilitated by an accelerator 1712, which is a coprocessor that may be configured to perform a specialized set of graphics, media, or computing operations. For example, in one embodiment, the accelerator 1712 is a matrix multiplication accelerator for optimizing machine learning or computing operations. In one embodiment, the accelerator 1712 is a ray tracing accelerator that may be used to perform ray tracing operations with the graphics processor 1708. In some embodiments, a display device 1711 may be connected to the processor(s) 1702. The display device 1711 can be one or more of an internal display device (as in a mobile electronic device or laptop device) or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment, the display device 1711 may be a Head Mounted Display (HMD), such as a stereoscopic display device for Virtual Reality (VR) applications or Augmented Reality (AR) applications.

In some embodiments, platform controller hub 1730 enables peripherals to connect to memory device 1720 and processor 1702 via a high speed I/O bus. I/O peripherals include, but are not limited to: audio controller 1746, network controller 1734, firmware interface 1728, wireless transceiver 1726, touch sensor 1725, data storage 1724 (e.g., non-volatile memory, hard drive, flash memory, NAND, 3D XPoint, etc.). The data storage 1724 may be connected via a storage device interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI express). The touch sensor 1725 may include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 1726 may be a Wi-Fi transceiver, a bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, 5G, or Long Term Evolution (LTE) transceiver. Firmware interface 1728 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). The network controller 1734 may enable a network connection to a wired network. In some embodiments, a high performance network controller (not shown) is coupled to interface bus 1710. In one embodiment, audio controller 1746 is a multi-channel high definition audio controller. In one embodiment, system 1700 includes an optional legacy I/O controller 1740 for coupling legacy (e.g., personal System 2 (PS/2)) devices to the system. The platform controller hub 1730 may also connect to one or more Universal Serial Bus (USB) controllers 1742 to connect input devices, such as a keyboard and mouse 1743 combination, a camera 1744, or other USB input devices.

It will be appreciated that the illustrated system 1700 is exemplary and not limiting, as other types of data processing systems configured in a different manner may also be used. For example, instances of memory controller 1716 and platform controller hub 1730 may be integrated into a discrete external graphics processor, such as external graphics processor 1718. In one embodiment, the platform controller hub 1730 and/or the memory controller 1716 may be located external to the one or more processors 1702. For example, the system 1700 may include an external memory controller 1716 and a platform controller hub 1730, which may be configured as a memory controller hub and a platform controller hub in a system chipset in communication with the processor(s) 1702.

For example, a circuit board ("sled") designed to improve thermal performance may be used to place components such as a CPU, memory, and other components. In some examples, a processing component such as a processor is located on the top of the sled, while a nearby memory such as a DIMM is located on the bottom of the sled. As a result of the enhanced airflow provided by this design, the components may operate at higher frequencies and power levels than in typical systems, thereby improving performance. In addition, the skis are configured to blindly mate with power and data communication cables in the chassis, thereby enhancing their ability to be quickly removed, upgraded, reinstalled, and/or replaced. Similarly, the individual components located on the ski (such as the processor, accelerator, memory and data storage drive) are configured to be easily upgradeable due to their increased spacing from each other. In an illustrative embodiment, the components additionally include hardware authentication features to prove their authenticity.

A data center may utilize a single network architecture ("fabric") that supports multiple other network architectures, including ethernet and Omni-Path. The sled may be coupled to the switch via optical fibers, which provides higher bandwidth and lower latency than typical twisted pair cabling (e.g., category 5e, category 6, etc.). Due to the high bandwidth, low latency interconnect and network architecture, the data center may pool resources, such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural networks, and/or artificial intelligence accelerators, etc.), and physically disaggregated data storage drives in use and provide them to computing resources (e.g., processors) as needed to enable the computing resources to access the pooled resources as if accessing local resources.

The power supply or power source may provide voltage and/or current to the system 1700 or any of the components or systems described herein. In one example, the power supply includes an AC to DC (alternating current to direct current) adapter that plugs into a wall outlet. Such AC power may be a renewable energy (e.g., solar) power source. In one example, the power supply includes a DC power supply, such as an external AC to DC converter. In one example, the power supply or power supply includes wireless charging hardware that charges via a proximity charging field. In one example, the power source may include an internal battery, an ac power supply, a motion-based power supply, a solar power supply, or a fuel cell power source.

FIG. 18 is a block diagram of an embodiment of a processor 1800 having one or more processor cores 1802A-1802N, an integrated memory controller 1814, and an integrated graphics processor 1808. Those elements of fig. 18 having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not so limited. The processor 1800 may include additional cores up to and including an additional core 1802N, represented by a dashed box. Each of processor cores 1802A-1802N includes one or more internal cache units 1804A-1804N. In some embodiments, each processor core also has access to one or more shared cache units 1806.

The internal cache units 1804A-1804N and the shared cache unit 1806 represent cache levels within the processor 1800. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other level cache, with the highest level cache ahead of external memory being categorized as an LLC. In some embodiments, cache coherency logic maintains coherency between the various cache molecules 1806 and 1804A-1804N.

In some embodiments, processor 1800 may also include a set of one or more bus controller units 1816 and a system agent core 1810. The one or more bus controller units 1816 manage a set of peripheral buses, such as one or more PCI or PCI express buses. The system proxy core 1810 provides management functionality for various processor components. In some embodiments, the system surrogate core 1810 includes one or more integrated memory controllers 1814 to manage access to various external memory devices (not shown).

In some embodiments, one or more of the processor cores 1802A-1802N include support for simultaneous multithreading. In such embodiments, the system proxy core 1810 includes components to coordinate and operate the cores 1802A-1802N during multi-threaded processing. System proxy core 1810 may additionally include a Power Control Unit (PCU) that includes logic and components for regulating the power states of processor cores 1802A-1802N and graphics processor 1808.

In some embodiments, the processor 1800 additionally includes a graphics processor 1808 for performing graphics processing operations. In some embodiments, the graphics processor 1808 is coupled to a set of shared cache units 1806 and a system proxy core 1810 (including one or more integrated memory controllers 1814). In some embodiments, the system surrogate core 1810 also includes a display controller 1811 to drive graphics processor output to one or more coupled displays. In some embodiments, the display controller 1811 may also be a separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor 1808.

In some embodiments, a ring-based interconnect unit 1812 is used to couple the internal components of the processor 1800. However, alternative interconnection elements may be used, such as point-to-point interconnections, switched interconnections, or other techniques, including those well known in the art. In some embodiments, graphics processor 1808 is coupled to ring interconnect 1812 via I/O link 1813.

Exemplary I/O link 1813 represents at least one of a variety of I/O interconnects, including an on-package I/O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 1818, such as an eDRAM module. In some embodiments, each of the processor cores 1802A-1802N and the graphics processor 1808 may use the embedded memory module 1818 as a shared last level cache.

In some embodiments, the processor cores 1802A-1802N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 1802A-1802N are heterogeneous in Instruction Set Architecture (ISA), wherein one or more of the processor cores 1802A-1802N execute a first instruction set and at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 1802A-1802N are heterogeneous in microarchitecture in which one or more cores having relatively higher power consumption are coupled with one or more power cores having lower power consumption. In one embodiment, the processor cores 1802A-1802N are heterogeneous in computing power. Further, processor 1800 may be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, among other components.

Fig. 19 is a block diagram of a graphics processor 1900, which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores or other semiconductor devices, such as but not limited to memory devices or network interfaces. In some embodiments, the graphics processor communicates via a memory mapped I/O interface to registers on the graphics processor and with commands placed in processor memory. In some embodiments, graphics processor 1900 includes a memory interface 1914 to access memory. Memory interface 1914 may be an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory.

In some embodiments, graphics processor 1900 also includes a display controller 1902 to drive display output data to a display device 1918. The display controller 1902 includes a composition of layers of video or user interface elements and hardware for one or more overlay planes of the display. The display device 1918 may be an internal or external display device. In one embodiment, the display device 1918 is a head mounted display device, such as a Virtual Reality (VR) display device or an Augmented Reality (AR) display device. In some embodiments, graphics processor 1900 includes a video codec engine 1906 for encoding, decoding, or transcoding media to, from, or between one or more media encoding formats, including but not limited to: moving Picture Experts Group (MPEG) formats, such as MPEG-2, Advanced Video Coding (AVC) formats, such as H.264/MPEG-4 AVC, H.265/HEVC, open media alliance (AOmedia) VP8, VP9, and Society of Motion Picture and Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic Experts Group (JPEG) formats, such as JPEG, and Motion JPEG (MJPEG) formats.

In some embodiments, graphics processor 1900 includes a block image transfer (BLIT) engine 1904 to perform two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of Graphics Processing Engine (GPE) 1910. In some embodiments, GPE 1910 is a compute engine to perform graphics operations, including three-dimensional (3D) graphics operations and media operations.

In some embodiments, GPE 1910 includes a 3D pipeline 1912 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 1912 contains programmable and fixed function elements that perform various tasks within the elements and/or generate threads of execution to the 3D/media subsystem 1915. While 3D pipeline 1912 may be used to perform media operations, embodiments of GPE 1910 also include media pipeline 1916 that is specifically used to perform media operations such as video post-processing and image enhancement.

In some embodiments, the media pipeline 1916 includes fixed-function or programmable logic units to perform one or more specialized media operations (such as video decoding acceleration, video de-interleaving, and video encoding acceleration) in place of or on behalf of the video codec engine 1906. In some embodiments, media pipeline 1916 additionally includes a thread generation unit to generate threads for execution on 3D/media subsystem 1915. The generated threads perform computations for media operations on one or more graphics execution units included in 3D/media subsystem 1915.

In some embodiments, 3D/media subsystem 1915 includes logic to execute threads generated by 3D pipeline 1912 and media pipeline 1916. In one embodiment, the pipeline sends thread execution requests to the 3D/media subsystem 1915, which includes thread dispatch logic for performing resource arbitration on available threads and dispatching various requests. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, 3D/media subsystem 1915 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem further includes a shared memory including registers and addressable memory for sharing data between threads and storing output data.

Graphics processing engine

FIG. 20 is a block diagram of a graphics processing engine 2010 of a graphics processor, according to some embodiments. In one embodiment, Graphics Processing Engine (GPE) 2010 is a version of GPE 1910 shown in FIG. 19. Elements in fig. 20 having the same reference numbers (or names) as elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. For example, the 3D pipeline 1912 and the media pipeline 1916 of fig. 19 are shown. Media pipeline 1916 is optional in some embodiments of GPE 2010 and may not be explicitly included in GPE 2010. For example, and in at least one embodiment, a separate media and/or image processor is coupled to GPE 2010.

In some embodiments, GPE 2010 is coupled with or includes command streamer 2003, which provides a command stream to 3D pipeline 1912 and/or media pipeline 1916. In some embodiments, command streamer 2003 is coupled to a memory, which may be a system memory, or one or more of an internal cache memory and a shared cache memory. In some embodiments, command streamer 2003 receives commands from memory and sends commands to 3D pipeline 1912 and/or media pipeline 1916. The command is an indication taken from a ring buffer that stores commands for the 3D pipeline 1912 and the media pipeline 1916. In one embodiment, the ring buffer may additionally include a batch command buffer that stores a batch of the plurality of commands. Commands to 3D pipeline 1912 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data to 3D pipeline 1912 and/or image data and memory objects to media pipeline 1916. 3D pipeline 1912 and media pipeline 1916 process commands and data by performing operations via logic within the respective pipelines or by dispatching one or more threads of execution to graphics core array 2014. In one embodiment, graphics core array 2014 includes one or more blocks of graphics cores (e.g., graphics core(s) 2015A, graphics core(s) 2015B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources including general and graphics-specific execution logic for performing graphics and computing operations, and fixed function texture processing and/or machine learning and artificial intelligence acceleration logic.

In various embodiments, 3D pipeline 1912 may include fixed functionality and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to graphics core array 2014. Graphics core array 2014 provides a unified execution resource block for processing these shader programs. Multipurpose execution logic (e.g., execution units) within graphics core(s) 2015A-2015B of graphics core array 2014 includes support for various 3D API shader languages and may execute concurrently executing threads associated with multiple shaders.

In some embodiments, graphics core array 2014 includes execution logic to perform media functions such as video and/or image processing. In one embodiment, the execution unit includes general purpose logic that is programmable to perform parallel general purpose computing operations in addition to graphics processing operations. The general purpose logic may perform processing operations in parallel with or in conjunction with the processor core(s) 1707 of FIG. 17 or the general purpose logic within cores 1802A-1802N of FIG. 18.

Output data generated by threads executing on graphics core array 2014 may output data to memory in Unified Return Buffer (URB) 2018. The URB 2018 may store data for multiple threads. In some embodiments, URB 2018 may be used to send data between different threads executing on graphics core array 2014. In some embodiments, URBs 2018 may additionally be used for synchronization between threads on the graphics core array and fixed function logic within shared function logic 2020.

In some embodiments, graphics core array 2014 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance levels of GPE 2010. In one embodiment, the execution resources are dynamically scalable such that the execution resources may be enabled or disabled as needed.

Graphics core array 2014 is coupled to shared functional logic 2020, which includes a plurality of resources shared between graphics cores in the graphics core array. The shared function within shared function logic 2020 is a hardware logic unit that provides specialized supplemental functionality to graphics core array 2014. In various embodiments, shared function logic 2020 includes, but is not limited to, sampler 2021, math 2022, and inter-thread communication (ITC) 2023 logic. Additionally, some embodiments implement one or more caches 2025 within the shared function logic 2020.

Shared functionality is implemented where the demand for a given specialized functionality is insufficient to be included within graphics core array 2014. Instead, a single instantiation of the specialized function is implemented as a separate entity in the shared function logic 2020 and is shared between execution resources within the graphics core array 2014. The precise set of functions shared between graphics core array 2014 and included within graphics core array 2014 varies across embodiments. In some embodiments, a particular shared function within shared function logic 2020, which is widely used by graphics core array 2014, may be included in shared function logic 2016 within graphics core array 2014. In various embodiments, shared function logic 2016 in graphics core array 2014 may include some or all of shared function logic 2020. In one embodiment, all logic elements in shared function logic 2020 may be duplicated in shared function logic 2016 in graphics core array 2014. In one embodiment, shared functional logic 2020 is excluded in favor of shared functional logic 2016 in graphics core array 2014.

Figure 21 is a block diagram of hardware logic of graphics processor core 2100, according to some embodiments described herein. Elements in fig. 21 having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such. In some embodiments, the illustrated graphics processor core 2100 is included in graphics core array 2014 of figure 20. Graphics processor core 2100 (sometimes referred to as a core slice) may be one or more graphics cores in a modular graphics processor. Graphics processor core 2100 is an example of one graphics core slice, and a graphics processor described herein may include multiple graphics core slices based on a target power and performance envelope (performance envelope). Each graphics processor core 2100 may contain a fixed function block 2130 coupled to multiple sub-cores 2101A-2101F (also known as subslices) that comprise modular blocks of general purpose and fixed function logic.

In some embodiments, fixed function block 2130 includes a geometry/fixed function pipeline 2136, which may be shared by all subcores in graphics processor core 2100, e.g., in a lower performance and/or lower power graphics processor implementation. In various embodiments, geometry/fixed function pipeline 2136 includes a 3D fixed function pipeline (e.g., like 3D pipeline 1912 in fig. 19 and 20), a video front end unit, a thread generator and thread dispatcher, and a unified return buffer manager that manages a unified return buffer, such as unified return buffer 2018 of fig. 20.

In one embodiment, fixed function block 2130 also includes a graphics SoC interface 2137, a graphics microcontroller 2138, and a media pipeline 2139. Graphics SoC interface 2137 provides an interface between graphics processor core 2100 and other processor cores within the system-on-a-chip integrated circuit. Graphics microcontroller 2138 is a programmable sub-processor that may be configured to manage various functions of graphics processor core 2100, including thread dispatch, scheduling, and preemption. Media pipeline 2139 (e.g., media pipeline 1916 of fig. 19 and 20) includes logic to facilitate decoding, encoding, pre-processing, and/or post-processing of multimedia data, including image and video data. The media pipeline 2139 implements media operations via requests to the computational or sampling logic within the sub-cores 2101-2101F.

In one embodiment, SoC interface 2137 enables graphics processor core 2100 to communicate with a general purpose application processor core (e.g., CPU) and/or other components within the SoC, including memory hierarchy elements such as shared last level cache memory, system RAM, and/or embedded on-chip or on-package DRAM. SoC interface 2137 may also enable communication with fixed-function devices within the SoC, such as camera imaging pipelines, and enable the use and/or implementation of global memory atoms that may be shared between graphics processor core 2100 and the CPUs within the SoC. SoC interface 2137 may also enable power management control of graphics processor core 2100 and enable interfaces between the clock domains of graphics core 2100 and other clock domains within the SoC. In one embodiment, SoC interface 2137 enables receiving a command buffer from a command streamer and a global thread dispatcher, which is configured to provide commands and instructions to each of one or more graphics cores in a graphics processor. Commands and instructions may be dispatched to the media pipeline 2139 when media operations are to be performed, or to the geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 2136, geometry and fixed function pipeline 2114) when graphics processing operations are to be performed.

Graphics microcontroller 2138 may be configured to perform various scheduling and management tasks for graphics processor core 2100. In one embodiment, the graphics microcontroller 2138 may execute graphics and/or compute workload scheduling on various graphics parallel engines in the Execution Unit (EU) arrays 2102A-2102F, 2104A-2104F within the sub-cores 2101A-2101F. In this scheduling model, host software executing on a CPU core of an SoC that includes graphics processor core 2100 may submit a workload to one of multiple graphics processor doorbell that will invoke a scheduling operation on the appropriate graphics engine. The scheduling operation includes: determining which workload to run next, submitting the workload to a command flow propagator, preempting an existing workload running on an engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In one embodiment, graphics microcontroller 2138 may also facilitate a low power or idle state of graphics processor core 2100, thereby providing graphics processor core 2100 with the ability to save and restore registers within graphics processor core 2100 across low power state transitions, independent of the operating system and/or graphics driver software on the system.

Graphics processor core 2100 may have more or fewer sub-cores than the illustrated sub-cores 2101A-2101F, up to a maximum ofNA modular sub-core. For each groupNPer sub-core, graphics processor core 2100 may also include shared function logic 2110, shared and/or cache memory 2112, geometry/fixed function pipeline 2114, and additional fixed function logic 2116 to accelerate various graphics and computing processing operations. Shared function logic 2110 may include logic units associated with shared function logic 2020 of fig. 20 (e.g., samplers, math and/or inter-thread communication logic) that may be utilized by each within graphics processor core 2100NAnd sharing the sub-cores. The shared and/or cache memory 2112 may be the set in the graphics processor core 2100NThe last level cache of the individual sub-cores 2101A-2101F, and may also act as a shared memory, which may be accessed by multiple sub-cores. Geometry-The fixed function pipeline 2114 may be contained in a fixed function block 2130 instead of a geometry/fixed function pipeline 2136 and may contain the same or similar logic elements.

In one embodiment, graphics processor core 2100 includes additional fixed function logic 2116, which may include various fixed function acceleration logic for use by graphics processor core 2100. In one embodiment, additional fixed function logic 2116 includes additional geometry pipelines for use in location-only shading. In position-only shading, there are two geometry pipelines, namely a full geometry pipeline and a picking pipeline in geometry/fixed function pipelines 2116, 2136, the picking pipeline being an additional geometry pipeline that may be included in additional fixed function logic 2116. In one embodiment, the picking pipeline is a reduced version of a full geometry pipeline. The full pipeline and the culling pipeline may execute different instances of the same application, each instance having a separate context. Location-only shading may hide long pick runs of discarded triangles to enable shading to be done ahead of time in some instances. For example, and in one embodiment, the pick pipeline logic in the additional fixed function logic 2116 may execute a position shader in parallel with the host application and generally generate critical results faster than a full pipeline, because the pick pipeline only fetches and colors the position attributes of vertices, and does not perform rasterization and rendering on pixels to the frame buffer. The culling pipeline may use the generated critical results to calculate visibility information for all triangles regardless of whether the triangles were culled. The full pipeline (which in this case may be referred to as a replay pipeline) may consume visibility information to skip culled triangles and only paint visible triangles that are eventually passed to the rasterization stage.

In one embodiment, the additional fixed function logic 2116 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementation of optimizations including machine learning training or reasoning.

Within each graphics sub-core 2101A-2101F, a set of execution resources is included that may be used to perform graphics, media, and computational operations in response to requests by a graphics pipeline, media pipeline, or shader program. The graphics sub-cores 2101A-2101F include a plurality of EU arrays 2102A-2102F, 2104A-2104F, thread dispatch and inter-thread communication (TD/IC) logic 2103A-2103F, 3D (e.g., texture) samplers 2105A-2105F, media samplers 2106A-2106F, shader processors 2107A-2107F, and Shared Local Memory (SLM) 2108A-2108F. The EU arrays 2102A-2102F, 2104A-2104F each include a plurality of execution units, which are general purpose graphics processing units capable of performing floating point and integer/fixed point logic operations in the services of graphics, media, or computing operations, including graphics, media, or compute shader programs. The TD/IC logic 2103A-2103F performs local thread dispatch and thread control operations for execution units within the sub-cores and facilitates communication between threads executing on the execution units of the sub-cores. 3D samplers 2105A-2105F may read texture or other 3D graphics related data into memory. The 3D sampler may read texture data differently based on the configured sampling state and the texture format associated with a given texture. Media samplers 2106A-2106F may perform similar read operations based on the type and format associated with the media data. In one embodiment, each graphics sub-core 2101A-2101F may alternatively comprise a unified 3D and media sampler. Threads executing on execution units within each of the sub-cores 2101A-2101F may utilize shared local memory 2108A-2108F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.

Execution unit

22A-22B illustrate thread execution logic 2200 that includes an array of processing elements employed in a graphics processor core according to embodiments described herein. Elements in fig. 22A-22B having the same reference numbers (or names) as elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not so limited. FIG. 22A illustrates an overview of thread execution logic 2200, which may include variations from the hardware logic illustrated by each of the sub-cores 2101A-2101F of FIG. 21. FIG. 22B shows exemplary internal details of an execution unit.

As shown in fig. 22A, in some embodiments, thread execution logic 2200 includes shader processor 2202, thread dispatcher 2204, instruction cache 2206, scalable execution unit array (including multiple execution units 2208A-2208N), sampler 2210, data cache 2212, and data port 2214. In one embodiment, the scalable array of execution units may be dynamically scaled by enabling or disabling one or more execution units (e.g., any of execution units 2208A, 2208B, 2208C, 2208D-2208N-1 and 2208N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnection fabric linked to each of the components. In some embodiments, thread execution logic 2200 includes one or more connections to memory (e.g., system memory or cache memory) through one or more of instruction cache 2206, data port 2214, sampler 2210, and execution units 2208A-2208N. In some embodiments, each execution unit (e.g., 2208A) is an independently programmable general purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the execution unit arrays 2208A-2208N are scalable to include any number of individual execution units.

In some embodiments, execution units 2208A-2208N are primarily used to execute shader programs. Shader processor 2202 can process various shader programs and dispatch threads of execution associated with the shader programs via thread dispatcher 2204. In one embodiment, the thread dispatcher includes logic to arbitrate thread initiation requests from the graphics and media pipelines and to instantiate the requested thread on one or more of the execution units 2208A-2208N. For example, the geometry pipeline may dispatch vertices, tessellations, or geometry shaders to thread execution logic for processing. In some embodiments, thread dispatcher 2204 may also process runtime thread generation requests from executing shader programs.

In some embodiments, execution units 2208A-2208N support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct3D and OpenGL) are executed with minimal translation. Execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general purpose processing (e.g., compute and media shaders). Each of the execution units 2208A-2208N is capable of multiple issue Single Instruction Multiple Data (SIMD) execution and multithreaded operations enable an efficient execution environment for higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high bandwidth register file and associated independent thread state. Execution is multiple per clock to a pipeline capable of integer, single and double precision floating point operations, SIMD branch capability, logical operations, override operations, and other miscellaneous operations. While waiting for data from one of the memory or shared functions, dependency logic within execution units 2208A-2208N causes the waiting thread to sleep until the requested data has returned. While waiting for a thread to be sleeping, the hardware resources may be dedicated to processing other threads. For example, during a delay associated with vertex shader operations, the execution unit may perform operations on a pixel shader, a fragment shader, or another type of shader program (which includes a different vertex shader). As an alternative to or in addition to using SIMD, various embodiments may be applied to using execution by using Single Instruction Multiple Threads (SIMT). References to SIMD cores or operations may also be applied to SIMT or to a combination of SIMD and SIMT.

Each of execution units 2208A-2208N operates on an array of data elements. The number of data elements is the "execution size" or number of lanes for the instruction. An execution channel is a logical unit for the execution of data element access, masking, and flow control within an instruction. The number of channels may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In some embodiments, execution units 2208A-2208N support both integer and floating point data types.

The execution unit instruction set includes SIMD instructions. Various data elements may be stored as packed data types in registers, and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four separate 64-bit packed data elements (data elements of a Quadword (QW) size), eight separate 32-bit packed data elements (data elements of a double word length (DW) size), sixteen separate 16-bit packed data elements (data elements of a word length (W) size), or thirty-two separate 8-bit data elements (data elements of a byte (B) size). However, different vector widths and register sizes are possible.

In one embodiment, one or more execution units may be combined into a fused execution unit 2209A-2209N having thread control logic (2207A-2207N) common to the fused EU. Multiple EUs can be fused into an EU group. Each EU in the fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in the fused EU group may vary according to the embodiment. In addition, various SIMD widths may be performed for each EU, including but not limited to SIMD8, SIMD16, and SIMD 32. Each fused graphics execution unit 2209A-2209N includes at least two execution units. For example, the fused execution unit 2209A includes a first EU 2208A, a second EU 2208B, and thread control logic 2207A common to the first EU 2208A and the second EU 2208B. The thread control logic 2207A controls threads executing on the fused graphics execution unit 2209A to allow each EU in the fused execution units 2209A-2209N to execute using a common instruction pointer register.

One or more internal instruction caches (e.g., 2206) are included in thread execution logic 2200 to cache thread instructions for execution units. In some embodiments, one or more data caches (e.g., 2212) are included to cache thread data during thread execution. In some embodiments, sampler 2210 is included to provide texture samples for 3D operations and media samples for media operations. In some embodiments, sampler 2210 includes specialized texture or media sampling functionality to process texture or media data during the sampling process prior to providing the sampled data to the execution units.

During execution, the graphics and media pipeline sends thread initiation requests to thread execution logic 2200 via thread generation and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within pixel shader 2202 is invoked to further compute output information and cause writing of results to an output surface (e.g., a color buffer, a depth buffer, a stencil buffer, etc.). In some embodiments, a pixel shader or fragment shader computes values for various vertex attributes to be interpolated across rasterized objects. In some embodiments, pixel processor logic within shader processor 2202 then executes an Application Programming Interface (API) supplied pixel or fragment shader program. To execute shader programs, shader processor 2202 dispatches threads to execution units (e.g., 2208A) via thread dispatcher 2204. In some embodiments, the pixel shader 2202 uses texture sampling logic in the sampler 2210 to access texture data in a texture map stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric segment, or discard one or more pixels from further processing.

In some embodiments, data port 2214 provides a memory access mechanism for causing thread execution logic 2200 to output processed data to memory for further processing on a graphics processor output pipeline. In some embodiments, data port 2214 includes or is coupled to one or more cache memories (e.g., data cache 2212) to cache data for memory access via the data port.

As shown in fig. 22B, graphics execution unit 2208 may include an instruction fetch unit 2237, a general register file array (GRF) 2224, an architectural register file Array (ARF) 2226, a thread arbiter 2222, a dispatch unit 2230, a branch unit 2232, a set of SIMD Floating Point Units (FPUs) 2234, and in one embodiment, a set of dedicated integer SIMD ALUs 2235. The GRF 2224 and ARF 2226 comprise a set of general purpose register files and architectural register files associated with each synchronous hardware thread that is movable within the graphics execution unit 2208. In one embodiment, each thread architecture state is maintained in the ARF 2226, while data used during thread execution is stored in the GRF 2224. The execution state of each thread (including the instruction pointer of each thread) may be retained in thread-specific registers in the ARF 2226.

In one embodiment, the graphics execution unit 2208 has an architecture that is a combination of Simultaneous Multithreading (SMT) and fine-grained Interleaved Multithreading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on a target number of synchronous threads and a number of registers per execution unit, where execution unit resources are divided across logic for executing multiple synchronous threads.

In one embodiment, the graphics execution unit 2208 may collectively issue multiple instructions, each of which may be a different instruction. The thread arbiter 2222 of the graphics execution unit thread 2208 may dispatch the instruction to one of the issue unit 2230, branch unit 2232, or SIMD FPU(s) 2234 for execution. Each execution thread may access 128 general purpose registers in GRF 2224, where each register may store 32 bytes, which may be accessed as an 8-element vector of 32-bit data elements. In one embodiment, each execution unit thread has access to 4 Kbytes in GRF 2224, although embodiments are not so limited and in other embodiments more or less register resources may be provided. In one embodiment, up to seven threads may be executed simultaneously, although the number of threads per execution unit may vary depending on the embodiment. In an embodiment where seven threads may access 4 Kbytes, GRF 2224 may store a total of 28 Kbytes. The flexible addressing scheme may allow registers to be addressed together, effectively building wider registers or representing a strided rectangular block data structure.

In one embodiment, memory operations, sampler operations, and other longer latency system communications are dispatched via "send" instructions, which are executed by message passing send unit 2230. In one embodiment, branch instructions are dispatched to a dedicated branch unit 2232 to facilitate SIMD divergence and eventual convergence.

In one embodiment, graphics execution unit 2208 includes one or more SIMD floating point units ((one or more) FPUs) 2234 to perform floating point operations. In one embodiment, FPU(s) 2234 also support integer computations. In one embodiment, FPU(s) 2234 may execute up to SIMDM32-bit floating-point (or integer) operations, or SIMD performs up to 2MA 16-bit integer or 16-bit floating point operation. In one embodiment, at least one FPU provides extended mathematical capabilities to support high throughput transcendental mathematical functions and double precision 64-bit floating points. In some embodiments, there is also a set of 8-bit integer SIMD ALUs 2235, and they may be specifically optimized to perform operations associated with machine learning computations.

In one embodiment, an array of multiple instances of graphics execution unit 2208 may be instantiated in a graphics sub-core grouping (e.g., a sub-slice). For scalability, the product architect may select the exact number of execution units per sub-core grouping. In one embodiment, execution unit 2208 may execute instructions across multiple execution lanes. In further embodiments, each thread executing on the graphics execution unit 2208 executes on a different channel.

Fig. 23 is a block diagram illustrating a graphics processor instruction format 2300, according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. The solid line boxes show components that are typically included in an execution unit instruction, while the dashed lines include components that are optional or included only in a subset of instructions. In some embodiments, the instruction format 2300 depicted and described is macro-instructions in that they are instructions supplied to an execution unit, as opposed to micro-operations that result from instruction decoding (once the instruction is processed).

In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit instruction format 2310. The 64-bit compact instruction format 2330 is available for some instructions based on the instruction selected, the instruction options, and the number of operands. Native 128-bit instruction format 2310 provides access to all instruction options, while some options and operations are restricted to 64-bit format 2330. Native instructions available in 64-bit format 2330 vary depending on the embodiment. In some embodiments, the instructions are partially compressed using a set of index values in the index field 2313. The execution unit hardware references a set of compact tables based on these index values and uses the compact table outputs to reconstruct the native instructions in a 128-bit instruction format 2310. Other sizes and formats of instructions may be used.

For each format, instruction opcode 2312 defines the operation to be performed by the execution unit. An execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel representing a texel or a picture element. The execution unit defaults to executing each instruction across all data lanes of operands. In some embodiments, instruction control field 2314 enables control of certain execution options such as channel selection (e.g., prediction) and data channel rank (e.g., deployment). For instructions in the 128-bit instruction format 2310, the execution size (exec-size) field 2316 limits the number of data lanes to be executed in parallel. In some embodiments, the execution size field 2316 is not available for use with the 64-bit compact instruction format 2330.

Some execution unit instructions have up to three operands, including two source operands, src 02320, src 12322, and one destination 2318. In some embodiments, the execution unit supports dual destination instructions, where one of these destinations is implicit. The data manipulation instruction may have a third source operand (e.g., SRC 22324), where the instruction opcode 2312 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed through the instruction.

In some embodiments, 128-bit instruction format 2310 includes an access/addressing mode field 2326 that specifies whether a direct register addressing mode or an indirect register addressing mode is used, for example. When the direct register addressing mode is used, the register addresses of one or more operands are provided directly by bits in the instruction.

In some embodiments, 128-bit instruction format 2310 includes an access/addressing mode field 2326 that specifies the addressing mode and/or access mode for the instruction. In one embodiment, the access pattern is used to define data access alignment for the instruction. Some embodiments support access patterns that include 16-byte aligned access patterns and 1-byte aligned access patterns, where the byte alignment of the access patterns determines the access alignment of instruction operands. For example, when in the first mode, the instruction may use byte aligned addressing for the source operand and the destination operand, and when in the second mode, the instruction may use 16 byte aligned addressing for all of the source operand and the destination operand.

In one embodiment, the addressing mode portion of access/addressing mode field 2326 determines whether the instruction will use direct addressing or indirect addressing. When using the direct register addressing mode, bits in the instruction directly provide the register address of one or more operands. When an indirect register addressing mode is used, register addresses for one or more operands may be calculated based on an address immediate field and an address register value in the instruction.

In some embodiments, instructions are grouped based on opcode 2312 bit fields to simplify opcode decoding 2340. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The exact operation code groupings shown are examples only. In some embodiments, the move and logical opcode group 2342 includes data move and logical instructions (e.g., move (mov), compare (cmp)). In some embodiments, move and logical group 2342 shares the five Most Significant Bits (MSBs), with a move (mov) instruction taking the form 0000 xxxxxxb and a logical instruction taking the form 0001 xxxxb. A group of flow control instructions 2344 (e.g., call, jump (jmp)) includes instructions in the form 0010 xxxxxxb (e.g., 0x 20). Miscellaneous instruction group 2346 includes a mixture of instructions that includes synchronous instructions (e.g., wait, issue) in the form 0011 xxxxxxb (e.g., 0x 30). The parallel mathematical instruction group 2348 includes component-by-component arithmetic instructions (e.g., add, multiply (mul)) in the form 0100 xxxxx (e.g., 0x 40). Parallel math group 2348 performs arithmetic operations in parallel across data lanes. Vector math group 2350 includes arithmetic instructions (e.g., dp 4) in the form 0101 xxxxx (e.g., 0x 50). The vector math group performs arithmetic such as dot product calculations on vector operands.

Graphics pipeline

FIG. 24 is a block diagram of another embodiment of a graphics processor 2400. Elements in fig. 24 having the same reference numbers (or names) as elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

In some embodiments, graphics processor 2400 includes geometry pipeline 2420, media pipeline 2430, display engine 2440, thread execution logic 2450, and rendering output pipeline 2470. In some embodiments, graphics processor 2400 is a graphics processor within a multi-core processing system that includes one or more general purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to the graphics processor 2400 via the ring interconnect 2402. In some embodiments, ring interconnect 2402 couples graphics processor 2400 to other processing components, such as other graphics processors or general purpose processors. Commands from ring interconnect 2402 are interpreted by command streamer 2403, which supplies instructions to individual components of geometry pipeline 2420 or media pipeline 2430.

In some embodiments, command streamer 2403 directs the operation of vertex fetcher (fetcher) 2405, which reads vertex data from memory and executes vertex processing commands provided by command streamer 2403. In some embodiments, vertex fetcher 2405 provides vertex data to vertex shader 2407, which performs coordinate space transformations and lighting operations on each vertex. In some embodiments, vertex fetcher 2405 and vertex shader 2407 execute vertex processing instructions by dispatching execution threads to execution units 2452A-2452B via thread dispatcher 2431.

In some embodiments, execution units 2452A-2452B are an array of vector processors having instruction sets for performing graphics and media operations. In some embodiments, execution units 2452A-2452B have an L1 cache 2451 specific to each array or the attachment shared between the arrays. The cache may be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

In some embodiments, geometry pipeline 2420 includes a tessellation component to perform hardware accelerated tessellation of 3D objects. In some embodiments, the programmable hull shader 2411 configures tessellation operations. The programmable domain shader 2417 provides back-end evaluation of the tessellation output. The tessellator 2413 operates in the direction of the hull shader 2411 and contains specialized logic for generating a detailed set of geometric objects based on a coarse geometry model that is provided as input to a geometry pipeline 2420. In some embodiments, if tessellation is not used, tessellation components (e.g., hull shader 2411, tessellator 2413, and domain shader 2417) may be bypassed.

In some embodiments, a complete geometric object may be processed by the geometry shader 2419 via one or more threads dispatched to the execution units 2452A-2452B, or may proceed directly to the clipper 2429. In some embodiments, the geometry shader operates on the entire geometry object rather than on patches or vertices as vertices in a previous stage of the graphics pipeline. If tessellation is disabled, the geometry shader 2419 receives input from the vertex shader 2407. In some embodiments, if the tessellation unit is disabled, the geometry shader 2419 may be programmed by a geometry shader program to perform geometry tessellation.

Prior to rasterization, a clipper 2429 processes the vertex data. Clipper 2429 may be a fixed function clipper or a programmable clipper with clipping and geometry shader functions. In some embodiments, a rasterizer and depth test component 2473 in rendering output pipeline 2470 dispatches pixel shaders to convert geometric objects to a per-pixel representation. In some embodiments, pixel shader logic is included in thread execution logic 2450. In some embodiments, the application may bypass the rasterizer and depth test component 2473 and access the un-rasterized vertex data via a stream out unit (stream out unit) 2423.

Graphics processor 2400 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed among the main components of the processor. In some embodiments, execution units 2452A-2452B and associated logic units (e.g., L1 cache 2451, sampler 2454, texture cache 2458, etc.) are interconnected via data port 2456 to perform memory accesses and communicate with the rendering output pipeline components of the processor. In some embodiments, sampler 2454, L1 cache 2451, texture cache 2458, and execution units 2452A-2452B each have separate memory access paths. In one embodiment, texture cache 2458 may also be configured as a sample cache.

In some embodiments, the rendering output pipeline 2470 includes a rasterizer and depth test component 2473 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower (window)/masker unit for performing fixed-function triangle and line rasterization. An associated render cache 2478 and depth cache 2479 may also be available in some embodiments. The pixel operations component 2477 performs pixel-based operations on the data, although in some examples, pixel operations associated with 2D operations (e.g., bit block images are transmitted with blending) are performed by the 2D engine 2441 or replaced at display time by the display controller 2443 using overlapping display planes. In some embodiments, the shared L3 cache 2475 may be used for all graphics components, allowing data to be shared without the use of main system memory.

In some embodiments, the graphics processor media pipeline 2430 includes a media engine 2437 and a video front end 2434. In some embodiments, video front end 2434 receives pipeline commands from command streamer 2403. In some embodiments, media pipeline 2430 includes a separate command streamer. In some embodiments, the video front end 2434 processes the media commands before sending the commands to the media engine 2437. In some embodiments, the media engine 2437 includes thread generation functionality for generating threads for dispatch to the thread execution logic 2450 via a thread dispatcher 2431.

In some embodiments, graphics processor 2400 includes a display engine 2440. In some embodiments, display engine 2440 is external to processor 2400 and is coupled with the graphics processor via ring interconnect 2402, or some other interconnect bus or fabric. In some embodiments, the display engine 2440 includes a 2D engine 2441 and a display controller 2443. In some embodiments, display engine 2440 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2443 is coupled with a display device (not shown), which may be a system-integrated display device (as in a laptop computer) or may be an external display device attached via a display device connector.

In some embodiments, geometry pipeline 2420 and media pipeline 2430 may be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one Application Programming Interface (API). In some embodiments, driver software for the graphics processor translates API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for an open graphics library (OpenGL), open computing language (OpenCL), and/or Vulkan graphics and computing APIs all from the kornas Group (khonos Group). In some embodiments, support may also be provided for the Direct3D library from microsoft corporation. In some embodiments, a combination of these libraries may be supported. Support may also be provided for an open source computer vision library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if a mapping from the pipeline of the future API to the pipeline of the graphics processor can be made.

Graphics pipeline programming

Fig. 25A is a block diagram illustrating a graphics processor command format 2500, according to some embodiments. FIG. 25B is a block diagram illustrating a graphics processor command sequence 2510, according to an embodiment. The solid line boxes in FIG. 25A show components that are typically included in graphics commands, while the dashed lines include components that are optional or included only in a subset of graphics commands. The exemplary graphics processor command format 2500 of FIG. 25A includes data fields for identifying a client 2502 of a command, a command operation code (opcode) 2504, and data 2506. Also included in some commands are a subopcode 2505 and a command size 2508.

In some embodiments, client 2502 specifies a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser (parser) examines the client field of each command to coordinate further processing of the command and to route the command data to the appropriate client unit. In some embodiments, a graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes commands. Once the command is received by the client unit, the client unit reads the operation code 2504 and, if present, the sub-operation code 2505 to determine the operation to perform. The client unit uses the information in data field 2506 to execute the command. For some commands, an explicit command size 2508 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, the commands are aligned via multiples of double the word length. Other command formats may be used.

The flowchart in FIG. 25B illustrates an exemplary graphics processor command sequence 2510. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses the illustrated version of the command sequence to set up, execute, and terminate a set of graphics operations. Sample command sequences are shown and described for purposes of example only, as embodiments are not limited to these particular commands or this sequence of commands. Further, the commands may be issued as a batch of commands in a command sequence such that the graphics processor will process the command sequence in an at least partially simultaneous manner.

In some embodiments, the graphics processor command sequence 2510 may begin with a pipeline flush command 2512 to cause any active graphics pipeline to complete a currently pending command for that pipeline. In some embodiments, 3D pipeline 2522 and media pipeline 2524 do not operate concurrently. The execution pipeline is flushed to have the active graphics pipeline complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will halt command processing until the active drawing engine completes the pending operation and the associated read cache is invalidated. Alternatively, any data in the render cache marked 'dirty' may be flushed to memory. In some embodiments, a pipeline flush command 2512 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

In some embodiments, the pipeline select command 2513 is used when the command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, the pipeline select command 2513 is only required once within the execution context before issuing the pipeline command unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush command 2512 is required immediately prior to a pipeline switch via a pipeline select command 2513.

In some embodiments, pipeline control commands 2514 configure a graphics pipeline for operation and are used to program 3D pipeline 2522 and media pipeline 2524. In some embodiments, the pipeline control command 2514 configures the pipeline state for the active pipeline. In one embodiment, the pipeline control commands 2514 are used for pipeline synchronization and to flush data from one or more cache memories within the active pipeline before processing a batch of commands.

In some embodiments, a set of return buffers for the respective pipeline to write data is configured using a command to configure return buffer status 2516. Some pipelining operations require allocation, selection, or configuration of one or more return buffers into which the operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communications. In some embodiments, the return buffer status 2516 includes a selection of the size and number of return buffers to use for a set of pipelined operations.

The remaining commands in the command sequence differ based on the active pipeline used for the operation. Based on the pipeline determination 2520, the command sequence is customized for either the 3D pipeline 2522 or the media pipeline 2524, the 3D pipeline starting in a 3D pipeline state 2530, the media pipeline starting in a media pipeline state 2540.

The commands to configure the 3D pipeline state 2530 include 3D state set commands for: vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables to be configured prior to processing the 3D primitive command. The values of these commands are determined based at least in part on the particular 3D API in use. In some embodiments, the 3D pipeline state 2530 commands can also selectively disable or bypass certain pipeline elements if those elements are not to be used.

In some embodiments, the 3D primitive 2532 command is used to submit a 3D primitive for processing by the 3D pipeline. Commands and associated parameters passed to the graphics processor via the 3D primitive 2532 commands are forwarded to a take vertex function in the graphics pipeline. The take vertex function uses the 3D primitive 2532 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 2532 commands are used to perform vertex operations on the 3D primitive via a vertex shader. To process the vertex shader, 3D pipeline 2522 dispatches the shader execution threads to the graphics processor execution units.

In some embodiments, the 3D pipeline 2522 is triggered via the execution 2534 of a command or event. In some embodiments, the register write triggers the command execution. In some embodiments, execution is triggered via a 'go (go)' or 'kick (kick)' command in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution to flush a command sequence through a graphics pipeline. The 3D pipeline will perform geometric processing for the 3D primitives. Once the operation is complete, the resulting geometric object is rasterized and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel back-end operations may also be included for those operations.

In some embodiments, graphics processor command sequence 2510 follows the media pipeline 2524 path when performing media operations. In general, the manner in which and the particular use of programming for media pipeline 2524 depends on the media or computing operations to be performed. During media decoding, certain media decoding operations may be offloaded to the media pipeline. In some embodiments, the media pipeline may also be bypassed and media decoding may be performed in whole or in part (using resources provided by one or more general purpose processing cores). In one embodiment, the media pipeline further comprises elements for General Purpose Graphics Processor Unit (GPGPU) operations, wherein the graphics processor is to perform SIMD vector operations using a compute shader program that is not explicitly related to the rendering of graphics primitives.

In some embodiments, media pipeline 2524 is configured in a similar manner as 3D pipeline 2522. A set of commands that configure media pipeline state 2540 are dispatched or placed into a command queue prior to media object command 2542. In some embodiments, the commands of media pipeline state 2540 include data to configure the media pipeline elements that will be used to process the media objects. This includes data (such as encoding or decoding formats) for configuring video decoding and video encoding logic within the media pipeline. In some embodiments, the commands of media pipeline state 2540 also support the use of one or more pointers to "indirect" state elements containing a collection of state settings.

In some embodiments, media object command 2542 supplies a pointer to the media object for processing by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all of the media pipeline state must be valid before issuing media object command 2542. Once the pipeline state is configured and the media object command 2542 is queued, the media pipeline 2524 is triggered via an execute command 2544 or equivalent execute event (e.g., a register write). The output from media pipeline 2524 may then be post-processed by operations provided by 3D pipeline 2522 or media pipeline 2524. In some embodiments, GPGPU operations are configured and performed in a similar manner as media operations.

Graphics software architecture

FIG. 26 illustrates an exemplary graphics software architecture for data processing system 2600 in accordance with some embodiments. In some embodiments, the software architecture includes a 3D graphics application 2610, an operating system 2620, and at least one processor 2630. In some embodiments, the processor 2630 includes a graphics processor 2632 and one or more general purpose processor cores 2634. Graphics application 2610 and operating system 2620 each execute in system memory 2650 of the data processing system.

In some embodiments, the 3D graphics application 2610 includes one or more shader programs, including shader instructions 2612. The shader language instructions may employ a high level shader language, such as High Level Shader Language (HLSL) of Direct3D, OpenGL shader language (GLSL), and so forth. The application also includes executable instructions 2614 in a machine language suitable for execution by the general purpose processor core 2634. The application also includes a graphical object 2616 defined by vertex data.

In some embodiments, the operating system 2620 is Microsoft Windows ® operating system, a proprietary UNIX operating system, or an open source UNIX operating system from Microsoft corporation that uses a variation of the Linux kernel. The operating system 2620 may support a graphics API 2622, such as a Direct3D API, an OpenGL API, or a Vulkan API. When the Direct3D API is in use, the operating system 2620 uses a front-end shader compiler 2624 to compile any shader instructions 2612 that employ HLSL into a lower-level shader language. The compilation may be a just-in-time (JIT) compilation or the application may execute a shader precompilation. In some embodiments, during compilation of the 3D graphics application 2610, a high-level shader is compiled into a low-level shader. In some embodiments, shader instructions 2612, e.g., a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API, are provided in an intermediate form.

In some embodiments, the user-mode graphics driver 2626 includes a back-end shader compiler 2627 to convert the shader instructions 2612 into a hardware-specific representation. When the OpenGL API is in use, shader instructions 2612 in the GLSL high-level language are passed to user mode graphics driver 2626 for compilation. In some embodiments, the user mode graphics driver 2626 communicates with a kernel mode graphics driver 2629 using operating system kernel mode functions 2628. In some embodiments, the kernel mode graphics driver 2629 communicates with the graphics processor 2632 to dispatch commands and instructions.

IP check cash

One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium which represents and/or defines logic within an integrated circuit such as a processor. For example, a machine-readable medium may include instructions representing various logic within a processor. When read by a machine, the instructions may cause the machine to fabricate logic to perform the techniques described herein. Such representations (referred to as "IP cores") are reusable units of logic for an integrated circuit that may be stored on tangible, machine-readable media as hardware models that describe the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities that load the hardware model on the manufacturing machines that manufacture the integrated circuits. An integrated circuit may be fabricated such that the circuit performs the operations described in association with any of the embodiments described herein.

Fig. 27A is a block diagram illustrating an IP core development system 2700 that may be used to fabricate integrated circuits to perform operations, according to an embodiment. IP core development system 2700 can be used to generate a modular, reusable design that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., an SOC integrated circuit). Design facility 2730 may generate software simulations 2710 of the IP core design in a high-level programming language (e.g., C/C + +). Software simulation 2710 may be used to design, test, and verify the behavior of an IP core using simulation model 2712. Simulation model 2712 may include functional, behavioral, and/or timing simulations. A Register Transfer Level (RTL) design 2715 may then be created or synthesized according to simulation model 2712. RTL design 2715 is an abstraction of behavior (abstraction) of an integrated circuit that models the flow of digital signals between hardware registers (including associated logic that is executed using the modeled digital signals). In addition to the RTL design 2715, lower level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation may vary.

RTL design 2715 or an equivalent may be further synthesized by the design facility into hardware model 2720, which may employ a Hardware Description Language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. Non-volatile memory 2740 (e.g., a hard disk, flash memory, or any non-volatile storage medium) may be used to store the IP core design for delivery to party 3 manufacturing facility 2765. Alternatively, the IP core design may be communicated (e.g., via the internet) over a wired connection 2750 or a wireless connection 2760. Manufacturing facility 2765 may then fabricate an integrated circuit based at least in part on the IP core design. The integrated circuit being fabricated may be configured to perform operations in accordance with at least one embodiment described herein.

Fig. 27B shows a cross-sectional side view of an integrated circuit package assembly 2770, according to some embodiments described herein. The integrated circuit package assembly 2770 illustrates an implementation of one or more processor or accelerator devices as described herein. The package assembly 2770 includes multiple units of hardware logic 2772, 2774 connected to a substrate 2780. The logic 2772, 2774 may be implemented at least in part in configurable logic or fixed function logic hardware, and may include one or more portions of any of the processor core(s), graphics processor(s), or other accelerator device described herein. Each element of logic 2772, 2774 may be implemented in a semiconductor die and coupled with substrate 2780 via interconnect structure 2773. Interconnect structure 2773 may be configured to route electrical signals between logic 2772, 2774 and substrate 2780, and may include interconnects such as, but not limited to, bumps or posts. In some embodiments, the interconnect structure 2773 may be configured to route electrical signals, such as, for example, input/output (I/O) signals and/or power or ground signals associated with operation of the logic 2772, 2774. In some embodiments, substrate 2780 is an epoxy-based laminate substrate. In other embodiments, substrate 2780 may comprise other suitable types of substrates. The package assembly 2770 may be connected to other electrical devices via package interconnects 2783. Package interconnect 2783 may be coupled to a surface of substrate 2780 to route electrical signals to other electrical devices, such as a motherboard, other chipset, or multi-chip module.

In some embodiments, the elements of logic 2772, 2774 are electrically coupled with bridge 2782, bridge 2782 being configured to route electrical signals between logic 2772, 2774. Bridge 2782 may be a dense interconnect structure that provides routing for electrical signals. Bridge 2782 may include a bridge substrate composed of glass or a suitable semiconductor material. Electrical routing features may be formed on the bridge substrate to provide chip-to-chip connections between the logics 2772, 2774.

Although two units of bridge 2782 and logic 2772, 2774 are shown, embodiments described herein may include more or fewer logic units on one or more dies. One or more dies may be connected by zero or more bridges, as bridges 2782 may be eliminated when logic is contained on a single die. Alternatively, multiple dies or logic units may be connected by one or more bridges. Additionally, multiple logic units, dies, and bridges may be connected together in other possible configurations, including three-dimensional configurations.

Exemplary System-on-a-chip Integrated Circuit

28-29 illustrate exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments described herein. Other logic and circuitry may be included in addition to that shown, including additional graphics processors/cores, peripheral interface controllers, or general purpose processor cores.

FIG. 28 is a block diagram illustrating an exemplary system on a chip integrated circuit 2800, which may be fabricated using one or more IP cores 2800, according to an embodiment. The exemplary integrated circuit 2800 includes one or more application processors 2805 (e.g., CPUs), at least one graphics processor 2810, and may additionally include an image processor 2815 and/or a video processor 2820, any of which may be modular IP cores from the same or multiple different design facilities. Integrated circuit 2800 includes peripheral or bus logic that includes USB controller 2825, UART controller 2830, SPI/SDIO controller 2835, and I²S/I²C controller 2840. Additionally, the integrated circuit may include a display device 2845 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2850 and a Mobile Industry Processor Interface (MIPI) display interface 2855. Storage may be provided by flash memory subsystem 2860 (including flash memory and flash memory controller). A memory interface may be provided via memory controller 2865 for accessing SDRAM orAn SRAM memory device. Some integrated circuits additionally include an embedded security engine 2870.

29A-29B are block diagrams illustrating exemplary graphics processors for use within a SoC according to embodiments described herein. Fig. 29A illustrates an exemplary graphics processor 2910 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. FIG. 29B illustrates an additional exemplary graphics processor 2940 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. The graphics processor 2910 of fig. 29A is an example of a low power graphics processor core. The graphics processor 2940 of FIG. 29B is an example of a high performance graphics processor core. Each of the graphics processors 2910, 2940 may be a variation of the graphics processor 2810 of fig. 28.

As shown in fig. 29A, the graphics processor 2910 includes a vertex processor 2905 and one or more fragment processors 2915A-2915N (e.g., 2915A, 2915B, 2915C, 2915D through 2915N-1, and 2915N). The graphics processor 2910 may execute different shader programs via separate logic, such that the vertex processor 2905 is optimized to perform operations of vertex shader programs, while one or more of the fragment processors 2915A-2915N perform fragment (e.g., pixel) shading operations of fragment or pixel shader programs. Vertex processor 2905 executes the vertex processing stages of the 3D graphics pipeline and generates primitive and vertex data. The fragment processor(s) 2915A-2915N use the primitives and vertex data generated by the vertex processor 2905 to generate frame buffers for display on a display device. In one embodiment, the fragment processor(s) 2915A-2915N are optimized to execute fragment shader programs as provided for in the OpenGL API, which may be used to perform similar operations as provided for in the Direct3D API.

The graphics processor 2910 additionally includes one or more Memory Management Units (MMUs) 2920A-2920B, cache(s) 2925A-2925B, and circuit interconnect(s) 2930A-2930B. The one or more MMUs 2920A-2920B provide virtual-to-physical address mapping to the graphics processor 2910 (which includes the vertex processor 2905 and/or the fragment processor(s) 2915A-2915N), which may reference vertex or image/texture data stored in memory in addition to vertex or image/texture data stored in one or more caches 2925A-2925B. In one embodiment, one or more of the MMUs 2920A-2920B may be synchronized with other MMUs within the system, including one or more MMUs associated with one or more of the application processor 2805, image processor 2815, and/or video processor 2820 of FIG. 28, such that each processor 2805 and 2820 may participate in a shared or unified virtual memory system. According to an embodiment, one or more circuit interconnects 2930A-2930B enable the graphics processor 2910 to interface with other IP cores within the SoC via the SoC's internal bus or via a direct connection.

As shown in FIG. 29B, the graphics processor 2940 includes one or more MMUs 2920A-2920B, cache(s) 2925A-2925B and circuit interconnect(s) 2930A-2930B of the graphics processor 2910 of FIG. 29A. The graphics processor 2940 includes one or more shader cores 2955A-2955N (e.g., 2955A, 2955B, 2955C, 2955D, 2955E, 2955F through 2955N-1 and 2955N) that provide a unified shader core architecture in which a single core or type of core may execute all types of programmable shader code (including shader program code) to implement a vertex shader, a fragment shader, and/or a compute shader. The exact number of shader cores present may vary between embodiments and implementations. Additionally, graphics processor 2940 includes an inter-core task manager 2945 that acts as a thread dispatcher to accelerate blocking operations for tile-based rendering to one or more shader cores 2955A-2955N and blocking unit 2958, where rendering operations for a scene are subdivided in image space, e.g., to exploit local spatial coherence within the scene or to optimize internal cache usage.

The following relates to further examples.

Example 1 is an apparatus comprising a processor to: receiving a virtual address that triggered a page fault of a computing process; checking virtual memory space for a virtual memory allocation, the virtual memory allocation being for the computing process that triggered the page fault; and managing the page fault according to one of: a first protocol in response to determining that the virtual address that triggered the page fault is the last page in the virtual memory allocation for the computing process, or a second protocol in response to determining that the virtual address that triggered the page fault is not the last page in the virtual memory allocation for the computing process.

In example 2, the subject matter of example 1 can optionally include a processor to allocate and map a predetermined number of pages in the virtual memory space for the computing process that triggered the page fault.

In example 3, the subject matter of any one of examples 1-2, wherein the predetermined number of pages begins from the virtual address that triggered the page fault.

In example 4, the subject matter of any of examples 1-3 can optionally include the processor to update a page table in the virtual memory space.

In example 5, the subject matter of any of examples 1-4 can optionally include the processor to store in the memory a page fault event data record including the process identifier, the virtual memory address, and the timestamp.

In example 6, the subject matter of any of examples 1-5 can optionally include the processor to: constructing a time series dataset from a series of page fault event data records stored in memory; generating a predicted page fault based on an analysis of the time series data; and preemptively retrieving data into virtual memory based on the predicted page fault.

In example 7, the subject matter of any of examples 1-6 can optionally include the arrangement wherein the processor is embedded in a memory management unit.

Example 8 is a method, comprising: receiving a virtual address that triggered a page fault of a computing process; checking virtual memory space for a virtual memory allocation, the virtual memory allocation being for the computing process that triggered the page fault; and managing the page fault according to one of: a first protocol in response to determining that the virtual address that triggered the page fault is the last page in the virtual memory allocation for the computing process, or a second protocol in response to determining that the virtual address that triggered the page fault is not the last page in the virtual memory allocation for the computing process.

In example 9, the subject matter of example 8 can optionally include allocating and mapping a predetermined number of pages in the virtual memory space for the computing process that triggered the page fault.

In example 10, the subject matter of any one of examples 8-9, wherein the predetermined number of pages starts from the virtual address that triggered the page fault.

In example 11, the subject matter of any of examples 8-10 can optionally include updating a page table in the virtual memory space.

In example 12, the subject matter of any of examples 8-11 can optionally include storing, in memory, a page fault event data record, the page fault event data record including a process identifier, a virtual memory address, and a timestamp.

In example 13, the subject matter of any of examples 8-12 may optionally include: constructing a time series dataset from a series of page fault event data records stored in memory; generating a predicted page fault based on an analysis of the time series data; and preemptively retrieving data into virtual memory based on the predicted page fault.

In example 14, the subject matter of any of examples 8-13 can optionally include the arrangement wherein the processor is embedded in a memory management unit.

Example 15 is a non-transitory computer-readable medium comprising instructions that, when executed by a processor, configure the processor to: receiving a virtual address that triggered a page fault of a computing process; checking virtual memory space for a virtual memory allocation, the virtual memory allocation being for the computing process that triggered the page fault; and managing the page fault according to one of: a first protocol in response to determining that the virtual address that triggered the page fault is the last page in the virtual memory allocation for the computing process, or a second protocol in response to determining that the virtual address that triggered the page fault is not the last page in the virtual memory allocation for the computing process.

In example 16, the subject matter of example 15 can optionally include one or more instructions that when executed on the at least one processor configure the at least one processor to allocate and map a predetermined number of pages in the virtual memory space for the computing process that triggered the page fault.

In example 17, the subject matter of any one of examples 15 to 16, wherein the predetermined number of pages starts from the virtual address that triggered the page fault.

In example 18, the subject matter of any of examples 15-17 may optionally include one or more instructions that, when executed on the at least one processor, configure the at least one processor to update a page table in the virtual memory space.

In example 19, the subject matter of any of examples 15-18 can optionally include one or more instructions that when executed on the at least one processor configure the at least one processor to store in memory a page fault event data record, the page fault event data record including a process identifier, a virtual memory address, and a timestamp.

In example 20, the subject matter of any of examples 15-19 may optionally include one or more instructions that, when executed on the at least one processor, configure the at least one processor to.

In example 21, the subject matter of any of examples 15-20 can optionally include the arrangement wherein the processor is embedded in a memory management unit.

In various embodiments, the operations discussed herein (e.g., with reference to fig. 1-16) may be implemented as hardware (e.g., logic circuitry), software, firmware, or combinations thereof, which may be provided as a computer program product having stored thereon instructions (or software programs) used to program a computer to perform a process discussed herein, e.g., including a tangible (e.g., non-transitory) machine-readable or computer-readable medium. The machine-readable medium may include a storage device (such as those discussed with respect to fig. 1-16).

Additionally, such computer-readable media may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals provided in a carrier wave or other propagation medium via a communication link (e.g., a bus, a modem, or a network connection).

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, and/or characteristic described in connection with the embodiment can be included in at least an implementation. The appearances of the phrase "in one embodiment" in various places in the specification may or may not be all referring to the same embodiment.

Furthermore, in the description and claims, the terms "coupled" and "connected," along with their derivatives, may be used. In some embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.

Thus, although embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing the claimed subject matter.