阅读说明：本技术 一种基于文字运算的三值忆阻全加器电路 (Three-value memory resistance full adder circuit based on character operation ) 是由 林弥 韩琪 罗文瑶 陈俊杰 王旭亮 于 2021-06-28 设计创作，主要内容包括：本发明公开了一种基于文字运算的三值忆阻全加器电路,包括加数A输入模块、加数B输入模块、进位C-(in)输入模块、文字运算模块、SUM输出模块和进位C-(out)输出模块；其中,所述加数A输入模块与进位C-(in)输入模块相连,用于产生文字运算模块的输入X；所述SUM输出模块与加数B输入模块、文字运算模块相连,用于实现和的输出；所述进位C-(out)输出模块与文字运算模块、SUM输出模块相连,用于实现进位C-(out)的输出。(The invention discloses a three-value memristor full adder circuit based on character operation, which comprises an addend A input module, an addend B input module and a carry C in Input module, character operation module, SUM output module and carry C out An output module; wherein the addend A input module and the carry C in The input module is connected and used for generating an input X of the character operation module; the SUM output module is connected with the addend B input module and the character operation module and is used for realizing output of SUM; the carry bit C out The output module is connected with the character operation module and the SUM output module and is used for realizing carry C out To output of (c).)

1. A three-value memristor full adder circuit based on character operation is characterized by comprising an addend A input moduleAn addend B input module and a carry C_inInput module, character operation module, SUM output module and carry C_outAn output module; wherein the addend A input module and the carry C_inThe input module is connected and used for generating an input X of the character operation module; the SUM output module is connected with the addend B input module and the character operation module and is used for realizing output of SUM; the carry bit C_outThe output module is connected with the character operation module and the SUM output module and is used for realizing carry C_outTo output of (c).

2. The literal operation-based three-valued memristive full-adder circuit of claim 1, wherein the addend a input module comprises a first PMOS transistor M₁A second PMOS transistor M₂A third NMOS transistor M₃A fourth NMOS transistor M₄First resistance R₁A second resistor R₂A third resistor R₃And a DC voltage source V_DD1(ii) a Wherein the first PMOS transistor M₁A second PMOS transistor M₂A third NMOS transistor M₃And a fourth NMOS transistor M₄The grid electrodes of the grid electrodes are connected with a signal input end A; a first resistor R₁And a second resistor R₂One end of the DC voltage source is connected with a DC voltage source V_DD1(ii) a A first resistor R₁And the other end of the first PMOS transistor M₁The source electrodes of the two-way transistor are connected; a second resistor R₂And the other end of the first NMOS transistor M₃The drain electrodes of the two electrodes are connected; first PMOS transistor M₁Is connected to the second PMOS transistor M₂A source electrode of (a); second PMOS transistor M₂Is connected with a third resistor R₃One end of (a); third NMOS transistor M₃Is connected to the fourth NMOS transistor M₄A drain electrode of (1); fourth NMOS transistor M₄Is connected with a third resistor R₃The other end of the first and second electrodes is grounded; output terminal A¹Is a first PMOS transistor M₁And a second PMOS transistor M₂Is also the third NMOS transistor M₃And a fourth NMOS transistor M₄The connection point of (a).

3. The literal operation-based three-valued memristive full-adder circuit of claim 2, wherein the addend B input module comprises a fifth PMOS transistor M₅And a sixth NMOS transistor M₆Seventh PMOS transistor M₇And an eighth NMOS transistor M₈And a ninth NMOS transistor M₉The tenth NMOS transistor M₁₀Eleventh NMOS transistor M₁₁Twelfth PMOS transistor M₁₂A fourth resistor R₄A fifth resistor R₅A sixth resistor R₆A seventh resistor R₇And a DC voltage source V_DD2(ii) a Wherein the fifth PMOS transistor M₅And a sixth NMOS transistor M₆Seventh PMOS transistor M₇And an eighth NMOS transistor M₈And a ninth NMOS transistor M₉The grid electrodes of the grid electrodes are connected with a signal input end B; fifth PMOS transistor M₅And a twelfth PMOS transistor M₁₂Source electrode of (1), fourth resistor R₄And a sixth resistor R₆One end of the two-way valve is connected with a direct current voltage source V_DD2(ii) a Fifth PMOS transistor M₅Is connected to the sixth NMOS transistor M₆A drain electrode of (1); sixth NMOS transistor M₆Is connected with a seventh PMOS transistor M₇A source electrode of (a); a fourth resistor R₄And the other end of the first NMOS transistor M and an eighth NMOS transistor M₈The drain electrodes of the two electrodes are connected; eighth NMOS transistor M₈Is connected to the ninth NMOS transistor M₉A drain electrode of (1); ninth NMOS transistor M₉Is connected with a fifth resistor R₅One end of (a); a sixth resistor R₆And the other end of the first NMOS transistor M₁₀The drain electrodes of the two electrodes are connected; tenth NMOS transistor M₁₀Is connected to the eleventh NMOS transistor M₁₁A drain electrode of (1); eleventh NMOS transistor M₁₁Is connected with a seventh resistor R₇One end of (a); seventh PMOS transistor M₇Drain electrode of (1), fifth resistor R₅And a seventh resistor R₇The other end of the first and second electrodes is grounded; output terminal B²Is a fifth PMOS transistor M₅And a sixth NMOS transistor M₆A connection point of (1), an eighth NMOS transistor M₈And a ninth NMOS transistor M₉The connection point of (a); twelfth PMOS transistor M₁₂Gate of is connected with output terminal B²(ii) a Output terminal B¹Is a tenth NMOS transistor M₁₀And an eleventh NMOS transistor M₁₁And a twelfth PMOS transistor M₁₂Is connected to the drain of (1).

4. The literal operation-based three-valued memristive full adder circuit of claim 3, wherein the carry C_inThe input module comprises a thirteenth PMOS transistor M₁₃Fourteenth NMOS transistor M₁₄Fifteenth PMOS transistor M₁₅Sixteenth NMOS transistor M₁₆Seventeenth PMOS transistor M₁₇Eighteenth NMOS transistor M₁₈Eighth resistor R₈A ninth resistor R₉And a DC voltage source V_DD3、V_DD4、V_DD5(ii) a Wherein the thirteenth PMOS transistor M₁₃And a fourteenth NMOS transistor M₁₄The grid electrodes are all connected with a signal input end C_in(ii) a Thirteenth PMOS transistor M₁₃The source electrode of the first transistor is connected with the signal input end A; thirteenth PMOS transistor M₁₃Is connected to the fourteenth NMOS transistor M₁₄A drain electrode of (1); fourteenth NMOS transistor M₁₄The source electrode of the adder A input module is connected with the output end A of the adder A input module¹(ii) a Fifteenth PMOS transistor M₁₅Gate of and sixteenth NMOS transistor M₁₆Are all connected with a thirteenth PMOS transistor M₁₃And a fourteenth NMOS transistor M₁₄The connection point of (a); fifteenth PMOS transistor M₁₅And a seventeenth PMOS transistor M₁₇Is connected with a DC voltage source V_DD3(ii) a Fifteenth PMOS transistor M₁₅Is connected with a sixteenth NMOS transistor M₁₆A drain electrode of (1); seventeenth PMOS transistor M₁₇Is connected with an eighteenth NMOS transistor M₁₈A drain electrode of (1); sixteenth NMOS transistor M₁₆And an eighteenth NMOS transistor M₁₈The source of (2) is grounded; seventeenth PMOS transistor M₁₇Gate of (1), eighteenth NMOS transistor M₁₈Gate and eighth resistor R₈Are all connected with a fifteenth PMOS transistor M₁₅And a sixteenth NMOS transistor M₁₆The connection point of (a); eighth resistor R₈The other end of the DC voltage source is connected with a DC voltage source V_DD4(ii) a Ninth resistor R₉One end of which is connected with a seventeenth PMOS transistor M₁₇And an eighteenth NMOS transistor M₁₈The connection point of (a); ninth resistor R₉The other end of the DC voltage source is connected with a DC voltage source V_DD5(ii) a The output end X is a seventeenth PMOS transistor M₁₇And an eighteenth NMOS transistor M₁₈The connection point of (a).

5. The literal operation-based three-valued memristive full-adder circuit of claim 4, wherein the literal operation module comprises a first threshold type memristor M_R1Second threshold type memristor M_R2And a third threshold type memristor M_R3And a fourth threshold type memristor M_R4And a fifth threshold type memristor M_R5Nineteenth PMOS transistor M₁₉Twentieth NMOS transistor M₂₀Twenty-first NMOS transistor M₂₁Twenty-second NMOS transistor M₂₂Twenty third PMOS transistor M₂₃Twenty fourth NMOS transistor M₂₄Twenty-fifth NMOS transistor M₂₅Twenty sixth NMOS transistor M₂₆Twenty seventh NMOS transistor M₂₇And a DC voltage source V_DD6(ii) a Wherein the nineteenth PMOS transistor M₁₉Gate of (D), twentieth NMOS transistor M₂₀Gate and first threshold type memristor M_R1The positive ends of the two are connected with an enable signal input end CP; nineteenth PMOS transistor M₁₉Drain electrode of the twenty-third PMOS transistor M₂₃Drain electrode of (1), third threshold type memristor M_R3Positive terminal, fourth threshold type memristor M_R4Positive terminal and fifth threshold type memristor M_R5The positive ends of the two are connected with a direct-current voltage source V_DD6(ii) a Nineteenth PMOS transistor M₁₉Is connected to the twentieth NMOS transistor M₂₀A source electrode of (a); twentieth NMOS transistor M₂₀The drain of (2) is grounded; twenty-first NMOS transistor M₂₁Is connected with a nineteenth PMOS transistor M₁₉And the twentieth NMOS transistor M₂₀The connection point of (a); twenty-first NMOS transistor M₂₁Is connected intoBit C_inAn output terminal X of the input module; twenty-first NMOS transistor M₂₁Drain of the first and twenty-second NMOS transistors M₂₂And a twenty-sixth NMOS transistor M₂₆The grid electrodes of the first and second memory resistor are connected with a first threshold type memristor M_R1And a second threshold type memristor M_R2A negative terminal of (a); second threshold type memristor M_R2The positive terminal of the power supply is grounded; twenty-second NMOS transistor M₂₂Source electrode of (1) is connected with a third threshold type memristor M_R3A negative terminal of (a); twenty third PMOS transistor M₂₃And a twenty-fourth NMOS transistor M₂₄The grids of the two NMOS transistors are connected with a twenty-second NMOS transistor M₂₂And a third threshold type memristor M_R3The connection point of (a); twenty third PMOS transistor M₂₃Is connected to the twenty-fourth NMOS transistor M₂₄A drain electrode of (1); twenty-fifth NMOS transistor M₂₅Is connected with a twenty-third PMOS transistor M₂₃And a twenty-fourth NMOS transistor M₂₄The connection point of (a); twenty-fifth NMOS transistor M₂₅Is connected with a fourth threshold type memristor M_R4A negative terminal of (a); twenty-second NMOS transistor M₂₂Source of (d), twenty-fourth NMOS transistor M₂₄And a twenty-fifth NMOS transistor M₂₅The source of (2) is grounded; twenty-sixth NMOS transistor M₂₆Is connected with a fifth threshold type memristor M_R5A negative terminal of (a); twenty-seventh NMOS transistor M₂₇Is connected with a twenty-sixth NMOS transistor M₂₆And a fifth threshold type memristor M_R5The connection point of (a); twenty-sixth NMOS transistor M₂₆And a twenty-seventh NMOS transistor M₂₇The source of (2) is grounded; output end⁰X⁰Is a twenty-sixth NMOS transistor M₂₆And a fifth threshold type memristor M_R5Connection point, output terminal of¹X¹Is a twenty-fifth NMOS transistor M₂₅And a fourth threshold type memristor M_R4Connection point, output terminal of²X²Is a twenty-third PMOS transistor M₂₃And a twenty-fourth NMOS transistor M₂₄The connection point of (a).

6. The base of claim 5The circuit is characterized in that the SUM output module comprises a twenty-eighth NMOS transistor M₂₈Twenty ninth NMOS transistor M₂₉Thirtieth NMOS transistor M₃₀The tenth resistor R₁₀An eleventh resistor R₁₁And a twelfth resistor R₁₂(ii) a Wherein, the tenth resistor R₁₀One end of the first switch is connected with the signal input end B; a tenth resistor R₁₀Is connected with a twenty-eighth NMOS transistor M₂₈A drain electrode of (1); twenty eighth NMOS transistor M₂₈Grid electrode of the grid electrode is connected with the output end of the character operation module⁰X⁰(ii) a Eleventh resistor R₁₁One end of the input module is connected with the output end B of the addend B input module¹(ii) a Eleventh resistor R₁₁The other end of the second NMOS transistor is connected with a twenty-ninth NMOS transistor M₂₉A drain electrode of (1); twenty-ninth NMOS transistor M₂₉Grid electrode of the grid electrode is connected with the output end of the character operation module¹X¹(ii) a Twelfth resistor R₁₂One end of the input module is connected with the output end B of the addend B input module²(ii) a Twelfth resistor R₁₂Is connected with a thirty NMOS transistor M₃₀A drain electrode of (1); thirtieth NMOS transistor M₃₀Grid electrode of the grid electrode is connected with the output end of the character operation module²X²(ii) a The output terminal SUM is a twenty-eighth NMOS transistor M₂₈Source electrode of, twenty ninth NMOS transistor M₂₉And a thirtieth NMOS transistor M₃₀Of the substrate.

7. The literal operation-based three-valued memristive full-adder circuit of claim 6, wherein the carry output C_outThe module comprises a thirty-first PMOS transistor M₃₁Thirty-second NMOS transistor M₃₂Thirty-third PMOS transistor M₃₃Thirty-fourth NMOS transistor M₃₄Thirty-fifth NMOS transistor M₃₅Thirty-sixth NMOS transistor M₃₆Thirty-seventh NMOS transistor M₃₇Thirty-eighth NMOS transistor M₃₈Thirty-ninth PMOS transistor M₃₉A forty-th PMOS transistor M₄₀Thirteenth resistance R₁₃A fourteenth resistor R₁₄A fifteenth resistor R₁₅Sixteenth resistor R₁₆Seventeenth resistor R₁₇Eighteenth resistor R₁₈And a DC voltage source V_DD7、V_DD8、V_DD9(ii) a Wherein, the thirty-first PMOS transistor M₃₁Gate of (1), thirty-second NMOS transistor M₃₂Gate of (1), a thirty-third PMOS transistor M₃₃And a thirty-fourth NMOS transistor M₃₄The grid electrodes of the grid electrodes are connected with the output end SUM of the SUM output module; thirteenth resistor R₁₃One end of (1), a fifteenth resistor R₁₅And a thirty-seventh NMOS transistor M₃₇The drain electrodes of the two are respectively connected with a direct current voltage source V_DD7、V_DD8、V_DD9(ii) a Thirteenth resistor R₁₃The other end of the first transistor is connected with a thirty-first PMOS transistor M₃₁A source electrode of (a); thirty-first PMOS transistor M₃₁Is connected to the thirty-second NMOS transistor M₃₂A drain electrode of (1); a fourteenth resistance R₁₄And a seventeenth resistor R₁₇Are all connected with a thirty-first PMOS transistor M₃₁And a thirty-second NMOS transistor M₃₂The connection point of (a); a fourteenth resistance R₁₄And a thirty-second NMOS transistor M₃₂The source of (2) is grounded; a fifteenth resistor R₁₅Is connected with a thirty-third PMOS transistor M₃₃A source electrode of (a); thirty-third PMOS transistor M₃₃Is connected to the thirty-fourth NMOS transistor M₃₄A drain electrode of (1); thirty-fourth NMOS transistor M₃₄Is connected with a sixteenth resistor R₁₆One end of (a); sixteenth resistor R₁₆The other end of the first and second electrodes is grounded; eighteenth resistor R₁₈One end of the second transistor is connected with a thirty-third PMOS transistor M₃₃And a thirty-fourth NMOS transistor M₃₄The connection point of (a); seventeenth resistor R₁₇Is connected with a thirty-fifth NMOS transistor M₃₅A drain electrode of (1); thirty-fifth NMOS transistor M₃₅Grid electrode of the grid electrode is connected with the output end of the character operation module¹X¹(ii) a Eighteenth resistor R₁₈Is connected with a thirty-sixth NMOS transistor M₃₆A drain electrode of (1); thirty-sixth NMOS transistor M₃₆Grid electrode of the grid electrode is connected with the output end of the character operation module²X²(ii) a Thirty-eighth NMOS transistor M₃₈Gate of (2) and a fortieth PMOS transistor M₄₀The grid of the grid is connected with the signal input end A; thirty-seventh NMOS transistor M₃₇And a thirty-ninth PMOS transistor M₃₉Is connected with the signal input terminal C_in(ii) a Thirty-seventh NMOS transistor M₃₇Is connected with a thirty-eighth NMOS transistor M₃₈A drain electrode of (1); forty-th PMOS transistor M₄₀The source of (2) is grounded; forty-th PMOS transistor M₄₀Is connected with a thirty ninth PMOS transistor M₃₉A source electrode of (a); output terminal C_outIs a thirty-fifth NMOS transistor M₃₅Source of (2), thirty-sixth NMOS transistor M₃₆And a thirty-eighth NMOS transistor M₃₈And a thirty-ninth PMOS transistor M₃₉Of the substrate.

Technical Field

The invention belongs to the technical field of circuit design, and particularly relates to a three-value memristor full adder circuit based on character operation.

Background

The memristor is a fourth basic circuit element which is subsequent to the resistor, the capacitor and the inductor and has a nonvolatile and nanoscale structure, so that the circuit area can be reduced, and the power-off retention is realized. The memristor is applied to digital logic circuits, chaotic circuits, neural networks and the like. At present, research in digital circuits mainly focuses on binary logic, and multi-valued logic has advantages over binary logic in the aspects of reducing network complexity and circuit area, increasing data processing speed and the like, so that the invention designs and realizes a three-valued memristor full adder circuit on the basis of the multi-valued logic theory.

The existing three-value memristor full adder adopts a core which is not a true three-value circuit or a binary circuit, converts a three-value signal into a binary signal for addition operation, and then converts the binary signal into a three-value signal for output, wherein the conversion process is a coding and decoding process, and the complexity of the circuit is increased.

Disclosure of Invention

Aiming at the problems in the prior art and research cost, the invention designs and invents a three-value memristor full adder by taking character operation as a core and adopting a threshold memristor, thereby providing a new application field and a new design idea for a memristor logic circuit.

In order to solve the technical problems, the invention adopts the following technical scheme:

a three-value memristor full adder circuit based on character operation comprises an addend A input module, an addend B input module and a carry C_inInput module, character operation module, SUM output module and carry C_outAn output module; wherein the addend A input module and the carry C_inThe input module is connected and used for generating an input X of the character operation module; the SUM output module is connected with the addend B input module and the character operation module and is used for realizing output of SUM; the carry bit C_outThe output module is connected with the character operation module and the SUM output module and is used for realizing carry C_outTo output of (c).

Preferably, the addend a input module comprises a first PMOS transistor M₁A second PMOS transistor M₂A third NMOS transistor M₃A fourth NMOS transistor M₄First resistance R₁A second resistor R₂A third resistor R₃And a DC voltage source V_DD1(ii) a Wherein, the firstA PMOS transistor M₁A second PMOS transistor M₂A third NMOS transistor M₃And a fourth NMOS transistor M₄The grid electrodes of the grid electrodes are connected with a signal input end A; a first resistor R₁And a second resistor R₂One end of the DC voltage source is connected with a DC voltage source V_DD1(ii) a A first resistor R₁And the other end of the first PMOS transistor M₁The source electrodes of the two-way transistor are connected; a second resistor R₂And the other end of the first NMOS transistor M₃The drain electrodes of the two electrodes are connected; first PMOS transistor M₁Is connected to the second PMOS transistor M₂A source electrode of (a); second PMOS transistor M₂Is connected with a third resistor R₃One end of (a); third NMOS transistor M₃Is connected to the fourth NMOS transistor M₄A drain electrode of (1); fourth NMOS transistor M₄Is connected with a third resistor R₃The other end of the first and second electrodes is grounded; output terminal A¹Is a first PMOS transistor M₁And a second PMOS transistor M₂Is also the third NMOS transistor M₃And a fourth NMOS transistor M₄The connection point of (a).

Preferably, the addend B input module comprises a fifth PMOS transistor M₅And a sixth NMOS transistor M₆Seventh PMOS transistor M₇And an eighth NMOS transistor M₈And a ninth NMOS transistor M₉The tenth NMOS transistor M₁₀Eleventh NMOS transistor M₁₁Twelfth PMOS transistor M₁₂A fourth resistor R₄A fifth resistor R₅A sixth resistor R₆A seventh resistor R₇And a DC voltage source V_DD2(ii) a Wherein the fifth PMOS transistor M₅And a sixth NMOS transistor M₆Seventh PMOS transistor M₇And an eighth NMOS transistor M₈And a ninth NMOS transistor M₉The grid electrodes of the grid electrodes are connected with a signal input end B; fifth PMOS transistor M₅And a twelfth PMOS transistor M₁₂Source electrode of (1), fourth resistor R₄And a sixth resistor R₆One end of the two-way valve is connected with a direct current voltage source V_DD2(ii) a Fifth PMOS transistor M₅Is connected to the sixth NMOS transistor M₆A drain electrode of (1); sixth NMOS transistor M₆Is connected with a seventh PMOS transistor M₇A source electrode of (a); a fourth resistor R₄And the other end of the first NMOS transistor M and an eighth NMOS transistor M₈The drain electrodes of the two electrodes are connected; eighth NMOS transistor M₈Is connected to the ninth NMOS transistor M₉A drain electrode of (1); ninth NMOS transistor M₉Is connected with a fifth resistor R₅One end of (a); a sixth resistor R₆And the other end of the first NMOS transistor M₁₀The drain electrodes of the two electrodes are connected; tenth NMOS transistor M₁₀Is connected to the eleventh NMOS transistor M₁₁A drain electrode of (1); eleventh NMOS transistor M₁₁Is connected with a seventh resistor R₇One end of (a); seventh PMOS transistor M₇Drain electrode of (1), fifth resistor R₅And a seventh resistor R₇The other end of the first and second electrodes is grounded; output terminal B²Is a fifth PMOS transistor M₅And a sixth NMOS transistor M₆A connection point of (1), an eighth NMOS transistor M₈And a ninth NMOS transistor M₉The connection point of (a); twelfth PMOS transistor M₁₂Gate of is connected with output terminal B²(ii) a Output terminal B¹Is a tenth NMOS transistor M₁₀And an eleventh NMOS transistor M₁₁And a twelfth PMOS transistor M₁₂Is connected to the drain of (1).

Preferably, the carry bit C_inThe input module comprises a thirteenth PMOS transistor M₁₃Fourteenth NMOS transistor M₁₄Fifteenth PMOS transistor M₁₅Sixteenth NMOS transistor M₁₆Seventeenth PMOS transistor M₁₇Eighteenth NMOS transistor M₁₈Eighth resistor R₈A ninth resistor R₉And a DC voltage source V_DD3、V_DD4、V_DD5. (ii) a Wherein the thirteenth PMOS transistor M₁₃And a fourteenth NMOS transistor M₁₄The grid electrodes are all connected with a signal input end C_in(ii) a Thirteenth PMOS transistor M₁₃The source electrode of the first transistor is connected with the signal input end A; thirteenth PMOS transistor M₁₃Is connected to the fourteenth NMOS transistor M₁₄A drain electrode of (1); fourteenth NMOS transistor M₁₄The source electrode of the adder A input module is connected with the output end A of the adder A input module¹(ii) a Fifteenth PMOS transistor M₁₅Gate of and sixteenth NMOS transistor M₁₆Are all connected with a thirteenth PMOS transistor M₁₃And a fourteenth NMOS transistor M₁₄The connection point of (a); fifteenth PMOS transistor M₁₅And a seventeenth PMOS transistor M₁₇Is connected with a DC voltage source V_DD3(ii) a Fifteenth PMOS transistor M₁₅Is connected with a sixteenth NMOS transistor M₁₆A drain electrode of (1); seventeenth PMOS transistor M₁₇Is connected with an eighteenth NMOS transistor M₁₈A drain electrode of (1); sixteenth NMOS transistor M₁₆And an eighteenth NMOS transistor M₁₈The source of (2) is grounded; seventeenth PMOS transistor M₁₇Gate of (1), eighteenth NMOS transistor M₁₈Gate and eighth resistor R₈Are all connected with a fifteenth PMOS transistor M₁₅And a sixteenth NMOS transistor M₁₆The connection point of (a); eighth resistor R₈The other end of the DC voltage source is connected with a DC voltage source V_DD4(ii) a Ninth resistor R₉One end of which is connected with a seventeenth PMOS transistor M₁₇And an eighteenth NMOS transistor M₁₈The connection point of (a); ninth resistor R₉The other end of the DC voltage source is connected with a DC voltage source V_DD5(ii) a The output end X is a seventeenth PMOS transistor M₁₇And an eighteenth NMOS transistor M₁₈The connection point of (a).

Preferably, the literal operation module comprises a first threshold-type memristor M_R1Second threshold type memristor M_R2And a third threshold type memristor M_R3And a fourth threshold type memristor M_R4And a fifth threshold type memristor M_R5Nineteenth PMOS transistor M₁₉Twentieth NMOS transistor M₂₀Twenty-first NMOS transistor M₂₁Twenty-second NMOS transistor M₂₂Twenty third PMOS transistor M₂₃Twenty fourth NMOS transistor M₂₄Twenty-fifth NMOS transistor M₂₅Twenty sixth NMOS transistor M₂₆Twenty seventh NMOS transistor M₂₇And a DC voltage source V_DD6(ii) a Wherein the nineteenth PMOS transistor M₁₉Gate of (D), twentieth NMOS transistor M₂₀Gate and first threshold type memristor M_R1The positive ends of the two are connected with an enable signal input end CP; nineteenth PMOS transistor M₁₉Drain electrode of the twenty-third PMOS transistor M₂₃Drain electrode of (1), third threshold type memristor M_R3Positive terminal, fourth threshold type memristor M_R4Positive terminal and fifth threshold type memristor M_R5The positive ends of the two are connected with a direct-current voltage source V_DD6(ii) a Nineteenth PMOS transistor M₁₉Is connected to the twentieth NMOS transistor M₂₀A source electrode of (a); twentieth NMOS transistor M₂₀The drain of (2) is grounded; twenty-first NMOS transistor M₂₁Is connected with a nineteenth PMOS transistor M₁₉And the twentieth NMOS transistor M₂₀The connection point of (a); twenty-first NMOS transistor M₂₁Is connected to carry C_inAn output terminal X of the input module; twenty-first NMOS transistor M₂₁Drain of the first and twenty-second NMOS transistors M₂₂And a twenty-sixth NMOS transistor M₂₆The grid electrodes of the first and second memory resistor are connected with a first threshold type memristor M_R1And a second threshold type memristor M_R2A negative terminal of (a); second threshold type memristor M_R2The positive terminal of the power supply is grounded; twenty-second NMOS transistor M₂₂Source electrode of (1) is connected with a third threshold type memristor M_R3A negative terminal of (a); twenty third PMOS transistor M₂₃And a twenty-fourth NMOS transistor M₂₄The grids of the two NMOS transistors are connected with a twenty-second NMOS transistor M₂₂And a third threshold type memristor M_R3The connection point of (a); twenty third PMOS transistor M₂₃Is connected to the twenty-fourth NMOS transistor M₂₄A drain electrode of (1); twenty-fifth NMOS transistor M₂₅Is connected with a twenty-third PMOS transistor M₂₃And a twenty-fourth NMOS transistor M₂₄The connection point of (a); twenty-fifth NMOS transistor M₂₅Is connected with a fourth threshold type memristor M_R4A negative terminal of (a); twenty-second NMOS transistor M₂₂Source of (d), twenty-fourth NMOS transistor M₂₄And a twenty-fifth NMOS transistor M₂₅The source of (2) is grounded; twenty-sixth NMOS transistor M₂₆Is connected with a fifth threshold type memristor M_R5A negative terminal of (a); twenty-seventh NMOS transistor M₂₇Is connected with a twenty-sixth NMOS transistor M₂₆And a fifth threshold type memristor M_R5The connection point of (a); twenty-sixth NMOS transistor M₂₆And a twenty-seventh NMOS transistor M₂₇The source of (2) is grounded; output end⁰X⁰Is a twenty-sixth NMOS transistor M₂₆And a fifth threshold type memristor M_R5Connection point, output terminal of¹X¹Is a twenty-fifth NMOS transistor M₂₅And a fourth threshold type memristor M_R4Connection point, output terminal of²X²Is a twenty-third PMOS transistor M₂₃And a twenty-fourth NMOS transistor M₂₄The connection point of (a).

Preferably, the SUM output module includes a twenty-eighth NMOS transistor M₂₈Twenty ninth NMOS transistor M₂₉Thirtieth NMOS transistor M₃₀The tenth resistor R₁₀An eleventh resistor R₁₁And a twelfth resistor R₁₂(ii) a Wherein, the tenth resistor R₁₀One end of the first switch is connected with the signal input end B; a tenth resistor R₁₀Is connected with a twenty-eighth NMOS transistor M₂₈A drain electrode of (1); twenty eighth NMOS transistor M₂₈Grid electrode of the grid electrode is connected with the output end of the character operation module⁰X⁰(ii) a Eleventh resistor R₁₁One end of the input module is connected with the output end B of the addend B input module¹(ii) a Eleventh resistor R₁₁The other end of the second NMOS transistor is connected with a twenty-ninth NMOS transistor M₂₉A drain electrode of (1); twenty-ninth NMOS transistor M₂₉Grid electrode of the grid electrode is connected with the output end of the character operation module¹X¹(ii) a Twelfth resistor R₁₂One end of the input module is connected with the output end B of the addend B input module²(ii) a Twelfth resistor R₁₂Is connected with a thirty NMOS transistor M₃₀A drain electrode of (1); thirtieth NMOS transistor M₃₀Grid electrode of the grid electrode is connected with the output end of the character operation module²X²(ii) a The output terminal SUM is a twenty-eighth NMOS transistor M₂₈Source electrode of, twenty ninth NMOS transistor M₂₉And a thirtieth NMOS transistor M₃₀Of the substrate.

Preferably, the carry output C_outThe module comprises a thirty-first PMOS transistor M₃₁Thirty secondNMOS transistor M₃₂Thirty-third PMOS transistor M₃₃Thirty-fourth NMOS transistor M₃₄Thirty-fifth NMOS transistor M₃₅Thirty-sixth NMOS transistor M₃₆Thirty-seventh NMOS transistor M₃₇Thirty-eighth NMOS transistor M₃₈Thirty-ninth PMOS transistor M₃₉A forty-th PMOS transistor M₄₀Thirteenth resistance R₁₃A fourteenth resistor R₁₄A fifteenth resistor R₁₅Sixteenth resistor R₁₆Seventeenth resistor R₁₇Eighteenth resistor R₁₈And a DC voltage source V_DD7、V_DD8、V_DD9(ii) a Wherein, the thirty-first PMOS transistor M₃₁Gate of (1), thirty-second NMOS transistor M₃₂Gate of (1), a thirty-third PMOS transistor M₃₃And a thirty-fourth NMOS transistor M₃₄The grid electrodes of the grid electrodes are connected with the output end SUM of the SUM output module; thirteenth resistor R₁₃One end of (1), a fifteenth resistor R₁₅And a thirty-seventh NMOS transistor M₃₇The drain electrodes of the two are respectively connected with a direct current voltage source V_DD7、V_DD8、V_DD9(ii) a Thirteenth resistor R₁₃The other end of the first transistor is connected with a thirty-first PMOS transistor M₃₁A source electrode of (a); thirty-first PMOS transistor M₃₁Is connected to the thirty-second NMOS transistor M₃₂A drain electrode of (1); a fourteenth resistance R₁₄And a seventeenth resistor R₁₇Are all connected with a thirty-first PMOS transistor M₃₁And a thirty-second NMOS transistor M₃₂The connection point of (a); a fourteenth resistance R₁₄And a thirty-second NMOS transistor M₃₂The source of (2) is grounded; a fifteenth resistor R₁₅Is connected with a thirty-third PMOS transistor M₃₃A source electrode of (a); thirty-third PMOS transistor M₃₃Is connected to the thirty-fourth NMOS transistor M₃₄A drain electrode of (1); thirty-fourth NMOS transistor M₃₄Is connected with a sixteenth resistor R₁₆One end of (a); sixteenth resistor R₁₆The other end of the first and second electrodes is grounded; eighteenth resistor R₁₈One end of the second transistor is connected with a thirty-third PMOS transistor M₃₃And a thirty-fourth NMOS transistor M₃₄The connection point of (a); seventeenth resistor R₁₇Is connected with a thirty-fifth NMOS transistor M₃₅A drain electrode of (1); thirty-fifth NMOS transistor M₃₅Grid electrode of the grid electrode is connected with the output end of the character operation module¹X¹(ii) a Eighteenth resistor R₁₈Is connected with a thirty-sixth NMOS transistor M₃₆A drain electrode of (1); thirty-sixth NMOS transistor M₃₆Grid electrode of the grid electrode is connected with the output end of the character operation module²X²(ii) a Thirty-eighth NMOS transistor M₃₈Gate of (2) and a fortieth PMOS transistor M₄₀The grid of the grid is connected with the signal input end A; thirty-seventh NMOS transistor M₃₇And a thirty-ninth PMOS transistor M₃₉Is connected with the signal input terminal C_in(ii) a Thirty-seventh NMOS transistor M₃₇Is connected with a thirty-eighth NMOS transistor M₃₈A drain electrode of (1); forty-th PMOS transistor M₄₀The source of (2) is grounded; forty-th PMOS transistor M₄₀Is connected with a thirty ninth PMOS transistor M₃₉A source electrode of (a); output terminal C_outIs a thirty-fifth NMOS transistor M₃₅Source of (2), thirty-sixth NMOS transistor M₃₆And a thirty-eighth NMOS transistor M₃₈And a thirty-ninth PMOS transistor M₃₉Of the substrate.

The invention has the following beneficial effects: the invention designs and invents a three-value memristor full adder by taking three-value character operation as a core, can simply realize the function of real three-value full addition by distinguishing three-value signals and controlling the output of signals through the character operation, and has important significance for the research and application of memristor circuits and multi-valued logic.

Compared with the prior art, the character operation-based three-value memristor full adder equivalent circuit can simply use the memristor and the MOS to realize the three-value full adder, and the number of devices, the number of lines of interconnection and the circuit area are greatly reduced.

Drawings

FIG. 1 is a memristor symbol and volt-ampere characteristic curve diagram of a three-valued memristor full adder circuit based on literal arithmetic according to an embodiment of the present invention;

FIG. 2 is a schematic block diagram of a three-valued memristor full adder circuit based on literal arithmetic according to an embodiment of the present disclosure;

fig. 3 is a schematic circuit diagram of a three-valued memristor full adder circuit based on literal arithmetic according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The circuit symbol and the current-voltage characteristic curve of the memristor are shown in figure 1, a threshold type memristor model is adopted, the threshold type memristor has two states of high resistance and low resistance, and when voltage is applied to the memristor, the memristor is in the low resistance state R along with the change of the voltage_ONAnd a high resistive state R_OFFTo change between. The end without the solid black line is set as the positive end.

Fig. 2 is a schematic block diagram of a three-valued memristor full adder based on literal operation, from which the connection relationship of each module can be seen.

FIG. 3 is a circuit diagram of a three-valued memristor full adder based on literal arithmetic. DC voltage source V in the circuit diagram_DD4、V_DD5、V_DD8And V_DD91V, and the rest direct current voltage sources are all 2V. The fourth, eighth, tenth, sixteenth, eighteenth, twenty-second and thirty-fourth NMOS transistors M₄、M₈、M₁₀、M₁₆、M₁₈、M₂₂And M₃₄Turn-on voltage V of_TH>1V, the third, ninth, eleventh, fourteenth, twenty-sixth, thirty-twelfth and thirty-seventh NMOS transistors M₃、M₉、M₁₁、M₁₄、M₂₆、M₃₂And M₃₇Turn-on voltage V of_TH<1V。

Referring to FIGS. 2 and 3, a text-based algorithm according to an embodiment of the present invention is shownThe three-value memristor full adder circuit comprises an addend A input module 10, an addend B input module 20 and a carry C_inInput module 30, literal operation module 40, SUM output module 50, and carry C_outAn output module 60; the addend A input module 10 and the carry C_inThe input module 30 is connected with the character operation module 40 and used for generating an input X; the SUM output module 50 is connected with the addend B input module 20 and the character operation module 40, and is used for realizing SUM output; the carry bit C_outThe output module 60 is connected to the text operation module 40 and the SUM output module 50, and is used for implementing carry C_outTo output of (c).

The addend-a input module 10 comprises a first PMOS transistor M₁A second PMOS transistor M₂A third NMOS transistor M₃A fourth NMOS transistor M₄First resistance R₁A second resistor R₂A third resistor R₃And a DC voltage source V_DD1(ii) a Wherein the first PMOS transistor M₁A second PMOS transistor M₂A third NMOS transistor M₃And a fourth NMOS transistor M₄The grid electrodes of the grid electrodes are connected with a signal input end A; a first resistor R₁And a second resistor R₂One end of the DC voltage source is connected with a DC voltage source V_DD1(ii) a A first resistor R₁And the other end of the first PMOS transistor M₁The source electrodes of the two-way transistor are connected; a second resistor R₂And the other end of the first NMOS transistor M₃The drain electrodes of the two electrodes are connected; first PMOS transistor M₁Is connected to the second PMOS transistor M₂A source electrode of (a); second PMOS transistor M₂Is connected with a third resistor R₃One end of (a); third NMOS transistor M₃Is connected to the fourth NMOS transistor M₄A drain electrode of (1); fourth NMOS transistor M₄Is connected with a third resistor R₃The other end of the first and second electrodes is grounded; output terminal A¹Is a first PMOS transistor M₁And a second PMOS transistor M₂Is also the third NMOS transistor M₃And a fourth NMOS transistor M₄The connection point of (a).

The addend-B input module 20 includes a fifth PMOS transistor M₅And a sixth NMOS transistor M₆Seventh, thePMOS transistor M₇And an eighth NMOS transistor M₈And a ninth NMOS transistor M₉The tenth NMOS transistor M₁₀Eleventh NMOS transistor M₁₁Twelfth PMOS transistor M₁₂A fourth resistor R₄A fifth resistor R₅A sixth resistor R₆A seventh resistor R₇And a DC voltage source V_DD2(ii) a Wherein the fifth PMOS transistor M₅And a sixth NMOS transistor M₆Seventh PMOS transistor M₇And an eighth NMOS transistor M₈And a ninth NMOS transistor M₉The grid electrodes of the grid electrodes are connected with a signal input end B; fifth PMOS transistor M₅And a twelfth PMOS transistor M₁₂Source electrode of (1), fourth resistor R₄And a sixth resistor R₆One end of the two-way valve is connected with a direct current voltage source V_DD2(ii) a Fifth PMOS transistor M₅Is connected to the sixth NMOS transistor M₆A drain electrode of (1); sixth NMOS transistor M₆Is connected with a seventh PMOS transistor M₇A source electrode of (a); a fourth resistor R₄And the other end of the first NMOS transistor M and an eighth NMOS transistor M₈The drain electrodes of the two electrodes are connected; eighth NMOS transistor M₈Is connected to the ninth NMOS transistor M₉A drain electrode of (1); ninth NMOS transistor M₉Is connected with a fifth resistor R₅One end of (a); a sixth resistor R₆And the other end of the first NMOS transistor M₁₀The drain electrodes of the two electrodes are connected; tenth NMOS transistor M₁₀Is connected to the eleventh NMOS transistor M₁₁A drain electrode of (1); eleventh NMOS transistor M₁₁Is connected with a seventh resistor R₇One end of (a); seventh PMOS transistor M₇Drain electrode of (1), fifth resistor R₅And a seventh resistor R₇The other end of the first and second electrodes is grounded; output terminal B²Is a fifth PMOS transistor M₅And a sixth NMOS transistor M₆A connection point of (1), an eighth NMOS transistor M₈And a ninth NMOS transistor M₉The connection point of (a); twelfth PMOS transistor M₁₂Gate of is connected with output terminal B²(ii) a Output terminal B¹Is a tenth NMOS transistor M₁₀And an eleventh NMOS transistor M₁₁And a twelfth PMOS transistor M₁₂Is connected to the drain of (1).

Carry bit C_inThe input module 30 comprises a thirteenth PMOS transistor M₁₃Fourteenth NMOS transistor M₁₄Fifteenth PMOS transistor M₁₅Sixteenth NMOS transistor M₁₆Seventeenth PMOS transistor M₁₇Eighteenth NMOS transistor M₁₈Eighth resistor R₈A ninth resistor R₉And a DC voltage source V_DD3、V_DD4、V_DD5. (ii) a Wherein the thirteenth PMOS transistor M₁₃And a fourteenth NMOS transistor M₁₄The grid electrodes are all connected with a signal input end C_in(ii) a Thirteenth PMOS transistor M₁₃The source electrode of the first transistor is connected with the signal input end A; thirteenth PMOS transistor M₁₃Is connected to the fourteenth NMOS transistor M₁₄A drain electrode of (1); fourteenth NMOS transistor M₁₄Is connected to the output terminal a of the addend a input module 10¹(ii) a Fifteenth PMOS transistor M₁₅Gate of and sixteenth NMOS transistor M₁₆Are all connected with a thirteenth PMOS transistor M₁₃And a fourteenth NMOS transistor M₁₄The connection point of (a); fifteenth PMOS transistor M₁₅And a seventeenth PMOS transistor M₁₇Is connected with a DC voltage source V_DD3(ii) a Fifteenth PMOS transistor M₁₅Is connected with a sixteenth NMOS transistor M₁₆A drain electrode of (1); seventeenth PMOS transistor M₁₇Is connected with an eighteenth NMOS transistor M₁₈A drain electrode of (1); sixteenth NMOS transistor M₁₆And an eighteenth NMOS transistor M₁₈The source of (2) is grounded; seventeenth PMOS transistor M₁₇Gate of (1), eighteenth NMOS transistor M₁₈Gate and eighth resistor R₈Are all connected with a fifteenth PMOS transistor M₁₅And a sixteenth NMOS transistor M₁₆The connection point of (a); eighth resistor R₈The other end of the DC voltage source is connected with a DC voltage source V_DD4(ii) a Ninth resistor R₉One end of which is connected with a seventeenth PMOS transistor M₁₇And an eighteenth NMOS transistor M₁₈The connection point of (a); ninth resistor R₉The other end of the DC voltage source is connected with a DC voltage source V_DD5(ii) a The output end X is a seventeenth PMOS transistor M₁₇And eighteenth NMOS crystalPipe M₁₈The connection point of (a).

The literal computation module 40 includes a first threshold type memristor M_R1Second threshold type memristor M_R2And a third threshold type memristor M_R3And a fourth threshold type memristor M_R4And a fifth threshold type memristor M_R5Nineteenth PMOS transistor M₁₉Twentieth NMOS transistor M₂₀Twenty-first NMOS transistor M₂₁Twenty-second NMOS transistor M₂₂Twenty third PMOS transistor M₂₃Twenty fourth NMOS transistor M₂₄Twenty-fifth NMOS transistor M₂₅Twenty sixth NMOS transistor M₂₆Twenty seventh NMOS transistor M₂₇And a DC voltage source V_DD6(ii) a Wherein the nineteenth PMOS transistor M₁₉Gate of (D), twentieth NMOS transistor M₂₀Gate and first threshold type memristor M_R1The positive ends of the two are connected with an enable signal input end CP; nineteenth PMOS transistor M₁₉Drain electrode of the twenty-third PMOS transistor M₂₃Drain electrode of (1), third threshold type memristor M_R3Positive terminal, fourth threshold type memristor M_R4Positive terminal and fifth threshold type memristor M_R5The positive ends of the two are connected with a direct-current voltage source V_DD6(ii) a Nineteenth PMOS transistor M₁₉Is connected to the twentieth NMOS transistor M₂₀A source electrode of (a); twentieth NMOS transistor M₂₀The drain of (2) is grounded; twenty-first NMOS transistor M₂₁Is connected with a nineteenth PMOS transistor M₁₉And the twentieth NMOS transistor M₂₀The connection point of (a); twenty-first NMOS transistor M₂₁Is connected to carry C_inAn output terminal X of the input module 30; twenty-first NMOS transistor M₂₁Drain of the first and twenty-second NMOS transistors M₂₂And a twenty-sixth NMOS transistor M₂₆The grid electrodes of the first and second memory resistor are connected with a first threshold type memristor M_R1And a second threshold type memristor M_R2A negative terminal of (a); second threshold type memristor M_R2The positive terminal of the power supply is grounded; twenty-second NMOS transistor M₂₂Source electrode of (1) is connected with a third threshold type memristor M_R3A negative terminal of (a); twenty third PMOS transistor M₂₃Gate and twentiethFour NMOS transistors M₂₄The grids of the two NMOS transistors are connected with a twenty-second NMOS transistor M₂₂And a third threshold type memristor M_R3The connection point of (a); twenty third PMOS transistor M₂₃Is connected to the twenty-fourth NMOS transistor M₂₄A drain electrode of (1); twenty-fifth NMOS transistor M₂₅Is connected with a twenty-third PMOS transistor M₂₃And a twenty-fourth NMOS transistor M₂₄The connection point of (a); twenty-fifth NMOS transistor M₂₅Is connected with a fourth threshold type memristor M_R4A negative terminal of (a); twenty-second NMOS transistor M₂₂Source of (d), twenty-fourth NMOS transistor M₂₄And a twenty-fifth NMOS transistor M₂₅The source of (2) is grounded; twenty-sixth NMOS transistor M₂₆Is connected with a fifth threshold type memristor M_R5A negative terminal of (a); twenty-seventh NMOS transistor M₂₇Is connected with a twenty-sixth NMOS transistor M₂₆And a fifth threshold type memristor M_R5The connection point of (a); twenty-sixth NMOS transistor M₂₆And a twenty-seventh NMOS transistor M₂₇The source of (2) is grounded; output end⁰X⁰Is a twenty-sixth NMOS transistor M₂₆And a fifth threshold type memristor M_R5Connection point, output terminal of¹X¹Is a twenty-fifth NMOS transistor M₂₅And a fourth threshold type memristor M_R4Connection point, output terminal of²X²Is a twenty-third PMOS transistor M₂₃And a twenty-fourth NMOS transistor M₂₄The connection point of (a).

SUM output module 50 includes a twenty-eighth NMOS transistor M₂₈Twenty ninth NMOS transistor M₂₉Thirtieth NMOS transistor M₃₀The tenth resistor R₁₀An eleventh resistor R₁₁And a twelfth resistor R₁₂(ii) a Wherein, the tenth resistor R₁₀One end of the first switch is connected with the signal input end B; a tenth resistor R₁₀Is connected with a twenty-eighth NMOS transistor M₂₈A drain electrode of (1); twenty eighth NMOS transistor M₂₈The grid electrode of the grid electrode is connected with the output end of the character operation module 40⁰X⁰(ii) a Eleventh resistor R₁₁Is connected to the output of the addend B input module 20B¹(ii) a Eleventh resistor R₁₁The other end of the second NMOS transistor is connected with a twenty-ninth NMOS transistor M₂₉A drain electrode of (1); twenty-ninth NMOS transistor M₂₉The grid electrode of the grid electrode is connected with the output end of the character operation module 40¹X¹(ii) a Twelfth resistor R₁₂One end of which is connected with the output end B of the addend B input module 20²(ii) a Twelfth resistor R₁₂Is connected with a thirty NMOS transistor M₃₀A drain electrode of (1); thirtieth NMOS transistor M₃₀The grid electrode of the grid electrode is connected with the output end of the character operation module 40²X²(ii) a The output terminal SUM is a twenty-eighth NMOS transistor M₂₈Source electrode of, twenty ninth NMOS transistor M₂₉And a thirtieth NMOS transistor M₃₀Of the substrate.

Carry out C_outThe module comprises a thirty-first PMOS transistor M₃₁Thirty-second NMOS transistor M₃₂Thirty-third PMOS transistor M₃₃Thirty-fourth NMOS transistor M₃₄Thirty-fifth NMOS transistor M₃₅Thirty-sixth NMOS transistor M₃₆Thirty-seventh NMOS transistor M₃₇Thirty-eighth NMOS transistor M₃₈Thirty-ninth PMOS transistor M₃₉A forty-th PMOS transistor M₄₀Thirteenth resistance R₁₃A fourteenth resistor R₁₄A fifteenth resistor R₁₅Sixteenth resistor R₁₆Seventeenth resistor R₁₇Eighteenth resistor R₁₈And a DC voltage source V_DD7、V_DD8、V_DD9(ii) a Wherein, the thirty-first PMOS transistor M₃₁Gate of (1), thirty-second NMOS transistor M₃₂Gate of (1), a thirty-third PMOS transistor M₃₃And a thirty-fourth NMOS transistor M₃₄The gates of which are all connected to the output end SUM of the SUM output module 50; thirteenth resistor R₁₃One end of (1), a fifteenth resistor R₁₅And a thirty-seventh NMOS transistor M₃₇The drain electrodes of the two are respectively connected with a direct current voltage source V_DD7、V_DD8、V_DD9(ii) a Thirteenth resistor R₁₃The other end of the first transistor is connected with a thirty-first PMOS transistor M₃₁A source electrode of (a); thirty-first PMOS transistor M₃₁Is connected to the thirty-second NMOS transistor M₃₂A drain electrode of (1); a fourteenth resistance R₁₄And a seventeenth resistor R₁₇Are all connected with a thirty-first PMOS transistor M₃₁And a thirty-second NMOS transistor M₃₂The connection point of (a); a fourteenth resistance R₁₄And a thirty-second NMOS transistor M₃₂The source of (2) is grounded; a fifteenth resistor R₁₅Is connected with a thirty-third PMOS transistor M₃₃A source electrode of (a); thirty-third PMOS transistor M₃₃Is connected to the thirty-fourth NMOS transistor M₃₄A drain electrode of (1); thirty-fourth NMOS transistor M₃₄Is connected with a sixteenth resistor R₁₆One end of (a); sixteenth resistor R₁₆The other end of the first and second electrodes is grounded; eighteenth resistor R₁₈One end of the second transistor is connected with a thirty-third PMOS transistor M₃₃And a thirty-fourth NMOS transistor M₃₄The connection point of (a); seventeenth resistor R₁₇Is connected with a thirty-fifth NMOS transistor M₃₅A drain electrode of (1); thirty-fifth NMOS transistor M₃₅The grid electrode of the grid electrode is connected with the output end of the character operation module 40¹X¹(ii) a Eighteenth resistor R₁₈Is connected with a thirty-sixth NMOS transistor M₃₆A drain electrode of (1); thirty-sixth NMOS transistor M₃₆The grid electrode of the grid electrode is connected with the output end of the character operation module 40²X²(ii) a Thirty-eighth NMOS transistor M₃₈Gate of (2) and a fortieth PMOS transistor M₄₀The grid of the grid is connected with the signal input end A; thirty-seventh NMOS transistor M₃₇And a thirty-ninth PMOS transistor M₃₉Is connected with the signal input terminal C_in(ii) a Thirty-seventh NMOS transistor M₃₇Is connected with a thirty-eighth NMOS transistor M₃₈A drain electrode of (1); forty-th PMOS transistor M₄₀The source of (2) is grounded; forty-th PMOS transistor M₄₀Is connected with a thirty ninth PMOS transistor M₃₉A source electrode of (a); output terminal C_outIs a thirty-fifth NMOS transistor M₃₅Source of (2), thirty-sixth NMOS transistor M₃₆And a thirty-eighth NMOS transistor M₃₈And a thirty-ninth PMOS transistor M₃₉Of the substrate.

The invention adopts two operation methods of modulo-3 addition operation and character operation.

The modulo-3 addition operation is defined as follows:

for simplicity, the present invention represents the modulo-3 addition operation as x^k。

The literal operation, the ternary and operation, and the ternary or operation form a complete set, defined as follows:

the truth table for literal operations is as follows:

table-character operation truth table

It can be transformed according to the truth table of a three-valued full adder as follows.

Truth table of full adder with two and three values

The results using modulo-3 addition and text operations are obtained as follows:

and: SUM ═ SUM⁰C_in ⁰(⁰A⁰·B⁰+¹A¹·B¹+²A²·B²)+¹C_in ¹(⁰A⁰·B¹+¹A¹·B²+²A²·B⁰) (3)

Carry: c_out＝⁰C_in ⁰[¹A¹·SUM₁+²A²·SUM₂]+¹C_in ¹[⁰A⁰·SUM₁+¹A¹·SUM₂]+¹C_in ¹·²A²(4)

In the formula (3) B^kThe meaning of (a): the input B is modulo-3 added with 0, 1, and 2, respectively, as follows:

truth table for table three-module 3 addition operation

While⁰C_in ⁰Representing when carry input C_inWhen the average molecular weight is 0, the average molecular weight,⁰A⁰.B⁰when A is 0, SUM is B⁰And so on. In order to simplify the circuit and realize the function of a three-value full adder, B⁰、B¹、B²The former part is used as input for text calculation, which can be realized by a simple text calculation module 40, as follows.

Order to

Further obtaining:

and: SUM ═ SUM⁰x⁰·B⁰+¹x¹·B¹+²x²·B² (7)

Carry: c_out＝¹x¹·SUM₁+²x²·SUM₂+¹C_in ¹·²A² (8)

The circuit is designed according to the equations (7) and (8).

The working process of each module of the invention is as follows:

1. addend a input module 10

The addend a input block 10 implements the function of modulo-3 adding the input signals a and 1. First PMOS transistor M₁And a second PMOS transistor M₂The model and the starting voltage of the resistor are the same, and the first resistor R₁And a third resistor R₃The resistance values are the same.

(1) When the input A is low, the first PMOS transistor M₁And a second PMOS transistor M₂Conducting, third NMOS transistor M₃And a fourth NMOS transistor M₄Cut-off, DC voltage source V_DD1Through a first resistor R₁A first PMOS transistor M₁And a third resistor R₃A second PMOS transistor M₂Dividing voltage and outputting an intermediate level;

(2) when the input A is at the middle level, the first PMOS transistor M₁And a second PMOS transistor M₂Off, third NMOS transistor M₃On, the fourth NMOS transistor M₄Cut-off, DC power supply V_DD1Through a third NMOS transistor M₃Outputting a high level;

(3) when the input A is high, the first PMOS transistor M₁And a second PMOS transistor M₂Off, third NMOS transistor M₃And a fourth NMOS transistor M₄Is turned on because of the fourth NMOS transistor M₄And is grounded, so a low level is output.

In summary, the addend a input block 10 implements a modulo-3 addition of the input signals a and 1, denoted as a¹The result will be taken as carry C_inPart of the input signals of the input module 30.

2. Addend B input module 20

The addend B input block 20 implements the function of modulo-3 addition of the input signal B with 1 and 2, respectively. A fourth resistor R₄A fifth resistor R₅A sixth resistor R₆And a seventh resistor R₇The eighth NMOS transistor M with the same resistance₈And a ninth NMOS transistor M₉Is the same as the start voltage, and a tenth NMOS transistor M₁₀And an eleventh NMOS transistor M₁₁Model and turn-on voltage ofThe same is true.

(1) When the input B is low, the fifth PMOS transistor M₅On, the sixth NMOS transistor M₆And an eighth NMOS transistor M₈And a ninth NMOS transistor M₉Are all cut off, the direct current voltage source V_DD2Through a fifth PMOS transistor M₅The output is high level, and the tenth NMOS transistor M is arranged₁₀And an eleventh NMOS transistor M₁₁Conducting, twelfth PMOS transistor M₁₂Cut-off, DC power supply V_DD2Through a sixth resistor R₆The tenth NMOS transistor M₁₀And a seventh resistor R₇Eleventh NMOS transistor M₁₁Dividing voltage and outputting an intermediate level;

(2) when the input B is at the middle level, the fifth PMOS transistor M₅Off, sixth NMOS transistor M₆On, the seventh PMOS transistor M₇Off, eighth NMOS transistor M₈Off, ninth NMOS transistor M₉Is turned on because of the ninth NMOS transistor M₉And is grounded, so a low level is output. At this time, the tenth NMOS transistor M₁₀And an eleventh NMOS transistor M₁₁Off, twelfth PMOS transistor M₁₂Conducting, DC power supply V_DD2Through a twelfth PMOS transistor M₁₂And outputting a high level.

(3) When the input B is high, the fifth PMOS transistor M₅Off, sixth NMOS transistor M₆On, the seventh PMOS transistor M₇Off, eighth NMOS transistor M₈And a ninth NMOS transistor M₉Are all conducted, and a DC power supply V_DD2Through a fourth resistor R₄And an eighth NMOS transistor M₈And a fifth resistor R₅And a ninth NMOS transistor M₉And dividing the voltage and outputting an intermediate level. At this time, the tenth NMOS transistor M₁₀Off, eleventh NMOS transistor M₁₁Conducting, twelfth PMOS transistor M₁₂Is turned off because of the eleventh NMOS transistor M₁₁Through a seventh resistor R₇And is grounded, so a low level is output.

In summary, the addend B input block 20 implements a modulo-3 addition of the input signal B with 1 and 2, respectively, denoted as B¹，B². Converting an input signal B into two different signal outputs, i.e. according to a three-valued full-adder definition, B¹，B²Will be the three inputs to SUM output module 50.

3. Carry bit C_inInput module 30

This block is connected to an addend a input block 10, the input of which is signal A, A¹And carry input signal C_in. In a three-valued full adder, carry input signal C_inThere are only two states, low and intermediate.

(1) When inputting C_inWhen low, the thirteenth NMOS transistor M₁₃Conducting the fourteenth NMOS transistor M₁₄Off, the input signal A passes through the thirteenth NMOS transistor M₁₃After flowing through the two-stage ternary inverter, the output end X is an addend A;

(2) when inputting C_inAt the middle level, the thirteenth NMOS transistor M₁₃Off, fourteenth NMOS transistor M₁₄Conducting and adding the output end A of the A input module 10¹Through a fourteenth NMOS transistor M₁₄After passing through the two-stage three-valued inverter, the output terminal X is a modulo-3 addition signal A of addend A and 1¹。

In summary, the input signal C_inRespectively control signals A and A¹The output of (3) is functionally equivalent to a transmission gate, and the output terminal X is used as an input of the character operation module 40.

4. Memristor-based character operation module 40

The character operation module 40 based on the memristor is composed of 5 threshold memristors and 9 MOS transistors, and the output is⁰X⁰，¹X¹，²X²For controlling the output of the SUM in the SUM output module 50.

Wherein the first threshold type memristor M_R1And a second threshold type memristor M_R2Is an OR gate unit, and when the input signal CP is at a high level, the first threshold type memristor M_R1Set to a low resistance state, a second threshold type memristor M_R2Is grounded, and a second threshold type memristor M_R2Set to high impedance state, Y is high level, nineteenth PMOS transistor M₁₉And the twentieth NMOS transistor M₂₀Is an inverter, N is low level, the twenty-first NMOS transistor M₂₁Off, Y is only high; when the input signal CP is at a low level, N is at a high level, and the twenty-first NMOS transistor M₂₁Conducting, wherein Y is an input signal X; i.e., CP is the enable signal, active low. When the input signal CP is at low level, the working process of the character circuit module is as follows:

(1) when the input X is at low level, the twenty-second NMOS transistor M₂₂Cut-off, third threshold type memristor M_R3Exhibits a low resistance state R_OND.C. power supply V_DD6Memristor M through third threshold type_R3Twenty third PMOS transistor M outputting high level₂₃Off, twenty-fourth NMOS transistor M₂₄Is turned on because of the twenty-fourth NMOS transistor M₂₄Grounded, so a low level is output; twenty-sixth NMOS transistor M₂₆Cut-off, fifth threshold type memristor M_R5Exhibits a low resistance state R_OND.C. power supply V_DD6Memristor M through fifth threshold type_R5Outputting a high level; twenty-seventh NMOS transistor M₂₇Is turned on because of the twenty-seventh NMOS transistor M₂₇Grounded, so a low level is output;

(2) when the input X is at the middle level, the twenty-second NMOS transistor M₂₂Cut-off, third threshold type memristor M_R3Exhibits a low resistance state R_OND.C. power supply V_DD6Memristor M through third threshold type_R3Twenty third PMOS transistor M outputting high level₂₃Off, twenty-fourth NMOS transistor M₂₄Is turned on because of the twenty-fourth NMOS transistor M₂₄Grounded, so a low level is output; twenty-sixth NMOS transistor M₂₆Is turned on because of the twenty-sixth NMOS transistor M₂₆Grounded, so a low level is output; twenty-fifth NMOS transistor M₂₅Cut-off, fourth threshold type memristor M_R4Exhibits a low resistance state R_ONTwenty seventh NMOS transistor M₂₇Cut-off, DC power supply V_DD6Memristor M through fourth threshold type_R4Output high level；

(3) When the input X is high level, the twenty-second NMOS transistor M₂₂Is turned on because of the twenty-second NMOS transistor M₂₂Grounded, so a low level is output; twenty third PMOS transistor M₂₃Conducting, twenty-fourth NMOS transistor M₂₄Cut-off, DC power supply V_DD6Through a twenty-third PMOS transistor M₂₃Outputting a high level; twenty-sixth NMOS transistor M₂₆Is turned on because of the twenty-sixth NMOS transistor M₂₆Grounded, so a low level is output; twenty-fifth NMOS transistor M₂₅On, the twenty seventh NMOS transistor M₂₇Is turned off because of the twenty-fifth NMOS transistor M₂₅And is grounded, so a low level is output.

In summary, when the input X is at a low level,⁰X⁰is at a high level,¹X¹Is at a low level,²X²Is low level; when the input X is at the intermediate level,⁰X⁰is at a low level,¹X¹Is at a high level,²X²Is low level; when the input X is at a high level,⁰X⁰is at a low level,¹X¹Is at a low level,²X²Is at a high level; the function of literal operation is realized.

5. SUM output module 50

Output of the word operation module 40⁰X⁰When high, the twenty-eighth NMOS transistor M₂₈Is turned on, the signal B passes through the twenty-eight NMOS transistor M₂₈Outputting; output of the word operation module 40¹X¹When the voltage is high, the twenty ninth NMOS transistor M₂₉On, signal B¹Through twenty ninth NMOS transistor M₂₉Outputting; output of the word operation module 40²X²When high, the thirty NMOS transistor M₃₀On, signal B²Through the thirty-eighth NMOS transistor M₃₀And (6) outputting.

In summary, SUM output module 50 realizes the selective output of SUM signal according to the output of character operation module 40⁰X⁰、¹X¹、²X²High-low separately output signal B, B of level¹、B²。

6. Carry bit C_outOutput module 60

Thirteenth resistor R in the module₁₃And a fourteenth resistance R₁₄The resistance values are the same.

When SUM is low, the thirty-first PMOS transistor M₃₁On, the thirty-second NMOS transistor M₃₂Cut-off, DC power supply V_DD7Through a thirteenth resistor R₁₃And a fourteenth resistor R₁₄Dividing voltage and outputting an intermediate level; thirty-third PMOS transistor M₃₃On, the thirty-fourth NMOS transistor M₃₄Cut-off, DC power supply V_DD8Through a thirteenth PMOS transistor M₃₃Outputting the intermediate level; when SUM is at the middle level, the thirty-first PMOS transistor M₃₁Off, thirty second NMOS transistor M₃₂Is turned on because of the thirty-second NMOS transistor M₃₂Grounded, so a low level is output; thirty-third PMOS transistor M₃₃On (threshold voltage of-0.5V), the thirty-fourth NMOS transistor M₃₄Cut-off, DC power supply V_DD8Through a thirteenth PMOS transistor M₃₃Outputting the intermediate level; when SUM is high, the thirty-first PMOS transistor M₃₁Off, thirty second NMOS transistor M₃₂Is turned on because of the thirty-second NMOS transistor M₃₂Grounded, so a low level is output; thirty-third PMOS transistor M₃₃On/off, thirty-fourth NMOS transistor M₃₄Is turned on because of the thirty-fourth NMOS transistor M₃₄Grounded, so a low level is output;

output of the word operation module 40¹X¹When high, the thirty-fifth NMOS transistor M₃₅Conducting, signal SUM₁Through the thirty-fifth NMOS transistor M₃₅Outputting; output of the word operation module 40²X²When high, the thirty-sixth NMOS transistor M₃₆Conducting, signal SUM₂Through a thirty-sixth NMOS transistor M₃₆Outputting; when addend A and carry input C_inAll at low level, outputC_outIs low level; when the addend A is high, carry is input into C_inAt an intermediate level, output C_outAt an intermediate level.

Carry bit C_outOutput module 60, when the signal is¹X¹At a high level, C_out＝SUM₁(ii) a When the signal is²X²At a high level, C_out＝SUM₂(ii) a When inputting signals A and C_inWhen all are low, C_out0; when the input signal A is high, the input signal C_inAt an intermediate level, C_out＝1。

The present invention is defined by a three-valued full adder, which directly generates the original sum input signal A, B, C through the addend B input module 20_inThe related sum signal passes through an addend A input module 10 and carries C_inThe combination of the input module 30 and the text operation module 40 generates a switching signal for controlling the output of each sum signal, i.e.⁰X⁰、¹X¹、²X²The SUM signal generated is selected and transmitted by the SUM output module 50, and a part of the carry output C is generated_outA signal; and carry C_outThe output module 60 also acts as a transmission gate, based on the control signal¹X¹、²X²To select C_outThe output is the kind of signal, so far, the function of the three-value full adder is realized. The character operation-based three-value memristor full adder adopts a new circuit design idea, and enriches the design method of memristor digital circuits.

It is to be understood that the exemplary embodiments described herein are illustrative and not restrictive. Although one or more embodiments of the present invention have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.