阅读说明：本技术 一种兼容多种ddr型号和容量的软件实现方法 (Software implementation method compatible with multiple DDR models and capacities ) 是由 唐华 于 2021-07-23 设计创作，主要内容包括：本发明提供的一种兼容多种DDR型号和容量的软件实现方法,包括以下步骤：分别侦测硬件CPU管脚上面多个GPIO的电平,并分别单独生成二进制数字,以该二进制数字为各类别的ID；根据该ID为各类别建立分支,写针对该ID对应的DDR的型号、容量的配置以及相关Training适应；适应完成后为各类别分别单独产生一个Training文件来适配该ID的DDR型号和容量。用一版软件可以兼容多种DDR型号和容量的实现,简便防呆。(The invention provides a software implementation method compatible with multiple DDR models and capacities, which comprises the following steps: respectively detecting the levels of a plurality of GPIOs on the pins of a hardware CPU (Central processing Unit), and respectively and independently generating binary digits, wherein the binary digits are used as IDs (identification) of various categories; establishing branches for each category according to the ID, and writing configuration aiming at the model and the capacity of the DDR corresponding to the ID and related Training adaptation; after the adaptation is completed, a Training file is separately generated for each category to adapt to the DDR model and the capacity of the ID. The realization of multiple DDR models and capacities can be compatible by one software, and the fool-proofing is simple and convenient.)

1. A software implementation method compatible with multiple DDR models and capacities is characterized by comprising the following steps:

respectively detecting the levels of a plurality of GPIOs on the pins of a hardware CPU (Central processing Unit), and respectively and independently generating binary digits, wherein the binary digits are used as IDs (identification) of various categories;

establishing branches for each category according to the ID, and writing configuration aiming at the model and the capacity of the DDR corresponding to the ID and related Training adaptation;

after the adaptation is completed, a Training file is separately generated for each category to adapt to the DDR model and the capacity of the ID.

2. The method as claimed in claim 1, wherein the hardware is a built-in screen with multiple models.

3. The method as claimed in claim 1, wherein the hardware is WIFI of multiple models.

4. The method as claimed in claim 1, wherein the hardware is a touch screen with multiple models.

5. The method as claimed in claim 1, wherein the hardware is a battery with multiple models.

Technical Field

The invention belongs to the technical field of electronic product software application, and particularly relates to a software implementation method compatible with multiple DDR models and capacities.

Background

In the prior electronic product, in DDR onboard design, only one software file corresponds to DDR type + capacity configuration, different configuration brushes different software, slot design is also adopted, strips with different DDR capacity can be inserted on a board for automatic identification, the strips are standard SO-DIMM or DIMM designs, the DDR configuration information is stored by arranging an SPD ROM on the DDR strip, when a mainboard is driven, BIOS bottom layer software reads the SPD information and configures the SPD information into BIOS software, and the capacity can be identified by different strips. The design that DDR board carried, only a DDR model + capacity configuration is corresponding to a software file, can make and produce very many DDR editions, just take very big energy and manpower to the management and control of software, it is wrong still to brush like this, the result of brushing wrong, do not show the capacity and make mistakes, most will cause and do not start the machine, the consequence that appears this kind is exactly need doing over again, do over again need to take very big manpower and expense, still can cause more badly, and influence the delivery date, the consequence is very serious.

Although SO-DIMM and DIMM slot designs can be compatible with different capacities, the SO-DIMM and DIMM slot designs cannot be compatible with different DDR particle types and models, and have limitation that the SO-DIMM and DIMM slot designs can only be compatible with different capacities of DDR stripes of the same type. In addition, SO-DIMM and DIMM occupy larger space and are higher. Under the trend of portability and lightness and thinness of electronic products, the space of the products cannot be reduced, and the thickness of the products cannot be reduced.

Disclosure of Invention

In view of the defects of the prior art, the invention aims to provide a software implementation method compatible with multiple DDR models and capacities, and aims to solve the problem that the prior art is not compatible with different DDR particle types and models and has limitation.

In order to achieve the purpose, the invention adopts the following technical scheme:

a software implementation method compatible with multiple DDR models and capacities comprises the following steps:

respectively detecting the levels of a plurality of GPIOs on the pins of a hardware CPU (Central processing Unit), and respectively and independently generating binary digits, wherein the binary digits are used as IDs (identification) of various categories;

establishing branches for each category according to the ID, and writing configuration aiming at the model and the capacity of the DDR corresponding to the ID and related Training adaptation;

after the adaptation is completed, a Training file is separately generated for each category to adapt to the DDR model and the capacity of the ID.

Preferably, the hardware is a built-in screen with various models.

Preferably, the hardware is WIFI of various models.

Preferably, the hardware is a touch screen with various models.

Preferably, the hardware is a plurality of types of batteries.

Compared with the prior art, the invention has the beneficial effects that:

the invention provides a software implementation method compatible with multiple DDR models and capacities, which comprises the following steps: respectively detecting the levels of a plurality of GPIOs on the pins of a hardware CPU (Central processing Unit), and respectively and independently generating binary digits, wherein the binary digits are used as IDs (identification) of various categories; establishing branches for each category according to the ID, and writing configuration aiming at the model and the capacity of the DDR corresponding to the ID and related Training adaptation; after the adaptation is completed, a Training file is separately generated for each category to adapt to the DDR model and the capacity of the ID. The realization of multiple DDR models and capacities can be compatible by one software, and the fool-proofing is simple and convenient.

Drawings

FIG. 1 is a block flow diagram of the present invention.

Detailed Description

In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

As shown in fig. 1, the software implementation method compatible with multiple DDR models and capacities provided by the present invention includes the following steps:

respectively detecting the levels of a plurality of GPIOs on the pins of a hardware CPU (Central processing Unit), and respectively and independently generating binary digits, wherein the binary digits are used as IDs (identification) of various categories;

establishing branches for each category according to the ID, and writing configuration aiming at the model and the capacity of the DDR corresponding to the ID and related Training adaptation;

after the adaptation is completed, a Training file is separately generated for each category to adapt to the DDR model and the capacity of the ID.

Specifically, the invention is mainly used for DDR on-board electronic products, because the electronic products are developed in the direction of miniaturization, portability and ultra-thinness all the time, the on-board DDR can save the PCB area and reduce the thickness of the PCBA, so the existing electronic products are slowly designed by the DDR on-board. N GPIOs are set on the CPU of the hardware as ID, the GPIOs are general purpose input/output interface of the CPU, the interfaces are pins on the CPU, the states of the pins can be detected by software, the GPIO can be connected to GND by a resistor or a power supply by a resistor, when the GPIO is connected with GND, the GPIO is in a 0 state, when the GPIO is connected with a power supply, the GPIO is in a 1 state, the n GPIOs will generate an n-bit binary number at power-on initialization, depending on whether they are pulled down to GND or up to power, e.g. (1010,0110, etc. is possible if there are 4 GPIOs), the string of second-level system digits can be defined as a DDR model and capacity configuration, the n GPIOs can generate 2 n-th-power binary digits, one second-level system digit is calculated as one configuration, one configuration corresponds to a DDR model + specific capacity, and the n GPIOs correspond to 2 n-th-power DDR models and specific capacity. After the boot-up operation, the CPU will run the software, and the software will detect the level of the n pins on the CPU. When the software code reads the high level and the low level of the GPIO on the pin of the hardware CPU, the pin of the high level is read to be a second level system 1, the pin of the low level is read to be a second level system 0, all the GPIOs are arranged to form a unique second level system number, the number can be used as an ID number, after the ID number is generated, the software code establishes a branch according to the ID number to write the configuration and the related tracing adaptation aiming at the type and the capacity of the DDR corresponding to the ID number, and after the adaptation is completed, a tracing file is generated to completely adapt to the type and the capacity of the DDR of the ID. Different DDR models and capacities are distinguished by high and low levels on the n GPIOs, so different DDR models and capacities generate different IDs, and several IDs are provided to establish several branches, so that all arrangement combinations of DDR types and capacities are compatible. The DDR system can be compatible with all different DDR types and capacities, each DDR type and capacity has an ID, the configuration of all DDR types and capacities can be compatible by using one software, and when the DDR system is started and operated, programs enter different ID branches, and the DDR system can be started. The problems of wrong brushing and wrong capacity non-alignment and non-startup caused by the wrong software brushing are completely avoided, the workload of software maintenance in research and development is greatly simplified, the efficiency is improved, the problems of wrong capacity non-alignment and non-startup caused by the wrong software brushing in production are also avoided, the time is saved, the efficiency is improved, and errors are avoided

In this embodiment, the hardware is a built-in screen with various models.

In this embodiment, the hardware is a plurality of models of WIFI.

In this embodiment, the hardware is a touch screen of multiple models.

In this embodiment, the hardware is a battery of various types.

In summary, the working principle of the invention is as follows:

the invention provides a software implementation method compatible with multiple DDR models and capacities, which comprises the following steps: respectively detecting the levels of a plurality of GPIOs on the pins of a hardware CPU (Central processing Unit), and respectively and independently generating binary digits, wherein the binary digits are used as IDs (identification) of various categories; establishing branches for each category according to the ID, and writing configuration aiming at the model and the capacity of the DDR corresponding to the ID and related Training adaptation; after the adaptation is completed, a Training file is separately generated for each category to adapt to the DDR model and the capacity of the ID. The realization of multiple DDR models and capacities can be compatible by one software, and the fool-proofing is simple and convenient.

It should be understood that equivalents and modifications of the technical solution and inventive concept thereof may occur to those skilled in the art, and all such modifications and alterations should fall within the scope of the appended claims.