阅读说明：本技术 一种基于cmos工艺的红外探测器及其制备方法 (Infrared detector based on CMOS (complementary Metal oxide semiconductor) process and preparation method thereof ) 是由 翟光杰 武佩 潘辉 翟光强 于 2021-03-26 设计创作，主要内容包括：本公开涉及一种基于CMOS工艺的红外探测器及其制备方法,红外探测器包括CMOS测量电路系统和位于CMOS测量电路系统上的CMOS红外传感结构,CMOS测量电路系统和CMOS红外传感结构均采用CMOS工艺制备；红外转换结构临近CMOS测量电路系统的表面对应柱状结构所在位置呈阶梯状,红外转换结构未与柱状结构接触的表面高于红外转换结构与柱状结构接触的表面。通过本公开的技术方案,解决了传统MEMS工艺红外探测器的性能低,像素规模低,良率低等问题,有效降低了牺牲层中间区域的凹陷程度,优化了整个红外探测器的平坦化程度。(The utility model relates to an infrared detector based on CMOS technology and a preparation method thereof, the infrared detector comprises a CMOS measuring circuit system and a CMOS infrared sensing structure positioned on the CMOS measuring circuit system, and the CMOS measuring circuit system and the CMOS infrared sensing structure are both prepared by the CMOS technology; the surface of the infrared conversion structure close to the CMOS measurement circuit system is in a step shape corresponding to the position of the columnar structure, and the surface of the infrared conversion structure which is not contacted with the columnar structure is higher than the surface of the infrared conversion structure which is contacted with the columnar structure. Through the technical scheme, the problems of low performance, low pixel scale, low yield and the like of the traditional MEMS process infrared detector are solved, the sunken degree of the middle area of the sacrificial layer is effectively reduced, and the flattening degree of the whole infrared detector is optimized.)

1. An infrared detector based on a CMOS process, comprising:

the CMOS infrared sensing structure comprises a CMOS measuring circuit system and a CMOS infrared sensing structure, wherein the CMOS measuring circuit system and the CMOS infrared sensing structure are both prepared by using a CMOS process, and the CMOS infrared sensing structure is directly prepared on the CMOS measuring circuit system;

the CMOS measurement circuit system comprises at least one layer of closed release isolation layer above the CMOS measurement circuit system, wherein the closed release isolation layer is used for protecting the CMOS measurement circuit system from being influenced by a process in the etching process of manufacturing the CMOS infrared sensing structure;

the CMOS manufacturing process of the CMOS infrared sensing structure comprises a metal interconnection process, a through hole process and an RDL (remote data link) process, wherein the CMOS infrared sensing structure comprises at least two metal interconnection layers, at least two dielectric layers and a plurality of interconnection through holes;

the CMOS infrared sensing structure comprises a reflecting layer, an infrared conversion structure and a plurality of columnar structures, wherein the reflecting layer, the infrared conversion structure and the columnar structures are positioned on the CMOS measuring circuit system;

the surface of the infrared conversion structure close to the CMOS measurement circuit system is in a step shape corresponding to the position of the columnar structure, and the surface of the infrared conversion structure which is not in contact with the columnar structure is higher than the surface of the infrared conversion structure which is in contact with the columnar structure.

2. The CMOS process-based infrared detector as claimed in claim 1, wherein a sacrificial layer to be released is disposed between the reflective layer and the infrared conversion structure, and the infrared conversion structure is electrically connected to the pillar structure through a first via hole formed in the sacrificial layer;

the surfaces of the sacrificial layers around the first through hole are higher than the bottom surface of the first through hole.

3. The CMOS process-based infrared detector as claimed in claim 2, wherein the sacrificial layer is used for making the CMOS infrared sensing structure form a hollowed-out structure, the material constituting the sacrificial layer is silicon oxide, and the sacrificial layer is etched by a post-CMOS process;

the post-CMOS process etches the sacrificial layer using at least one of gaseous hydrogen fluoride, carbon tetrafluoride, and trifluoromethane.

4. The CMOS process-based infrared detector of claim 1, wherein the CMOS infrared sensing structure further comprises a first dielectric layer comprising a patterned dielectric structure, the patterned dielectric structure is located on a same layer as the reflector plate and the support base, and a CMP process is used to make a surface of the first dielectric layer facing away from the CMOS measurement circuitry flush with a surface of the reflector layer facing away from the CMOS measurement circuitry.

5. The CMOS process-based infrared detector of claim 1, wherein said CMOS infrared sensing structure further comprises a third dielectric layer, said third dielectric layer covers a side of said pillar structure, and said infrared conversion structure is electrically connected to said pillar structure through a via formed by said third dielectric layer.

6. The CMOS process-based infrared detector according to claim 1, wherein the infrared conversion structure comprises a plurality of beam structures and an absorption plate for converting an infrared signal into an electrical signal and electrically connecting with the corresponding pillar structures through the corresponding beam structures;

the absorption plate comprises a supporting layer, an electrode layer, a heat-sensitive layer and a passivation layer, the beam structure comprises the supporting layer, the electrode layer and the passivation layer, the supporting layer is located on one side, close to the CMOS measurement circuit system, of the passivation layer, the electrode layer and the heat-sensitive layer are located between the supporting layer and the passivation layer, and the passivation layer wraps the electrode layer and the heat-sensitive layer.

7. A method for manufacturing an infrared detector based on a CMOS process, which is used for manufacturing the infrared detector based on a CMOS process according to any one of claims 1 to 6, the method for manufacturing the infrared detector based on a CMOS process comprising:

forming the reflective layer on the CMOS measurement circuitry;

forming the columnar structure on the reflective layer;

forming a sacrificial layer on the reflecting layer and processing the sacrificial layer by adopting a CMP (chemical mechanical polishing) process; wherein a polish stop interface of the CMP process for the sacrificial layer is higher than a surface of the columnar structure away from the CMOS measurement circuitry;

etching the sacrificial layer to form a first through hole corresponding to the position of the columnar structure; wherein the first through hole exposes at least part of the columnar structure;

forming the infrared conversion structure over the sacrificial layer; the infrared conversion structure is electrically connected with the columnar structure through the first through hole.

8. The method of claim 7, further comprising, before forming the pillar structure on the reflective layer:

forming a whole layer of reflecting layer on the CMOS measuring circuit system;

etching the whole reflecting layer to form the reflecting plate and the supporting base;

forming a first dielectric layer on the reflecting layer and processing the first dielectric layer by adopting a CMP (chemical mechanical polishing) process; wherein a polishing termination interface of the CMP process for the first dielectric layer is flush with a surface of the reflective layer away from the CMOS measurement circuitry.

9. The method of claim 8, wherein after depositing a first dielectric layer and processing the first dielectric layer using a CMP process, further comprising:

forming at least one protective dielectric layer on the reflecting layer;

etching the protective medium layer to form a second through hole corresponding to the position of the supporting base; wherein the second through hole exposes at least a portion of the support base.

10. The method of claim 7, further comprising, after forming the pillar structure on the reflective layer:

forming a whole third dielectric layer;

forming a sacrificial layer on the reflective layer, comprising:

and forming the sacrificial layer on the third dielectric layer.

11. The method for manufacturing an infrared detector based on a CMOS process according to claim 7, further comprising, after forming the infrared conversion structure over the sacrificial layer:

and releasing the sacrificial layer.

Technical Field

The disclosure relates to the technical field of infrared detection, in particular to an infrared detector based on a CMOS (complementary metal oxide semiconductor) process and a preparation method thereof.

Background

The fields of monitoring markets, vehicle and auxiliary markets, home markets, intelligent manufacturing markets, mobile phone applications and the like have strong demands on uncooled high-performance chips, certain requirements are provided for the performance of the chips, the performance consistency and the product price, the potential demands of more than one hundred million chips are expected every year, and the current process scheme and architecture cannot meet the market demands.

At present, an infrared detector adopts a mode of combining a measuring circuit and an infrared sensing structure, the measuring circuit is prepared by adopting a Complementary Metal-Oxide-Semiconductor (CMOS) process, and the infrared sensing structure is prepared by adopting a Micro-Electro-Mechanical System (MEMS) process, so that the following problems are caused:

(1) the infrared sensing structure is prepared by adopting an MEMS (micro-electromechanical systems) process, polyimide is used as a sacrificial layer, and the infrared sensing structure is incompatible with a CMOS (complementary metal oxide semiconductor) process.

(2) Polyimide is used as a sacrificial layer, so that the problem that the vacuum degree of a detector chip is influenced due to incomplete release exists, the growth temperature of a subsequent film is limited, and the selection of materials is not facilitated.

(3) Polyimide can cause the height of the resonant cavity to be inconsistent, and the working dominant wavelength is difficult to guarantee.

(4) The control of the MEMS process is far worse than that of the CMOS process, and the performance consistency and the detection performance of the chip are restricted.

(5) MEMS has low productivity, low yield and high cost, and can not realize large-scale batch production.

(6) The existing process capability of the MEMS is not enough to support the preparation of a detector with higher performance, and the MEMS has smaller line width and thinner film thickness, thereby being not beneficial to realizing the miniaturization of a chip.

In addition, the planarization degree of the infrared detector directly affects the infrared detection performance of the infrared detector, and how to optimize the planarization degree of the infrared detector becomes a key problem for optimizing the infrared detection performance of the infrared detector.

Disclosure of Invention

In order to solve the technical problems or at least partially solve the technical problems, the present disclosure provides an infrared detector based on a CMOS process and a method for manufacturing the same, which solve the problems of low performance, low pixel scale, low yield, and the like of the conventional MEMS process infrared detector, effectively reduce the degree of recess in the middle region of the sacrificial layer, and optimize the degree of planarization of the entire infrared detector.

In a first aspect, the present disclosure provides an infrared detector based on a CMOS process, including:

the CMOS infrared sensing structure comprises a CMOS measuring circuit system and a CMOS infrared sensing structure, wherein the CMOS measuring circuit system and the CMOS infrared sensing structure are both prepared by using a CMOS process, and the CMOS infrared sensing structure is directly prepared on the CMOS measuring circuit system;

the CMOS measurement circuit system comprises at least one layer of closed release isolation layer above the CMOS measurement circuit system, wherein the closed release isolation layer is used for protecting the CMOS measurement circuit system from being influenced by a process in the etching process of manufacturing the CMOS infrared sensing structure;

the CMOS manufacturing process of the CMOS infrared sensing structure comprises a metal interconnection process, a through hole process and an RDL (remote data link) process, wherein the CMOS infrared sensing structure comprises at least two metal interconnection layers, at least two dielectric layers and a plurality of interconnection through holes;

the CMOS infrared sensing structure comprises a reflecting layer, an infrared conversion structure and a plurality of columnar structures, wherein the reflecting layer, the infrared conversion structure and the columnar structures are positioned on the CMOS measuring circuit system;

the surface of the infrared conversion structure close to the CMOS measurement circuit system is in a step shape corresponding to the position of the columnar structure, and the surface of the infrared conversion structure which is not in contact with the columnar structure is higher than the surface of the infrared conversion structure which is in contact with the columnar structure.

Optionally, a sacrificial layer to be released is disposed between the reflective layer and the infrared conversion structure, and the infrared conversion structure is electrically connected to the columnar structure through a first through hole formed in the sacrificial layer;

the surfaces of the sacrificial layers around the first through hole are higher than the bottom surface of the first through hole.

Optionally, the sacrificial layer is used for enabling the CMOS infrared sensing structure to form a hollow structure, the material forming the sacrificial layer is silicon oxide, and the sacrificial layer is etched by a post-CMOS process;

the post-CMOS process etches the sacrificial layer using at least one of gaseous hydrogen fluoride, carbon tetrafluoride, and trifluoromethane.

Optionally, the CMOS infrared sensing structure further includes a first dielectric layer, the first dielectric layer includes a patterned dielectric structure, the reflection plate and the support base are located on the same layer, and a CMP process is used to make a surface of the first dielectric layer away from the CMOS measurement circuit system flush with a surface of the reflection layer away from the CMOS measurement circuit system.

Optionally, the CMOS infrared sensing structure further includes a third dielectric layer, the third dielectric layer covers the side surface of the columnar structure, and the infrared conversion structure is electrically connected to the columnar structure through a through hole formed in the third dielectric layer.

Optionally, the infrared conversion structure includes an absorption plate and a plurality of beam structures, the absorption plate is used for converting an infrared signal into an electrical signal and is electrically connected with the corresponding columnar structure through the corresponding beam structure;

the absorption plate comprises a supporting layer, an electrode layer, a heat-sensitive layer and a passivation layer, the beam structure comprises the supporting layer, the electrode layer and the passivation layer, the supporting layer is located on one side, close to the CMOS measurement circuit system, of the passivation layer, the electrode layer and the heat-sensitive layer are located between the supporting layer and the passivation layer, and the passivation layer wraps the electrode layer and the heat-sensitive layer.

In a second aspect, the present disclosure provides a method for manufacturing an infrared detector based on a CMOS process, which is used to manufacture the infrared detector based on a CMOS process according to the first aspect, and the method for manufacturing an infrared detector based on a CMOS process includes:

forming the reflective layer on the CMOS measurement circuitry;

forming the columnar structure on the reflective layer;

forming a sacrificial layer on the reflecting layer and processing the sacrificial layer by adopting a CMP (chemical mechanical polishing) process; wherein a polish stop interface of the CMP process for the sacrificial layer is higher than a surface of the columnar structure away from the CMOS measurement circuitry;

etching the sacrificial layer to form a first through hole corresponding to the position of the columnar structure; wherein the first through hole exposes at least part of the columnar structure;

forming the infrared conversion structure over the sacrificial layer; the infrared conversion structure is electrically connected with the columnar structure through the first through hole.

Optionally, before forming the columnar structure on the reflective layer, the method further includes:

forming a whole layer of reflecting layer on the CMOS measuring circuit system;

etching the whole reflecting layer to form the reflecting plate and the supporting base;

forming a first dielectric layer on the reflecting layer and processing the first dielectric layer by adopting a CMP (chemical mechanical polishing) process; wherein a polishing termination interface of the CMP process for the first dielectric layer is flush with a surface of the reflective layer away from the CMOS measurement circuitry.

Optionally, after depositing a first dielectric layer and processing the first dielectric layer by using a CMP process, the method further includes:

forming at least one protective dielectric layer on the reflecting layer;

etching the protective medium layer to form a second through hole corresponding to the position of the supporting base; wherein the second through hole exposes at least a portion of the support base.

Optionally, after forming the columnar structure on the reflective layer, the method further includes:

forming a whole third dielectric layer;

forming a sacrificial layer on the reflective layer, comprising:

and forming the sacrificial layer on the third dielectric layer.

Optionally, after forming the infrared conversion structure over the sacrificial layer, the method further includes:

and releasing the sacrificial layer.

Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:

(1) the CMOS measurement circuit system and the CMOS infrared sensing structure are integrally prepared on the CMOS production line by utilizing the CMOS process, compared with the MEMS process, the CMOS does not have the process compatibility problem, the technical difficulty of the MEMS process is solved, the transportation cost can be reduced by adopting the CMOS process production line process to prepare the infrared detector, and the risk caused by the transportation problem and the like is reduced; the infrared detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the polyimide of the sacrificial layer is not released cleanly to influence the vacuum degree of a detector chip, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the planarization can be easily realized by using the sacrificial layer, and the process difficulty and the possible risks are reduced; the infrared detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared detector; the infrared detector based on the CMOS process can realize smaller size and thinner film thickness of a characteristic structure, so that the infrared detector has larger duty ratio, lower thermal conductivity and smaller thermal capacity, and the infrared detector has higher detection sensitivity, longer detection distance and better detection performance; the infrared detector based on the CMOS process can make the pixel size of the detector smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of a chip; the infrared detector based on the CMOS process has the advantages of mature process production line, higher process control precision, better meeting design requirements, better product consistency, more contribution to circuit chip adjustment performance and more contribution to industrialized mass production.

(2) The CMOS infrared sensing structure comprises a reflecting layer located on the CMOS measuring circuit system, an infrared conversion structure and a plurality of columnar structures, the columnar structures are located between the reflecting layer and the infrared conversion structure, the reflecting layer comprises a reflecting plate and a supporting base, the infrared conversion structure is electrically connected with the CMOS measuring circuit system through the columnar structures and the supporting base, the infrared detector converts infrared signals into electric signals, the CMOS measuring circuit system reflects temperature signals corresponding to the infrared signals, and the temperature detection function of effective pixels of the infrared detector is achieved. In addition, the position of the surface of the infrared conversion structure close to the CMOS measurement circuit system, corresponding to the columnar structure, is in a step shape, the surface of the infrared conversion structure, which is not in contact with the columnar structure, is higher than the surface of the infrared conversion structure, which is in contact with the columnar structure, a step-shaped structure corresponding to the infrared conversion structure can be formed by utilizing the sacrificial layer, and the surface of the sacrificial layer, which is not in correspondence with the columnar structure, is higher than the surface of the sacrificial layer, which is in correspondence with the columnar structure, so that the problem that the middle part of the sacrificial layer is sunken due to a CMP process to influence the planarization degree of a subsequent preparation film layer of the infrared detector is effectively solved, the sunken degree of the middle area of the sacrificial layer can be effectively reduced, and the planarization degree of the whole infrared detector is optimized.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a schematic perspective view of an infrared detector according to an embodiment of the present disclosure;

fig. 2 is a schematic cross-sectional structure diagram of an infrared detector provided in an embodiment of the present disclosure;

fig. 3 is a schematic cross-sectional view of another infrared detector provided in the embodiments of the present disclosure;

fig. 4 is a schematic cross-sectional view of another infrared detector provided in the embodiments of the present disclosure;

fig. 5 is a schematic cross-sectional view of another infrared detector provided in the embodiments of the present disclosure;

FIG. 6 is a schematic cross-sectional view of another infrared detector provided in the embodiments of the present disclosure;

fig. 7 is a schematic structural diagram of a CMOS measurement circuitry according to an embodiment of the disclosure;

FIG. 8 is a schematic cross-sectional view of another infrared detector provided in accordance with an embodiment of the present disclosure;

fig. 9 is a schematic perspective view of another infrared detector provided in the embodiments of the present disclosure;

fig. 10 is a schematic flow chart illustrating a method for manufacturing an infrared detector according to an embodiment of the present disclosure;

fig. 11 to 21 are schematic cross-sectional structures of steps in the method for manufacturing the infrared detector shown in fig. 10.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.

Fig. 1 is a schematic perspective structure diagram of an infrared detector provided in an embodiment of the present disclosure, and fig. 2 is a schematic cross-sectional structure diagram of an infrared detector provided in an embodiment of the present disclosure. With reference to fig. 1 and 2, the CMOS process-based infrared detector includes a CMOS measurement circuit system 1 and a CMOS infrared sensing structure 2, both the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are manufactured by using a CMOS process, and the CMOS infrared sensing structure 2 is directly manufactured on the CMOS measurement circuit system 1.

Specifically, the CMOS infrared sensing structure 2 is configured to convert an external infrared signal into an electrical signal and transmit the electrical signal to the CMOS measurement circuit system 1, and the CMOS measurement circuit system 1 reflects temperature information corresponding to the infrared signal according to the received electrical signal, thereby implementing a temperature detection function of the infrared detector. The CMOS measuring circuit system 1 and the CMOS infrared sensing structure 2 are both prepared by using a CMOS process, and the CMOS infrared sensing structure 2 is directly prepared on the CMOS measuring circuit system 1, namely, the CMOS measuring circuit system 1 is prepared by using the CMOS process, and then the CMOS infrared sensing structure 2 is continuously prepared by using the CMOS process by using the CMOS production line and parameters of various processes compatible with the production line.

Therefore, the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are integrally prepared on the CMOS production line by utilizing the CMOS process, compared with the MEMS process, the CMOS process does not have the process compatibility problem, the technical difficulty of the MEMS process is solved, the transportation cost can be reduced by adopting the CMOS production line process to prepare the infrared detector, and the risk caused by the transportation problem and the like is reduced; the infrared detector takes silicon oxide as a sacrificial layer, the silicon oxide is completely compatible with a CMOS (complementary metal oxide semiconductor) process, the preparation process is simple and easy to control, the CMOS process does not have the problem that the polyimide of the sacrificial layer is not released cleanly to influence the vacuum degree of a detector chip, the subsequent film growth temperature is not limited by the material of the sacrificial layer, the multilayer process design of the sacrificial layer can be realized, the process is not limited, the planarization can be easily realized by using the sacrificial layer, and the process difficulty and the possible risks are reduced; the infrared detector prepared by the integrated CMOS process can realize the aims of high yield, low cost, high yield and large-scale integrated production of chips, and provides a wider application market for the infrared detector; the infrared detector based on the CMOS process can realize smaller size and thinner film thickness of a characteristic structure, so that the infrared detector has larger duty ratio, lower thermal conductivity and smaller thermal capacity, and the infrared detector has higher detection sensitivity, longer detection distance and better detection performance; the infrared detector based on the CMOS process can make the pixel size of the detector smaller, realize smaller chip area under the same array pixel, and is more beneficial to realizing the miniaturization of a chip; the infrared detector based on the CMOS process has the advantages of mature process production line, higher process control precision, better meeting design requirements, better product consistency, more contribution to circuit chip adjustment performance and more contribution to industrialized mass production.

With reference to fig. 1 and 2, the CMOS infrared sensing structure 2 includes a reflective layer 3, an infrared conversion structure 4, and a plurality of columnar structures 5 on the CMOS measurement circuitry 1, the columnar structures 5 are located between the reflective layer 3 and the infrared conversion structure 4, the reflective layer 3 includes a reflective plate 6 and a supporting base 7, and the infrared conversion structure 4 is electrically connected to the CMOS measurement circuitry 1 through the columnar structures 5 and the supporting base 7. Specifically, the columnar structure 5 is located between the reflective layer 3 and the infrared conversion structure 4 and used for supporting the infrared conversion structure 4 after a sacrificial layer on the CMOS measurement circuit system 1 is released, the columnar structure 5 is a metal structure, an electrical signal converted by the infrared conversion structure 4 through an infrared signal is transmitted to the CMOS measurement circuit system 1 through the corresponding columnar structure 5 and the corresponding supporting base 7, and the CMOS measurement circuit system 1 processes the electrical signal to reflect temperature information, so that non-contact infrared temperature detection of the infrared detector is realized. The infrared conversion structure 4 outputs a positive electric signal and a ground electric signal through different electrode structures, the positive electric signal and the ground electric signal are transmitted to the supporting base 7 electrically connected with the corresponding columnar structures 5 through different columnar structures 5, fig. 1 schematically illustrates that the infrared detector comprises two columnar structures 5, one of the columnar structures 5 can be set for transmitting the positive electric signal, the other columnar structure 5 is used for transmitting the ground electric signal, the infrared detector also can be set to comprise four columnar structures 5, and every two of the columnar structures 5 are a group and respectively transmit the positive electric signal and the ground electric signal.

In addition, the reflecting layer 3 comprises a reflecting plate 6 and a supporting base 7, a part of the reflecting layer 3 is used as a dielectric medium electrically connected with the CMOS measuring circuit system 1 through the columnar structure 5, namely, the supporting base 7, the reflecting plate 6 is used for reflecting infrared rays to the infrared conversion structure 4, and the secondary absorption of the infrared rays is realized by matching with a resonant cavity formed between the reflecting layer 3 and the infrared conversion structure 4, so that the infrared absorption rate of the infrared detector is improved, and the infrared detection performance of the infrared detector is optimized.

Referring to fig. 1 and fig. 2, the surface of the infrared conversion structure 4 close to the CMOS measurement circuit system 1 is disposed in a step shape corresponding to the position of the pillar structure 5, and the surface of the infrared conversion structure 4 not in contact with the pillar structure 5 is higher than the surface of the infrared conversion structure 4 in contact with the pillar structure 5, that is, the distance from the surface a to the CMOS measurement circuit system 1 in fig. 2 is greater than the distance from the surface B to the CMOS measurement circuit system 1. As shown in fig. 3, a sacrificial layer 8 is further disposed between the infrared conversion structure 4 and the reflective layer 3, the material constituting the sacrificial layer 8 may include, for example, silicon oxide to be compatible with CMOS process, the sacrificial layer 8 provides a preparation substrate for forming the infrared conversion structure 4, and the sacrificial layer 8 is released in the final infrared detector product.

The sacrificial layer 8 needs to be planarized by a CMP (Chemical Mechanical Polishing) process, and if the surface a of the infrared conversion structure 4 not in contact with the pillar structure 5 is arranged to be flush with the surface B of the infrared conversion structure 4 in contact with the pillar structure 5, a Polishing termination interface of the CMP process of the sacrificial layer 8 is flush with the upper surface of the pillar structure 5, and since Chemical reagents and grinding process parameters in the CMP process are not easy to adjust and control, the surface of the sacrificial layer 8 in the middle area in fig. 2 and 3 is lower than the surface of the sacrificial layer 8 in other areas, that is, a concave area is formed in the middle of the sacrificial layer 8, which affects the planarization degree of a subsequent film layer of the infrared detector.

The embodiment of the disclosure can utilize the sacrificial layer 8 to form a stepped structure corresponding to the infrared conversion structure 4, that is, the position of the surface of the infrared conversion structure 4 close to the CMOS measurement circuit system 1 corresponding to the columnar structure 5 is stepped, the surface a of the infrared conversion structure 4 not in contact with the columnar structure 5 is higher than the surface B of the infrared conversion structure 4 in contact with the columnar structure 5, and the polishing termination interface of the CMP process corresponding to the sacrificial layer 8 is higher than the upper surface of the columnar structure 5, so that the degree of recess of the middle region of the sacrificial layer 8 can be effectively reduced, and the degree of planarization of the whole infrared detector is optimized. The sacrificial layer 8 is used for forming the CMOS infrared sensing structure 2 into a hollow structure, the sacrificial layer 8 is made of silicon oxide, and the sacrificial layer is etched by a post-CMOS process, which may be used for etching the sacrificial layer by at least one of gaseous hydrogen fluoride, carbon tetrafluoride and trifluoromethane, the sacrificial layer 8 is made of silicon oxide to be compatible with the CMOS process, and the sacrificial layer 8 is etched by a post-CMOS process to release the sacrificial layer 8 in the final infrared detection chip product.

Optionally, with reference to fig. 1 to 3, a sacrificial layer 8 to be released is disposed between the reflective layer 3 and the infrared conversion structure 4, the infrared conversion structure 4 is electrically connected to the columnar structure 5 through a first through hole 9 formed by the sacrificial layer 8, the surface of the sacrificial layer 8 around the first through hole 9 is higher than the bottom surface of the first through hole 9, so that the position of the columnar structure 5 corresponding to the surface of the CMOS measurement circuit system 1, where the infrared conversion structure 4 is close to the CMOS measurement circuit system 1, is stepped after the sacrificial layer 8 is released, and a surface a, where the infrared conversion structure 4 is not in contact with the columnar structure 5, is higher than a surface B, where the infrared conversion structure 4 is in contact with the columnar structure 5, thereby effectively reducing the degree of recess in the middle region of the sacrificial layer 8 and optimizing the degree of planarization of the entire infrared detector.

Optionally, the CMOS infrared sensing structure 2 further includes a first dielectric layer 10, the first dielectric layer 10 includes a patterned dielectric structure, the patterned dielectric structure is located on the same layer as the reflective plate 6 and the supporting base 7, and a CMP process is adopted to make a surface of the first dielectric layer 10 away from the CMOS measurement circuitry 1 flush with a surface of the reflective layer 3 away from the CMOS measurement circuitry 1. Specifically, after the reflecting plate 6 and the supporting base 7 are prepared and formed, the first dielectric layer 10 of the whole layer is deposited on the reflecting plate 6 and the supporting base, the first dielectric layer 10 fills a gap between the reflecting plate 6 and the supporting base 7, and the first dielectric layer 10 and the reflecting layer 3 are processed by adopting a CMP (chemical mechanical polishing) process, so that the surface of the first dielectric layer 10 departing from the CMOS (complementary metal oxide semiconductor) measuring circuit system 1 is flush with the surface of the reflecting layer 3 departing from the CMOS measuring circuit system 1, the planarization of the surface of the patterned dielectric structure, the reflecting plate 6 and the supporting base 7 is effectively realized, the preparation difficulty of subsequent films can be reduced, and the planarization degree of the whole infrared detector is favorably optimized. In addition, the first dielectric layer 10, the reflector 6 and the supporting base 7 are reasonably matched, so that the CMOS measuring circuit system 1 can be well protected. Illustratively, the material constituting the first dielectric layer 10 may be configured to include at least one of silicon, germanium, a silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon carbon nitride, or silicon nitride, and the thickness of the first dielectric layer 10 may be greater than or equal to 1000A and less than or equal to 10000A. In addition, the first dielectric layer 10 also plays a role of electrical insulation, which can effectively prevent the columnar structure 5 and the reflector 7 from being electrically connected, and the first dielectric layer 10 also plays a role of isolation, which is used as an etching stop interface of the columnar structure 5.

Optionally, with reference to fig. 1 to 3, a protective dielectric layer 19 may be further disposed above the reflective layer 3, a through hole is formed at a position of the protective dielectric layer 19 corresponding to the support base 7, and the columnar structure 5 is electrically connected to the corresponding support base 7 through the through hole. Illustratively, the material constituting the support base 7 may include, for example, aluminum, the material constituting the protective dielectric layer 19 may include, for example, one or more of silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride, and the protective dielectric layer 19 may protect the support base 7 from oxidation and corrosion after the sacrificial layer 8 is released.

Optionally, with reference to fig. 1 to fig. 3, the CMOS infrared sensing structure 2 further includes a third dielectric layer 12, the third dielectric layer 12 covers a side surface of the columnar structure 5, and the infrared conversion structure 4 is electrically connected to the columnar structure 5 through a through hole formed in the third dielectric layer 12. Specifically, after the columnar structure 5 is formed, the entire third dielectric layer 12 is formed on the columnar structure 5, the material constituting the third dielectric layer 12 may be, for example, silicon carbide, a through hole penetrating through the third dielectric layer 12 is formed at a position corresponding to the columnar structure 5, the infrared conversion structure 4 is electrically connected to the columnar structure 5 through the through hole formed in the third dielectric layer 12 to realize transmission of an electrical signal obtained through conversion of an infrared signal, and the third dielectric layer 12 covers the side surface of the columnar structure 5 and covers the CMOS measurement circuit system 1, so that the columnar structure 5 and the CMOS measurement circuit system 1 are effectively protected, and the columnar structure 5 and the CMOS measurement circuit system 1 are not affected by water and oxygen in an external environment and are not affected by a reagent for releasing a sacrificial layer.

Alternatively, with reference to fig. 1 to 3, the infrared conversion structure 4 comprises an absorbing plate 13 and a plurality of beam structures 14, the absorbing plate 13 is used for converting infrared signals into electrical signals and is electrically connected with the corresponding pillar structures 5 through the corresponding beam structures 14, the absorbing plate 13 comprises a supporting layer 15, an electrode layer 16, a heat sensitive layer 17 and a passivation layer 18, the beam structures 14 comprise the supporting layer 15, the electrode layer 16 and the passivation layer 18, the supporting layer 15 is located on one side of the passivation layer 18 adjacent to the CMOS measurement circuitry 1, the electrode layer 16 and the heat sensitive layer 17 are located between the supporting layer 15 and the passivation layer 18, and the passivation layer 18 covers the electrode layer 16 and the heat sensitive layer 17.

Specifically, the pillar structure 5 is located on the CMOS measurement circuit system 1, and is configured to support the infrared conversion structure 4 after the sacrificial layer 8 on the CMOS measurement circuit system 1 is released, where the infrared conversion structure 4 includes an absorption plate 13 and a plurality of beam structures 14, and the pillar structure 5 is overlapped with the beam structures 14 to further support the infrared conversion structure 4. The supporting layer 15 is used for supporting an upper film layer in the infrared conversion structure 4 after the sacrificial layer 8 is released, the thermosensitive layer 17 is used for converting infrared temperature detection signals into infrared detection electric signals, the electrode layer 16 is used for transmitting the infrared detection electric signals converted by the thermosensitive layer 17 to the CMOS measurement circuit system 1 through the beam structures 14 on the left side and the right side, the two beam structures 14 respectively transmit positive and negative signals of the infrared detection electric signals, a reading circuit in the CMOS measurement circuit system 1 realizes non-contact infrared temperature detection through analysis of the acquired infrared detection electric signals, and passivation is used for protecting the electrode layer 16 and the thermosensitive layer 17 from oxidation or corrosion. The thermosensitive layer 17 may be located above the electrode layer 16, or may be located below the electrode layer 16. The corresponding absorption plate 13 can be arranged, the thermosensitive layer 17 and the electrode layer 16 are positioned in a closed space formed by the supporting layer 15 and the passivation layer 18 to realize protection of the thermosensitive layer 17 and the electrode layer 16 in the absorption plate 13, and the electrode layer 16 is positioned in a closed space formed by the supporting layer 15 and the passivation layer 18 to realize protection of the electrode layer 16 in the beam structure 14 corresponding to the beam structure 14.

With reference to fig. 1 to 3, the CMOS infrared sensing structure 2 includes a reflective layer 3, an infrared conversion structure 4 and a plurality of columnar structures 5 on the CMOS measurement circuitry 1, the columnar structures 5 are located between the reflective layer 3 and the infrared conversion structure 4, the reflective layer 3 includes a reflective plate 6 and a supporting base 7, and the infrared conversion structure 4 is electrically connected to the CMOS measurement circuitry 1 through the columnar structures 5 and the supporting base 7.

Specifically, the columnar structure 5 is located between the reflective layer 3 and the infrared conversion structure 4 and used for supporting the infrared conversion structure 4 after a sacrificial layer 8 on the CMOS measurement circuit system 1 is released, the sacrificial layer 8 is located between the reflective layer 3 and the infrared conversion structure 4, the columnar structure 5 is a metal structure, an electric signal converted by the infrared conversion structure 4 through an infrared signal is transmitted to the CMOS measurement circuit system 1 through the corresponding columnar structure 5 and the corresponding supporting base 7, and the CMOS measurement circuit system 1 processes the electric signal to reflect temperature information, so that non-contact infrared temperature detection of the infrared detector is realized. The CMOS infrared sensing structure 2 outputs a positive electric signal and a ground electric signal through different electrode structures, the positive electric signal and the ground electric signal are transmitted to a supporting base 7 electrically connected with the columnar structures 5 through different columnar structures 5, fig. 1 to 3 schematically show the direction parallel to the CMOS measuring circuit system 1, the CMOS infrared sensing structure 2 comprises two columnar structures 5, one of the columnar structures 5 can be arranged for transmitting the positive electric signal, the other columnar structure 5 is arranged for transmitting the ground electric signal, the CMOS infrared sensing structure 2 also comprises four columnar structures 5, and the two columnar structures are respectively a group for transmitting the positive electric signal and the ground electric signal. In addition, the reflecting layer 3 comprises a reflecting plate 6 and a supporting base 7, a part of the reflecting layer 3 is used as a dielectric medium electrically connected with the CMOS measuring circuit system 1 through the columnar structure 5, namely, the supporting base 7, the reflecting plate 6 is used for reflecting infrared rays to the infrared conversion structure 4, and the secondary absorption of the infrared rays is realized by matching with a resonant cavity formed between the reflecting layer 3 and the infrared conversion structure 4, so that the infrared absorption rate of the infrared detector is improved, and the infrared detection performance of the infrared detector is optimized.

Referring to fig. 1 to 3, the infrared conversion structure 4 includes an absorption plate 13 and a plurality of beam structures 14, and the absorption plate 13 is used to convert an infrared signal into an electrical signal and is electrically connected to the corresponding pillar structures 5 through the corresponding beam structures 14. In particular, the absorption plate 13 is used for converting infrared signals into electrical signals and electrically connecting the corresponding pillar structures 5 through the corresponding beam structures 14, the absorption plate 13 includes a support layer 15, an electrode layer 16, a thermal sensitive layer 17 and a passivation layer 18, the beam structures 14 may include a support layer 15, an electrode layer 16 and a passivation layer 18, the beam structures 14 may further include a thermal sensitive layer 17, the support layer 15 is located on one side of the passivation layer 18 adjacent to the CMOS measurement circuitry 1, the electrode layer 16 and the thermal sensitive layer 17 are located between the support layer 15 and the passivation layer 18, the passivation layer 18 covers the electrode layer 16, the thermal sensitive layer 17 can be arranged to cover the position of the beam structure 14, the thermal conductivity of the beam structure 14 can be reduced by using the characteristic of small thermal conductivity of a thermal sensitive material such as amorphous silicon, amorphous germanium or amorphous silicon germanium, and the thermal sensitive layer 17 can be used as a support material of the beam structure 14 instead of the support layer 15 and can also be used as an electrode protection material of the beam structure 14 instead of the passivation layer 18.

Specifically, the supporting layer 15 is used to support an upper film layer in the infrared conversion structure 4 after the sacrificial layer 8 is released, the thermosensitive layer 17 is used to convert an infrared temperature detection signal into an infrared detection electrical signal, the electrode layer 16 is used to transmit the infrared detection electrical signal converted by the thermosensitive layer 17 to the CMOS measurement circuit system 1 through the beam structures 14 on the left and right sides, the two beam structures 14 respectively transmit positive and negative signals of the infrared detection electrical signal, a readout circuit in the CMOS measurement circuit system 1 realizes non-contact infrared temperature detection through analysis of the acquired infrared detection electrical signal, and the passivation layer 18 is used to protect the electrode layer 16 from oxidation or corrosion. The thermosensitive layer 17 may be located above the electrode layer 16, or may be located below the electrode layer 16. The corresponding absorption plate 13 can be arranged, the thermosensitive layer 17 and the electrode layer 16 are positioned in a closed space formed by the supporting layer 15 and the passivation layer 18 to realize protection of the thermosensitive layer 17 and the electrode layer 16 in the absorption plate 13, and the electrode layer 16 is positioned in a closed space formed by the supporting layer 15 and the passivation layer 18 to realize protection of the electrode layer 16 in the beam structure 14 corresponding to the beam structure 14.

Illustratively, the material constituting the heat sensitive layer 17 may include at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, titanium oxide, vanadium oxide, or titanium vanadium oxide, the material constituting the support layer 15 may include one or more of amorphous carbon, aluminum oxide, amorphous silicon, amorphous germanium, or amorphous silicon germanium, the material constituting the electrode layer 16 may include one or more of titanium, titanium nitride, tantalum nitride, titanium tungsten alloy, nickel-chromium alloy, nickel-silicon alloy, nickel, or chromium, and the material constituting the passivation layer 18 may include one or more of amorphous carbon, aluminum oxide, amorphous silicon, amorphous germanium, or amorphous silicon germanium. In addition, when the absorption plate 13 is provided with the thermal sensitive layer 17, and the thermal sensitive layer 17 is made of amorphous silicon, amorphous carbon, amorphous germanium or amorphous silicon germanium, the supporting layer 15 and/or the passivation layer 18 on the beam structure 14 can be replaced by the thermal sensitive layer 17, because the thermal conductivity of the amorphous silicon, the amorphous germanium or the amorphous silicon germanium is small, which is beneficial to reducing the thermal conductivity of the beam structure 14 and further improving the infrared responsivity of the infrared detector.

With reference to fig. 1 to 3, at least one layer of hermetic release isolation layer 11 may be included above the CMOS measurement circuitry 1, where the hermetic release isolation layer 11 is used to protect the CMOS measurement circuitry 1 from process influence during an etching process for manufacturing the CMOS infrared sensing structure 2. Optionally, a hermetic release barrier 11 is located at an interface between the CMOS measurement circuitry 1 and the CMOS infrared sensing structure 2 and/or in the CMOS infrared sensing structure 2, the hermetic release barrier 11 is used to protect the CMOS measurement circuitry 1 from erosion when performing a corrosion process to release the sacrificial layer, and the hermetic release barrier 11 is made of a CMOS process corrosion resistant material including at least one of silicon, germanium, silicon germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, or silicon carbonitride.

Fig. 2 exemplarily sets up the hermetic release insulating layer 11 in the CMOS infrared sensing structure 2, the hermetic release insulating layer 11 may be located above the metal interconnection layer of the reflective layer 3, for example, the hermetic release insulating layer 11 covers the columnar structure 5, and by setting up the hermetic release insulating layer 11 to cover the columnar structure 5, on one hand, the hermetic release insulating layer 11 may be utilized as a support at the columnar structure 5, so as to improve the stability of the columnar structure 5, and ensure the electrical connection between the columnar structure 5 and the infrared conversion structure 4 and the supporting base 7. On the other hand, the airtight release insulating layer 11 covering the columnar structure 5 can reduce the contact between the columnar structure 5 and the external environment, reduce the contact resistance between the columnar structure 5 and the external environment, further reduce the noise of the infrared detector pixel, and improve the detection sensitivity of the infrared detection sensor. In addition, the resonant cavity of the infrared detector is realized by releasing the vacuum cavity after the silicon oxide sacrifice layer 8, the reflecting layer 3 is used as the reflecting layer of the resonant cavity, the sacrifice layer is positioned between the reflecting layer 3 and the infrared conversion structure 4, and when at least one layer of closed release isolation layer 11 positioned on the reflecting layer 3 selects silicon, germanium, silicon-germanium alloy, amorphous silicon, amorphous germanium or amorphous silicon-germanium as a part of the resonant cavity, the reflecting effect of the reflecting layer is not influenced, the height of the resonant cavity can be reduced, the thickness of the sacrifice layer 8 is further reduced, and the release difficulty of the sacrifice layer 8 formed by silicon oxide is reduced. In addition, a closed release isolation layer 11 and the columnar structure 5 are arranged to form a closed structure, so that the CMOS measurement circuit system 1 is completely separated from the sacrificial layer, and the CMOS measurement circuit system 1 is protected.

Fig. 4 is a schematic cross-sectional structure view of another infrared detector provided in the embodiment of the present disclosure. Unlike the infrared detector having the structure shown in fig. 2 and 3, in the infrared detector having the structure shown in fig. 4, the hermetic release insulating layer 11 is located at the interface between the CMOS measurement circuitry 1 and the CMOS infrared sensing structure 2, for example, the hermetic release insulating layer 11 is located between the reflective layer 3 and the CMOS measurement circuitry 1, that is, the hermetic release insulating layer 11 is located below the metal interconnection layer of the reflective layer 3, and the support base 7 is electrically connected to the CMOS measurement circuitry 1 through a through hole penetrating through the hermetic release insulating layer 11. Specifically, because the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are both formed by using a CMOS process, after the CMOS measurement circuit system 1 is formed, a wafer including the CMOS measurement circuit system 1 is transferred to a next process to form the CMOS infrared sensing structure 2, and since silicon oxide is the most commonly used dielectric material in the CMOS process and silicon oxide is mostly used as an insulating layer between metal layers on the CMOS circuit, if no insulating layer is used as a barrier when silicon oxide with a thickness of about 2um is corroded, the circuit will be seriously affected, so that a silicon oxide medium on the CMOS measurement circuit system is not corroded when the silicon oxide of the sacrificial layer is released, and a closed release insulating layer 11 is provided. After the CMOS measuring circuit system 1 is prepared and formed, a closed release isolation layer 11 is prepared and formed on the CMOS measuring circuit system 1, the CMOS measuring circuit system 1 is protected by the closed release isolation layer 11, in order to ensure the electric connection between the support base 7 and the CMOS measuring circuit system 1, after the closed release isolation layer 11 is prepared and formed, a through hole is formed in the area, corresponding to the support base 7, of the closed release isolation layer 11 through an etching process, and the support base 7 is electrically connected with the CMOS measuring circuit system 1 through the through hole. In addition, a closed release isolation layer 11 and the support base 7 are arranged to form a closed structure, so that the CMOS measurement circuit system 1 is completely separated from the sacrificial layer, and the CMOS measurement circuit system 1 is protected.

Fig. 5 is a schematic cross-sectional structure view of another infrared detector provided in the embodiment of the present disclosure. Different from the infrared detector with the structure shown in fig. 2 to 4, in the infrared detector with the structure shown in fig. 5, the interface between the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 is provided with at least one layer of closed release insulating layer 11, that is, at least one layer of closed release insulating layer 11 is provided between the reflection layer 3 and the CMOS measurement circuit system 1, and at least one layer of closed release insulating layer 11 is provided on the reflection layer 3, the effect is the same as above, and the description is omitted here.

Illustratively, the material constituting the hermetic release barrier layer 11 may include at least one of silicon, germanium, a silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, or silicon carbonitride, and the thickness of the hermetic release barrier layer 11 is equal to or greater than 100A and equal to or less than 2000A. Specifically, silicon, germanium, a silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride, and silicon carbonitride are all CMOS process corrosion resistant materials, i.e., these materials are not corroded by the sacrificial layer release agent, so the hermetic release barrier layer 11 can be used to protect the CMOS measurement circuitry 1 from corrosion when the corrosion process is performed to release the sacrificial layer. In addition, the closed release isolation layer 11 covers the CMOS measurement circuit system 1, and the closed release isolation layer 11 can also be used for protecting the CMOS measurement circuit system 1 from process influence during the etching process for manufacturing the CMOS infrared sensing structure 2. In addition, when at least one layer of airtight release isolation layer 11 is arranged on the reflection layer 3, the material for forming the airtight release isolation layer 11 is arranged to include at least one of silicon, germanium, silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon nitride or silicon carbonitride, the thickness of the first dielectric layer is greater than 100A and less than or equal to 2000A, when the airtight release isolation layer 11 is arranged to improve the stability of the columnar structure 5, the airtight release isolation layer 11 hardly influences the reflection process in the resonant cavity, the influence of the airtight release isolation layer 11 on the reflection process of the resonant cavity can be avoided, and further the influence of the airtight release isolation layer 11 on the detection sensitivity of the infrared detector is avoided.

With reference to fig. 1 to 5, a CMOS fabrication process of the CMOS infrared sensing structure 2 includes a metal interconnection process, a via process and an RDL process, the CMOS infrared sensing structure 2 includes at least two metal interconnection layers, at least two dielectric layers and a plurality of interconnection vias, the dielectric layers include at least one sacrificial layer and one heat-sensitive dielectric layer, the heat-sensitive dielectric layer includes at least a heat-sensitive layer 17, and may further include a supporting layer 15 and/or a passivation layer 18, and the metal interconnection layers include at least a reflective layer 3 and an electrode layer 16; the thermal sensitive medium layer comprises a thermal sensitive material with a resistance temperature coefficient larger than a set value, the resistance temperature coefficient can be larger than or equal to 0.015/K, for example, the thermal sensitive material with the resistance temperature coefficient larger than the set value forms a thermal sensitive layer 17 in the thermal sensitive medium layer, the thermal sensitive medium layer is used for converting temperature change corresponding to infrared radiation absorbed by the thermal sensitive medium layer into resistance change, and further converting an infrared target signal into a signal capable of realizing electric reading through the CMOS measuring circuit system 1.

Specifically, the metal interconnection process is used for realizing the electrical connection of an upper metal interconnection layer and a lower metal interconnection layer, the through hole process is used for forming an interconnection through hole for connecting the upper metal interconnection layer and the lower metal interconnection layer, the RDL process is a rewiring layer process, specifically, a layer of metal is re-distributed above the top metal of the circuit and is electrically connected with the top metal of the circuit through a tungsten column, the RDL process can be adopted to prepare the reflection layer 3 in the infrared detector on the top metal of the CMOS measurement circuit system 1, and the support base 7 on the reflection layer 3 is electrically connected with the top metal of the CMOS measurement circuit system 1. In addition, the heat-sensitive dielectric layer comprises a heat-sensitive material with a resistance temperature coefficient larger than a set value, and the resistance temperature coefficient can be larger than or equal to 0.015/K, so that the detection sensitivity of the infrared detector can be improved.

Fig. 6 is a schematic cross-sectional view of another infrared detector provided in the embodiments of the present disclosure. As shown in fig. 6, on the basis of the above embodiment, the CMOS manufacturing process of the CMOS measurement circuit system 1 may also include a metal interconnection process and a via process, the CMOS measurement circuit system 1 includes metal interconnection layers 101, dielectric layers 102 and a silicon substrate 103 at the bottom, the upper and lower metal interconnection layers 101 are electrically connected through vias 104,

with reference to fig. 1 to 6, the CMOS infrared sensing structure 2 includes a resonant cavity formed by a reflective layer 3 and a thermal sensitive dielectric layer, a suspended microbridge structure for controlling heat transfer, and a pillar structure 5 having electrical connection and support functions, and the CMOS measurement circuit system 1 is configured to measure and process an array resistance value formed by one or more CMOS infrared sensing structures 2, and convert an infrared signal into an image electrical signal.

Specifically, the resonant cavity may be formed by a cavity between the reflective layer 3 and the absorbing plate 13, for example, infrared light is reflected back and forth in the resonant cavity through the absorbing plate 13 to improve the detection sensitivity of the infrared detector, and due to the arrangement of the columnar structure 5, the beam structure 14 and the absorbing plate 13 form a suspended micro-bridge structure for controlling heat transfer, and the columnar structure 5 is electrically connected to the supporting base 7 and the corresponding beam structure 14 and is also used for supporting the infrared conversion structure 4 on the columnar structure 5.

Fig. 7 is a schematic structural diagram of a CMOS measurement circuit system according to an embodiment of the present disclosure. With reference to fig. 1 to fig. 7, the CMOS measurement circuit system 1 includes a bias voltage generation circuit 701, a column-level analog front-end circuit 801 and a row-level circuit 901, an input terminal of the bias voltage generation circuit 701 is connected to an output terminal of the row-level circuit 901, an input terminal of the column-level analog front-end circuit 801 is connected to an output terminal of the bias voltage generation circuit 701, the row-level circuit 901 includes a row-level mirror image element Rsm and a row selection switch K1, and the column-level analog front-end circuit 801 includes a blind image element RD; the row-level circuit 901 is distributed in each pixel, selects a signal to be processed according to a row strobe signal of the timing generation circuit, and outputs a current signal to the column-level analog front-end circuit 801 under the action of the bias generation circuit 701 to perform current-voltage conversion output; the row stage circuit 901 outputs a third bias voltage VRsm to the bias generation circuit 701 when being controlled by the row selection switch K1 to be gated, the bias generation circuit 701 outputs a first bias voltage V1 and a second bias voltage V2 according to the input constant voltage and the third bias voltage VRsm, and the column stage analog front-end circuit 801 obtains two currents according to the first bias voltage V1 and the second bias voltage V2, performs transimpedance amplification on the difference between the two generated currents, and outputs the amplified current as an output voltage.

Specifically, the row-level circuit 901 includes a row-level mirror image element Rsm and a row selection switch K1, and the row-level circuit 901 is configured to generate a third bias voltage VRsm according to a gating state of the row selection switch K1. For example, the row-level image elements Rsm may be subjected to a shading process such that the row-level image elements Rsm are subjected to a fixed radiation by a shading sheet having a temperature constantly equal to a substrate temperature, the row selection switch K1 may be implemented by a transistor, the row selection switch K1 is closed, and the row-level image elements Rsm are connected to the bias generation circuit 701, that is, the row-level circuit 901 outputs the third bias voltage VRsm to the bias generation circuit 701 when being gated by the row selection switch K1. The bias generation circuit 701 may include a first bias generation circuit 71 and a second bias generation circuit 72, the first bias generation circuit 71 being configured to generate a first bias voltage V1 according to an input constant voltage, which may be, for example, a positive power supply signal with a constant voltage. The second bias generating circuit 72 may include a bias control sub-circuit 721 and a plurality of gate driving sub-circuits 722, the bias control sub-circuit 721 controlling the gate driving sub-circuits 722 to generate the corresponding second bias voltages V, respectively, according to the third bias voltage VRsm.

The column-level analog front-end circuit 801 includes a plurality of column control sub-circuits 81, the column control sub-circuits 81 are disposed corresponding to the gate driving sub-circuits 722, and exemplarily, the column control sub-circuits 81 may be disposed corresponding to the gate driving sub-circuits 722 in a one-to-one manner, and the gate driving sub-circuits 722 are configured to provide the second bias voltage V2 to the corresponding column control sub-circuits 81 according to their own gate states. For example, it may be set that when the gate driving sub-circuit 722 is gated, the gate driving sub-circuit 722 supplies the second bias voltage V2 to the corresponding column control sub-circuit 81; when the gate driving sub-circuit 722 is not gated, the gate driving sub-circuit 722 stops supplying the second bias voltage V2 to the corresponding column control sub-circuit 81.

The column-level analog front-end circuit 801 comprises an effective pixel RS and a blind pixel RD, the column control sub-circuit is used for generating a first current I1 according to a first bias voltage V1 and the blind pixel RD, generating a second current I2 according to a second bias voltage V2 and the effective pixel RS, performing transimpedance amplification on a difference value between the first current I1 and the second current I2, and outputting the difference value, and the row-level mirror image pixel Rsm and the effective pixel RS have the same temperature drift amount at the same ambient temperature.

Illustratively, the row-level image elements Rsm are thermally insulated from the CMOS measurement circuitry 1 and are shaded, and the row-level image elements Rsm are subjected to a fixed radiation from a shade sheet having a temperature constantly equal to the substrate temperature. The absorption plate 13 of the active pixel RS is thermally insulated from the CMOS measurement circuitry 1 and the active pixel RS receives external radiation. The absorbing plates 13 of the row-level mirror image elements Rsm and the effective elements RS are thermally insulated from the CMOS measuring circuit system 1, so that the row-level mirror image elements Rsm and the effective elements RS have a self-heating effect.

When the corresponding row-level mirror image element Rsm is gated through the row selection switch K1, the resistance value of the row-level mirror image element Rsm and the resistance value of the effective element RS are changed due to joule heat, but when the row-level mirror image element Rsm and the effective element RS are subjected to the same fixed radiation, the resistance value of the row-level mirror image element Rsm and the resistance value of the effective element RS are the same, the temperature coefficients of the row-level mirror image element Rsm and the temperature coefficient of the effective element RS are the same, the temperature drift amounts of the row-level mirror image element Rsm and the effective element RS are the same at the same ambient temperature, the change of the row-level mirror image element Rsm and the temperature drift amounts of the effective element RS at the same ambient temperature are synchronized, the resistance value change of the row-level mirror image element Rsm and the effective element RS due to the self-heating effect is effectively compensated, and the stable output of the reading circuit is achieved.

In addition, by arranging the second bias generating circuit 701 to include a bias control sub-circuit 721 and a plurality of gate driving sub-circuits 722, the bias control sub-circuit 721 is configured to control the gate driving sub-circuits 722 to generate corresponding second bias voltages V2 respectively according to the row control signal, so that each row of pixels has one path to drive the whole columns of pixels of the row individually, the requirement for the second bias voltage V2 is reduced, that is, the driving capability of the bias generating circuit 701 is improved, and the readout circuit is advantageously used for driving a larger-scale infrared detector pixel array. In addition, the specific detailed operation principle of the CMOS measurement circuit system 1 is well known to those skilled in the art and will not be described herein.

Alternatively, the CMOS infrared sensing structure 2 may be disposed on a metal interconnect layer of the CMOS measurement circuitry 1 or fabricated on the same layer. Specifically, the metal interconnection layer of the CMOS measurement circuitry 1 may be a top metal layer in the CMOS measurement circuitry 1, and in conjunction with fig. 1 to 7, the CMOS infrared sensing structure 2 may be fabricated on the metal interconnection layer of the CMOS measurement circuitry 1, and the CMOS infrared sensing structure 2 is electrically connected to the CMOS measurement circuitry 1 through a supporting base 7 on the metal interconnection layer of the CMOS measurement circuitry 1, so as to transmit an electrical signal converted by an infrared signal to the CMOS measurement circuitry 1.

Fig. 8 is a schematic cross-sectional structure view of another infrared detector provided in the embodiment of the present disclosure, and as shown in fig. 8, a CMOS infrared sensing structure 2 is prepared on the same layer of a metal interconnection layer of a CMOS measurement circuit system 1, that is, the CMOS measurement circuit system 1 and the CMOS infrared sensing structure 2 are arranged on the same layer, as shown in fig. 8, the CMOS infrared sensing structure 2 is arranged on one side of the CMOS measurement circuit system 1, and a hermetic release isolation layer 11 may also be arranged on the top of the CMOS measurement circuit system 1 to protect the CMOS measurement circuit system 1.

Optionally, in conjunction with fig. 1 to 8, the CMOS infrared sensing structure 2 includes an absorption plate 13, a beam structure 14, a reflection layer 3 and a pillar structure 5, the absorption plate 13 includes a metal interconnection layer and at least one thermal sensitive medium layer, the material constituting the thermal sensitive medium layer includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, titanium oxide, vanadium oxide or vanadium titanium oxide, the metal interconnection layer in the absorption plate 13 is an electrode layer 16 in the absorption plate 13 for transmitting the electrical signal converted from the infrared signal, the thermal sensitive medium layer includes at least a thermal sensitive layer 17 and may further include a supporting layer 15 and a passivation layer 18, the material constituting the thermal sensitive medium layer includes at least one of amorphous silicon, amorphous germanium, amorphous silicon germanium, titanium oxide, vanadium oxide or vanadium titanium oxide, that is, the material constituting the thermosensitive layer 17 includes at least one of amorphous silicon, amorphous germanium, amorphous silicon-germanium, titanium oxide, vanadium oxide, or titanium vanadium oxide.

The beam structures 14 and the columnar structures 5 are used for transmitting electrical signals and for supporting and connecting the absorption plates 13, the electrode layers 16 in the absorption plates 13 include two patterned electrode structures, the two patterned electrode structures output positive electrical signals and ground electrical signals respectively, the positive electrical signals and the ground electrical signals are transmitted to the supporting base electrically connected with the columnar structures 5 through the different beam structures 14 and the different columnar structures 5 and then transmitted to the CMOS measurement circuit system 1, the beam structures 14 include metal interconnection layers and at least one dielectric layer, the metal interconnection layers in the beam structures 14 are the electrode layers 16 in the beam structures 14, the electrode layers 16 in the beam structures 14 are electrically connected with the electrode layers 16 in the absorption plates 13, and the dielectric layers in the beam structures 14 may include supporting layers 15 and passivation layers 18.

The columnar structure 5 is connected with the beam structure 14 and the CMOS measuring circuit system 1 by adopting a metal interconnection process and a through hole process, the upper part of the columnar structure 5 is required to be electrically connected with an electrode layer 16 in the beam structure 14 through a through hole penetrating through a supporting layer 15 in the beam structure 14, and the lower part of the columnar structure 5 is required to be electrically connected with a corresponding supporting base 7 through a through hole penetrating through a dielectric layer on the supporting base 7. The reflecting plate 6 is used for reflecting infrared signals and forms a resonant cavity with the heat-sensitive medium layer, namely the reflecting plate 6 is used for reflecting infrared signals and forms a resonant cavity with the heat-sensitive medium layer in the heat-sensitive medium layer, and the reflecting layer 3 comprises at least one metal interconnection layer which is used for forming a supporting base 7 and is also used for forming the reflecting plate 6.

Alternatively, it is possible to provide that at least two ends of the beam structure 14 and the absorber plate 13 are electrically connected, the CMOS infrared sensing structure 2 includes at least two columnar structures 5 and at least two support bases 7, and the electrode layer 16 includes at least two electrode terminals. Specifically, as shown in fig. 1, the beam structures 14 are electrically connected to two ends of the absorbing plate 13, each beam structure 14 is electrically connected to one end of the absorbing plate 13, the CMOS infrared sensing structure 2 includes two pillar structures 5, the electrode layer 16 includes at least two electrode terminals, at least a portion of the electrode terminals transmit a positive electrical signal, at least a portion of the electrode terminals transmit a negative electrical signal, and the signals are transmitted to the supporting base 7 through the corresponding beam structures 14 and pillar structures 5.

Fig. 9 is a schematic perspective view of another infrared detector provided in the embodiments of the present disclosure. As shown in fig. 9, it is also possible to provide beam structures 14 electrically connected to four ends of the absorbing plate 13, each beam structure 14 electrically connected to two ends of the absorbing plate 13, and the CMOS infrared sensing structure 2 includes four columnar structures 5, and one beam structure 14 connects two columnar structures 5. It should be noted that, in the embodiment of the present disclosure, the number of the connecting ends of the beam structure 14 and the absorbing plate 13 is not particularly limited, and it is sufficient that the beam structure 14 and the electrode terminal are respectively present, and the beam structure 14 is used for transmitting the electrical signal output by the corresponding electrode terminal.

Alternatively, the infrared detector may be configured based on a 3nm, 7nm, 10nm, 14nm, 22nm, 28nm, 32nm, 45nm, 65nm, 90nm, 130nm, 150nm, 180nm, 250nm or 350nm CMOS process, which characterizes process nodes of the integrated circuit, i.e., features during the processing of the integrated circuit.

Alternatively, the metal wiring material constituting the metal interconnection layer in the infrared detector may be configured to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt, and for example, the material constituting the reflective layer may be configured to include at least one of aluminum, copper, tungsten, titanium, nickel, chromium, platinum, silver, ruthenium, or cobalt. In addition, the CMOS measuring circuit system 1 and the CMOS infrared sensing structure 2 are both prepared by using a CMOS process, the CMOS infrared sensing structure 2 is directly prepared on the CMOS measuring circuit system 1, the radial side length of the columnar structure 5 is more than or equal to 0.5um and less than or equal to 3um, the width of the beam structure 14, namely the width of a single line in the beam structure 14 is less than or equal to 0.3um, the height of a resonant cavity is more than or equal to 1.5um and less than or equal to 2.5um, and the side length of a single pixel of the CMOS infrared sensing structure 2 is more than or equal to 6um and less than or equal to 17 um.

The embodiment of the disclosure also provides a method for manufacturing an infrared detector based on a CMOS process, and fig. 10 is a schematic flow chart of the method for manufacturing an infrared detector provided by the embodiment of the disclosure. The method of manufacturing the infrared detector may be used to manufacture the infrared detector as in the above embodiments. As shown in fig. 10, the method for manufacturing the infrared detector based on the CMOS process includes:

and S110, forming a reflecting layer on the CMOS measuring circuit system.

As shown in fig. 11 and 12, a CMOS measurement circuit system 1 is provided, an entire reflection layer 3 is formed on the CMOS measurement circuit system 1, a material constituting the reflection layer 3 may be, for example, aluminum, the entire reflection layer 3 is etched to form a reflection plate 6 and a support base 7, a first dielectric layer 10 is formed on the reflection layer 3, and the first dielectric layer 10 is processed by a CMP process, the material constituting the first dielectric layer 10 may be, for example, silicon oxide, and a polishing termination interface of the CMP process for the first dielectric layer 10 is flush with a surface of the reflection layer 3 away from the CMOS measurement circuit system 1, that is, an upper surface of the first dielectric layer 10 is polished flush with an upper surface of the reflection layer 3. Therefore, the patterned medium structure, the reflecting plate 6 and the supporting base 7 are effectively flattened, the preparation difficulty of subsequent films can be reduced, and the flattening degree of the whole infrared detector can be optimized. In addition, the first dielectric layer 10, the reflector 6 and the supporting base 7 are reasonably matched, so that the CMOS measuring circuit system 1 can be well protected. Illustratively, the material constituting the first dielectric layer 10 may be at least one of silicon, germanium, a silicon-germanium alloy, amorphous silicon, amorphous germanium, amorphous silicon-germanium, amorphous carbon, silicon carbide, aluminum oxide, silicon carbonitride or silicon nitride, and the thickness of the first dielectric layer 10 may be greater than or equal to 1000A and less than or equal to 10000A.

As shown in fig. 13, after depositing the first dielectric layer 10 and processing the first dielectric layer 10 by using a CMP process, at least one protective dielectric layer 19 is formed on the reflective layer 3, the protective dielectric layer 19 is etched to form a second through hole corresponding to the position of the support base 7, at least a portion of the support base 7 is exposed out of the second through hole, the material forming the protective dielectric layer 19 may be, for example, silicon nitride, and the thickness of the protective dielectric layer 19 may be, for example, 1000A, and the protective dielectric layer 19 can effectively protect the reflective layer 3 and the first dielectric layer 10 from external water oxygen or a reagent for releasing the sacrificial layer 8. In addition, the first dielectric layer 10 also plays a role of electrical insulation, and can effectively prevent the columnar structure 5 and the reflector 7 from being electrically connected, and the fourth dielectric layer 21 also plays a role of isolation, and serves as an etching stop interface of the columnar structure 5.

And S120, forming a columnar structure on the reflecting layer.

As shown in fig. 14, the columnar structure 5 may be formed on the reflective layer 3, for example, the columnar structure 5 may be formed on the protective dielectric layer 19 shown in fig. 13, the material constituting the columnar structure 5 may be, for example, aluminum, and the cross section of the columnar structure 5 may be in a regular trapezoid shape.

As shown in fig. 15, after the pillar-shaped structure 5 is formed on the reflective layer 3, an entire third dielectric layer 12 is formed, for example, the entire third dielectric layer 12 may be formed above the pillar-shaped structure 5, the material constituting the third dielectric layer 12 may be, for example, silicon carbide, and the third dielectric layer 12 covers the side surface of the pillar-shaped structure 5 and covers the CMOS measurement circuit system 1, so that the pillar-shaped structure 5 and the CMOS measurement circuit system 1 are effectively protected, and the pillar-shaped structure 5 and the CMOS measurement circuit system 1 are not affected by water and oxygen in the external environment and are not affected by the reagent for releasing the sacrificial layer.

S130, forming a sacrificial layer on the reflecting layer and processing the sacrificial layer by adopting a CMP (chemical mechanical polishing) process; wherein the CMP process for the sacrificial layer has a polish stop interface higher than a surface of the pillar structures away from the CMOS measurement circuitry.

As shown in fig. 16, the sacrificial layer 8 is formed on the reflective layer 3, and the sacrificial layer 8 may be formed on the third dielectric layer 12, and the sacrificial layer 8 is processed by a CMP process, wherein a polishing stop interface of the CMP process for the sacrificial layer 8 is higher than a surface of the columnar structure 5 away from the CMOS measurement circuit system 1.

S140, etching the sacrificial layer to form a first through hole corresponding to the position of the columnar structure; wherein, the first through hole exposes at least part of the columnar structure.

As shown in fig. 16, the sacrificial layer 8 is etched to form a first through hole 9 corresponding to the position of the columnar structure 5, and at least part of the columnar structure 5 is exposed from the first through hole 9, so that the surface of the sacrificial layer 8 around the first through hole 9 is higher than the bottom surface of the first through hole 9, and thus the surface of the infrared conversion structure 4 adjacent to the CMOS measurement circuit system 1 is stepped corresponding to the position of the columnar structure 5 after the sacrificial layer 8 is released, and the surface of the infrared conversion structure 4 not in contact with the columnar structure 5 is higher than the surface of the infrared conversion structure 4 in contact with the columnar structure 5, thereby effectively reducing the degree of depression in the middle area of the sacrificial layer 8 and optimizing the planarization degree of the entire infrared detector.

S150, forming an infrared conversion structure above the sacrificial layer; the infrared conversion structure is electrically connected with the columnar structure through the first through hole.

As shown in fig. 17, the infrared conversion structure 4 is formed above the sacrificial layer 8, a support layer 15 may be formed on the sacrificial layer 8, and the third dielectric layer 12 and the support layer 15 disposed at positions corresponding to the pillar structures 5 may be etched to form through holes exposing the upper surfaces of the pillar structures 5.

As shown in fig. 18, the electrode layer 16 is formed on the support layer 15, the electrode layer 16 is etched to form a patterned electrode structure, the patterned structure corresponding to the position of the absorbing plate 13 includes two patterned electrode structures for transmitting positive and negative signals, respectively, and the patterned electrode structure corresponding to the shape of the beam structure 14 is formed at the same time, and the patterned electrode structure is electrically connected to the corresponding columnar structure 5 through a through hole corresponding to the upper surface of the columnar structure 5.

As shown in fig. 19, the entire surface of the heat sensitive layer 17 is formed on the electrode layer 16, the heat sensitive layer 17 is etched to form a patterned heat sensitive structure, and the patterned heat sensitive structure is formed at least in the region of the absorber plate 13, and the beam structure 14 may or may not have the patterned heat sensitive structure.

As shown in fig. 20, a passivation layer 18 is formed on the entire surface of the thermal sensitive layer 17, and the passivation layer 18 and the support layer 15 are etched, so that the thermal sensitive layer 17 and the electrode layer 16 are located in a closed space formed by the support layer 15 and the passivation layer 18 corresponding to the absorber plate 13, and the thermal sensitive layer 17 and the electrode layer 16 in the absorber plate 13 are protected, and the electrode layer 16 is located in a closed space formed by the support layer 15 and the passivation layer 18 corresponding to the beam structure 14, and the electrode layer 16 in the beam structure 14 is protected.

As shown in fig. 21, after forming the infrared conversion structure 4 over the sacrificial layer 8, a release sacrificial layer 8 is further included to form a final infrared detector product, and the material constituting the sacrificial layer 8 may include silicon oxide, for example, the sacrificial layer 8 may be released using at least one of gas-phase hydrogen fluoride, carbon tetrafluoride and trifluoromethane.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.