阅读说明：本技术 存储器装置 (Memory device ) 是由 葛新城 于 2020-05-25 设计创作，主要内容包括：本公开的实施例涉及存储器装置。一种存储器装置包含至少一个第一寄存器、一存储器电路、一分析电路以及一控制电路。存储器电路包含多个位单元。分析电路被配置为对这些位单元执行一分析程序,以产生一分析结果。若分析结果指示这些位单元中的一第一位单元失效,控制电路控制一数据写入至少一个第一寄存器,及控制数据从至少一个第一寄存器读出,以完成一修复程序。(Embodiments of the present disclosure relate to memory devices. A memory device includes at least a first register, a memory circuit, an analysis circuit, and a control circuit. The memory circuit includes a plurality of bit cells. The analysis circuit is configured to perform an analysis procedure on the bit cells to generate an analysis result. If the analysis result indicates that a first bit cell in the bit cells fails, the control circuit controls data to be written into the at least one first register and controls data to be read out from the at least one first register so as to complete a repair procedure.)

1. A memory device, comprising:

at least one first register;

a memory circuit comprising a plurality of bit cells;

an analysis circuit configured to perform an analysis procedure on the bit cell to produce an analysis result; and

control circuitry, wherein if the analysis result indicates a failure of a first one of the bit cells, the control circuitry controls writing of data to the at least one first register and controls reading of the data from the at least one first register to complete a repair procedure.

2. The memory device of claim 1, wherein a capacity of the at least one first register is equal to a column capacity or a row capacity of the memory circuit.

3. The memory device of claim 1, wherein the number of the at least one first register is N, and N is a positive integer greater than 1.

4. The memory device of claim 3, further comprising:

a selection circuit coupled to N of the first registers,

wherein the control circuit is configured to output a selection signal according to the analysis result, and the selection circuit is configured to read out the data from one of the N first registers according to the selection signal.

5. The memory device according to claim 1, wherein the control circuit is configured to enable the at least one first register to write the data into the at least one first register or to read the data out of the at least one first register depending on one of a write address and a read address and an invalid address of the first bit cell.

6. The memory device of claim 5, further comprising:

a second register to store the failing address.

7. The memory device of claim 5, further comprising:

a non-transitory storage circuit to store the fail address.

8. The memory device of claim 1, wherein the memory device is to perform the analysis procedure based on a plurality of operating voltages to obtain a plurality of fail addresses, and the control circuitry performs the repair procedure on the fail addresses.

9. The memory device of claim 1, wherein the control circuit is further configured to adjust a transmission gear of the memory device to generate a plurality of adjusted transmission gears, and the memory device is configured to execute the analysis procedure according to the adjusted transmission gears to obtain a plurality of fail addresses, and the control circuit executes the repair procedure on the fail addresses, wherein the transmission gears correspond to an upper frequency limit.

10. A memory device, comprising:

a memory circuit comprising a plurality of bit cells;

an analysis circuit configured to analyze the bit cell to produce an analysis result; and

a control circuit, wherein if the analysis result indicates that a first one of the bit cells is failed, the control circuit adjusts an operating voltage of the memory device to generate an adjusted operating voltage, and the memory device operates according to the adjusted operating voltage.

Technical Field

Embodiments described in the present disclosure relate to a memory technology, and more particularly, to a memory device having a repair mechanism.

Background

With the development of memory technology, memory devices have been applied to various fields to store various data. Based on different applications (e.g., different power consumption), the memory device needs to operate under different environmental conditions. When a bit cell (bit cell) in the memory device fails, the normal operation of the memory device will be affected.

Disclosure of Invention

Some embodiments of the present disclosure relate to a memory device. The memory device includes at least one first register, a memory circuit, an analysis circuit, and a control circuit. The memory circuit includes a plurality of bit cells. The analysis circuit is configured to perform an analysis procedure on the bit cells to generate an analysis result. If the analysis result indicates that a first bit cell in the bit cells fails, the control circuit controls data to be written into the at least one first register and controls data to be read out from the at least one first register so as to complete a repair procedure.

Some embodiments of the present disclosure relate to a memory device. The memory device includes a memory circuit, an analysis circuit, and a control circuit. The memory circuit includes a plurality of bit cells. The analysis circuit is configured to analyze the bit cells to produce an analysis result. If the analysis result indicates that a first bit cell of the bit cells fails, the control circuit adjusts an operating voltage of the memory device to generate an adjusted operating voltage, and the memory device operates according to the adjusted operating voltage.

In summary, the memory device of the present disclosure has a better repair mechanism, and the overall yield can be improved.

Drawings

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more comprehensible, the following description is given:

FIG. 1 is a schematic diagram of a memory device according to some embodiments of the present disclosure;

FIG. 2 is a schematic diagram of a memory device according to some embodiments of the present disclosure;

FIG. 3 is a schematic diagram of a memory device according to some embodiments of the present disclosure;

and

fig. 4 is a schematic diagram of a memory device according to some embodiments of the present disclosure.

Detailed Description

All terms used herein have their ordinary meaning. The definitions of the above-mentioned words in commonly used dictionaries, any use of the words discussed herein in this disclosure is intended to be exemplary only and should not be construed as limiting the scope and meaning of the disclosure. Likewise, the present disclosure is not limited to the various embodiments shown in this specification.

The term "coupled," as used herein, may also refer to "electrically coupled," and the term "connected," may also refer to "electrically connected. "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.

Refer to fig. 1. Fig. 1 is a schematic diagram of a memory device 100 according to some embodiments of the disclosure. Taking the example of fig. 1, the memory device 100 includes a memory circuit 120, an analyzing circuit 130, a control circuit 140, a selecting circuit 150, and a register REG 2. Memory device 100 also includes registers REG [1] -REG [ N ], where N is a positive integer equal to or greater than 1.

Memory circuit 120 is coupled to analysis circuit 130, control circuit 140, and selection circuit 150. The analysis circuit 130 is coupled to a control circuit 140. Control circuit 140 is coupled to selection circuit 150, registers REG [1] -REG [ N ], and register REG 2. Registers REG [1] -REG [ N ] are coupled to selection circuit 150.

The memory circuit 120 includes a plurality of Bit Cells (BC). The bit cells may also be referred to as memory cells. In this example, the memory circuit 120 includes 8192 × 64 bit cells BC. That is, the bit cells BC are arranged in an array of 8192 rows (row) and 64 columns (column). The above-mentioned number of bit cells BC in the memory circuit 120 is only used as an example, and various applicable numbers are all within the scope of the present disclosure.

The analysis circuit 130 is configured to perform an analysis procedure on the bit cells BC in the memory circuit 120 to determine which bit cells BC of the bit cells BC are failed (fail), thereby generating an analysis result AR. If one of the bit cells BC fails, it means that the bit cell BC cannot read and write data normally. The analysis result AR will carry the address (fail address) of this bit cell BC.

The control circuit 140 is used for receiving the analysis result AR. As described above, the control circuit 140 receives the analysis result AR carrying the address of the failed bit cell BC. In some embodiments, the control circuit 140 stores the analysis result AR in the register REG 2. That is, the register REG2 may store the address of the failed bit cell BC.

When an external processor (not shown) wants to perform a write procedure on the memory device 100, the external processor sends a control signal CS to the control circuit 140 to control the control circuit 140 to power on/off. The external processor also sends the write address AD to the memory circuit 120 and the control circuit 140, and sends the DATA to be written to the memory circuit 120. The control circuit 140 can determine whether the write address AD is a failed address according to the analysis result AR. For example, the control circuit 140 may compare the write address AD with the fail address carried in the analysis result AR to determine whether the write address AD is the fail address. If the write address AD is a fail address, the control circuit 140 sends an enable signal EN to enable a corresponding register (e.g., register REG [1]) to write the DATA DATA to be written into the register REG [1 ]. Therefore, the DATA to be written can be prevented from being stored into the memory circuit 120 at the failed address, so that the memory device 100 can operate normally.

When the external processor wants to execute a read program on the memory device 100, the external processor sends a read address AD to the memory circuit 120 and the control circuit 140. If the control circuit 140 determines that the read address AD is a fail address, the control circuit 140 sends a selection signal SEL to the selection port of the selection circuit 150 based on the read address AD. The selection circuit 150 selects a corresponding register (e.g., register REG [1]) according to the selection signal SEL, and reads OUT the data in the register REG [1] as the output data OUT.

Based on the above, when one-bit cell BC fails, DATA DATA is written into and read out of one of the registers (e.g., register REG [1 ]). That is, the present disclosure utilizes registers REG [1] -REG [ N ] to change the paths of the write procedure and the read procedure (so that the DATA DATA does not pass through the memory circuit 120), thereby completing the repair procedure. The term "repair procedure" is used herein to refer to a specific mechanism for the memory device 100 to still function when a bit cell of the memory circuit 120 fails.

In some embodiments, the control circuit 140 is implemented with a processor or microcontroller, but the disclosure is not limited thereto. In some embodiments, the selection circuit 150 is implemented as a multiplexer, but the disclosure is not limited thereto.

In some related art, a column (column) spare memory circuit is additionally disposed in the memory device. When one bit cell in the memory circuit fails, the column of spare memory circuits is used to perform a repair procedure. That is, data is written into the memory space of the column or read out from the memory space of the column to complete the repair process. However, since the spare memory circuit cannot be arbitrarily disposed in other fragmentary spaces in the circuit layout, the circuit layout of the entire circuit is limited.

In contrast to the related art, the memory device 100 of the present disclosure can utilize the registers REG [1] -REG [ N ] to complete the repair procedure. Since the registers can be arranged in some fragmentary spaces on the circuit layout, the circuit layout flexibility can be improved without changing the circuit layout of other components.

In some embodiments, if the write address AD does not fail, the control circuit 140 sends an enable signal EN to enable the memory circuit 120 to write the DATA to the bit cell BC in the memory circuit 120 corresponding to the write address AD. Similarly, if the read address AD does not fail, the selection circuit 150 can directly read OUT the data from the memory circuit 120 as the output data OUT.

The capacity of each of registers REG [1] -REG [ N ] may be equal to the capacity of one row (row) of memory circuit 120. In this example, the capacity of one row of the memory circuit 120 is 64 bits, but the disclosure is not limited thereto. In practice, if a bit cell BC in the memory circuit 120 fails and the bit cell BC is located in the first row, when an external processor is going to perform a write procedure and a read procedure on each bit cell BC in the first row, the controller 140 may be utilized to control the register REG [1] to change the paths of the write procedure and the read procedure (so that the DATA does not pass through the memory circuit 120), so as to complete the repair procedure. If the failed bit cell BC is located in the second row, when the external processor is going to perform the write procedure and the read procedure on each bit cell BC in the second row, the controller 140 can be used to control the register REG [2] to change the path of the write procedure and/or the read procedure (so that the DATA DATA does not pass through the memory circuit 120) to complete the repair procedure. And so on.

In some other embodiments, the capacity of each of the registers REG [1] -REG [ N ] may be equal to the capacity of one column (column) of the memory circuit 120.

In some embodiments, the memory device 100 may perform the above analysis procedure during the test phase according to a plurality of operating voltages OV with different voltage values to store all fail addresses corresponding to these operating voltages OV in the register REG 2. Thus, when the external processor is going to perform the write procedure and the read procedure on the memory circuit 120, the memory circuit 120 can operate at the optimum operating voltage OV (least failed address), and the controller 140 can control the registers REG [1] -REG [ N ] to perform the repair procedure on all the failed addresses recorded in the register REG 2.

In some embodiments, the operating voltage OV for performing the analysis procedure includes three voltage values. For example, the memory device 100 generally operates at the optimal operating voltage, and the operating voltage OV for performing the analysis process may include the optimal operating voltage, a high voltage higher than the optimal operating voltage, and a low voltage lower than the optimal operating voltage. Thus, when the operating voltage OV of the memory device 120 slightly shifts, the memory device 120 can still function normally. However, the present disclosure is not limited to three voltage values. In some other embodiments, the operating voltage OV for performing the analysis process may include more than three voltage values.

Refer to fig. 2. Fig. 2 is a schematic diagram of a memory device 200 according to some embodiments of the present disclosure. The main difference between the memory device 200 of fig. 2 and the memory device 100 of fig. 1 is that the memory device 200 of fig. 2 can perform the above-described analysis procedure according to different transmission gear CK (also referred to as "margin gear") during a test phase. The "transmission gear" mentioned herein refers to the upper frequency limit of the writing process and the reading process. For example, the higher the transmission gear, the higher the upper limit of the frequency of the memory device 200 executing the write process and the read process, and the faster the frequency of the memory device 200. The faster the frequency of the memory device 200, the more likely the bit cell BC will fail.

After the memory device 200 performs the above analysis procedure according to different transmission ranks CK in the testing stage, all fail addresses corresponding to the transmission ranks CK can be stored in the register REG 2. Thus, when the external processor is going to perform the write procedure and the read procedure on the memory circuit 120, the memory circuit 120 can operate in the optimal transmission stage CK, and the controller 140 can control the registers REG [1] -REG [ N ] to perform the repair procedure on all the fail addresses recorded in the register REG 2.

Since a portion of the operation of the memory device 200 of fig. 2 is similar to that of the memory device 100 of fig. 1, further description is omitted here.

Refer to fig. 3. Fig. 3 is a schematic diagram of a memory device 300 according to some embodiments of the present disclosure. The main difference between the memory device 300 of FIG. 3 and the memory device 100 of FIG. 1 is that the memory device 300 of FIG. 3 includes a NON-transitory storage circuit NON.

In some embodiments, fail addresses tested under different test conditions (different operating voltages OV/different transmission ranks CK) during the test phase may be stored in the NON-transitory storage circuit NON. When the memory device 300 is powered down, the data in the NON-transitory memory circuit NON will not be lost. Accordingly, when the external processor is going to execute the write program and the read program to the memory circuit 120, the repair program can be executed to the fail address directly using the registers REG [1] -REG [ N ] based on the fail address stored in the NON-transitory memory circuit NON.

In some embodiments, the NON-transitory memory circuit NON is implemented by an electrical fuse, but the disclosure is not limited thereto. Various suitable non-transitory memory circuits are within the scope of the present disclosure.

Since a portion of the operation of the memory device 300 of fig. 3 is similar to that of the memory device 100 of fig. 1, further description is omitted here.

Refer to fig. 4. Fig. 4 is a schematic diagram of a memory device 400 according to some embodiments of the present disclosure. Taking the example of fig. 4, the memory device 400 includes a memory circuit 420, an analyzing circuit 430, a control circuit 440, and a register REG 3.

The memory circuit 420 is coupled to the analysis circuit 430. The analysis circuit 430 is coupled to a control circuit 440. The control circuit 440 is coupled to the memory circuit 420 and the register REG 3.

The analysis circuit 430 is configured to perform an analysis procedure on the bit cells BC in the memory circuit 420 to determine which of the bit cells BC is failed, so as to generate an analysis result AR. When one of the bit cells BC is failed, the control circuit 440 adjusts the operating voltage OV of the memory device 400 (e.g., generally, increasing the operating voltage OV makes the bit cells BC in the memory circuit 420 less prone to fail) until an operating voltage OV is found at which the bit cells BC of the memory circuit 420 do not fail (or at which the failure location is relatively small). In some embodiments, the memory device 400 can be configured to operate according to the raised operating voltage OV (referred to as the adjusted operating voltage). Thereby increasing the normal operation rate of the memory device 400.

In summary, the memory device of the present disclosure has a better repair mechanism, and the overall yield can be improved.

Various functional components and blocks have been disclosed herein. It will be apparent to those skilled in the art that functional blocks may be implemented by circuits (whether dedicated circuits or general purpose circuits that operate under the control of one or more processors and coded instructions), which generally comprise transistors or other circuit elements that control the operation of the electrical circuits in accordance with the functions and operations described herein. It is further understood that the specific structure and interconnections of circuit elements in general may be determined by a compiler, such as a Register Transfer Language (RTL) compiler. A register transfer language compiler operates on scripts (scripts) that are fairly similar to assembly language code (assembly language code) and compiles the scripts into a form for layout or fabrication of the final circuit.

Although the present disclosure has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present disclosure, and therefore, the scope of the present disclosure should be determined by that defined in the appended claims.

[ notation ] to show

100 memory device

120 memory circuit

130 analysis circuit

140 control circuit

150 selection circuit

200 memory device

300 memory device

400 memory device

420 memory circuit

430 analysis circuit

440: control circuit

REG [1] -REG [ N ]: register

REG2 register

REG3 register

BC bit cell

Results of AR analysis

CS control signal

AD is address

DATA DATA

EN enable signal

SEL select signal

OUT output data

OV operating voltage

CK transmission gear

NON-TRANSITORY STORAGE CIRCUIT