阅读说明：本技术 数据储存装置与数据处理方法 (Data storage device and data processing method ) 是由 邱慎廷 于 2020-06-19 设计创作，主要内容包括：本发明涉及一种存储器控制器,耦接一存储器装置,用以控制存储器装置的存取操作,包括一数据保护引擎以及一微处理器。数据保护引擎用以根据接收自一主机装置的数据产生对应的保护资讯。微处理器响应于将数据写入存储器装置之一或多个写入操作检测存储器装置的一状态,根据状态决定数据保护引擎于产生保护资讯时是否需排除数据的一部分,并产生一决定结果,以及将保护资讯与决定结果一并储存于存储器装置,其中决定结果指示出保护资讯是根据数据的哪些部分被产生。(The invention relates to a memory controller, which is coupled with a memory device and is used for controlling the access operation of the memory device. The data protection engine is used for generating corresponding protection information according to data received from a host device. The microprocessor detects a state of the memory device in response to one or more write operations to write data into the memory device, determines whether the data protection engine is to exclude a portion of the data when generating the protection information based on the state, and generates a determination result indicating which portions of the data the protection information is generated based on, and stores the protection information and the determination result in the memory device.)

1. A memory controller coupled to a memory device for controlling access operations of the memory device, comprising:

a data protection engine for generating corresponding protection information according to data received from a host device; and

a microprocessor, detecting a state of the memory device in response to one or more write operations to write the data to the memory device, determining whether the data protection engine is to exclude a portion of the data when generating the protection information based on the state, and generating a determination result, and storing the protection information and the determination result in the memory device, wherein the determination result indicates which portions of the data the protection information is generated based on.

2. The memory controller of claim 1, wherein the microprocessor further directs the data protection engine to exclude a first portion of the data when generating the protection information when the microprocessor determines that the data protection engine needs to exclude the first portion of the data when generating the protection information based on the status.

3. The memory controller of claim 1, wherein the protection information is stored in a data area of a memory space, and the determination result is stored in a spare area of the memory space as metadata (meta data) of the memory space.

4. The memory controller of claim 1, wherein the determination result is expressed in bits, a bit indicates whether the data of a predetermined storage unit is excluded, and the predetermined storage unit is identical to a basic protection unit of the protection information.

5. The memory controller of claim 1, wherein the determination result is expressed in bits, a bit indicates whether the data of a predetermined storage unit needs to be excluded, and the predetermined storage unit is larger than a basic protection unit of the protection information.

6. The memory controller of claim 2, wherein the microprocessor instructs the data protection engine to exclude the first portion of the data when the status indicates that the write operation corresponding to the first portion of the data failed.

7. The memory controller of claim 2, wherein the microprocessor instructs the data protection engine to exclude the first portion of the data when the status indicates a power supply voltage change to the memory device during the write operation corresponding to the first portion of the data.

8. The memory controller as recited in claim 2, wherein the microprocessor instructs the data protection engine to exclude the first portion of the data when the status indicates an abrupt power down of the memory device during the write operation corresponding to the first portion of the data.

9. The memory controller of claim 1, wherein the data protection engine is further configured to recover damaged or missing data, and when the microprocessor determines that a second portion of the data is damaged or missing, the microprocessor accesses the memory device to obtain the protection information and the determination result corresponding to the data, and instructs the data protection engine to recover the damaged or missing second portion using which portion of the data according to the determination result.

10. A data processing method performed by a memory controller coupled to a memory device, comprising:

detecting a state of the memory device in response to one or more write operations to write data received from a host device to the memory device;

determining whether a portion of the data is to be excluded when generating protection information corresponding to the data according to the status, and generating a determination result;

Generating the protection information corresponding to the data according to the determination result and the data; and

storing the protection information in the memory device along with the determination result, wherein the determination result indicates which portions of the data the protection information is generated based on.

11. The data processing method of claim 10, further comprising:

when a first portion of the data is to be excluded when generating the protection information corresponding to the data based on the status, instructing a data protection engine to exclude the first portion of the data when generating the protection information.

12. The data processing method as claimed in claim 10, wherein the protection information is stored in a data area of a memory space, and the determination result is stored in a spare area of the memory space as metadata (meta data) of the memory space.

13. The data processing method of claim 10, wherein the determination result is expressed by a plurality of bits, a bit indicates whether the data of a predetermined storage unit is excluded, and the predetermined storage unit is identical to a basic protection unit of the protection information.

14. The data processing method of claim 10, wherein the determination result is expressed by a plurality of bits, a bit indicating whether the data of a predetermined storage unit needs to be excluded is provided, and the predetermined storage unit is larger than a basic protection unit of the protection information.

15. The data processing method of claim 11, wherein when the status indicates that the write operation corresponding to the first portion of the data failed, determining to exclude the first portion of the data when generating the protection information corresponding to the data.

16. The data processing method as claimed in claim 11, wherein when the status indicates a power voltage change of the memory device during the write operation corresponding to the first portion of the data, the first portion of the data is excluded when generating the protection information corresponding to the data.

17. The data processing method as claimed in claim 11, wherein when the status indicates an abrupt power down of the memory device during the write operation corresponding to the first portion of the data, it is determined that the first portion of the data is to be excluded when generating the protection information corresponding to the data.

18. The data processing method of claim 10, further comprising:

accessing the memory device to obtain the protection information and the determination result corresponding to the data when determining that a second part of the data is damaged or lost; and

instructing a data protection engine to use which portions of the data to recover the second portion that is damaged or missing based on the determination.

Technical Field

The present invention relates to a data processing method, and more particularly, to a data processing method capable of effectively protecting data stored in a memory device.

Background

As the technology of data Storage devices has rapidly grown in recent years, many data Storage devices, such as Memory cards conforming to the Secure Digital (SD) format, the multimedia Card (MMC) format, the Compact Flash (CF) format, the Memory Stick (MS) format and the Extreme Digital (XD) format, solid state Memory (ssd), embedded multimedia Memory (eMMC) Card, and Universal Flash Storage (UFS) have been widely used for various purposes. Therefore, efficient access control also becomes an important issue in these data storage devices.

In order to improve the access performance of the data storage device and protect the data stored in the memory device, the invention provides a novel data processing method, which can effectively protect the data stored in the memory device and avoid reducing the access performance of the data storage device due to the implementation of an error protection mechanism.

Disclosure of Invention

An objective of the present invention is to effectively protect data stored in a memory device and to prevent the access performance of the data storage device from being degraded due to the implementation of an error protection mechanism.

According to an embodiment of the present invention, a memory controller, coupled to a memory device, for controlling access operations of the memory device includes a data protection engine and a microprocessor. The data protection engine is used for generating corresponding protection information according to data received from a host device. The microprocessor detects a state of the memory device in response to one or more write operations to write data into the memory device, determines whether the data protection engine is to exclude a portion of the data when generating the protection information based on the state, and generates a determination result indicating which portions of the data the protection information is generated based on, and stores the protection information and the determination result in the memory device.

According to another embodiment of the present invention, a data processing method performed by a memory controller coupled to a memory device comprises: detecting a state of the memory device in response to one or more write operations that write data received from a host device to the memory device; determining whether a part of the data needs to be excluded when generating protection information corresponding to the data according to the state, and generating a determination result; generating protection information corresponding to the data according to the determination result and the data; and storing the protection information in the memory device together with a determination result indicating which portions of the data the protection information is generated based on.

Drawings

Fig. 1 is a schematic diagram illustrating a data storage device 100 according to an embodiment of the invention.

Fig. 2 is a flowchart illustrating a data processing method according to an embodiment of the invention.

FIG. 3 is a diagram illustrating protection information corresponding to a plurality of multi-plane data pages according to a first embodiment of the invention.

FIG. 4 is a diagram illustrating an example of a bit table established according to the protection information shown in FIG. 3.

FIG. 5 is a diagram illustrating protection information corresponding to a plurality of multi-plane data pages according to a second embodiment of the invention.

FIG. 6 is a diagram illustrating an example of a bit table established according to the protection information shown in FIG. 5.

Description of the symbols

100 data storage device

110 memory controller

112 microprocessor

112C program code

112M read-only memory

114 memory interface

116 buffer memory

115 data protection engine

118 host interface

120 memory device

130 host device

132 encoder

134 decoder

136 voltage detection circuit

310,510,520,530,540,550, LP _ Party, MP _ Party, P _ S0-P _ S383, Pj _ S0-Pj _ S7, S0_ L, S0_ M, S0_ U, UP _ Pairty, protection information

410,610 bit table

710 spare area

720 data area

Die 0, Die 1, Die 2, Die n-1 memory Die

Lower _ Page, Middle _ Page, Page [0], Page [1], Page [2], Upper _ Page

META metadata

Plane [0], Plane [1] Plane

WL _0 to WL _95 word lines

Detailed Description

In the following description, numerous specific details are described to provide a thorough understanding of embodiments of the invention. However, those skilled in the art will understand how to implement the invention without one or more of the specific details or depending on other methods, components or materials. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

Reference throughout this specification to "one embodiment," "an example" or "an example" means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment," "in an example" or "in an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples.

In order to make the objects, features and advantages of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below. For the purpose of illustrating the spirit of the present invention and not for the purpose of limiting the scope of the present invention, it is to be understood that the following embodiments may be implemented via software, hardware, firmware, or any combination thereof.

Fig. 1 is a schematic diagram illustrating a data storage device 100 according to an embodiment of the invention. The data storage device 100 includes a Memory device 120, such as a Flash Memory (Flash Memory) module, and a Memory controller 110. The memory controller 110 is used to Access (Access) the memory device 120. According to an embodiment of the present invention, the Memory controller 110 includes a microprocessor 112, a Read Only Memory (ROM) 112M, a Memory interface 114, a data protection engine 115, a buffer Memory 116, and a host interface 118. The rom 112M is used to store a program code 112C, and the program code 112C may include one or more program modules, such as boot loader (boot loader) code, and the microprocessor 112C executes the program code 112C to perform initialization operations to load an In-System Programming (ISP) code (not shown) from the memory device 120 when the host device 130 supplies power to the data storage device 100. The microprocessor 112 can execute the ISP code to provide the data storage device 100 with various functions. According to the present embodiment, the ISP group code may include, but is not limited to, a plurality of program modules related to access (e.g., read, write and erase), such as a read operation module, a lookup table module, a wear leveling (wear leveling) module, a read refresh (read refresh) module, a read recovery (read recover) module, a garbage collection (garbage collection) module, a sudden power recovery (SPOR) module, and an Uncorrectable Error Correction Code (UECC) module, for performing read, lookup table, wear leveling, read refresh, read recovery, garbage collection, sudden power recovery and error handling for UECC errors, respectively. The memory interface 114 includes an encoder 132, a decoder 134, and a voltage detection circuit 136. The encoder 132 is used for encoding data written into the memory device 120 to generate a corresponding check Code (or Error Correction Code (ECC)). The decoder 134 is used to decode data read out of the memory device 120. The voltage detection circuit 136 is used for detecting a voltage level of the memory device 120, such as a level of the power voltage, and generating a corresponding detection result. The microprocessor 112 can determine whether a power supply voltage variation (e.g., unstable power supply voltage) occurs in the memory device 120, or an unexpected or Sudden Power Off (SPO) occurs, etc. according to the detection result. The data protection engine 115 is configured to generate corresponding protection information based on data received from a host device, and to recover damaged or missing data based on the protection information, wherein the protection information may be encoded information generated based on the data to be protected, such as parity information. When a portion of data protected by a given protection information is damaged or lost, the data protection engine 115 may perform a corresponding decoding operation according to the given protection information and the remaining portion of data protected thereby to derive the damaged or lost portion.

Typically, the memory device 120 comprises a plurality of flash memory chips or dies, each of which comprises a plurality of memory blocks (blocks), and the erase data operation of the memory device 120 by the memory controller 110 is performed in units of blocks. In addition, a memory block can record (include) a specific number of pages (pages), i.e. physical pages, wherein the operation of writing data to the memory device 120 by the memory controller 110 is performed in units of pages.

In practice, the memory controller 110 may utilize its internal components to perform various control operations, such as: the memory interface 114 is used to control the access operations of the memory Device 120 (especially, the access operations of at least one block or at least one data page), the buffer memory 116 is used to perform the required buffering, and the Host interface 118 is used to communicate with a Host Device (Host Device) 130. The host interface 118 may also be regarded as a front-end controller engine for transmitting communication signals, write/read data, and control task scheduling between the memory controller 110 and the host device 130.

In one embodiment, the memory controller 110 communicates with the host device 130 via the host interface 118 using a standard communication protocol. For example, the standard communication protocols include (but are not limited to): universal Serial Bus (abbreviated USB) standard, Secure Digital (SD) interface standard, Ultra High Speed-I (abbreviated UHS-I) interface standard, Ultra High Speed-II (abbreviated UHS-II) interface standard, Compact Flash (abbreviated CF) interface standard, Multimedia Card (abbreviated MMC) interface standard, Embedded Multimedia Card (abbreviated eMMC) interface standard, Universal Flash Storage (abbreviated ufms) interface standard, Advanced Technology Attachment (abbreviated ATA) standard, Serial ATA (abbreviated Serial ATA), Peripheral Express Peripheral equipment (PCI Express) standard, and Peripheral Component Interconnect (Peripheral Component Interconnect) standard, Parallel Advanced Technology Attachment (abbreviated as PATA) standard.

In one embodiment, the buffer Memory 116 is implemented by a Random Access Memory (RAM). For example, the buffer memory 116 may be a Static random access memory (Static RAM, abbreviated as SRAM), but the invention is not limited thereto. In other embodiments, the buffer memory 116 may be a Dynamic Random Access Memory (DRAM).

In one embodiment, the data storage device 100 may be a portable memory device (e.g., a memory card conforming to SD/MMC, CF, MS, XD, UFS standards), and the host device 130 is an electronic device connectable to the data storage device, such as a mobile phone, a notebook computer, a desktop computer …, or the like. In another embodiment, the data storage device 100 may be a solid state hard disk or an embedded storage device conforming to the UFS or eMMC specification, and is installed in an electronic device, such as a mobile phone, a notebook computer, or a desktop computer, and the host device 130 may be a processor of the electronic device.

The host device 130 can issue commands, such as read commands or write commands, to the data storage device 100 to access data stored in the memory device 120, or further control and manage the data storage device 100.

According to an embodiment of the present invention, the plurality of memory blocks included in the memory device 120 may include Single-Level Cell (SLC) memory blocks, multi-Level Cell (MLC) memory blocks, and/or Triple-Level Cell (TLC) memory blocks. One bit of data is stored in each memory cell of the SLC memory block, two bit of data is stored in each memory cell of the MLC memory block, and three bit of data is stored in each memory cell of the TLC memory block. According to an embodiment of the present invention, the memory device 120 is a stereo NAND type flash memory (3D NAND-type flash).

Generally, to protect a memory device from valid data loss due to the damage of a memory unit, the memory device may use an error protection mechanism adopted in a Redundant Array of Independent Disks (RAID) technology for data protection. In the error protection scheme employed by RAID, the memory controller may calculate protection information based on data written to the memory devices. When the loss of the valid data is found, the protection information can be used to reversely derive the content of the lost valid data.

However, in some cases, damage has occurred as data is written to the memory device. If the memory controller knows that the written data is damaged, it usually needs to trigger a data moving procedure to re-form the remaining undamaged data (i.e. correct data) into a predetermined memory area, and then calculate protection information for the data in the predetermined memory area to protect the remaining undamaged data. However, since the protection information must be calculated to generate the protection effect for the data, if a data error occurs during the data moving process, the data cannot be recovered because the data is not protected during the moving process. Therefore, there is a risk that data errors occur during the data transfer process. In addition, data migration and re-organization are also time consuming operations.

To solve the above problems, the present invention provides a novel data processing method, which can effectively protect the data stored in the memory device and effectively avoid the reduction of the access performance of the data storage device due to the implementation of the error protection mechanism.

According to an embodiment of the present invention, in addition to storing the protection information, the memory controller 110 also stores related information indicating which portions of the data the protection information is generated according to in the memory space storing the protection information, so that when the memory controller 110 finds that a portion of the data is not needed or can not be encrypted or protected, the portion of the data can be skipped directly, and only the encryption or protection operation is performed on the rest of the data, without performing a data moving operation for collecting a predetermined amount of correct data. The protection information stored by the memory controller 110 is used when decoding the data is required based on the related information generated from which portions of the data. For example, when the memory controller 110 finds that another part of the protected data is lost or damaged, it can know from the stored information which part of the data the protection information is generated according to, and correctly access the required data to perform the data repair operation.

Fig. 2 is a flowchart illustrating a data processing method according to an embodiment of the invention. The data processing method of the present invention may be executed by the memory controller 110 or one or more components included in the memory controller, and includes the following steps:

a state of the memory device 120 is detected in response to one or more write operations to write data received from the host device 130 to the memory device 120 or a state of data written to the memory device 120 in accordance with the one or more write operations, step S202.

Step S204, determining whether to exclude a part of the data when generating the protection information corresponding to the data according to the state, and correspondingly generating a determination result.

Step S206, generating the protection information corresponding to the data according to the determined result and the data. For example, the memory controller 110 (or the microprocessor 112) may instruct the data protection engine 115 which portions of the data should be used or which portions of the data should be excluded in generating the protection information corresponding to the data according to the determination result. The data protection engine 115 generates corresponding protection information according to the non-excluded data according to the contents instructed by the memory controller 110.

Step S208, the protection information and the decision result are stored in the memory device together.

Please note that, if substantially the same result is obtained, the steps are not necessarily performed according to the order shown in FIG. 2, and other steps may be inserted therein. For example, steps S204 and S206 may be executed simultaneously, or the execution order may be interchanged. More specifically, data from the host device 130 may be buffered in the buffer memory 116. Assuming that the data protection engine 115 is configured to generate protection information corresponding to a Super page (Super page) according to the content of the Super page, wherein the basic protection unit of the data protection engine 115 is a data page, and a Super page includes a first number of data pages, the data protection engine 115 may generate protection information according to all data pages of the Super page stored in the buffer memory 116 while a Super page temporarily stored in the buffer memory 116 is written into the memory device 120. That is, the data protection engine 115 may first generate protection information according to the data stored in the buffer memory 116. If the microprocessor 112 determines in step S204 that one or more data pages in the super data page need to be excluded, the data protection engine 115 may be further instructed to perform a corresponding data exclusion operation for removing the related content of the one or more data pages from the protection information, which is equivalent to the data protection engine 115 generating corresponding protection information according to other data pages in the super data page that do not include the one or more data pages. Alternatively, the microprocessor 112 instructs the data protection engine 115 to regenerate the corresponding protection information after excluding the one or more data pages of the super data page, i.e., the data protection engine 115 finally regenerates the corresponding protection information according to other data pages of the super data page that do not include the one or more data pages. Thus, where one or more data pages are to be excluded, the protection information for the superpage is actually generated based on less than the first number of data pages.

In embodiments of the present invention, the determination result may be used to indicate which portions of data (e.g., which data pages of a superpage) the protection information is generated based on. In addition, according to an embodiment of the present invention, in step S208, the memory controller 110 may represent the determination result by a plurality of bits. For example, the memory controller 110 may establish a bit map for the protection information according to the determination result to record that the protection information is generated according to the corresponding data portion, and store the protection information and the bit map in the same memory space, such as a data page (e.g., a physical data page), wherein a size of the physical data page may be, for example, but not limited to, 16K bytes, and a physical data page may include a data area and a spare area, and the memory controller 110 may store the protection information in the data area and store the determination result or the bit map in the spare area as a portion of the metadata (meta data) of the memory space.

When the memory controller 110 (or the microprocessor 112) determines that a portion of the data stored in the memory device 120 is damaged or lost, the memory device 120 may be accessed to obtain protection information and a determination result (or a bit table) corresponding to the damaged or lost portion, and instruct the data protection engine 115 to use which portions of the data to decode the corresponding protection information to derive the damaged or lost portion according to the determination result (or the bit table).

As described above, in an embodiment of the present invention, the determination result may be represented by a plurality of bits, and one bit is used to indicate whether data of a predetermined storage unit is excluded, wherein the predetermined storage unit may be set to be the same as the basic protection unit of the data protection engine 115, or the size of the predetermined storage unit may be larger than the basic protection unit of the data protection engine 115.

For example, assuming that the basic protection unit set currently is one data page, the size of the protection information generated by the data protection engine 115 may be one data page, for example, the protection information may be a parity of one data page.

In one embodiment of the present invention, the size of the predetermined storage unit may also be set to the size of one data page, and thus, one bit is used to indicate whether the data of the corresponding one data page is excluded when generating the corresponding protection information. In this embodiment, when the data protection engine 115 generates protection information according to all data pages of a single-plane superpage, the determination result corresponding to the single-plane superpage may include the first number of bits.

Alternatively, in another embodiment of the present invention, the size of the predetermined storage unit may be set to the size of a multi-plane page (multi-plane page), wherein a multi-plane page may include, for example, but not limited to, two pages located on different planes, and therefore, in this embodiment, a bit is used to indicate whether the data of the corresponding multi-plane page (e.g., two pages) is excluded when generating the corresponding protection information. In this embodiment, when the data protection engine 115 generates protection information according to all data pages of a multi-plane superpage, the corresponding determination result of the multi-plane superpage may include the first number of bits, and each bit may be compressed information indicating whether data of the plurality of data pages is excluded from generating the corresponding protection information.

It is noted that, in the embodiment of the present invention, the data protection engine 115 can flexibly generate corresponding protection information for data of different sizes, and the basic protection unit of the data protection engine 115 is not limited to one data page. For example, the data protection engine 115 may generate protection information corresponding to a single-plane or multi-plane superpage based on the contents of the superpage, generate protection information corresponding to a memory block based on the contents of a memory block, generate protection information corresponding to a superpage block based on the contents of a superpage block (where a superpage block may include multiple memory blocks), or the like. The basic unit of protection for the data protection engine 115 may be a page of data, a multi-plane page of data, a page of superpage, a block of memory, etc.

FIG. 3 is a diagram illustrating protection information corresponding to a plurality of multi-plane data pages according to a first embodiment of the invention. In this embodiment, the memory device 120 may comprise a plurality of flash memory dies (or memory dies), and the data protection engine 115 may encode n of the memory dies bound together to generate corresponding protection information, such as the memory dies Die [0] Die [ n-1] shown in the figure, where n is a positive integer. Each memory die may include one or more planes, such as the planes Plane [0] and Plane [1] shown in the figures. Each plane may contain multiple pages of data, e.g., pages [0], pages [1], pages [2], etc. In this embodiment, assuming that the memory device 120 is written by Triple-Level Cell (TLC), one physical data Page may correspond to three logical data pages, such as the low, Middle, and high data pages (logical data pages) shown in the figure, Lower _ Page, Middle _ Page, and Upper _ Page. The pages of each plane may be low pages, pages of pages [0], [3], [6], [9], etc., medium pages, pages of pages [1], [4], [7], [10], etc., high pages, and so on.

In the embodiment shown in FIG. 3, the data protection engine 115 classifies n memory dies into a protection group and generates corresponding protection information according to data corresponding to each data page of each plane of the n memory dies. For example, assuming that n is 8, the data protection engine 115 may classify each 8 memory dies into a protection group, where a protection group includes the memory dies Die [0] Die [7] shown in fig. 3. The data pages of the memory dies Die [0] through Die [7] may form a plurality of superpage data pages, where a superpage data page contains a first number of data pages, e.g., 8 data pages. It is noted that the superpage may be a single plane superpage, or a multi-plane superpage. For example, the first Page [0] of the first Plane [0] of the memory dies Die [0] to Die [7] may constitute a single-Plane superpage, the first Page [0] of the second Plane [1] of the memory dies Die [0] to Die [7] may constitute another single-Plane superpage, or the first Page [0] of the two planes of the memory dies Die [0] to Die [7] may constitute a multi-Plane superpage.

In an embodiment of the present invention, a set of low, medium, and high data pages may form a string. The data protection engine 115 may perform exclusive OR (XOR) operation on the data corresponding to the low, middle and high data pages of the memory dies Die [0] Die [7] to obtain a string of corresponding protection information, for example, the protection information 310 corresponding to the first string shown in FIG. 3, wherein the protection information 310 may include protection information S0_ L obtained by the data protection engine 115 performing XOR operation on the data corresponding to the first data Page Page [0] (low data Page) of the memory dies Die [0] Die [7], protection information S0_ M obtained by performing XOR operation on the data corresponding to the second data Page Page [1] (middle data Page) of the memory dies [0] Die [7], and protection information S0_ U obtained by performing XOR operation on the data corresponding to the third data Page [2] (high data Page) of the memory dies Die [0] Die [7] (high data Page), the protection information S0-L, S0-M, S0_ U of the first Plane [0] and the second Plane [1] is used to protect the data corresponding to the low, middle and high data pages contained in the first string of the Plane for the memory dies Die [0] -Die [7], respectively.

Fig. 4 shows an example of a bit table established according to the protection information 310 shown in fig. 3. In this embodiment, assuming that the memory controller 110 determines that all data can be used to generate the protection information corresponding to the first string according to the state of the memory device 120 when performing the write operation corresponding to the first string or the state of the first string of data written into the memory device 120 (i.e., the data protection engine 115 does not need to exclude any data page shown in fig. 3 when generating the protection information corresponding to the first string), the memory controller 110 may set each bit included in the bit table 410 to a corresponding value (e.g., 1) to indicate that all data pages are protected by the protection information 310. Wherein a Byte (Byte) of the bit table 410 corresponds to a super page of a plane, and a bit of a Byte can be used to indicate whether a page of data included in the corresponding super page is excluded. On the other hand, if the memory controller 110 determines that a data page needs to be excluded, the memory controller 110 may set the corresponding bit in the bit table 410 to another corresponding value (e.g., 0) to indicate that the data page is not protected by the protection information 310, and may further instruct the data protection engine 115 to exclude the data page when generating protection information corresponding to a super data page including the data page.

It is noted that, as described above, the protection information may also be compressed information. For example, in another embodiment of the present invention, the content recorded by each bit in a bit set corresponding to the first Plane [0] and the second Plane [1] in the bit table 410 can be compressed and represented by a bit to indicate whether the multi-Plane superpage corresponding to the bit is protected by the protection information 310. That is, the bit table 410 can be compressed into a bit set.

In addition, the data processing method and the error protection mechanism of the present invention can be applied to a single-plane architecture as well as a multi-plane architecture. For example, in yet another embodiment of the present invention, each memory die may include a single plane, e.g., the contents of FIGS. 3 and 4 may be reduced to include only one plane of data pages. The data protection engine 115 classifies the n memory dies into a protection group and generates protection information corresponding to each data page of the n memory dies based on data corresponding to each data page.

FIG. 5 is a diagram illustrating protection information corresponding to a plurality of multi-plane data pages according to a second embodiment of the invention. The second embodiment of the present invention may be an extension of the first embodiment. As described above, a set of low, medium, and high data pages may form a string (string). Pages [0], [1] and [2] may form a first string S0, pages [3], [4] and [5] may form a second string S1, pages [6], [7] and [8] may form a third string S2, and so on.

In a second embodiment of the present invention, the data protection engine 115 can repeatedly perform the operations described in the first embodiment to obtain protection information corresponding to different strings.

As shown in FIG. 5, the protection information P _ S0 is protection information corresponding to the first string S0, which may further include protection information S0_ L, S0_ M and S0_ U as shown in FIG. 3, and the protection information P _ S1 is protection information corresponding to the second string S1, which may further include protection information corresponding to the low, middle and high data pages of the second string, and so on. In addition, in the second embodiment of the present invention, a set of four strings may form a Word Line (abbreviated WL), and thus, the protection information 510 may include protection information corresponding to the Word lines WL _0 and WL _1, the protection information 520 may include protection information corresponding to the Word lines WL _2 and WL _3, the protection information 530 may include protection information corresponding to the Word lines WL _4 and WL _5, the protection information 540 may include protection information corresponding to the Word lines WL _94 and WL _95, and so on. In this embodiment, each memory die may contain 1152 pages of data, corresponding to 384 strings, and also corresponding to 96 word lines.

In the second embodiment of the present invention, after obtaining 384 strings of corresponding protection information P _ S0-P _ S383, the data protection engine 115 may further form a set of protection information corresponding to two word lines, such as protection information 510-540 shown in the figure, and perform exclusive OR (XOR) operation on each set to obtain protection information 550 corresponding to a super memory block, where the protection information 550 may include two planes of protection information Pj _ S0-Pj _ S7, the first Plane [0 ]/the second Plane [1] of protection information Pj _ S0 is the protection information obtained by the data protection engine 115 performing XOR operation according to the protection information P _ S0, P _ S8, P _ S16 … P _ S376 of the first Plane [0 ]/the second Plane [1], and the first Plane [0 ]/the second Plane [1] of protection information Pj _ S1 is the first Plane [0 ]/the first Plane [ 84/P _ S350 ] of protection information P _ S35115 The protection information P _ S1, P _ S9, P _ S17 … P _ S377 of the Plane [1] is XOR-operated to obtain protection information, and so on.

FIG. 6 is a diagram illustrating an example of a bit table established according to the protection information shown in FIG. 5. A Byte (Byte) of the Byte table 610 corresponds to a super page of a plane, and a bit of a Byte can be used to indicate whether a page of data included in the corresponding super page is to be excluded. Similarly, if the memory controller 110 determines that a data page needs to be excluded, the memory controller 110 may set the corresponding bit in the bit table 610 to a corresponding value (e.g., 0) to indicate that the data page is not protected by the protection information 550.

According to an embodiment of the present invention, the memory controller 110 may store protection information in a physical data page together with its corresponding bit table (determination result), wherein the protection information is stored in the data area, and the bit table is stored in the spare area as part of the metadata (e.g., META in the figure) of the physical data page. As shown in FIG. 6, the data area 720 stores protection information Pj _ S2 in the first Plane [0], which is protection information obtained by the data protection engine 115 performing XOR operation according to the protection information P _ S2, P _ S10 and P _ S18 … P _ S378 of the first Plane [0], and may further include protection information LP _ Party, MP _ Party and UP _ Pairty corresponding to the low, medium and high data pages. A bit table associated with each protection information is stored in the corresponding spare area. As shown, the spare area 710 is used for storing a bit table corresponding to protection information LP _ Party of protection information Pj _ S2 on the lower page of the first Plane [0], wherein bits corresponding to protection information LP _ Party of protection information Pj _ S2 on the lower page of the first Plane [0] are highlighted in boxes in FIG. 6 and indicate that its content is stored in the spare area 710 by pointing to the spare area 710.

According to an embodiment of the present invention, the determination result or bit table may be temporarily stored in the buffer memory 116 during the encoding process of the data protection engine 115 and written into the memory device 120 after the protection information is generated. In addition, in the embodiment of the present invention, the data protection engine 115 may generate the final protection information according to a predetermined number of data pages and/or protection information, for example, in the first embodiment, the data protection engine 115 may generate the protection information according to a first number of data pages, for example, the protection information of the super data page shown in fig. 3, and in the second embodiment, the data protection engine 115 may further generate the protection information of the super memory block shown in fig. 5 according to a set of a second number of protection information. Since the predetermined number is known, when a part of the data is damaged or lost, the data protection engine 115 can calculate the storage location of the protection information corresponding to the data according to the information of the predetermined number (e.g., the first number, the second number, etc.), and access the metadata according to the location to obtain the bit table corresponding to the protection information. Then, the data protection engine 115 can perform a corresponding decoding operation according to the obtained protection information and the content indicated by the bit table, thereby deriving the damaged or lost data.

In addition, in the embodiment of the present invention, the data exclusion operation may be a reverse operation of generating the protection information. For example, when the data protection engine 115 generates protection information by performing an exclusive-or (XOR) operation, the data exclusion operation may be a reverse XOR operation. It should be noted that the data protection engine 115 may also generate the protection information by performing other operations, and thus, the present invention is not limited to generating the protection information using exclusive-or (XOR) operations.

In addition, in the embodiment of the present invention, the memory controller 110 can determine whether to exclude one or more data pages according to a state of the memory device 120 or according to a state of data written into the memory device 120. Thus, in the case where the data protection engine 115 predefines protection information for a superpage based on the first number of data pages, one or more of which need to be excluded, the protection information for the superpage is actually generated based on less than the first number of data pages.

Referring back to FIG. 2, in step S202, the microprocessor 112 may detect the status of the memory device 120 in response to one or more write operations to write data received from the host device 130 to the memory device 120.

For example, the microprocessor 112 may detect a status message returned by the memory device 120 after the write operation is performed, so as to know whether the write operation is successful or failed. When the status message indicates that the write operation of the first portion of the data failed, the microprocessor 112 may determine to instruct the data protection engine 115 to exclude the first portion when generating the protection information, and set the corresponding information of the determination result or the corresponding bits in the bit table to the corresponding value (e.g., 0).

For another example, the voltage detection circuit 136 may send a message to notify the microprocessor 112 when a power supply voltage change (e.g., a voltage drop, a voltage instability, or a power off of the memory device) of the memory device is detected, so that the microprocessor 112 can know the status of the memory device 120 in performing the write operation. When the status indicates that the power voltage of the memory device 120 is changed during the write operation corresponding to the first portion of the data, the microprocessor 120 may determine to instruct the data protection engine 115 to exclude the first portion when generating the protection information, and set the corresponding information of the determination result or the corresponding bits in the bit table to the corresponding value (e.g., 0), because the unstable voltage may cause the write data to be erroneous or the data cannot be written.

For example, the microprocessor 120 may also determine the status of the memory device 120 performing the write operation according to the status of the data storage device 100. If the data storage device 100 is suddenly powered down during the write operation of the memory device 120, it is also the case that the memory device 120 is suddenly powered down. Since a sudden power failure may damage the data being written, when the status indicates that a sudden power failure occurs in the memory device 120 during the write operation corresponding to the first portion of the data being executed, the microprocessor 120 may determine to instruct the data protection engine 115 to exclude the first portion when generating the protection information, and set the corresponding information of the determination result or the corresponding bits in the bit table to the corresponding value (e.g., 0).

According to another embodiment of the present invention, in step S202, in response to one or more write operations for writing data received from the host device 130 into the memory device 120, the microprocessor 112 may also detect a status of the data written into the memory device 120 according to the one or more write operations. For example, the microprocessor 112 can read the data written into the memory device 120 and attempt to decode the contents thereof through the decoder 134 to know whether a data error occurs (e.g., the error bits are too many to correct the error contents of the decoder 134). When the status of the data written into the memory device 120 indicates that the first portion of the data has been corrupted or contains an uncorrectable error, the microprocessor 120 may determine to instruct the data protection engine 115 to exclude the first portion when generating the protection information and set the corresponding information of the determination result or the corresponding bits in the bit table to a corresponding value (e.g., 0).

In summary, the data processing method of the present invention can effectively protect the data stored in the memory device and can effectively prevent the access performance of the data storage device from being reduced due to the implementation of the error protection mechanism. In the embodiment of the present invention, in addition to storing the protection information, the memory controller 110 also stores the related information indicating which portions of the data the protection information is generated according to in the memory space storing the protection information, so that when the memory controller 110 finds that a portion of the data is not needed or can not be encrypted or protected, the memory controller can directly skip the portion of the data and only perform the encryption or protection operation on the rest of the data without performing the data moving operation for collecting a predetermined amount of correct data. When the memory controller 110 finds that another part of the protected data is lost or damaged, it can know from the stored information which part of the data the protection information is generated according to, and correctly access the required data to perform the data repair operation.

The above-mentioned embodiments are only preferred embodiments of the present invention, and all equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the present invention.