阅读说明：本技术 用于存储设备的写、读数据方法、存储控制器以及dma引擎 (Writing and reading data method for storage device, storage controller and DMA engine ) 是由 涂友钢 黄好城 刘传杰 张泽 于 2021-07-22 设计创作，主要内容包括：本发明涉及一种用于存储设备的写、读数据方法、存储控制器及DMA引擎,用于存储设备的写数据方法包括响应于接收到与写命令对应的一个或多个DMA命令,根据所述DMA命令从主机获取所述DMA命令指示的数据；检测所述数据是否为特定数据；将非特定数据写入NVM。本申请的技术方案提升了数据读写的效率。(The invention relates to a write-read data method, a memory controller and a DMA engine for a memory device, wherein the write-data method for the memory device comprises the steps of responding to one or more received DMA commands corresponding to a write command, and acquiring data indicated by the DMA commands from a host according to the DMA commands; detecting whether the data is specific data; non-specific data is written to NVM. The technical scheme of the application improves the efficiency of data reading and writing.)

1. A method of writing data for a memory device, comprising:

in response to receiving one or more DMA commands corresponding to a write command, acquiring data indicated by the DMA commands from a host according to the DMA commands;

detecting whether the data is specific data;

non-specific data is written to NVM.

2. The method of claim 1, wherein writing non-specific data to NVM comprises:

responding to the data is nonspecific data, allocating corresponding physical addresses for the nonspecific data, and recording the relation between the logical addresses and the physical addresses corresponding to the nonspecific data in an FTL table; and

and writing the non-specific data into the NVM according to the physical address.

3. The method of claim 1 or 2, further comprising:

and responding to the data as the specific data, identifying the DMA command corresponding to the specific data, and storing the identification in the shared memory, so that the storage command processor controls the storage medium management unit to record the relation between the logical address and the identification corresponding to the specific data in the FTL table.

4. The method of any of claims 1-3, wherein writing non-specific data to the NVM comprises:

and writing the non-specific data from the memory of the storage device to the NVM through the back-end module without writing the specific data from the memory of the storage device to the NVM.

5. A storage controller, comprising:

the device comprises a host command processing unit, a storage medium management unit and a storage command processing unit;

the host command processing unit comprises a DMA engine and a shared memory, and is used for responding to the received write command, generating one or more storage commands and one or more DMA commands corresponding to the storage commands, providing the one or more DMA commands to the DMA engine, and providing the one or more storage commands to the storage command processing unit;

the DMA engine comprises a first data moving circuit, a second data moving circuit and a data protection and monitoring circuit;

the first data moving circuit is used for responding to a received DMA command, acquiring data indicated by the DMA command according to the DMA command and providing the acquired data to the data monitoring circuit;

the data protection and monitoring circuit is used for encrypting and/or carrying out integrity check on the data, detecting whether the data is specific data or not, and recording a detection result in the shared memory;

the data protection and monitoring circuit provides the result data of the data encryption and/or integrity check to the second data moving circuit;

the second data moving circuit moves the result data acquired from the data protection and monitoring circuit to a memory;

and the storage command processing unit is used for responding to the received storage command and determining whether to write the result data in the storage into the NVM controlled by the storage controller according to the detection result of the data corresponding to the storage command.

6. A method for reading data for a memory device, comprising:

acquiring a read command, generating one or more storage commands according to the read command, and acquiring a physical address or a first specific identifier corresponding to a logical address carried by the storage command through an FTL (flash translation layer) table;

generating a DMA command corresponding to each storage command according to the storage command, wherein the DMA command carries second information, and the second information comprises a memory address of the storage device and/or a second specific identifier;

and if the second information of the DMA command is the second specific identifier, generating the specific data according to the second specific identifier, and sending the specific data to the host according to the DMA command.

7. The method of claim 6, further comprising:

and if the second information of the DMA command is the memory address of the storage device, reading data from the NVM to the memory of the storage device according to the physical address corresponding to the logical address carried by the storage command corresponding to the DMA command and acquired through the FTL table and the memory address of the storage device.

8. The method of claim 7, further comprising:

and if the physical address corresponding to the logical address carried by the storage command is obtained through the FTL table, reading data from the NVM according to the physical address, and writing the data read from the NVM into a memory of the storage device according to the memory address of the storage device carried by the DMA command corresponding to the storage command.

9. The method of claim 7 or 8, further comprising:

if the first specific identifier corresponding to the logical address carried by the storage command is obtained through the FTL table, the second specific identifier is recorded in the DMA command corresponding to the storage command, and data is not read from the NVM.

10. A DMA engine, comprising:

the first data moving unit acquires data to be moved from the local memory according to the DMA command and provides the data to the data protection and monitoring circuit; if the DMA command indicates a mark, the first data moving unit generates the data to be moved;

the data protection and monitoring circuit decrypts and/or performs data verification on the received data to be moved and provides the result data to the second data moving unit;

and the second data unit moves the result data to an external memory according to the DMA command.

Technical Field

The present invention relates generally to the field of data processing technology. More particularly, the present invention relates to a write and read data method for a memory device, a memory controller and a DMA engine.

Background

FIG. 1A illustrates a block diagram of a storage device. The storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the storage device 102 may be coupled by various methods, including but not limited to, connecting the host and the storage device 102 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIE, high speed Peripheral Component Interconnect), NVMe (NVM Express, high speed nonvolatile storage), ethernet, fibre channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The Memory device 102 (hereinafter, the Memory device is simply referred to as a Memory device) includes an interface 103, a control section 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.

The NVM chip 105 includes a NAND flash Memory, a phase change Memory, a FeRAM (Ferroelectric RAM), a MRAM (magnetoresistive Memory), a RRAM (Resistive Random Access Memory), and the like, which are common storage media.

The interface 103 may be adapted to exchange data with a host by means of, for example, SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.

The control unit 104 is used for controlling data transmission among the interface 103, the NVM chip 105, and the DRAM110, and also for memory management, host logical address to flash physical address mapping, erase balancing, bad block management, and the like. The control component 104 can be implemented in various manners of software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application-Specific Integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. The control component 104 may also be coupled to the DRAM110 and may access data of the DRAM 110. FTL tables and/or cached IO command data may be stored in the DRAM.

The control section 104 issues a command to the NVM chip 105 in a manner conforming to the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives a command execution result output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

In the storage device 102, mapping information from a logical address (LBA) to a physical address is maintained by an FTL (Flash Translation Layer). The logical addresses constitute storage space of the storage device as perceived by upper level software, such as an operating system. The physical address is an address for accessing a physical memory location of the memory device. Address mapping may also be implemented using an intermediate address modality in the related art. E.g. mapping the logical address to an intermediate address, which in turn is further mapped to a physical address. A table structure storing mapping information from logical addresses to physical addresses is called an FTL table. FTL tables are important metadata in storage devices. The data entry of the FTL table records the address mapping relationship in units of data units in the storage device.

Referring to fig. 1B, the control means includes a host interface 1041, a host command processing unit 1042, a storage command processing unit 1043, a media interface controller 1044, and a storage media management unit 1045. The host interface 1041 acquires IO commands provided by the host. The host command processing unit 1042 generates a storage command according to the IO command and provides the storage command to the storage command processing unit 1043. The store command may access the same size of memory space, e.g., 4 KB. A data unit recorded in the NVM chip corresponding to data accessed by one storage command is referred to as a data frame. A physical page records one or more frames of data. For example, a physical page is 17664 bytes in size, and a data frame is 4KB in size, then one physical page can store 4 data frames.

The storage media management unit 1045 maintains a logical to physical address translation for each storage command. For example, the storage medium management unit 1045 includes an FTL table (FTL will be explained below). For a read command, the storage media management unit 1045 outputs a physical address corresponding to a logical address (LBA) accessed by the storage command. For a write command, the storage media management unit 1045 allocates an available physical address to it, and records a mapping relationship between a logical address (LBA) accessed by it and the allocated physical address. The storage medium management unit 1045 also maintains functions required to manage the NVM chips such as garbage collection, wear leveling, etc.

The storage command processing unit 1043 operates the media interface controller 1044 to issue a storage media access command to the NVM chip 105 according to the physical address provided by the storage media management unit 1045.

For clarity, commands sent by the host to the storage device 102 are referred to as IO commands, commands sent by the host command processing unit 1042 to the storage command processing unit 1043 are referred to as storage commands, commands sent by the storage command processing unit 1043 to the media interface controller 1044 are referred to as media interface commands, and commands sent by the media interface controller 1044 to the NVM chip 105 are referred to as storage media access commands. The storage medium access commands follow the interface protocol of the NVM chip.

In the NVMe protocol, after receiving a write command, the storage device 102 obtains data from the memory of the host through the host interface 1041, and then writes the data into the flash memory. For a read command, the storage device 102 moves data to host memory through the host interface 1041 when the data is read from the flash memory.

Fig. 1C shows a basic structure of a host command processing unit 1042 of the prior art. As shown in FIG. 1C, host command processing unit 1042 mainly comprises a shared memory, a DMA module and a CPU subsystem. The CPU subsystem comprises a plurality of CPUs, and the CPUs are used for running programs to process SGLs or PRPs and configuring DMA modules. The DMA module is used for processing the DMA command and implementing data transmission between the host and the storage device. A shared memory (share memory) is used to store data, NVMe commands, and the like.

Disclosure of Invention

In the process of executing the write command, after the storage device 102 receives the write command, it obtains data from the memory of the host through the host interface 1041, the storage media management unit 1045 allocates an available physical address to the write command, and records the mapping relationship between the accessed logical address (LBA) and the allocated physical address, and then the media interface controller 1044 writes these data into the flash memory according to the allocated physical address. However, for the NVM chip 105, the data written therein needs to have a high degree of randomization, and in order to ensure that the data written in the NVM chip 105 has a high degree of randomization, the written data is usually scrambled by the bottom layer, and if the written data is specific data, for example, data with the same bits or repeated cycles, scrambling code added to the specific data can raise the probability of data error.

In addition, the host may also send a deallocation command to the storage device, and the storage device may delete data in a segment of the logical address space according to the deallocation command, for example, the segment of the logical address space indicated by the deallocation command is 10 physical pages, but for the storage device, it can execute the delete command only in units of physical blocks, and usually one physical block contains hundreds or thousands of physical pages, so that the storage device does not delete the NVM if the segment of the logical address space indicated by the deallocation command is several pages.

In the scheme provided by the embodiment of the application, the DMA engine acquires data from the host memory according to one or more DMA commands corresponding to the write command, detects the data, writes non-specific data into the NVM, and does not write specific data into the NVM, so that the probability of data errors is reduced. In addition, if the command received by the storage device is a deallocation command, the control component in the storage device identifies a segment of the logical address space corresponding to the command according to the deallocation command, where the identification indicates that the segment of the logical address space is deallocated and is recorded in the FTL table, and when the read command received by the storage device indicates to access data in the segment of the logical address space, the DMA engine will not read the data from the segment of the logical address space in the NVM, but send an error prompt or specific data to the host.

According to the scheme, in the process of controlling data to be written into the storage device, whether the data is the specific data or not is detected, and the non-specific data is written into the NVM, so that errors caused by the fact that the specific data cannot be written into the flash memory due to the inherent property of the NVM chip 105 are avoided. Due to the adoption of the scheme, the time for writing the specific data into the flash memory of the storage equipment is saved, and the data writing efficiency can be improved.

Further, in the scheme of the application, in the process of controlling the host to read data from the NVM of the storage device, the specific data is generated according to the specific identifier carried by the DMA command corresponding to the read command, and the specific data is sent to the host according to the DMA command, so that a read error caused by the fact that the specific data in the special data mode cannot be read from the flash memory is avoided. Due to the fact that the scheme saves time for reading the specific data from the NVM, the data reading efficiency can be improved.

According to a first aspect of the present application, there is provided a method of writing data for a memory device according to the first aspect of the present application, comprising: in response to receiving one or more DMA commands corresponding to a write command, acquiring data indicated by the DMA commands from a host according to the DMA commands; detecting whether the data is specific data; non-specific data is written to NVM.

According to the first method for writing data of a storage device of the first aspect of the present application, there is provided a second method for writing data of a storage device of the first aspect of the present application, further comprising: if the data is specific data, the data is not written to the NVM.

The first method for writing data to a memory device according to the first aspect of the present application provides a third method for writing data to a memory device according to the first aspect of the present application, further comprising: if the data is specific data, the data need not be written to the NVM.

According to the first method for writing data for a memory device of the first aspect of the present application, there is provided the fourth method for writing data for a memory device of the first aspect of the present application, the specific data including data in a non-random form.

According to a fourth method for writing data of a memory device of the first aspect of the present application, there is provided a fifth method for writing data of a memory device of the first aspect of the present application, the non-random form of data including any one of: all 0, all 1,

According to the method for writing data for a storage device of any one of the first to fifth aspects of the present application, there is provided the method for writing data for a storage device of the sixth aspect of the present application, the writing of the unspecified data to the NVM includes: responding to the data is nonspecific data, allocating corresponding physical addresses for the nonspecific data, and recording the relation between the logical addresses and the physical addresses corresponding to the nonspecific data in an FTL table; and writing the non-specific data to the NVM according to the physical address.

According to the method for writing data of the storage device of any one of the first to fifth aspects of the present application, there is provided a seventh method for writing data of a storage device according to the first aspect of the present application, further comprising: and responding to the data as the specific data, identifying the DMA command corresponding to the specific data, and storing the identification in the shared memory, so that the storage command processor controls the storage medium management unit to record the relation between the logical address and the identification corresponding to the specific data in the FTL table.

According to the method for writing data for a memory device of any one of the first to seventh aspects of the present application, there is provided the eighth method for writing data for a memory device according to the first aspect of the present application, the writing of non-specific data to the NVM further comprises: non-specific data is written to the memory of the storage device without writing specific data to the memory of the storage device.

According to the method for writing data for a memory device of any one of the first to seventh aspects of the present application, there is provided the method for writing data for a memory device of the ninth aspect of the present application, the writing of the unspecified data to the NVM further includes: and writing the non-specific data and the specific data into a memory of the storage device.

According to the eighth or ninth method for writing data of a memory device of the first aspect of the present application, there is provided a method for writing data of a memory device of the tenth aspect of the present application, writing non-specific data to an NVM, comprising: and writing the non-specific data from the memory of the storage device to the NVM through the back-end module without writing the specific data from the memory of the storage device to the NVM.

The method for writing data for a storage device according to any one of the first to tenth aspects of the present application provides the method for writing data for a storage device according to the eleventh aspect of the present application, further comprising: enabling to detect whether the data is specific data according to a first switching signal in response to detecting the write command; and in response to not detecting that the write command is to be executed, stopping detecting whether the data is the specific data according to the second switching signal.

A method of writing data for a memory device according to any one of the first to eleventh aspects of the present application provides the method of writing data for a memory device according to the twelfth aspect of the present application, further comprising: and carrying out PI signature or AES encryption on the acquired data.

According to the method for writing data of the storage device of any one of the first to twelfth aspects of the present application, there is provided the method for writing data of the storage device of the thirteenth aspect of the present application, further comprising: the step of performing PI signature or AES encryption on the data is processed in parallel with the step of detecting whether the data is specific data.

According to a second aspect of the present application, there is provided a first storage controller according to the second aspect of the present application, comprising: the device comprises a host command processing unit, a storage medium management unit and a storage command processing unit; the host command processing unit comprises a DMA engine and a shared memory, and is used for responding to the received write command, generating one or more storage commands and one or more DMA commands corresponding to the storage commands, providing the one or more DMA commands to the DMA engine, and providing the one or more storage commands to the storage command processing unit; the DMA engine comprises a first data moving circuit, a second data moving circuit and a data protection and monitoring circuit; the first data moving circuit is used for responding to a received DMA command, acquiring data indicated by the DMA command according to the DMA command and providing the acquired data to the data monitoring circuit; the data protection and monitoring circuit is used for encrypting and/or carrying out integrity check on the data, detecting whether the data is specific data or not, and recording a detection result in the shared memory; the data protection and monitoring circuit provides the result data of the data encryption and/or integrity check to the second data moving circuit; the second data moving circuit moves the result data acquired from the data protection and monitoring circuit to a memory; and the storage command processing unit is used for responding to the received storage command and determining whether to write the result data in the storage into the NVM controlled by the storage controller according to the detection result of the data corresponding to the storage command.

According to the first memory controller of the second aspect of the present application, there is provided the second memory controller of the second aspect of the present application, wherein the memory command processing unit is further configured to: if the detection result indicates that the data is specific data, the command processing unit provides the detection result to the storage medium management unit; if the detection result indicates that the data is not the specific data, the command processing unit requests the storage medium management unit to allocate a physical address; the storage medium management unit records a designated mark corresponding to a logical address corresponding to the data according to the detection result; and the command processing unit writes the data corresponding to the storage command into the NVM according to the physical address provided by the storage medium management unit.

According to the first memory controller of the second aspect of the present application, there is provided the third memory controller of the second aspect of the present application, wherein if the detection result indicates that the data is specific data, the command processing unit does not write the data corresponding to the memory command into the NVM and frees up a memory space of the data in the memory.

According to the second or third storage controller of the second aspect of the present application, there is provided the fourth storage controller of the second aspect of the present application, and if the detection result indicates that the data is not the specific data, the command processing unit writes the data corresponding to the storage command into the memory of the storage device according to the physical address provided by the storage medium management unit, so that the backend module writes the data into the NVM from the memory of the storage device.

According to a third or fourth storage controller of the second aspect of the present application, there is provided the fifth storage controller of the second aspect of the present application, wherein if the detection result indicates that the data is specific data, the command processing unit writes the data into a storage device memory or does not write the data into the storage device memory.

There is provided a sixth storage controller according to the second aspect of the present application, according to any one of the first to fifth storage controllers of the second aspect of the present application, further comprising: a detection control switch configured to: enabling to detect whether the data is specific data according to a first switching signal in response to detecting the write command; and in response to not detecting that the write command is to be executed, stopping detecting whether the data is the specific data according to the second switching signal.

According to any one of the first to sixth memory controllers of the second aspect of the present application, there is provided the seventh memory controller of the second aspect of the present application, wherein the second data moving circuit is further configured to: if the detection result indicates that the data is specific data, the result data acquired from the data protection and monitoring circuit does not need to be moved to a memory.

According to a third aspect of the present application, there is provided a first storage device according to the third aspect of the present application, comprising: the storage controller comprises a host command processing unit, a storage medium management unit and a storage command processing unit; the host command processing unit comprises a DMA engine and a shared memory, and is used for responding to the received write command, generating one or more storage commands and one or more DMA commands corresponding to the storage commands, providing the one or more DMA commands to the DMA engine, and providing the one or more storage commands to the storage command processing unit; the DMA engine comprises a first data moving circuit, a second data moving circuit and a data protection and monitoring circuit; the first data moving circuit is used for responding to a received DMA command, acquiring data indicated by the DMA command according to the DMA command and providing the acquired data to the data monitoring circuit; the data protection and monitoring circuit is used for encrypting and/or carrying out integrity check on the data, detecting whether the data is specific data or not, and recording a detection result in the shared memory; the data protection and monitoring circuit provides result data for encrypting and/or carrying out integrity check on the data to the second data moving circuit; the second data moving circuit moves the result data acquired from the data protection and monitoring circuit to the memory; and the storage command processing unit is used for responding to the received storage command and determining whether to write the result data in the memory into the NVM controlled by the storage controller according to the detection result of the data corresponding to the storage command.

According to the first storage device of the third aspect of the present application, there is provided the second storage device of the third aspect of the present application, wherein the storage command processing unit is further configured to: if the detection result indicates that the data is specific data, the command processing unit provides the detection result to the storage medium management unit; if the detection result indicates that the data is not the specific data, the command processing unit requests the storage medium management unit to allocate a physical address; the storage medium management unit records a designated mark corresponding to a logical address corresponding to the result data according to the detection result; and the command processing unit writes the result data corresponding to the storage command into an NVM according to the physical address provided by the storage medium management unit.

According to the first storage device of the third aspect of the present application, there is provided the third storage device of the third aspect of the present application, wherein the storage command processing unit further includes a backend module, and the storage command processing unit is configured to control the backend module to write the non-specific data from the memory of the storage device to the NVM.

According to the first or second memory device of the third aspect of the present application, there is provided the fourth memory device of the third aspect of the present application, wherein the second data moving circuit is further configured to: if the detection result indicates that the data is specific data, the result data acquired from the data protection and monitoring circuit does not need to be moved to the memory of the storage device.

According to a fourth aspect of the present application, there is provided a method of reading data for a memory device according to the fourth aspect of the present application, comprising: acquiring a read command, generating one or more storage commands according to the read command, and acquiring a physical address or a first specific identifier corresponding to a logical address carried by the storage command through an FTL (flash translation layer) table; generating a DMA command corresponding to each storage command according to the storage command, wherein the DMA command carries second information, and the second information comprises a memory address of the storage device and/or a second specific identifier; and if the second information of the DMA command is the second specific identifier, generating the specific data according to the second specific identifier, and sending the specific data to the host according to the DMA command.

The first method for reading data of a memory device according to the fourth aspect of the present application provides the second method for reading data of a memory device according to the fourth aspect of the present application, further comprising: and if the second information of the DMA command is the memory address of the storage device, reading data from the NVM to the memory of the storage device according to the physical address corresponding to the logical address carried by the storage command corresponding to the DMA command and acquired through the FTL table and the memory address of the storage device.

The first method for reading data of a memory device according to the fourth aspect of the present application provides the third method for reading data of a memory device according to the fourth aspect of the present application, wherein the specific data includes data in a non-random form.

A method for reading data for a memory device according to the fourth aspect of the present application is provided, wherein the data in a non-random form includes any one of the following: all 0, all 1,

A method of reading data for a memory device according to any one of the first to fourth aspects of the present application provides a fifth method of reading data for a memory device according to the fourth aspect of the present application, further comprising: in response to generating the specific data, sending a notification that the specific data has been read out.

According to a first method for reading data of a memory device of a fourth aspect of the present application, there is provided a sixth method for reading data of a memory device according to the fourth aspect of the present application, further comprising: and if the physical address corresponding to the logical address carried by the storage command is obtained through the FTL table, reading data from the NVM according to the physical address, and writing the data read from the NVM into a memory of the storage device according to the memory address of the storage device carried by the DMA command corresponding to the storage command.

According to a fifth method for reading data of a memory device of the fourth aspect of the present application, there is provided a seventh method for reading data of a memory device according to the fourth aspect of the present application, further comprising: if the first specific identifier corresponding to the logical address carried by the storage command is obtained through the FTL table, the second specific identifier is recorded in the DMA command corresponding to the storage command, and data is not read from the NVM.

A method of reading data for a memory device according to any one of the first to seventh aspects of the present application provides the eighth method of reading data for a memory device according to the fourth aspect of the present application, further comprising: in response to detecting the read command, enabling transmission of the generated specific data to the host according to a third switching signal; and stopping sending the generated specific data to the host according to the fourth switching signal in response to detecting that the read command is completely executed.

A method of reading data for a memory device according to any one of the third to eighth aspects of the present application provides the ninth method of reading data for a memory device according to the fourth aspect of the present application, further comprising: the step of generating the specific data and the step of performing AES decryption and/or PI signature on the specific data are processed simultaneously.

According to a fifth aspect of the present application, there is provided a first DMA engine according to the fifth aspect of the present application, comprising: the first data moving unit acquires data to be moved from the local memory according to the DMA command and provides the data to the data protection and monitoring circuit; if the DMA command indicates a mark, the first data moving unit generates the data to be moved; the data protection and monitoring circuit decrypts and/or performs data verification on the received data to be moved and provides the result data to the second data moving unit; and the second data unit moves the result data to an external memory according to the DMA command.

The first DMA engine according to the fifth aspect of the present application provides the second DMA engine according to the fifth aspect of the present application, further comprising: a second switching circuit configuration configured to: in response to detecting the read command, enabling transmission of the generated specific data to the host according to a third switching signal; and stopping sending the generated specific data to the host according to the fourth switching signal in response to detecting that the read command is completely executed.

According to a sixth aspect of the present application, there is provided a first controller according to the sixth aspect of the present application, comprising any one of the memory controllers according to the second aspect of the present application and any one of the DMA engines according to the fifth aspect of the present application, or any one of the memory devices according to the third aspect of the present disclosure.

According to a seventh aspect of the present disclosure, there is provided a first electronic device according to the seventh aspect of the present disclosure, comprising the first controller according to the sixth aspect of the present disclosure.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.

FIG. 1A is a block diagram of a prior art memory device;

FIG. 1B is a schematic diagram of a control unit in the prior art;

FIG. 1C is a schematic diagram of a host command processing unit in the prior art;

FIG. 2 is a flow chart of a method for writing data to a memory device according to an embodiment of the present application;

FIG. 3A is a schematic diagram illustrating a method for writing non-specific data to an NVM according to an embodiment of the present application;

FIG. 3B is a schematic diagram of an embodiment of the present application, illustrating that no specific data is written to the NVM;

FIG. 3C is a schematic diagram illustrating data writing by a method for writing data in a memory device according to an embodiment of the present disclosure;

FIG. 3D is a diagram illustrating a method for writing specific data into a memory of a storage device according to an embodiment of the present disclosure;

fig. 4A is a circuit structure diagram of a memory controller according to an embodiment of the present application;

FIG. 4B is a diagram illustrating a DMA engine operating at different times according to an embodiment of the present application;

fig. 4C is a schematic structural diagram of a storage device according to an embodiment of the present application;

FIG. 5A is a flowchart of a method for reading data of a memory device according to an embodiment of the present disclosure;

FIG. 5B is a diagram illustrating a process for transferring data according to DMA commands according to an embodiment of the present application;

FIG. 5C is a diagram illustrating a process of reading data from a memory according to a read command according to an embodiment of the present application;

FIG. 6 is a circuit configuration of a method for reading data of a memory device according to an embodiment of the present application;

fig. 7 is a circuit configuration diagram of a DMA engine according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 2 shows a flowchart of a method for writing data to a storage device according to an embodiment of the present application, that is, a method for a storage device to receive a command as a write command. As shown in fig. 2, first, step 201 is executed to, in response to receiving one or more DMA commands corresponding to a write command, obtain data indicated by the DMA command from the host according to the DMA command.

By way of example, the write command described above may be transmitted between the host and the storage device by way of the NVMe protocol, and thus the write command may be an NVMe command. NVMe has two commands, one is an admin command for the host to manage and control the storage device, and the other is an IO command, including a read command and a write command, for controlling data transfer between the host and the storage device. The field (or field) in the IO command that relates to the SGL or PRP indicates the location of the data in the host memory (for write commands) or the host memory address to which the data needs to be written (for read commands). By way of example, an IO command may transfer, for example, 128KB of data.

In addition, the IO command further includes a starting logical address (LBA) of the storage device to be accessed, a host memory address, and a data length. For a write command, after acquiring data from a host memory according to a host memory address, the storage device allocates a corresponding physical address for the write command by querying the FTL table, writes the data into the flash memory according to the physical address, generates a mapping relationship between the logical address LBA and the physical address, and records the mapping relationship through the FTL table. For the read command, the storage device searches the FTL table according to the LBA carried in the read command, finds a corresponding physical address, and obtains data from a physical block corresponding to the physical address.

Further, since the length of the IO command received by the storage device is random and variable, the convenience and the regularity of the processing are poor. In order to improve the convenience and the regularity of the processing, for example, one or more DMA (Direct Memory Access) command groups are generated by analyzing the SGL/PRP corresponding to the IO command, where the DMA is also called a group data transfer method, one DMA command group is formed by one or more DMA commands, and the data size indicated by each DMA command is not fixed. For example, one DMA command group is made up of 4 DMA commands, each indicating 1KB of data; as another example, a group of DMA commands consists of 5 DMA commands, one DMA command indicating 1KB of data and four other DMA commands indicating 0.5KB of data. The data size indicated by a DMA command is related to the size of the address space described by the corresponding SGL descriptor, e.g., SGL indicates 60 address spaces of 1KB, then a DMA command group may include 4 DMA commands indicating 1KB of data; as another example, where the SGL indicates 30 address spaces of 2KB, then a DMA command group includes 2 DMA commands indicating 2KB of data.

In one application scenario, a DMA command group lists multiple DMA commands, one DMA command group for manipulating data of a specified length. In the example of the present application, the specified length may be one data frame size, i.e., 4 KB; the size of 4KB can be called a Data Transfer Unit (DTU) corresponding to each entry of the FTL table; and when the storage equipment processes the IO command, initiating data transmission according to the DTU as a unit.

Based on this, one IO command may include one or more DMA command groups. For example, an IO command indicates a data size of 4KB, which corresponds to a DMA command group. As another example, an IO command indicates a data size of 12KB, which corresponds to 3 DMA command groups.

In another application scenario, the data size indicated by the DMA command group may also be less than the length of one DTU. For example, an IO command indicates a data size of 13KB, which corresponds to 4 DMA command groups, the first 3 DMA command groups indicating a data size of 4KB, and the 4 th DMA command group indicating a data size of 1 KB. That is, the data size indicated by the DMA command group may be a fixed value (4KB), or the data size indicated by the IO command modulo the fixed value, that is, modulo 13KB to 4KB, may be 1 KB.

In this embodiment, the DMA transfer may be performed via a DMA command. DMA transfers refer to copying data from one address space to another address space that provides high speed data transfer between a host and memory or between memory and memory. The transfer action itself is implemented and completed by the DMA controller. The DMA transmission mode does not need a CPU to directly control transmission, does not have an interrupt processing mode, and opens up a channel for directly transmitting data through hardware, so that the efficiency of the CPU is greatly improved.

One DMA command as described above can implement one data transfer by the DMA technique. The DMA command includes a host memory address and a storage device memory address (e.g., a DRAM address), so the set of DMA commands indicates a mapping of the host memory address space to the storage device memory address space. For a write command, the memory address of the host is a source address, and the memory address of the storage device is a destination address; for a read command, the host memory address is the destination address and the storage device memory address is the source address. The host memory address contained in the DMA command is determined according to the address space described by the SGL or the PRP, the memory address of the storage device is allocated by the storage device, and the storage device can allocate a continuous memory address space of the storage device, so as to improve the processing efficiency of the DMA.

And when the IO command is a write command, responding to one or more DMA commands corresponding to the received write command, and acquiring the data indicated by the DMA command from the host according to the host memory address indicated by the DMA command.

Then, step 202 is executed to detect whether the data is specific data. The host command processing unit described in FIG. 1B may process one or more DM's that pass byThe data corresponding to the command A is detected so as to identify whether the data is specific data. By way of example, the specific data may be designated as data that is not suitable for writing into the NVM chip 105, for example, the designated data is data with low randomness (non-random data), such as data with low randomness that all bit data in the data are the same or data that is repeatedly cycled. By way of example, the non-random data includes any of: all 0, all 1,WhereinIt is shown that the data is cycled through in 01,data is shown in 10 cycles. In this embodiment, data corresponding to each DMA command may be set as a detection unit, or data indicated by a DMA command group composed of a plurality of DMA commands may be set as a detection unit. For example, if a DMA command group consists of 4 DMA commands, each of which indicates 1KB of data, then the four 1KB of data may be detected separately, or the four 4KB of data indicated by the DMA command group may be detected together; if another DMA command group is composed of 5 DMA commands, one DMA command indicates 1KB of data, and the other four DMA commands indicate 0.5KB of data, then 1KB of data and four 0.5KB of data may be detected in sequence, or 3KB of data indicated by the DMA command group may be detected.

Finally, step 203 is executed to write the non-specific data to the NVM. By way of example, the non-specific data may be relatively random data, such as all bit data in the data are not all the same and/or are repeatedly cycled with a certain rule, for example, the non-specific data may be non-all 0 data or non-all 1 data. As another example, the non-specific data may be data other than the specific data, that is, if the data is not the specific data, the data is the non-specific data; or the non-specific data is data acquired from data other than the specific data.

In some embodiments, writing non-specific data to NVM includes: responding to the fact that the data are nonspecific data, distributing corresponding physical addresses for the nonspecific data, and recording the relation between the logical addresses and the physical addresses corresponding to the nonspecific data in an FTL table; and writing non-specific data to the NVM according to the physical address. In the process of executing the write command, after the storage device 102 acquires non-specific data corresponding to the write command, the storage command processing unit 1045 may allocate an available physical address for the non-specific data, record a mapping relationship between a logical address (LBA) accessed by the write command and the allocated physical address in an FTL table in the storage medium management unit 1043, and then control the media interface controller 1044 by the storage command processing unit 1045 to write the non-specific data into the NVM chip 105 according to the allocated physical address.

NVM has a variety of specifications. For example, NVMs of the same or different vendors vary in number and size of physical blocks, number and size of physical pages, etc., which introduces additional burden on the controlling component to manage the NVM. To facilitate the use of diverse NVMs, the control unit or its storage management unit organizes the diverse NVMs into a standard or uniform form. For example, a unified morphological physical block includes 1000 physical pages, each of 16KB in size. It is understood that 1000 physical pages, 16KB are examples. Still by way of example, a NVM chip has physical blocks that actually include 512 physical pages, each physical page being 16KB in size. At this time, the 2 physical blocks of the NVM chip are combined to obtain physical blocks with unified form, each real physical block provides 500 physical pages for the physical blocks with unified form, and the rest physical pages are reserved or not used. It will be appreciated that the physical blocks of a unified form are constructed from one or more real physical blocks, depending on the actual specifications of the NVM chip. FIG. 3A shows a schematic diagram of the present application for writing non-specific data to an NVM.

In the storage device, a mapping relationship from a Logical Block Address (LBA) physical Block Address is maintained by using an FTL (Flash Translation Layer). As shown in fig. 3A, the NVM includes physical block 0, physical block 1, physical block 2, physical block 3, physical block 4, physical block 5, physical block 6, and physical block 7, if the control unit receives an I/O command sent by the host, the I/O command is a write command, and the write command carries the LBA3 of the logical block. Allocating a logical block space provided by a physical block 1 for the write command, and then writing data corresponding to the write command into the physical block 1; and recording LBA3 in the FTL table with the address (e.g., physical address) for physical block 1. Further, LBA0, LBA1, LBA2, LBA4, LBA5, LBA6, and LBA7 may be allocated with corresponding physical addresses in a similar manner, for example, the physical address of physical block 0 corresponding to LBA0, the physical address of physical block 1 corresponding to LBA1, and so on.

In other embodiments, if the data corresponding to the one or more DMA commands is the specific data as a result of the detection in step 202, the specific data is not written to the NVM or is not required to be written to the NVM. In this embodiment, if the data corresponding to one or more DMA commands is specific data, the DMA command corresponding to the specific data may be identified, and the identifier is stored in the shared memory in fig. 1C, so that the storage command processing unit 1045 controls the storage medium management unit 1043 to record the relationship between the logical address and the identifier corresponding to the specific data in the FTL table.

Fig. 3B shows a schematic diagram of the present application without writing specific data to NVM. After the host command processing unit 1042 in fig. 1B receives a write command (i.e., "NVMe CMD (write)" in fig. 3B) from the host interface 1041, the host command processing unit 1042 may generate a DMA command group. If 6 DMA command sets generated according to the NVMe write command correspond to one DTU, each DMA command set has 6 DTUs such as DTU0, DTU1, DTU2, DTU3, DTU4 and DTU5 in total, if the Data indicated by the DMA command set corresponding to DTU3 is all 0 Data, the host command processing Unit only moves the Data corresponding to DTU0, DTU1, DTU2, DTU4 and DTU5 from the host memory to the storage device memory respectively, and does not move the Data corresponding to DTU3 to the storage device memory, and then the back-end module (media interface controller 1044) moves the Data corresponding to DTU0, DTU 84, DTU2, DTU4 and DTU5 from the storage device memory to the NVM memory respectively, wherein the Data include five Data units corresponding to NVM 5, 24 and 5730, and 2, respectively, DU1 corresponds to DTU1, DU2 corresponds to DTU2, DU4 corresponds to DTU4, and DU5 corresponds to DTU 5.

Fig. 3C is a schematic diagram illustrating data writing by a method for writing data of a storage device according to an embodiment of the present application. After the host command processing unit 1042 in fig. 1B receives the write command from the host interface 1041, the host command processing unit 1042 generates 6 DMA command groups according to the write command, if the 6 DMA command groups are generated according to the NVMe write command, each DMA command group corresponds to one DTU, there are 6 DTUs such as DTU0, DTU1, DTU2, DTU3, DTU4, and DTU5, and the logical addresses corresponding to each DTU are: if the data indicated by the DMA command group corresponding to DTU3 is all 0 data, the host command processing unit performs data transfer (writes data from the host to the storage device) according to the 6 DMA command groups, only the data corresponding to DTU0, DTU1, DTU2, DTU4, and DTU5 are respectively transferred from the host memory to the storage device memory, and the data corresponding to DTU3 is not transferred to the storage device memory. In addition, the storage command processing Unit 1045 allocates a physical address to each Data Unit corresponding to each DTU, and the storage space corresponding to each physical address is a Data Unit (DU, Data Unit), that is, five DUs are allocated, which are DU 0, DU1, DU2, DU4, and DU5, respectively, and the physical address corresponding to DU 0 is PA0, the physical address corresponding to DU1 is PA1, the physical address corresponding to DU2 is PA2, the physical address corresponding to DU4 is PA4, and the physical address corresponding to DU5 is PA 5. After the storage command processing unit 1045 allocates the physical address, for the non-specific data (i.e. DTU0, DTU1, DTU2, DTU4, DTU5 in fig. 3C), the storage command processing unit 1045 may allocate the physical address for it and record the correspondence between its logical address and the allocated physical address in the FTL table in the storage medium management unit 1043. As shown in fig. 3C, the FTL table records the correspondence between logical addresses LA0, LA1, LA2, LA4, and LA5 of DTUs 0, DTUs 1, DTUs 2, DTUs 4, and DTUs 5 and their allocated physical addresses PA0, PA1, PA2, PA4, and PA 5. The logical addresses corresponding to the unassigned physical addresses (shown as LA6, LA7 in FIG. 3C) may remain unassigned (i.e., "Null" in FIG. 3C). Here, "Null" refers to Null, which means that the logical address is not assigned a corresponding physical address.

For specific data (i.e., DTU3 in fig. 3C), the DMA command group corresponding to the specific data may be identified (i.e., logical address LA3 of DTU3 is identified as "all 0" in fig. 3C), and the identification is stored in the shared memory in fig. 1C, and the storage command processing unit 1045 may control the storage medium management unit 1043 to record the relationship between logical address LA3 corresponding to DTU3 and the identification "all 0" in the FTL table.

By way of example, writing non-specific data to NVM includes two steps: the first step is to move the non-specific data from the host to the memory of the storage device through the storage command processing unit 1045, for example, the memory of the storage device is a dynamic random access memory DRAM; the second step is writing the non-specific data from the DRAM to the NVM by the back-end module (the media interface controller shown in fig. 1B) according to the physical address corresponding to the non-specific data.

Further, in the solution provided by the embodiment of the present application, if the data indicated by one or more DMA commands is specific data, the specific data is not written to the NVM. Since writing data to NVM includes at least two steps, not writing specific data to NVM may include writing specific data to DRAM.

By way of example, step 203 as described above further comprises: non-specific data is written to the memory of the storage device without writing specific data to the memory of the storage device. If the data indicated by the DMA command is non-specific data, the data indicated by the DMA command may be stored in a memory (e.g., a DRAM in fig. 1A) of the storage device according to the logical address carried by the DMA command, and if the data indicated by the DMA command is specific data, the data indicated by the DMA command does not need to be stored in the memory (e.g., a DRAM in fig. 1A) of the storage device according to the logical address carried by the DMA command.

As another example, if the data indicated by the DMA command is specific data, the data indicated by the DMA command may be stored in a memory of the storage device according to a logical address carried by the DMA command.

Fig. 3D is a schematic diagram illustrating a process for writing specific data into a memory of a storage device according to the present application. After the host command processing unit 1042 in fig. 1B receives a write command (i.e., "NVMe CMD (write)" in fig. 3D) from the host interface 1041, the host command processing unit 1042 may generate a DMA command group. Fig. 3D shows 6 DMA command groups generated according to the NVMe CMD write command, where each DMA command group corresponds to one DTU, and there are 6 DTUs such as DTU0, DTU1, DTU2, DTU3, DTU4, DTU5, and the like, where data corresponding to DTUs 0, DTU1, DTU2, DTU4, and DTU5 is non-specific data, and data corresponding to DTU3 is specific data (e.g., all 0), and when the storage device initiates data write according to DTUs 0, DTU1, DTU2, DTU3, DTU4, and DTU5, data corresponding to DTUs 0, DTU1, DTU2, DTU3, DTU4, and DTU5 are all stored in the memory of the storage device. Then, the back-end module (media interface controller) moves the data corresponding to DTU0, DTU1, DTU2, DTU4, and DTU5 from the memory of the storage device to the NVM, respectively, without moving the data corresponding to DTU3 to the NVM.

In still other embodiments, the method for writing data to a storage device further includes: enabling whether the detection data is the specific data according to the first switch signal in response to the detection of the write command; and in response to not detecting that the write command is to be executed, stopping detecting whether the data is the specific data according to the second switching signal. The host command processing unit 1042 in fig. 1B may determine whether to perform data type detection on data indicated by a DMA command corresponding to the write command according to the write command, and if the host command processing unit 1042 detects the write command, generate an enable signal (i.e., the aforementioned "first switch signal") to enable detection of whether the data is specific data; if the host command processing unit 1042 does not detect the write command to be executed, it generates a close signal (i.e. the above-mentioned "second switch signal") to stop detecting whether the data is the specific data.

In other embodiments, the method for writing data to a memory device further includes: and carrying out PI signature or AES encryption on the acquired data. In this embodiment, the DMA module in fig. 1C may perform PI signature or AES encryption on the data indicated by the DMA command corresponding to the write command. Pi (protect information) refers to signing transmitted data. Aes (advanced Encryption standard) is an advanced Encryption standard adopted for blocks. AES is a symmetric encryption algorithm, with the same key used for encryption and decryption. Optionally, PI signature or AES encryption is performed on the data indicated by the DMA command corresponding to the write command, and whether the data is specific data is detected, and the data is executed and processed in parallel.

According to the above steps 203-203, in the process of controlling data to be written into the storage device, according to the scheme of the present application, by detecting that non-specific data is written into the NVM and specific data is not written into the NVM, the problem of high error rate caused by subsequent read data due to low randomness of data after scrambling the data in the NVM is avoided. In addition, due to the fact that only non-specific data are written into the NVM and specific data are not written into the NVM, time for writing data indicated by the write command into a flash memory of the storage device is saved, and data writing efficiency can be improved.

The specific hardware circuitry that implements the read command processing described above will be further described below.

FIG. 4A is a circuit diagram of a memory controller according to an embodiment of the present application. As shown in fig. 4A, the storage controller includes a host command processing unit 1042, a storage medium management unit 1045, and a storage command processing unit 1043. The host command processing unit 1042 includes the DMA engine 400 and a shared memory. Host command processing unit 1042 may, in response to receiving a write command from host interface 1041, generate one or more storage commands and one or more DMA commands corresponding to the storage commands and store the one or more DMA commands in shared memory, where DMA engine 400 receives the one or more DMA commands and provides the one or more storage commands to storage command processing unit 1043. The DMA engine 400 includes a first data shifting circuit 401, a second data shifting circuit 403, and a data protection and monitoring circuit 402.

The first data move circuit 401 acquires data indicated by a DMA command from the host according to the DMA command (i.e., (1) "in fig. 4A) in response to receiving the DMA command, and supplies the acquired data to the data monitor circuit 502 (i.e., (2)" in fig. 4A). The data protection and monitoring circuit 402 is used for encrypting and/or integrity-checking data and detecting whether the data is specific data, and recording a detection result (i.e., (3.1) "in fig. 4A) in the shared memory, for example, the detection result includes a detection result of encrypting and/or integrity-checking data or a detection result that the data is specific data. The data protection and monitoring circuit 402 provides the result data of encrypting and/or integrity checking the data to the second data moving circuit 403 (i.e., (3.2) "in fig. 4A). Pi (protect information) refers to signing transmitted data. Aes (advanced Encryption standard) is an advanced Encryption standard adopted for blocks, which is a symmetric Encryption algorithm, and the same key is used for Encryption and decryption. The data protection and monitoring circuit 402 may encrypt the data using an AES encryption algorithm and may perform integrity check on the data using a PI signature.

The second data moving circuit 403 moves the result data acquired from the data protection and monitoring circuit 402 to the DRAM110 (i.e., (4) "in fig. 4A). The storage command processing unit 1043 is configured to determine whether to write the result data in the DRAM110 to the NVM105 controlled by the storage controller in response to receiving the storage command and according to the detection result of the data corresponding to the storage command. If the storage command processing unit 1045 obtains a detection result of the data corresponding to the storage command, that is, the data is non-specific data (i.e., "5" in fig. 4A), the storage command processing unit 1045 may allocate an available physical address to the non-specific data, and record a mapping relationship between a logical address (LBA) accessed by the write command and the allocated physical address (i.e., "6" in fig. 4A) in an FTL table in the storage medium management unit 1043, and then the storage command processing unit 1045 controls the media interface controller 1044 to write the non-specific data from the DRAM110 (i.e., "DTU" in fig. 4A) to the NVM chip 105 (i.e., "8" in fig. 4A) according to the allocated physical address (i.e., "7" in fig. 4A).

If the detection result that the storage command processing unit 1045 acquires the data corresponding to the storage command is that the data is the specific data (i.e., "5" in fig. 4A), the storage command processing unit 1045 may control the storage medium management unit 1043 to record a relationship between a logical address corresponding to the specific data and a specific identifier (e.g., "all 0") indicating the specific data in the FTL table (i.e., "6" in fig. 4A). These specific data are not written to the NVM or need not be written to the NVM at this time, i.e. step (7) and step (8) in fig. 4A no longer occur.

FIG. 4B shows a diagram of a DMA engine operating at different times. As shown in fig. 4B, T0, T1, T2, T3 refer to consecutive different times (fig. 4B shows only four different times by way of example, and the present embodiment is not limited thereto). At time T0, the first data transfer circuit responds to DMA command 1 to obtain data, and the data protection and monitoring circuit and the second data transfer circuit are in idle state (i.e. not working state); at the time of T1, the first data moving circuit acquires data in response to the DMA command 2, the data protection and monitoring circuit detects whether the data (i.e., the data acquired by the first data moving circuit at the time of T0) is specific data and encrypts and/or performs integrity check on the data to obtain result data, and the second data moving circuit is in an idle state; at a time T2, the first data moving circuit is in an idle state, the data protection and monitoring circuit detects whether data (i.e., data acquired by the first data moving circuit at the time T1) is specific data and encrypts and/or performs integrity check on the data to obtain result data, and the second data moving circuit moves the data protection and monitoring circuit to the DRAM110 to obtain the result data at the time T1 and/or the data detected at the time T1; at time T3, the first data movement circuit and the data protection and monitoring circuit are in idle state, and the second data movement circuit moves the data protection and monitoring circuit to the DRAM110, which obtains the result data at time T2 and/or the data detected at time T2.

For example, if the data protection and monitoring circuit 402 detects that the data indicated by the DMA command is specific data, the second data moving circuit 403 does not need to move the result data obtained from the data protection and monitoring circuit 402 to the DRAM110 (i.e. step "(4)" in fig. 4A does not occur any more). Alternatively, if the data protection and monitoring circuit 402 detects that the data indicated by the DMA command is specific data, the second data moving circuit 403 may move the result data obtained from the data protection and monitoring circuit 402 to the DRAM110 (i.e., as shown in "(4)" in fig. 4A). In this embodiment, the storage command processing unit 1045 obtains that the data corresponding to the storage command is the specific data (i.e., (5) "in fig. 4A) as a result of detecting that the data is the specific data, and since the storage command processing unit 1045 does not write the data corresponding to the storage command into the NVM, the storage space corresponding to the specific data and the storage space of the shared memory occupied by the DMA command corresponding to the specific data in the DRAM110 of fig. 4A are released.

In some embodiments, the memory controller in the above embodiments further includes: a detection control switch 404, the detection control switch 404 configured to: enabling whether the detection data is the specific data according to the first switch signal in response to the detection of the write command; and in response to not detecting that the write command is to be executed, stopping detecting whether the data is the specific data according to the second switching signal. The host command processing unit 1042 may determine whether to perform data type detection on data indicated by a DMA command corresponding to the write command according to the write command, and if the host command processing unit 1042 detects the write command, generate an enable signal (i.e. the above-mentioned "first switch signal") to enable detection of whether the data is specific data; if the host command processing unit 1042 does not detect the write command to be executed, it generates a close signal (i.e. the above-mentioned "second switch signal") to stop detecting whether the data is the specific data.

Fig. 4C shows a schematic structural diagram of a memory device according to an embodiment of the present application. As shown in fig. 4C, the storage device includes: a storage controller (i.e., the control unit 104 in fig. 4C), a memory 110, and an NVM105, the storage controller including a host command processing unit 1042, a storage medium management unit 1045, and a storage command processing unit 1043; the host command processing unit includes a DMA engine 400 and a shared memory for generating one or more memory commands and one or more DMA commands corresponding to the memory commands in response to receiving a write command, and providing the one or more DMA commands to the DMA engine 400 and the one or more memory commands to the memory command processing unit; the DMA engine comprises a first data moving circuit 401, a second data moving circuit 403 and a data protection and monitoring circuit 402; the first data moving circuit 401 is configured to, in response to receiving a DMA command, obtain data indicated by the DMA command according to the DMA command, and provide the obtained data to a data monitoring circuit; a data protection and monitoring circuit 402, configured to encrypt and/or perform integrity check on the data, and detect whether the data is specific data, and record a detection result in the shared memory; the data protection and monitoring circuit 402 provides the result data of encrypting and/or integrity checking the data to the second data moving circuit 403; the second data moving circuit 403 moves the result data obtained from the data protection and monitoring circuit 402 to the memory; the storage command processing unit 1043 is configured to, in response to receiving a storage command, determine whether to write result data in the memory to the NVM105 controlled by the storage controller according to the detection result of data corresponding to the storage command. The memory controller of the memory device is the control unit 104 in fig. 1A, the memory is the DRAM in fig. 1A, and the NVM is the NVM105 in fig. 1A. The memory controller of the memory device has the circuit structure of the memory controller shown in fig. 4A, and the components and functions thereof are the same as those of the memory controller shown in fig. 4A, and are not described again here.

Fig. 5A is a flowchart illustrating a method for reading data of a memory device, that is, a method for processing a read command according to an embodiment of the present application. As shown in fig. 5A, first, step 501 is executed to obtain a read command, generate one or more storage commands according to the read command, and obtain a physical address or a first specific identifier corresponding to a logical address carried by the storage command through an FTL table. For a read command, the storage device searches the FTL table according to the LBA, finds a corresponding physical address or a first specific identifier referring to specific data. The first specific flag here may be, in the method for writing data to the storage device according to the foregoing embodiment of the present application, the storage medium management unit 1043 records, in the FTL table according to a detection result of the data corresponding to the write command (that is, the data corresponding to the write command is the specific data), a specific flag corresponding to the logical address corresponding to the specific data (for example, in the FTL table in fig. 3C, the specific flag "all 0" corresponding to the logical address LA 3).

Next, step 502 is performed to generate a DMA command corresponding to each memory command. The DMA command carries second information, and the second information comprises a memory address of the storage device and/or a second specific identifier. For example, if the storage device queries the FTL table to determine that the logical address indicated by one or more DMA commands corresponding to the read command corresponds to the first specific identifier, the host command processing unit 1042 in fig. 1B may generate a DMA command corresponding to each storage command according to the storage command, identify the DMA command, that is, the DMA command carries the second specific identifier, and store the DMA command in the shared memory. The second specific identifier here is the same as the function of identifying the DMA commands corresponding to the specific data in the method for writing data in a storage device according to the foregoing embodiment, and all the functions are to mark the data indicated by the DMA commands as specific data, if the data corresponding to one or more DMA commands corresponding to the write commands are specific data.

Finally, step 503 is executed, if the second information of the DMA command is the second specific identifier, specific data is generated according to the second specific identifier, and the specific data is sent to the host according to the DMA command. The DMA engine of fig. 4A may generate the particular data based on the second particular identification and send the particular data to the host based on the DMA command. For example, the DMA engine may transfer data corresponding to one DMA command group at a time, and since one DMA command group may contain more than one DMA command, for example, data indicated by a first part of DMA commands in one DMA command group is specific data, and data indicated by a second part of DMA commands is non-specific data, the DMA engine acquires the non-specific data from the NVM according to the second part of DMA commands, generates specific data according to the first part of DMA commands, and then sends the acquired non-specific data and the generated specific data to the host.

Fig. 5B is a schematic diagram illustrating a process of moving data according to a DMA command according to an embodiment of the present application. As shown in fig. 5B, one DMA command group is composed of 4 DMA commands, which are DMA command 1, DMA command 2, DMA command 3, and DMA command 4, respectively, where the data indicated by DMA command 1 is all 0, the data indicated by DMA command 4 is all 1, the data indicated by DMA command 2 is unspecified data 1, the data indicated by DMA command 3 is unspecified data 2, the backend module moves the unspecified data 1 and the unspecified data 2 from the NVM chip to the memory of the storage device according to DMA command 2 and DMA command 3, then the DMA engine obtains the unspecified data 1 and the unspecified data 2 from the memory of the storage Device (DRAM) according to DMA command 2 and DMA command 3, and generates all 0 data according to DMA command 1, and the DMA command 4 generates all 1 data, and moves all 0 data, unspecified data 1, unspecified data 2, and all 1 data to the host.

Fig. 5C is a schematic diagram illustrating a process of reading data from a memory according to a read command according to an embodiment of the present application. As shown in fig. 5C, first, the host command processing unit acquires an NVMe command (i.e., a read command) and generates a storage command (i.e., (1) "in fig. 5C) according to the NVMe command, where the NVMe command includes a logical address and a host memory address; then, a physical address corresponding to the logical address is queried through an FTL table or a specific mark (shown in "(2 a)" in fig. 5C) referring to specific data is found, a corresponding storage device memory address (shown in "(2 b)" in fig. 5C) is allocated to the logical address corresponding to the NVMe command allocation, and then one or more storage commands are obtained according to the NVMe command, where the storage commands carry the logical address and the physical address or the specific mark corresponding thereto; then, generating a DMA command (i.e., (3) "in fig. 5C) according to the storage command, where the DMA command carries a memory address of the storage device and a memory address of the host, and if the storage command carries a specific tag, then the DMA command also carries the specific tag; finally, if the DMA command also carries the specific tag, the specific data is generated and moved to the host memory according to the memory address of the storage device and the memory address of the host (as shown in "(4 a)" in fig. 5C), and if the DMA command does not carry the specific tag, the data is moved from the memory of the storage device to the host memory according to the memory address of the storage device and the memory address of the host.

By way of example, the above step 503 may further include sending a notification that the specific data has been read out in response to generating the specific data. The storage command processing unit 1043 in fig. 1B may send a notification that specific data has been read out to the host command processing unit 1042.

In other embodiments, if the second information of the DMA command is a memory address of the storage device, data is read from the NVM to the memory of the storage device according to the physical address corresponding to the logical address carried by the storage command corresponding to the DMA command and the memory address of the storage device, which are obtained through the FTL table. If the second information of the DMA command is a memory address of the storage device, but not the second specific identifier, then the data indicated by the DMA command is non-specific data. Therefore, in the method for writing data to a storage device according to the above embodiment of the present application, the storage command processing unit 1045 may allocate an available physical address for the non-specific data, and read data from the NVM105 to the DRAM110 according to the mapping relationship between the storage device memory address and the allocated physical address recorded in the FTL table in the storage medium management unit 1043.

In still other embodiments, if the physical address corresponding to the logical address carried by the storage command is obtained through the FTL table, the data is read from the NVM according to the physical address, and the data read from the NVM is written into the memory of the storage device according to the memory address of the storage device carried by the DMA command corresponding to the storage command. The physical address here may be a physical address available by the storage command processing unit 1045 in the method for writing data of the storage device according to the above-described embodiment of the present application, and records a mapping relationship between the physical address and a memory address of the storage device in the FTL table in the storage medium management unit 1043.

In other embodiments, if the first specific identifier corresponding to the logical address carried by the storage command is obtained through the FTL table, the second specific identifier is recorded in the DMA command corresponding to the storage command, and data is not read from the NVM. The first specific flag here may be, in the method for writing data to the storage device according to the foregoing embodiment of the present application, the storage medium management unit 1043 records, in the FTL table according to a detection result of the data corresponding to the write command (that is, the data corresponding to the write command is the specific data), a specific flag corresponding to the logical address corresponding to the specific data (for example, in the FTL table in fig. 3C, the specific flag "all 0" corresponding to the logical address LA 3). If the first specific identifier corresponding to the logical address of the storage command is obtained in the FTL table, the second specific identifier can be recorded in the DMA command corresponding to the storage command to perform step 503 without or without reading data from the NVM 105.

In still other embodiments, the method for reading data of a memory device further includes: in response to detecting the read command, enabling transmission of the generated specific data to the host according to a third switching signal; and stopping sending the generated specific data to the host according to the fourth switching signal in response to detecting that the read command is completely executed. The host command processing unit 1042 in fig. 1B may determine whether to send the generated specific data to the host according to the read command, and if the host command processing unit 1042 detects the read command, generate an enable signal (i.e. the aforementioned "third switch signal") to enable sending the generated specific data to the host; if the host command processing unit 1042 detects that the read command is completely executed, it generates a close signal (i.e. the above-mentioned "fourth switch signal") to send the generated specific data to the host.

In other embodiments, the method for reading data of a memory device further includes: the step of generating the specific data and the step of performing AES decryption and/or PI signature on the specific data are processed simultaneously.

According to steps 501-503, in the method for reading data of a storage device according to the embodiment of the present application, in the process of controlling a host to read data from an NVM of the storage device, specific data is generated according to a specific identifier carried by a DMA command corresponding to a read command, and the specific data is sent to the host according to the DMA command. According to the scheme of the application, when the data indicated by the DMA is the special data, the special data does not need to be read from the NVM, so that the time for reading the data from the NVM is saved, and the data reading efficiency can be improved. The specific hardware circuitry that implements the read command processing described above will be further described below.

Fig. 6 is a circuit diagram illustrating a method for reading data of a memory device according to an embodiment of the present application. As shown in FIG. 6, the host transmits a read command to the storage device through the host interface, which transmits the read command to the shared memory for storage. Storage command processing unit 1043 extracts the PRP/SGL field in the read command and provides the read command to the SGL/PRP unit. Taking the processing process of the SGL unit as an example (the processing process of the PRP unit is the same, so the processing process of the PRP unit is not described any more), if the read command carries the SGL, caching the SGL in a cache unit, and if the read command carries the SGL pointer, acquiring the SGL from the host through the host interface and caching the SGL in the cache unit; and then, generating one or more DMA command groups according to the information described by the one or more SGL descriptors in the SGL, and storing the DMA command groups in the shared memory. In this embodiment, if the storage command processing unit 1043 acquires, through the FTL table, the physical address (i.e., (1) "in fig. 6) corresponding to the logical address carried in the storage command corresponding to the read command, the storage command processing unit 1043 may send the read command (i.e., (2)" in fig. 6) to the media interface controller 1044, and the media interface controller 1044 accesses the physical address (i.e., (3) "in fig. 6) of the NVM105 according to the read command and stores the read data in the DRAM110 in fig. 1C. Thereafter, the storage command processing unit 1043 may issue a notification to the read initiate circuit that the data has been read (i.e., (4) "in fig. 6). In this embodiment, if the storage command processing unit 1043 acquires, through the FTL table, that the logical address carried by the storage command corresponding to the read command corresponds to the first specific identifier (i.e., (1) "in fig. 6), the storage command processing unit 1043 does not need to send the read command to the media interface controller 1044 (i.e., (2)" step does not execute in fig. 6), and the media interface controller 1044 does not need to access the physical address of the NVM105 according to the read command (i.e., (3) "step does not execute in fig. 6). The storage command processing unit 1043 may issue a notification to the read initiate circuit that the data has been read (i.e., (4) "in fig. 6).

Fig. 7 shows a circuit structure diagram of a DMA engine according to an embodiment of the present application. The DMA engine 400 includes: a first data transfer unit 401, a data protection and monitoring circuit 402, and a second data transfer unit 403. The first data moving unit 401 is configured to obtain data to be moved from the local memory according to the DMA command and provide the data to the data protection and monitoring circuit 402, if the DMA command indicates the flag, the first data moving unit 401 generates the data to be moved, the data protection and monitoring circuit 402 decrypts and/or performs data verification on the received data to be moved, and provides the result data to the second data moving unit 403. The second data transfer unit 403 transfers the result data to an external memory according to the DMA command. In this embodiment, if the second information carried by the DMA command acquired by the DMA engine 400 is a memory address of the storage device (i.e., (1) "in fig. 7), the first data moving unit 401 in the DMA engine 400 acquires data to be moved from the DRAM110 according to the DMA command (i.e., (2)" in fig. 7), and the first data moving unit 401 may provide the acquired data to be moved to the data protection and monitoring circuit 402 for data decryption and/or integrity check (i.e., (3) "in fig. 7). The data protection and monitoring circuit 402 may provide the decrypted and/or data-checked result data to the second data moving unit 403 (i.e., (4) "in fig. 7), and the second data moving unit 403 moves the result data to the host through the host interface 1041 according to the DMA command (i.e., (5)" in fig. 7).

In this embodiment, if the second information carried by the DMA command acquired by the DMA engine 400 is a second specific identifier (shown by "(1)" in fig. 7) referring to specific data, the first data moving unit 401 generates the specific data and provides the generated specific data to the data protection and monitoring circuit 402 for data decryption and/or integrity check (shown by "(3)" in fig. 7). The data protection and monitoring circuit 402 may provide the decrypted and/or data-checked result data to the second data moving unit 403 (i.e., (4) "in fig. 7), and the second data moving unit 403 moves the result data to the host through the host interface 1041 according to the DMA command (i.e., (5)" in fig. 7).

In other embodiments, the DMA engine according to embodiments of the present application further includes a second switch circuit 704, the second switch circuit 704 configured to: enabling transmission of the generated specific data to the host according to a third switching signal in response to detection of the read command; and stopping sending the generated specific data to the host according to the fourth switching signal in response to detecting that the read command is completely executed. The host command processing unit 1042 in fig. 1B may determine whether to send the generated specific data to the host according to the read command, and if the host command processing unit 1042 detects the read command, generate an enable signal (i.e. the aforementioned "third switch signal") to enable sending the generated specific data to the host; if the host command processing unit 1042 detects that the read command is completely executed, it generates a close signal (i.e. the above-mentioned "fourth switch signal") to send the generated specific data to the host.

According to an aspect of the present application, the embodiment of the present application further provides a controller, which includes the memory controller, the DMA engine 400, and the memory device as described above. The memory controller, the DMA engine 400, and the memory device employ the circuits described in the above embodiments, which are not described in detail since they have been described in detail above.

According to an aspect of the present application, an electronic device is further provided, where the electronic device includes a controller, and the controller is the controller mentioned in the above embodiments. Since it has been described in detail above, it will not be described in detail.

It is noted that for the sake of brevity, this application describes some methods and embodiments thereof as a series of acts and combinations thereof, but those skilled in the art will appreciate that the aspects of the application are not limited by the order of the acts described. Accordingly, one of ordinary skill in the art will appreciate that certain steps may be performed in other sequences or simultaneously, in accordance with the disclosure or teachings herein. Further, those skilled in the art will appreciate that the embodiments described herein are capable of alternative embodiments, i.e., acts or modules referred to herein are not necessarily required for the implementation of the solution or solutions described herein. In addition, the description of some embodiments of the present application is also focused on different schemes. In view of the above, those skilled in the art will understand that portions that are not described in detail in one embodiment of the present application may also be referred to in the related description of other embodiments.

In particular implementation, based on the disclosure and teachings of the present application, one of ordinary skill in the art will appreciate that the several embodiments disclosed in the present application may be implemented in other ways not disclosed herein. For example, as for the units in the foregoing embodiments of the electronic device or apparatus, the units are split based on the logic function, and there may be another splitting manner in the actual implementation. Also for example, multiple units or components may be combined or integrated with another system or some features or functions in a unit or component may be selectively disabled. The connections discussed above in connection with the figures may be direct or indirect couplings between the units or components in terms of connectivity between the different units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection utilizing an interface, where the communication interface may support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.