阅读说明：本技术 数据储存装置与数据处理方法 (Data storage device and data processing method ) 是由 邱慎廷 于 2020-06-16 设计创作，主要内容包括：本发明涉及一种存储器控制器,其耦接一存储器装置与一主机装置,用以控制存储器装置的存取操作,包括一缓冲存储器、一主机接口、一微处理器以及一数据保护引擎。主机接口耦接主机装置,用以将自主机装置接收的数据写入缓冲存储器,并且于数据被写入缓冲存储器后,发出一缓冲存储器写入完成通知。微处理器响应于缓冲存储器写入完成通知触发一数据保护操作。数据保护引擎用以根据储存于缓冲存储器的数据执行数据保护操作以产生对应的保护资讯。微处理器于确认数据被写入缓冲存储器后直接触发数据保护操作。(The invention relates to a memory controller, which is coupled with a memory device and a host device and is used for controlling the access operation of the memory device. The host interface is coupled to the host device and used for writing the data received from the host device into the buffer memory and sending a buffer memory writing completion notice after the data is written into the buffer memory. The microprocessor triggers a data protection operation in response to the buffer write completion notification. The data protection engine is used for executing data protection operation according to the data stored in the buffer memory so as to generate corresponding protection information. The microprocessor directly triggers the data protection operation after confirming that the data is written into the buffer memory.)

1. A memory controller, coupled to a memory device and a host device, for controlling access operations of the memory device, comprising:

a buffer memory;

a host interface, coupled to the host device, for writing data received from the host device into the buffer memory, and sending a buffer memory write completion notification after the data is written into the buffer memory;

A microprocessor, responding to the buffer memory write-in completion notice to trigger a data protection operation; and

a data protection engine for executing the data protection operation according to the data stored in the buffer memory to generate corresponding protection information,

wherein the microprocessor directly triggers the data protection operation after confirming that the data is written into the buffer memory.

2. The memory controller as recited in claim 1, wherein the data received from the host device comprises a plurality of portions, and the microprocessor directly drives the data protection engine to perform the corresponding data protection operation on the portions after confirming that the portions are written into the buffer memory.

3. The memory controller of claim 1, further comprising:

a memory interface coupled to the memory device,

the microprocessor also drives the memory interface to execute a data write operation in response to the buffer memory write completion notification, and the memory interface writes the data stored in the buffer memory into the memory device in response to the data write operation.

4. The memory controller as recited in claim 3 wherein said microprocessor concurrently drives said data protection engine to perform said data protection operation and said memory interface to perform said data write operation in response to said buffer write completion notification.

5. The memory controller of claim 3, wherein an execution time of the data protection operation corresponding to the data overlaps an execution time of the data write operation corresponding to the data.

6. The memory controller as recited in claim 3, wherein the microprocessor drives the data protection engine to perform the data protection operation corresponding to the data before the data write operation corresponding to the data is completed.

7. The memory controller of claim 3, wherein the microprocessor further determines whether the data protection engine needs to exclude a portion of the data when generating the protection information corresponding to the data according to the data writing operation corresponding to the data, and instructs the data protection engine to remove the relevant content of the portion of the data from the protection information when the microprocessor determines that the portion of the data needs to be excluded when generating the protection information corresponding to the data.

8. A data processing method performed by a memory controller coupled to a memory device, comprising:

writing data received from a host device into a buffer memory of the memory controller; and

And directly executing a data protection operation after the data is written into the buffer memory so as to generate corresponding protection information according to the data stored in the buffer memory.

9. The data processing method as claimed in claim 8, wherein the data received from the host device comprises a plurality of portions, and a data protection engine of the memory controller is driven to perform the corresponding data protection operation on the portions directly after the portions are written into the buffer memory.

10. The data processing method of claim 8, further comprising:

and executing a data writing operation after the data is written into the buffer memory, so as to write the data stored in the buffer memory into the memory device.

11. The data processing method of claim 10, wherein the data protection operation corresponding to the data is performed concurrently with the data write operation corresponding to the data.

12. The data processing method as claimed in claim 10, wherein the execution time of the data protection operation corresponding to the data overlaps with the execution time of the data write operation corresponding to the data.

13. The data processing method of claim 10, wherein the data protection operation corresponding to the data is performed before the data write operation corresponding to the data is completed.

14. The data processing method of claim 10, further comprising:

determining whether a portion of the data is to be excluded when the protection information corresponding to the data is generated according to the data write operation corresponding to the data; and

when it is determined that a portion of the data is to be excluded when the protection information corresponding to the data is generated, a data exclusion operation is performed to remove the relevant content of the portion from the protection information.

Technical Field

The present invention relates to a data processing method, and more particularly, to a data processing method capable of effectively protecting data stored in a memory device.

Background

As the technology of data Storage devices has rapidly grown in recent years, many data Storage devices, such as Memory cards conforming to the Secure Digital (SD) format, the multimedia Card (MMC) format, the Compact Flash (CF) format, the Memory Stick (MS) format and the Extreme Digital (XD) format, solid state Memory (ssd), embedded multimedia Memory (eMMC) Card, and Universal Flash Storage (UFS) have been widely used for various purposes. Therefore, efficient access control also becomes an important issue in these data storage devices.

In order to improve the access performance of the data storage device and protect the data stored in the memory device, the invention provides a novel data processing method, which can effectively protect the data stored in the memory device and avoid reducing the access performance of the data storage device due to the implementation of an error protection mechanism.

Disclosure of Invention

An objective of the present invention is to effectively protect data stored in a memory device and to prevent the access performance of the data storage device from being degraded due to the implementation of an error protection mechanism.

According to an embodiment of the present invention, a memory controller, coupled to a memory device and a host device, for controlling access operations of the memory device includes a buffer memory, a host interface, a microprocessor, and a data protection engine. The host interface is coupled to the host device and used for writing the data received from the host device into the buffer memory and sending a buffer memory writing completion notice after the data is written into the buffer memory. The microprocessor triggers a data protection operation in response to the buffer write completion notification. The data protection engine is used for executing data protection operation according to the data stored in the buffer memory so as to generate corresponding protection information. The microprocessor directly triggers the data protection operation after confirming that the data is written into the buffer memory.

According to another embodiment of the present invention, a data processing method performed by a memory controller coupled to a memory device comprises: writing data received from a host device into a buffer memory of the memory controller; and directly executing a data protection operation after the data is written into the buffer memory, so as to generate corresponding protection information according to the data stored in the buffer memory.

Drawings

Fig. 1 is a schematic diagram illustrating a data storage device 100 according to an embodiment of the invention.

Fig. 2 is a flowchart illustrating a data processing method according to an embodiment of the invention.

FIG. 3 is a diagram illustrating an example of a task schedule of a memory controller according to an embodiment of the present invention.

Description of the symbols

100 data storage device

110 memory controller

112 microprocessor

112C program code

112M read-only memory

114 memory interface

116 buffer memory

115 data protection engine

118 host interface

120 memory device

130 host device

132 encoder

134 decoder

136 voltage detection circuit

310,320, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 and data

315 protecting information

Detailed Description

In the following description, numerous specific details are described to provide a thorough understanding of embodiments of the invention. However, those skilled in the art will understand how to implement the invention without one or more of the specific details or depending on other methods, components or materials. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

Reference throughout this specification to "one embodiment," "an example" or "an example" means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment," "in an example" or "in an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples.

In order to make the objects, features and advantages of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below. For the purposes of illustrating the spirit of the present invention and not for limiting the scope of the present invention, it is to be understood that the following embodiments may be implemented via software, hardware, firmware, or any combination thereof.

Fig. 1 is a schematic diagram illustrating a data storage device 100 according to an embodiment of the invention. The data storage device 100 includes a Memory device 120, such as a Flash Memory (Flash Memory) module, and a Memory controller 110. The memory controller 110 is used to Access (Access) the memory device 120. According to an embodiment of the present invention, the Memory controller 110 includes a microprocessor 112, a Read Only Memory (ROM) 112M, a Memory interface 114, a data protection engine 115, a buffer Memory 116, and a host interface 118. The rom 112M is used to store a program code 112C, and the program code 112C may include one or more program modules, such as boot loader (boot loader) code, and the microprocessor 112C executes the program code 112C to perform an initialization operation to load an In-System Programming (ISP) program (not shown) from the memory device 120 when the host device 130 supplies power to the data storage device 100. The microprocessor 112 can execute the ISP code to provide the data storage device 100 with various functions. According to the present embodiment, the ISP group code may include, but is not limited to, a plurality of program modules related to access (e.g., read, write and erase), such as a read operation module, a lookup table module, a wear leveling (wear leveling) module, a read refresh (read refresh) module, a read recovery (read recover) module, a garbage collection (garbage collection) module, a sudden power recovery (SPOR) module, and an Uncorrectable Error Correction Code (UECC) module, for performing read, lookup table, wear leveling, read refresh, read recovery, garbage collection, sudden power recovery and error handling for UECC errors, respectively. The memory interface 114 includes an encoder 132, a decoder 134, and a voltage detection circuit 136. The encoder 132 is used for encoding data written into the memory device 120 to generate a corresponding check Code (or Error Correction Code (ECC)). The decoder 134 is used to decode data read out of the memory device 120. The voltage detection circuit 136 is used for detecting a voltage level of the memory device 120, such as a level of the power voltage, and generating a corresponding detection result. The microprocessor 112 can determine whether a power supply voltage variation (e.g., unstable power supply voltage) occurs in the memory device 120, or an unexpected or Sudden Power Off (SPO) occurs, etc. according to the detection result. The data protection engine 115 is configured to generate corresponding protection information according to data received from the host device 130, and to recover damaged or missing data according to the protection information, wherein the protection information may be encoded information generated according to the data to be protected, such as parity information. When a portion of data protected by a given protection information is damaged or lost, the data protection engine 115 may perform a corresponding decoding operation according to the given protection information and the remaining portion of data protected thereby to derive the damaged or lost portion.

Typically, the memory device 120 comprises a plurality of flash memory chips or dies, each of which comprises a plurality of memory blocks (blocks), and the erase data operation of the memory device 120 by the memory controller 110 is performed in units of blocks. In addition, a memory block can record (include) a specific number of pages (pages), i.e. physical pages, wherein the operation of writing data to the memory device 120 by the memory controller 110 is performed in units of pages.

In practice, the memory controller 110 may utilize its internal components to perform various control operations, such as: the memory interface 114 is used to control the access operations of the memory Device 120 (especially, the access operations of at least one block or at least one data page), the buffer memory 116 is used to perform the required buffering, and the Host interface 118 is used to communicate with a Host Device (Host Device) 130. The host interface 118 can also be regarded as a front-end controller engine for transmitting communication signals between the memory controller 110 and the host device 130, transmitting data written/read by the host device 130, and controlling the task schedule of reading/writing data. The memory interface 114 can also be considered as a back-end controller engine for communicating communication signals between the memory controller 110 and the memory device 120, communicating data to be written/read from the memory device 120, performing corresponding encoding operations via the encoder 132 before writing data into the memory device 120, and performing corresponding decoding operations on data via the decoder 134 after reading data from the memory device 120.

In one embodiment, the memory controller 110 communicates with the host device 130 via the host interface 118 using a standard communication protocol. For example, the standard communication protocols include (but are not limited to): universal Serial Bus (abbreviated USB) standard, Secure Digital (SD) interface standard, Ultra High Speed-I (abbreviated UHS-I) interface standard, Ultra High Speed-II (abbreviated UHS-II) interface standard, Compact Flash (abbreviated CF) interface standard, Multimedia Card (abbreviated MMC) interface standard, Embedded Multimedia Card (abbreviated mc) interface standard, Universal Flash Storage (abbreviated UFS) interface standard, Advanced Technology Attachment (abbreviated ATA) standard, Serial ATA (abbreviated Serial ATA), Peripheral Component Interconnect (SATA) standard, Peripheral Component Interconnect (PCI-abbreviated PCI) standard, and the like, Parallel Advanced Technology Attachment (abbreviated as PATA) standard.

In one embodiment, the buffer Memory 116 is implemented as a Random Access Memory (RAM). For example, the buffer memory 116 may be a Static random access memory (Static RAM, abbreviated as SRAM), but the invention is not limited thereto. In other embodiments, the buffer memory 116 may be a Dynamic Random Access Memory (DRAM).

In one embodiment, the data storage device 100 may be a portable memory device (e.g., a memory card conforming to SD/MMC, CF, MS, XD, UFS standards), and the host device 130 is an electronic device connectable to the data storage device, such as a mobile phone, a notebook computer, a desktop computer …, or the like. In another embodiment, the data storage device 100 may be a solid state drive or embedded storage device of UFS or eMMC specification, which is installed in an electronic device, such as a mobile phone, a notebook computer, or a desktop computer, and the host device 130 may be a processor of the electronic device.

The host device 130 can issue commands, such as read commands or write commands, to the data storage device 100 to access data stored in the memory device 120, or further control and manage the data storage device 100.

According to an embodiment of the present invention, the plurality of memory blocks included in the memory device 120 may include Single-Level Cell (SLC) memory blocks, multi-Level Cell (MLC) memory blocks, and/or Triple-Level Cell (TLC) memory blocks. One bit of data is stored in each memory cell of the SLC memory block, two bit of data is stored in each memory cell of the MLC memory block, and three bit of data is stored in each memory cell of the TLC memory block. According to an embodiment of the present invention, the memory device 120 is a stereo NAND type flash memory (3D NAND-type flash).

Generally, to protect a memory device from valid data loss due to the damage of a memory unit, the memory device may use an error protection mechanism adopted in a Redundant Array of Independent Disks (RAID) technology for data protection. In the error protection scheme employed by RAID, the memory controller may calculate protection information based on data written to the memory devices. When the loss of the valid data is found, the protection information can be used to reversely derive the content of the lost valid data.

However, in some cases, memory cell corruption or data corruption has occurred as data is written to the memory device. A damaged memory cell may cause an error in the data it stores. For example, a damaged memory cell may not be able to maintain a fixed voltage level, and thus, the memory controller 110 may obtain a different value each time data stored in the damaged memory cell is read. Therefore, the lost effective data content cannot be deduced reversely by using the data.

Therefore, to ensure that protection information is generated based on uncorrupted data (i.e., correct data), the memory controller's task schedule is typically designed to begin calculating corresponding protection information based on correct data written to the memory device after determining that the data has been successfully written to the memory device and that the data is not erroneous or corrupted, or that information about correct data is known.

However, the above task schedule significantly compromises the write efficiency of the memory device 120. For example, the buffer memory 116 must hold the data received from the host device 130 until the data protection engine 115 generates protection information corresponding to the data. Therefore, after the data protection engine 115 generates the protection information, the corresponding storage space of the buffer memory 116 can be cleared and reused for storing the data written by the next host device 130. Therefore, the space utilization of the buffer memory 116 and the writing efficiency of the memory device 120 cannot be improved.

To solve the above problems, the present invention provides a novel data processing method, which can effectively protect the data stored in the memory device, and can greatly improve the space utilization of the buffer memory 116 and the writing efficiency of the memory device 120 by means of a novel task schedule.

Fig. 2 is a flowchart illustrating a data processing method according to an embodiment of the invention. The data processing method of the present invention may be executed by the memory controller 110 or one or more components included in the memory controller, and includes the following steps:

in step S202, the host device 130 receives data and writes (or temporarily stores) the data in the buffer memory 116.

In step S204, after the data is written into the buffer memory 116, the driving data protection engine 115 performs a data protection operation corresponding to the data, and the driving memory interface 114 performs a data writing operation corresponding to the data.

Step S206, determining whether to exclude a portion of the data when generating the protection information corresponding to the data according to the information related to the data writing operation corresponding to the data. If yes, go to step S208. If not, go to step S210.

In step S208, the related content of the portion of the data is removed from the protection information to regenerate the protection information, and the regenerated protection information is written into the memory device 120.

In step S210, the protection information is written into the memory device 120.

According to an embodiment of the present invention, the host interface 118 is used to write the data received from the host device 130 into the buffer memory 116, and after the data is written into the buffer memory 116, the host interface 118 issues a buffer memory write completion notification to notify the microprocessor 112 that the data has been written into the buffer memory 116.

In response to receiving the buffer write completion notification from the host interface 118, the microprocessor 112 can drive the data protection engine 115 to perform a corresponding data protection operation on the data, so as to generate corresponding protection information according to the data stored in the buffer 116.

According to an embodiment of the present invention, the microprocessor 112 can know that the data has been written into the buffer memory 116 by the buffer memory write completion notification, and can directly trigger the data protection operation after the microprocessor 112 confirms that the data has been written into the buffer memory 116. In other words, the memory controller can directly perform a corresponding data protection operation after the data is written into the buffer memory 116, so as to generate corresponding protection information according to the data stored in the buffer memory 116. According to an embodiment of the present invention, the direct execution of the corresponding protection operation means that the data protection engine 115 starts to execute the data protection operation before the data stored in the buffer memory 116 is written into the memory device 120.

In addition, in response to receiving the buffer write completion notification from the host interface 118, the microprocessor 112 can also drive the memory interface 114 to perform a data write operation corresponding to the data, so as to write the data stored in the buffer 116 into the memory device 120.

According to an embodiment of the present invention, in response to the buffer write completion notification, the microprocessor 112 can simultaneously or nearly simultaneously drive the data protection engine 115 to perform the data protection operation corresponding to the data and drive the memory interface 114 to perform the data write operation corresponding to the data. For example, the microprocessor 112 may issue corresponding instructions at the same time to drive the data protection engine 115 and the memory interface 114 to perform the corresponding operations. Alternatively, the microprocessor 112 may issue the corresponding instructions at different time points with very small time difference, and the time difference between the instructions issued by the microprocessor 112 for driving the data protection engine 115 and the memory interface 114 to perform the corresponding operations may be smaller than a predetermined value or smaller than a predetermined number of clock pulses. The instruction for triggering the data protection operation may be earlier or later than the instruction for triggering the data write operation.

In addition, in an embodiment of the present invention, the microprocessor 112 may drive the data protection engine 115 to execute the data protection operation corresponding to the data before the data writing operation corresponding to the data is completed. In another embodiment of the present invention, the microprocessor 112 may drive the memory interface 114 to perform the data writing operation corresponding to the data before the data protection operation corresponding to the data is completed.

It is noted that, in other embodiments of the present invention, the microprocessor 112 may issue corresponding instructions at different time points with significant time differences to drive the data protection engine 115 and the memory interface 114 to perform the corresponding operations.

In addition, according to an embodiment of the present invention, the execution time of the data protection operation performed by the data protection engine 115 for one data set overlaps with the execution time of the data write operation performed by the memory interface 114 for the same data set. Therefore, the time for the buffer memory 116 to retain the data can be effectively shortened.

FIG. 3 is a diagram illustrating an example of a task schedule of a memory controller according to an embodiment of the invention, wherein the horizontal axis is the time axis. In this example, the host device 130 is going to write two data (host data) into the memory device 120, the data 310 written into the buffer memory 116 is the first data, and the data 320 written into the buffer memory 116 is the second data, wherein each data includes a plurality of portions, such as the data D [0] D [7] and D [8] D [15] (shown in the first row). Wherein a portion of data may comprise, for example, a page of data or a predetermined number of pages of data.

In addition, in this example, memory device 120 may include eight memory dies, and memory interface 114 may include two transmission channels CH 0 and CH 1, each coupled to four memory dies for transmitting data from the four memory dies. Thus, the data processing operations of memory dies Die [0] Die [3] coupled to channel CH [0] and the data processing operations of memory dies Die [0] Die [3] coupled to channel CH [1] are shown. In a multi-die and multi-channel architecture, the microprocessor 112 may write data to the memory device 120 in parallel through multiple channels by appropriate scheduling, so that data write operations may be more efficient.

In the example shown in fig. 3, the length of the data (i.e., the length of the box) distributed on the time axis can indicate the relative time required to process the data. Wherein the first column of the figure may represent the operation of host data being written into buffer memory 116. The second through ninth columns may represent operations in which host data written into buffer memory 116 is transferred to memory device 120 through channel CH [0] or CH [1] and written into a corresponding memory die. The last row of the diagram may represent the operation of the data protection engine 115 to generate protection information based on host data.

As shown, taking the second row of operations as an example, the box labeled data D [0] represents the operation of channel CH [0] transmitting data D [0], while the line filled with diagonal lines represents the busy state of the memory. During the process of writing or programming (program) the data D [0] into the corresponding memory grain Die [0], the memory status is busy, and therefore, a busy flag is raised to indicate the busy status of the memory. After the programming is finished, the corresponding busy flag can be reset, which represents the non-busy state of the memory.

In addition, the last row of the figure shows that the data protection engine 115 sequentially reads the data written into the buffer memory 116 and generates the corresponding protection information, for example, the data protection engine 115 may generate the protection information 315 corresponding to the first data 310 and the protection information corresponding to the second data 320 (not shown in the figure due to the font restriction).

According to an embodiment of the present invention, for the same data, the microprocessor 112 can simultaneously or nearly simultaneously drive the data protection engine 115 to perform the data protection operation corresponding to the data and drive the memory interface 114 to perform the data write operation corresponding to the data. In addition, for the same data stored in the buffer memory 116, the execution time of the data protection operation and the data write operation corresponding to the data overlaps.

In addition, as described above, the data received from the host device 130 may include a plurality of portions, such as the data D [0] to D [7] and D [8] to D [15] shown in the figure, and after the microprocessor 112 confirms that each portion is written into the buffer memory 116 (for example, according to a buffer memory write completion notification confirmation corresponding to each portion), the microprocessor may directly drive the data protection engine 115 to perform a corresponding data protection operation on the portion. For example, as indicated by the vertical broken lines in FIG. 3, immediately after the data D [0] to D [7] and D [8] to D [15] are written into the buffer memory 116, the data write operation and the data protection operation corresponding to each data start to be executed.

For a data, such as data 310, in the embodiment of the present invention, after the data writing operation for writing data 310 into memory device 120 is completed, the corresponding storage space of buffer memory 116 for storing data 310 can be released and reused for storing the data written by the next host device 130. This is because the data protection engine 115 typically performs data protection operations faster than the memory interface 114 performs data write operations on the same piece of data.

Therefore, the data write operation and the data protection operation corresponding to the next data are immediately started to be executed after the busy state of the memory is finished, and the data protection operation does not need to wait for the data write operation to be finished due to the staggered (non-overlapped) execution time of the data write operation and the data protection operation, and can be started to be executed after the busy state of the memory is finished. In addition, in the prior art, after the later data protection operation is completed, the corresponding storage space of the buffer memory 116 is released so that the buffer memory 116 can receive the data written by the next host device 130. Thereby significantly compromising the space utilization of the buffer memory 116 and the writing efficiency of the memory device 120.

Unlike the previous designs, the space utilization of the buffer memory 116 and the write efficiency of the memory device 120 are greatly improved by the novel data processing method provided by the present invention, which utilizes the aforementioned task schedule.

Since the data protection operation is performed in advance when it is not confirmed that the data has been successfully written into the memory device 120, in the embodiment of the invention, as shown in step S206, the microprocessor 112 can further determine whether the data protection engine 115 needs to exclude a portion of the data when generating the protection information corresponding to the data according to the information related to the data writing operation corresponding to each data.

If the microprocessor 112 determines in step S206 that a portion (e.g., one or more data pages) of the data needs to be excluded, the data protection engine 115 may be further instructed to perform a corresponding data exclusion operation for removing the relevant content of the portion from the protection information, which is equivalent to the data protection engine 115 generating corresponding protection information according to other portions of the data that do not include the portion. Alternatively, the microprocessor 112 instructs the data protection engine 115 to exclude the portion and then regenerate the corresponding protection information, i.e., the data protection engine 115 may regenerate the corresponding protection information according to other portions of the data that do not include the portion. All of the above operations can be regarded as regenerating protection information, and the generated protection information can be regarded as regenerating protection information.

In embodiments of the present invention, the data exclusion operation may be a reverse operation that generates the protection information. For example, when the data protection engine 115 generates protection information by performing an exclusive-or (XOR) operation, the data exclusion operation may be a reverse XOR operation. It should be noted that the data protection engine 115 may also generate the protection information by performing other operations, and thus, the present invention is not limited to generating the protection information using exclusive-or (XOR) operations.

In addition, in the embodiment of the present invention, the information related to the data writing operation may include a state of the memory device 120 and/or a state of data written into the memory device 120.

For example, the microprocessor 112 may detect a status message returned by the memory device 120 after the write operation is performed, so as to know whether the write operation is successful or failed. The microprocessor 112 may actively query the status of the memory device 120 and wait for the memory device 120 to return a status message. When the status message indicates that the write operation of a portion of the data failed, the microprocessor 112 may determine that the data protection engine 115 needs to exclude the portion when generating the protection information corresponding to the data, and instruct the data protection engine 115 to exclude the relevant content of the portion to regenerate the protection information.

For another example, the voltage detection circuit 136 may send a message to notify the microprocessor 112 when a power supply voltage change (e.g., a voltage drop, a voltage instability, or a power off of the memory device) of the memory device is detected, so that the microprocessor 112 can know the status of the memory device 120 in performing the write operation. When the status indicates that the power voltage of the memory device 120 has changed during the write operation corresponding to a certain portion of the data, the microprocessor 120 may determine that the data protection engine 115 should exclude the portion when generating the protection information corresponding to the data, and instruct the data protection engine 115 to exclude the relevant content of the portion to regenerate the protection information, because the unstable voltage may cause the write data to be erroneous or the data cannot be written.

For example, the microprocessor 120 may also determine the status of the memory device 120 performing the write operation according to the status of the data storage device 100. If the data storage device 100 is suddenly powered down during the write operation of the memory device 120, it is also the case that the memory device 120 is suddenly powered down. Since a sudden power failure may damage the data being written, when the status indicates that a sudden power failure occurs in the memory device 120 during the write operation corresponding to a certain portion of the data, the microprocessor 120 may determine that the data protection engine 115 needs to exclude the portion when generating the protection information corresponding to the data, and instruct the data protection engine 115 to exclude the relevant content of the portion to regenerate the protection information.

According to another embodiment of the present invention, the microprocessor 112 can read the data written into the memory device 120 and attempt to decode the contents thereof through the decoder 134 to know whether a data error occurs (e.g., the decoder 134 cannot correct the erroneous contents due to too many error bits). When the status of the data written into the memory device 120 indicates that a portion of the data has been corrupted or contains uncorrectable errors, the microprocessor 120 may determine that the data protection engine 115 is to exclude the portion when generating the protection information corresponding to the data, and instruct the data protection engine 115 to exclude the relevant content of the portion to regenerate the protection information.

In summary, in the novel data processing method provided by the present invention, the execution time of the data protection operation and the execution time of the data write operation corresponding to the same data are overlapped by using the work schedule, and the execution of the data protection operation and the execution of the data write operation can be started at the same time or at approximately the same time. Alternatively, the data protection operation may begin earlier than the data write operation is completed. Since the data protection operation can be performed in advance and the protection information can be adjusted according to the information related to the data write operation after being generated, the space utilization of the buffer memory 116 and the write efficiency of the memory device 120 can be greatly improved compared to the prior art.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.