阅读说明：本技术 一种时钟树布局方法、装置、电子设备及存储介质 (Clock tree layout method and device, electronic equipment and storage medium ) 是由 陈韬 于 2021-08-04 设计创作，主要内容包括：本申请提供了一种时钟树布局方法、装置、电子设备及存储介质,涉及时钟树技术领域。首先依据预设的tap单元的位置对tap单元进行分层连接,以形成时钟网络,然后按预设位置布置缓冲器,并通过缓冲器形成从时钟输入端口到时钟网络的连接,再删除未连接负载的tap单元,再删除部分或全部未连接tap单元的网络线段,最后确定每个tap单元的延时偏差,并在当延时偏差大于阈值时,重新删除未连接负载的tap单元与网络线段,直至tap单元的延时偏差小于或等于阈值,以完成时钟树布局。本申请提供的时钟树布局方法、装置、电子设备及存储介质具有缩短了时钟网络线长,降低了线间电容以及降低了时钟功耗的优点。(The application provides a clock tree layout method and device, electronic equipment and a storage medium, and relates to the technical field of clock trees. Firstly, hierarchical connection is carried out on tap units according to the position of a preset tap unit to form a clock network, then a buffer is arranged according to the preset position, connection from a clock input port to the clock network is formed through the buffer, then the tap units which are not connected with loads are deleted, then part or all of network line segments which are not connected with the tap units are deleted, finally the delay deviation of each tap unit is determined, and when the delay deviation is larger than a threshold value, the tap units which are not connected with the loads and the network line segments are deleted again until the delay deviation of the tap units is smaller than or equal to the threshold value, so that the clock tree layout is completed. The clock tree layout method, the clock tree layout device, the electronic equipment and the storage medium have the advantages of shortening the length of a clock network line, reducing the capacitance between lines and reducing the power consumption of a clock.)

1. A method of clock tree layout, the method comprising:

carrying out layered connection on the tap units according to the preset positions of the tap units to form a clock network;

arranging buffers at preset positions and forming a connection from a clock input port to the clock network through the buffers;

deleting tap units of unconnected loads;

deleting part or all of the network line segments which are not connected with the tap units;

and determining the delay deviation of each tap unit, and when the delay deviation is larger than a threshold value, deleting the tap units which are not connected with the load and the network line segment again until the delay deviation of the tap units is smaller than or equal to the threshold value so as to complete the clock tree layout.

2. The clock tree layout method of claim 1, wherein the step of re-deleting tap cells and network segments not connected to a load when the delay skew is greater than a threshold value comprises:

when the delay deviation is larger than a threshold value, recovering at least one tap unit which is not connected with a load and a corresponding network line segment;

and re-determining the delay deviation of each tap unit, and when the delay deviation is greater than a threshold value, re-deleting the tap units which are not connected with the load and the network line segment until the delay deviation of the tap units is less than or equal to the threshold value.

3. The clock tree layout method of claim 1, wherein the step of re-deleting tap cells and network segments not connected to a load when the delay skew is greater than a threshold value comprises:

when the delay deviation is larger than a threshold value, determining a target area with the maximum delay deviation;

recovering a tap unit which is partially or completely not connected with a load in the target area;

and re-determining the delay deviation of each tap unit, and when the delay deviation is greater than a threshold value, re-deleting the tap units which are not connected with the load and the network line segment until the delay deviation of the tap units is less than or equal to the threshold value.

4. The clock tree layout method of claim 1, wherein the step of determining the delay skew of each tap cell comprises:

taking any tap unit as a target tap unit;

comparing the delay of a tap cell adjacent to the target tap cell with the delay of the target tap cell to determine a delay skew of each tap cell.

5. The clock tree layout method of claim 1, wherein the step of deleting some or all network segments not connected to a tap cell comprises:

and determining the network line segment to be deleted according to a preset layout rule and an antenna effect.

6. The clock tree layout method according to claim 1, wherein the step of hierarchically connecting the tap units according to the preset positions of the tap units comprises:

and utilizing metal wires to carry out layered connection on the tap units, wherein the layer number, the width and the spacing of the metal wires are related to the performance of the buffer and the resistance and the capacitance between the metal wires.

7. An apparatus for clock tree layout, the apparatus comprising:

the connection unit is used for carrying out layered connection on the tap units according to the preset positions of the tap units so as to form a clock network;

the connection unit is also used for arranging a buffer according to a preset position and forming connection from a clock input port to the clock network through the buffer;

a deleting unit configured to delete a tap unit to which a load is not connected;

the deleting unit is also used for deleting part or all of the network line segments which are not connected with the tap units;

and the deleting unit is also used for determining the delay deviation of each tap unit, and when the delay deviation is greater than a threshold value, deleting the tap units which are not connected with the load and the network line segment again until the delay deviation of the tap units is less than or equal to the threshold value so as to complete the layout of the clock tree.

8. The clock tree arrangement apparatus of claim 7, wherein the deleting unit is configured to recover at least one tap cell and a corresponding network line segment of an unconnected load when the delay offset is greater than a threshold; and re-determining the delay deviation of each tap unit, and when the delay deviation is greater than a threshold value, re-deleting the tap units which are not connected with the load and the network line segment until the delay deviation of the tap units is less than or equal to the threshold value.

9. An electronic device, comprising:

a memory for storing one or more programs;

a processor;

the one or more programs, when executed by the processor, implement the method of any of claims 1-6.

10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-6.

Technical Field

The present disclosure relates to the field of clock tree technologies, and in particular, to a clock tree layout method and apparatus, an electronic device, and a storage medium.

Background

The clock tree technology is one of high-speed clock tree realization technologies in the field of integrated circuit design, and can transmit clock signals in a large area range through a large driving unit and high-level metal wiring, reduce the number of integrated circuit devices on a clock main path, reduce line delay on the clock tree main path, and further reduce the total delay of the clock tree. In addition, the technology moves the branch point of the clock path backwards, thereby reducing On-Chip Variation (OCV) and being beneficial to improving the design performance.

In order to realize fast transmission of clock signals, a mesh clock tree structure generally adopts a large driving buffer and high-level metal wide lines. In the design module, tap units are placed in advance to be connected with the design module, and clock signals are transmitted through the tap points, so that timing convergence is facilitated, but a large amount of routing resources are occupied by a mesh clock structure. Because the design of the CPU and the GPU needs to support a high-frequency clock signal, and the whole power consumption, the voltage, the capacitance and the frequency of the chip are closely related, the reduction of the capacitance of the clock network becomes an effective means for low-power design. In terms of physical implementation, because high-level metal traces with high width are adopted, when the high-level metal traces are connected to a clock tap unit inside a module, a huge metal-to-device gate area ratio is formed, and thus antenna effect violation is caused. To fix the violation, the designer needs to insert a large number of redundant devices, further compressing the active area of the chip.

In summary, the mesh clock tree structure provided in the prior art has the problems of high power consumption, high resource occupation and physical design violation.

Disclosure of Invention

The present application aims to provide a clock tree layout method, device, electronic device, and storage medium, so as to solve the problems of high power consumption, high resource occupation, and physical design violation of a mesh clock tree structure in the prior art.

In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:

in a first aspect, an embodiment of the present application provides a clock tree layout method, where the method includes:

carrying out layered connection on the tap units according to the preset positions of the tap units to form a clock network;

arranging buffers at preset positions and forming a connection from a clock input port to the clock network through the buffers;

deleting tap units of unconnected loads;

deleting part or all of the network line segments which are not connected with the tap units;

and determining the delay deviation of each tap unit, and when the delay deviation is larger than a threshold value, deleting the tap units which are not connected with the load and the network line segment again until the delay deviation of the tap units is smaller than or equal to the threshold value so as to complete the clock tree layout.

Optionally, when the delay deviation is greater than a threshold, the step of deleting the tap unit and the network segment of the unconnected load again includes:

when the delay deviation is larger than a threshold value, recovering at least one tap unit which is not connected with a load and a corresponding network line segment;

and re-determining the delay deviation of each tap unit, and when the delay deviation is greater than a threshold value, re-deleting the tap units which are not connected with the load and the network line segment until the delay deviation of the tap units is less than or equal to the threshold value.

Optionally, when the delay deviation is greater than a threshold, the step of deleting the tap unit and the network segment of the unconnected load again includes:

when the delay deviation is larger than a threshold value, determining a target area with the maximum delay deviation;

recovering a tap unit which is partially or completely not connected with a load in the target area;

and re-determining the delay deviation of each tap unit, and when the delay deviation is greater than a threshold value, re-deleting the tap units which are not connected with the load and the network line segment until the delay deviation of the tap units is less than or equal to the threshold value.

Optionally, the step of determining the delay offset of each tap unit comprises:

taking any tap unit as a target tap unit;

comparing the delay of a tap cell adjacent to the target tap cell with the delay of the target tap cell to determine a delay skew of each tap cell.

Optionally, the step of deleting some or all network segments not connected with tap units includes:

and determining the network line segment to be deleted according to a preset layout rule and an antenna effect.

Optionally, the step of hierarchically connecting the tap units according to the preset positions of the tap units includes:

and utilizing metal wires to carry out layered connection on the tap units, wherein the layer number, the width and the spacing of the metal wires are related to the performance of the buffer and the resistance and the capacitance between the metal wires.

In a second aspect, an embodiment of the present application further provides a clock tree layout apparatus, where the apparatus includes:

the connection unit is used for carrying out layered connection on the tap units according to the preset positions of the tap units so as to form a clock network;

the connection unit is also used for arranging a buffer according to a preset position and forming connection from a clock input port to the clock network through the buffer;

a deleting unit configured to delete a tap unit to which a load is not connected;

the deleting unit is also used for deleting part or all of the network line segments which are not connected with the tap units;

and the deleting unit is also used for determining the delay deviation of each tap unit, and when the delay deviation is greater than a threshold value, deleting the tap units which are not connected with the load and the network line segment again until the delay deviation of the tap units is less than or equal to the threshold value so as to complete the layout of the clock tree.

Optionally, the deleting unit is configured to recover at least one tap unit not connected with a load and a corresponding network segment when the delay deviation is greater than a threshold; and re-determining the delay deviation of each tap unit, and when the delay deviation is greater than a threshold value, re-deleting the tap units which are not connected with the load and the network line segment until the delay deviation of the tap units is less than or equal to the threshold value.

In a third aspect, an embodiment of the present application further provides an electronic device, including: a memory to store one or more programs; a processor; the one or more programs, when executed by the processor, implement the methods described above.

In a fourth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to implement the method described above.

Compared with the prior art, the method has the following beneficial effects:

the application provides a clock tree layout method, a device, electronic equipment and a storage medium, wherein firstly, the tap units are connected in a layered mode according to the preset positions of the tap units to form a clock network, then a buffer is arranged according to the preset positions, the connection from a clock input port to the clock network is formed through the buffer, then the tap units which are not connected with loads are deleted, part or all of network line segments which are not connected with the tap units are deleted, finally, the delay deviation of each tap unit is determined, and when the delay deviation is larger than a threshold value, the tap units which are not connected with the loads and the network line segments are deleted again until the delay deviation of the tap units is smaller than or equal to the threshold value, so that the clock tree layout is completed. When the clock tree layout is carried out, redundant tap units and network line segments can be deleted, so that the length of a clock network line can be effectively shortened, the line-to-line capacitance is reduced, and the clock power consumption is reduced. Meanwhile, due to the fact that the area of the metal layer is reduced, the antenna effect violation is obviously reduced.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic block diagram of an electronic device according to an embodiment of the present disclosure.

Fig. 2 is a schematic flow chart of a clock tree layout method according to an embodiment of the present application.

Fig. 3 is a schematic connection diagram of a tap unit provided in an embodiment of the present application.

Fig. 4 is a schematic diagram of connection between a tap unit and a buffer according to an embodiment of the present disclosure.

Fig. 5 is a schematic connection diagram after a tap unit of a non-load is connected according to an embodiment of the present application.

Fig. 6 is a block diagram of a clock tree layout apparatus according to an embodiment of the present application.

In the figure: 100-an electronic device; 101-a processor; 102-a memory; 103-a communication interface; 200-a clock tree layout means; 210-a connection unit; 220-delete unit.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

As described in the background art, at present, a mesh clock tree structure brings convenience to timing convergence, and introduces a series of problems such as high power consumption, high resource occupation, and physical design violation, and it is necessary to reduce a redundant unit and reduce the overall capacitance of a clock structure by optimizing a clock network structure and a design process.

In view of this, the present application provides a clock tree layout method, which achieves the effects of reducing the power consumption all the time, reducing the resource occupation, and reducing the physical design violation by deleting redundant tap units and network line segments.

The clock tree layout method provided by the present application is applied to electronic devices, such as intelligent terminal electronic devices like computers and servers. Fig. 1 shows a schematic structural block diagram of an electronic device provided in an embodiment of the present application, where the electronic device 100 includes a memory 102, a processor 101, and a communication interface 103, and the memory 102, the processor 101, and the communication interface 103 are electrically connected to each other directly or indirectly to implement data transmission or interaction. For example, the components may be electrically connected to each other via one or more communication buses or signal lines.

The memory 102 may be used to store software programs and modules, such as program instructions or modules corresponding to the clock tree layout apparatus 200 provided in the embodiment of the present application, and the processor 101 executes the software programs and modules stored in the memory 102 to execute various functional applications and data processing, thereby executing the steps of the clock tree layout method provided in the embodiment of the present application. The communication interface 103 may be used for communicating signaling or data with other node devices.

The Memory 102 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Programmable Read-Only Memory (EEPROM), and the like.

The processor 101 may be an integrated circuit chip having signal processing capabilities. The Processor 101 may be a general-purpose Processor 101, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.

It will be appreciated that the configuration shown in FIG. 1 is merely illustrative and that electronic device 100 may include more or fewer components than shown in FIG. 1 or have a different configuration than shown in FIG. 1. The components shown in fig. 1 may be implemented in hardware, software, or a combination thereof.

The following is an exemplary description of the clock tree layout method described in the present application:

as an implementation manner, please refer to fig. 2, the clock tree layout method includes:

s102, layering and connecting the tap units according to the preset positions of the tap units to form a clock network.

S104, arranging buffers according to preset positions, and forming connection from the clock input port to the clock network through the buffers.

And S106, deleting the tap unit of the unconnected load.

And S108, deleting part or all of the network line segments which are not connected with the tap units.

S110, determining the delay deviation of each tap unit, and when the delay deviation is larger than a threshold value, deleting the tap units which are not connected with the load and the network line segment again until the delay deviation of the tap units is smaller than or equal to the threshold value, so as to complete the layout of the clock tree.

The tap unit refers to a terminal part of a clock tree, the rear end of the tap unit can be connected with a load, a delay function can be achieved through the tap unit, and delay of units of different modules can be different.

It should be noted that the delay refers to how fast the rising edge and the falling edge change in the PWM pulse, i.e., how fast the rising edge and the falling edge change from 0 to 1, or from 1 to 0.

The positions of the tap units are generally fixed according to design requirements, and the positions and the number of the tap units can be changed under different design requirements, so that when clock tree layout is performed, the positions of the tap units can be fixed according to the design requirements, then the tap units are connected in a layered mode, for example, please refer to fig. 3, connection is performed according to a horizontal mode, and then the tap units are arranged in rows, or connection is performed according to a vertical mode, and then the tap units are arranged in columns, and a clock network is formed. As shown in fig. 3, the tap unit may also be divided into different modules, and the different modules may perform different functions.

Certainly, the clock network further includes a backbone (a vertical line in fig. 3 is the backbone), the backbone is connected to the clock network, and one end of the backbone is connected to the clock input port. And the trunk and the metal wire connected with the tap unit jointly form a high-level metal wire, and then a mesh clock tree structure is formed through the implementation mode.

It is understood that as the trunk extends, the delay of the tap unit is higher the farther away from the clock input port, and therefore, in order to reduce the delay of the tap unit, a buffer is also required to be arranged, and the buffer can play a role of middleware to reduce the delay of the tap unit away from the clock input port.

For example, referring to fig. 4, in a certain area, two buffers need to be arranged, or, in a certain module, three buffers need to be arranged, and a connection from the clock input port to the clock network is formed through the buffers, but of course, other numbers of buffers may be arranged, and no limitation is made herein.

In actual use, the tap units may be connected to a load and provide a clock signal to the load, and of course, some of the tap units may not be connected to the load, on this basis, in order to reduce clock power consumption, the tap units not connected to the load are deleted, and the structure after deletion is as shown in fig. 5.

Meanwhile, after the tap unit is deleted, the network line segment connected with the deleted tap unit is in a suspended state, so that in order to shorten the length of the clock network line, part or all of the network line segments which are not connected with the tap unit can be deleted.

Of course, the above deletion is not the final result, because the redundant tap unit can play the role of balancing the clock network, and therefore, after the deletion is performed, the formed clock tree needs to be verified. As an implementation manner, whether to retain the deleting action may be determined by analyzing the delay time deviation of each tap unit. For example, when the delay deviation of a certain tap unit is greater than the threshold, the tap unit and the network line segment which are not connected with the load are deleted again, and then verification is performed until the delay deviation of the tap unit is less than or equal to the threshold, so as to complete the clock tree layout.

In other words, in the verification process, the actions of deleting again and determining the delay skew need to be executed circularly, and the loop cannot be exited until the delay skew of the tap unit is smaller than or equal to the threshold, and it can be understood that the tap unit and the network segment at this time are the shortest clock network and the least number of tap units satisfying the constraint condition.

Through the implementation mode, redundant tap units and clock network line segments are deleted, and a fishbone-shaped network structure is formed. The structure can effectively shorten the length of the clock network line and reduce the capacitance between the lines, thereby reducing the power consumption of the clock. Meanwhile, due to the fact that the area of the metal layer is reduced, the antenna effect violation is obviously reduced. Designers do not need to insert a large number of redundant diodes to repair the physical design violation, and the effective design area of the chip is improved to a certain extent.

As one implementation, the step of S102 includes:

and (3) utilizing the metal wires to carry out layered connection on the tap units, wherein the layer number, the width and the spacing of the metal wires are related to the performance of the buffer and the resistance and the capacitance between the metal wires.

Due to the fact that the delay of the tap unit is higher and higher due to the fact that the delay of the tap unit extends in the direction away from the clock input port, the performance of each buffer is different, the distance between every two adjacent metal lines is different, along with the increase of the distance, the resistance between the metal lines is reduced, the capacitance is increased, the number of layers, the width and the distance of the metal lines are determined by the driving capacity of the buffers and the resistance capacitance of the metal lines.

As one implementation, the step of S108 includes:

and determining the network line segment to be deleted according to a preset layout rule and an antenna effect.

When deleting a network line segment, the shortest line segment connecting the tap units needs to be reserved under the condition of not violating physical design rules, and then a fishbone-shaped network structure is formed. The physical design rules described herein include, but are not limited to, preset layout rules and antenna effects.

It should be noted that deleting a network segment described in the present application may be deleting a whole network segment that is suspended, or deleting only a part of the network segment that is suspended, and on this basis, the suspended network segment may be completely deleted, or the network segment may be shortened, so as to satisfy the physical design rule. For example, for a certain network segment, its connected tap cells have been deleted, its length is shortened by half according to the physical design rule, or it is deleted entirely.

Through the implementation mode, all redundant tap units can be guaranteed to be deleted, and meanwhile, the network line segment can achieve the effect of shortest line segment on the premise of meeting the physical design rule.

As one implementation, the step of S110 includes:

s1101, sets any one tap cell as a target tap cell.

S1102, comparing the delay of a tap cell adjacent to the target tap cell with the delay of the target tap cell to determine the delay deviation of each tap cell.

That is, when determining the delay skew of each tap unit, in order to make the determination more convenient, the delay of each tap unit may be differentiated from the delay of the adjacent tap unit, and the absolute value of the difference may be used as the delay skew. Of course, the number of adjacent tap cells is not limited in the present application, and for example, the delay skew may be determined for the target tap cell and 1 adjacent tap cell, or may be determined for 2 or more adjacent tap cells, which is not specifically limited herein.

It should be further noted that, when determining the delay time offset by using a plurality of adjacent tap units, the target tap unit may be sequentially subtracted from the adjacent tap units, and then the absolute value of the difference may be determined. When determining the delay time deviation, the maximum value of all absolute values may be used as the delay time deviation, or the sum of all absolute values may be used as the delay time deviation, or the average value of all absolute values may be used as the delay time deviation, which is not limited herein.

Determining whether the layout of the clock tree at the moment meets the constraint condition or not by comparing with a threshold value in a mode of determining delay deviation, and if so, taking the layout of the clock tree as a final layout; if not, continuing to perform iterative analysis by using the steps of S106-S110 until the condition is met.

As an implementation manner, S110 further includes:

and S1103, when the delay deviation is larger than the threshold value, recovering at least one tap unit which is not connected with the load and the corresponding network line segment.

And S1104, re-determining the delay deviation of each tap unit, and when the delay deviation is greater than the threshold, re-deleting the tap units which are not connected with the load and the network line segment until the delay deviation of the tap units is less than or equal to the threshold.

When the delay deviation is analyzed, if the delay deviation does not meet the constraint condition, it indicates that some tap units and/or some network line segments cannot be deleted, on this basis, the delay deviation of each tap unit can be re-determined in a manner of recovering the tap units not connected with the load and the corresponding network line segments, and then the delay deviation is analyzed.

For example, one deleted tap unit may be restored at a time, or multiple deleted tap units may be restored at a time. Of course, it is also possible to randomly recover the deleted tap units, then perform the delay deviation analysis, and determine whether the iterative analysis step needs to be continued.

Here, it should be noted that, when there are a plurality of recovered tap units and the delay deviation analysis is performed, and the constraint condition of the delay deviation is still not satisfied, part of the recovered tap units and the network line segment may also be deleted, and then the steps of recovering and deleting are continuously performed until the delay deviation of the tap units is less than or equal to the threshold, so as to complete the clock tree layout.

In another implementation, S110 includes:

and S1105, when the delay deviation is larger than the threshold value, determining the target area with the maximum delay deviation.

S1106, restoring some or all of the tap cells not connected with the load in the target area.

S1107, re-determine the delay deviation of each tap unit, and when the delay deviation is greater than the threshold, re-delete the tap unit and the network line segment that are not connected to the load until the delay deviation of the tap unit is less than or equal to the threshold.

In this implementation, a region with the largest delay deviation may be determined, for example, if the sum of the delay deviations of the tap units of the region is the largest, the delay deviation of the region is determined to be the largest, and then part or all of the tap units are recovered by region.

By the implementation mode, iterative analysis can be carried out from the region with the largest delay deviation, so that the efficiency is higher.

Based on the foregoing implementation, please refer to fig. 6, an embodiment of the present application further provides a clock tree layout apparatus 200, where the clock tree layout apparatus 200 includes:

the connection unit 210 is configured to perform hierarchical connection on the tap units according to a preset position of the tap unit to form a clock network.

It is understood that S102 may be performed through the connection unit 210.

The connection unit 210 is further configured to arrange the buffers in preset positions and form a connection from the clock input port to the clock network through the buffers.

It is understood that S104 may be performed through the connection unit 210.

And a deleting unit 220 for deleting the tap unit to which the load is not connected.

It is understood that S106 may be performed by the deletion unit 220.

And the deleting unit 220 is further configured to delete part or all of the network line segments to which the tap units are not connected.

It is understood that S108 may be performed by deleting the single executable.

And the deleting unit 220 is further configured to determine a delay deviation of each tap unit, and when the delay deviation is greater than a threshold, delete the tap unit not connected with the load and the network line segment again until the delay deviation of the tap unit is less than or equal to the threshold, so as to complete the clock tree layout.

It is understood that S110 may be performed by deleting the single executable.

In addition, the deleting unit 220 is configured to recover at least one tap unit not connected with a load and a corresponding network segment when the delay deviation is greater than the threshold; and re-determining the delay deviation of each tap unit, and when the delay deviation is greater than the threshold value, re-deleting the tap units which are not connected with the load and the network line segment until the delay deviation of the tap units is less than or equal to the threshold value.

To sum up, the present application provides a clock tree layout method, apparatus, electronic device and storage medium, wherein the tap units are hierarchically connected according to the preset positions of the tap units to form a clock network, then buffers are arranged according to the preset positions, the buffers form a connection from a clock input port to the clock network, then the tap units not connected with a load are deleted, then part or all of the network line segments not connected with the tap units are deleted, and finally, the delay skew of each tap unit is determined, and when the delay skew is greater than a threshold, the tap units not connected with a load and the network line segments are deleted again until the delay skew of the tap units is less than or equal to the threshold, so as to complete the clock tree layout. When the clock tree layout is carried out, redundant tap units and network line segments can be deleted, so that the length of a clock network line can be effectively shortened, the line-to-line capacitance is reduced, and the clock power consumption is reduced. Meanwhile, due to the fact that the area of the metal layer is reduced, the antenna effect violation is obviously reduced.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s).

It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.

It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: u disk, removable hard disk, read only memory, random access memory, magnetic or optical disk, etc. for storing program codes.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.