阅读说明：本技术 一种后端修调控制电路 (Rear end trimming control circuit ) 是由 周泽坤 邓晓军 孙启元 王卓 张波 于 2021-09-29 设计创作，主要内容包括：本发明属于集成电路技术领域,具体涉及一种后端修调控制电路。本发明提通过一个引脚外端输入时钟信号,通过时钟检测电路检测时钟信号的频率以及电平范围,生成的修调时钟使能信号用于触发修调时钟生成电路模块,修调时钟生成电路模块产生修调时钟信号输入到译码器模块和窄脉冲检测电路模块,由修调时钟信号的脉冲个数来决定译码器模块输出的修调数据,窄脉冲检测电路模块来检测的修调时钟信号,防止其他信号对修调烧断电路的影响,预防误烧断,译码器模块输出的修调数据和窄脉冲检测电路模块输出的修调使能信号共同决定修调有效位,用于完成修调。通过一个引脚实现修调数据的传输及对修调过程的控制,节省芯片的外部引脚资源。(The invention belongs to the technical field of integrated circuits, and particularly relates to a rear-end trimming control circuit. The invention provides a method for detecting the frequency and level range of a clock signal by a clock detection circuit, wherein the clock signal is input from the outer end of a pin, the generated trimming clock enabling signal is used for triggering a trimming clock generation circuit module, the trimming clock generation circuit module generates a trimming clock signal and inputs the trimming clock signal into a decoder module and a narrow pulse detection circuit module, trimming data output by the decoder module is determined by the number of pulses of the trimming clock signal, the trimming clock signal detected by the narrow pulse detection circuit module prevents other signals from influencing a trimming blow-out circuit and prevents error blow-out, and the trimming data output by the decoder module and the trimming enabling signal output by the narrow pulse detection circuit module jointly determine a trimming valid bit for finishing trimming. The transmission of trimming data and the control of the trimming process are realized through one pin, and the external pin resource of the chip is saved.)

1. A rear end trimming control circuit is characterized by comprising a starting circuit module, a clock signal detection circuit module, a trimming enabling generation circuit module, a trimming clock generation circuit module, a decoder module and a narrow pulse detection circuit module;

the start circuit module is used for detecting whether a clock signal is input from a clock input port, the input is the clock signal AND an enable signal, the start circuit module comprises an ESD circuit, a Delay circuit, a first power-on reset circuit POR1, a first AND gate AND1, a first OR gate OR1, a first inverter NOT1 AND a first buffer BUF1, the enable signal passes through the first buffer BUF1 AND then is connected with one input end of the first OR gate OR1, the output of the first power-on reset circuit POR1 passes through the first inverter NOT1 AND is connected with the other input end of the first OR gate OR1, the output of the first OR gate OR1 is connected with one input end of the first AND gate AND1, the clock signal input from the outer end passes through the ESD circuit AND enters the Delay circuit, the output of the Delay circuit is connected with the other input end of the first AND gate 1, AND1 outputs the start signal which is used as the enable signal of the clock signal detection circuit module;

the input of the clock signal detection circuit module is a clock signal, an enable signal and a start signal output by the start circuit module; the clock signal detection circuit module comprises a second power-on reset circuit POR2, a first C²MOS circuit, second C²MOS circuit, current mirror circuit, first NMOS transistor NM1, second NMOS transistor NM2, third NMOS transistor NM3, fourth NMOS transistor NM4, first PMOS transistor PM1, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, fifth resistor R5 and first capacitor C1. A first capacitor C2, a first schmitt trigger ST1, a second schmitt trigger ST2, a first NAND gate NAND1, a second buffer BUF2, a third buffer BUF3, a fourth buffer BUF4, a fifth buffer BUF5, a second inverter NOT2, a third inverter NOT3, a fourth inverter NOT4, a fifth inverter NOT5, a sixth inverter NOT6, a seventh inverter NOT7, an eighth inverter NOT8, and a ninth inverter NOT;

the first NMOS transistor NM1 is used as ESD, the grid electrode and the source electrode are grounded, the first PMOS transistor PM1 limits the level range, and the grid electrode and the source electrode are connected with power supply voltage; the drain of the first NMOS transistor NM1 is connected to the drain of the first PMOS transistor PM1, and the drain of the first NMOS transistor NM1 is further connected to the input terminal of the second inverter NOT 2; the clock signal passes through a first resistor R1 and then is connected with the drain of a second NMOS tube NM2, the gate of the second NMOS tube is connected with one input end of a first NAND gate NAND1, the source of the second NMOS tube NM2 is connected with the other input end of the first NAND gate 1 through a second resistor R2 and a second inverter NOT2, and the source of the first NMOS tube is grounded through a third resistor R3; the output signal of the first NAND gate NAND1 is connected into the first C²One input end of the MOS circuit, a second power-on reset circuit POR2 is connected with the first C²The other input end of the MOS circuit is connected with the starting signal into the second buffer BUF2 and the third inverter NOT3, and the output signals of the second buffer BUF2 and the third inverter NOT3 are connected with the first C²Two control ports of the MOS circuit; first C²The output of the MOS circuit is connected to the drain of the third MOS transistor NM3 and one end of a fourth resistor R4 through a fourth inverter NOT4, the source of the third MOS transistor NM3 is connected to the other end of the fourth resistor R4, then connected to the input end of the first schmitt trigger ST1 through a fifth resistor R5, and the source of the third MOS transistor NM3 is also connected to the ground through a first capacitor C1; the output end of the first Schmitt trigger ST1 is connected to the drain electrode of a third MOS tube NM3 after passing through a fifth inverter NOT5, meanwhile, the output end of the fifth inverter NOT5 is connected with a third buffer BUF3, and the third buffer BUF3 outputs a qualified clock signal;

the qualified clock signal is connected to the control end of the current mirror circuit after passing through a sixth inverter NOT6, the output end of the sixth inverter NOT6 is connected to the grid electrode of a fourth NMOS tube NM4 after passing through a seventh inverter NOT7, and the drain of the fourth NMOS tube NM4The electrode is connected with one output end of the current mirror circuit, and the drain electrode of the fourth NMOS tube NM4 is connected with the input end of the second Schmitt trigger ST2 and grounded after passing through a second capacitor C2; the other output end signal of the current mirror circuit is defined as the current I _ REF _ T, the qualified clock signal passes through a fourth buffer BUF4 and an eighth inverter NOT8, and the outputs of the fourth buffer BUF4 and the eighth inverter NOT8 are respectively connected to a second C²Two control terminals of the MOS circuit and the first transmission gate TG 1; the output end of the second Schmitt trigger ST2 is connected with the input end of the first transmission gate TG1, the output end of the first transmission gate TG1 is connected with the second C after passing through the ninth inverter NOT9²Input terminal of MOS circuit, second C²The output end of the MOS circuit is connected with the output end of a transmission gate TG1 and the input end of a fifth buffer BUF5, and the output end of the fifth buffer BUF5 is a frequency detection signal FD;

the input signals of the trimming clock enable signal generating circuit module are enable signals, qualified clock signals and frequency detection signals; the trimming clock enabling signal generating circuit module comprises an eight-frequency dividing circuit, a delay circuit, a third power-on reset circuit POR3, a first Latch circuit Latch1, a second Latch circuit Latch2, a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth D flip-flop D5, a sixth D flip-flop D6, a second OR gate OR2, a first three-input AND gate AND1, a first four-input AND gate AND2, a tenth inverter NOT10, an eleventh inverter NOT11 AND a twelfth inverter NOT 12;

the qualified clock signal is connected to the input end of the eight-frequency dividing circuit, the enable signal is connected to the reset end of the eight-frequency dividing circuit, the output ends of the two-frequency dividing, four-frequency dividing AND eight-frequency dividing of the eight-frequency dividing circuit are connected to the input end of a first three-input AND gate AND1, a first three-input AND gate AND1 is connected to the input end of a first Latch circuit Latch1, the enable signal is connected to the control end of the first Latch circuit Latch1 after passing through a tenth inverter NOT10, the output end of the first Latch circuit Latch1 is connected to one input end of a second OR gate OR2, the qualified clock signal is connected to the other input end of a second OR gate OR2 after passing through an eleventh inverter NOT11, the output end of the second OR gate OR2 is connected to the clock ports of a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3 AND a fourth D flip-flop D4, AND the enable signal is connected to the clock ports of the first D flip-flop D1, the second D flip-flop D2, the third D flip-flop D3 AND the fourth D4D 7D flip-flop, The reset end of a fifth D flip-flop D5, the frequency detection signal are connected to the input end of a first D flip-flop D1, the output end of a first D flip-flop D1 is connected to the input end of a second D flip-flop D2, the output end of the second D flip-flop D2 is connected to the input end of a third D flip-flop D3, the output end of the third D flip-flop D3 is connected to the input end of a fourth D flip-flop D4, the output ends of the first D flip-flop D1, the second D flip-flop D2, the third D flip-flop D3 AND the fourth D flip-flop D4 are also connected to the input end of a first four-input AND gate 2 respectively, the output end of the first four-input AND gate 2 is connected to the input end of a second Latch circuit Latch2, the enable signal is connected to the control end of a second Latch circuit Latch2 after passing through a twelfth inverter NOT12, the output end of the second Latch circuit Latch2 is connected to the input end of a fifth D flip-flop D5, the qualified clock signal is connected to the output end of a sixth D599, the output end of a sixth flip-flop D599, the output end of the third power-on reset circuit POR3 is connected with the input end of the sixth D flip-flop D6, and the output of the sixth D flip-flop D6 is a trimming clock enabling signal;

the input signals of the trimming clock generation circuit module are trimming clock enabling signals, qualified clock signals AND frequency detection signals, AND the trimming clock generation circuit module comprises a second three-input AND gate AND3, a third three-input AND gate AND4, a three-input NAND gate NAND2, an AND gate AND5, a NOR gate NOR, a thirteenth inverter NOT13, a fourteenth inverter NOT14, a sixth buffer BUF6 AND a seventh buffer BUF 7;

wherein, the trimming clock enable signal is accessed to one input end of a second three-input AND gate AND3, a third three-input AND gate AND4 AND a three-input NAND gate NAND2 through a thirteenth inverter NOT13, the trimming clock enable signal is also accessed to one input end of the AND gate AND5, the qualified clock signal is accessed to the other input end of the AND gate AND5, the output of the AND gate AND5 is accessed to one input end of the second three-input AND gate AND3 AND the third three-input AND gate AND4, meanwhile, the output of the AND gate AND4 is also accessed to one input end of the three-input NAND gate NAND2, the frequency detection signal is accessed to one input end of the third three-input AND gate 4, the frequency detection signal is accessed to the other input end of the second three-input AND gate AND3 after passing through a fourteenth inverter NOT14, the output end of the second three-input AND gate AND3 is accessed to one input end of the NOR gate through a sixth buffer BUF6, the output end of the third three-input AND gate 4 is accessed to the other input end of the NOR gate through a seventh buffer BUF7, the NOR output end is connected with the other input end of the three-input NAND gate NAND2, and the output of the three-input NAND gate NAND2 is the trimming clock signal;

the decoder module inputs signals including a trimming clock signal AND an enabling signal, AND comprises a sixteen-frequency division circuit, a second four-input AND gate AND7, a third four-input AND gate AND8 … …, a seventeenth four-input AND gate AND 22; wherein, the enable signal is connected to the reset terminal of the sixteen frequency dividing circuit, the trimming clock signal is connected to the input terminal of the sixteen frequency dividing circuit, the divide-by-two forward output, divide-by-four forward output, divide-by-eight forward output, divide-by-sixteen forward output of the sixteen frequency dividing circuit are respectively connected to the input terminals of the second four-input AND gate AND7, the output trimming code DO _0 of the second four-input AND gate AND7, the divide-by-two reverse output, divide-by-four forward output, divide-by-eight forward output, divide-by-sixteen forward output of the sixteen frequency dividing circuit are respectively connected to the input terminals of the third four-input AND gate AND8, the output trimming code DO _1 of the third four-input AND gate 8, AND so on, the divide-by-two reverse output, divide-by four reverse output, divide-by eight reverse output, divide-by sixteen reverse output of the sixteen frequency dividing circuit are respectively connected to the input terminals of the seventeenth four-input AND gate AND gate 22, the output trimming code DO _15 of the seventeenth four-input AND gate 22, thus obtaining DO _ 0-DO _15, namely 16 different modifying codes;

the input signals of the narrow pulse detection circuit are a trimming clock signal and a current I _ REF _ T, and the narrow pulse detection circuit module comprises a third C²The circuit comprises a MOS circuit, a third Schmitt trigger ST3, a second transmission gate TG2, a fifteenth inverter NOT15, a sixteenth inverter NOT16, a seventeenth inverter NOT17, an eighteenth inverter NOT18, an eighth buffer BUF8, a fifth NMOS tube NM5 and a third capacitor C3; the modified clock signal is connected to the gate of the fifth NMOS transistor NM5 after passing through a fifteenth inverter NOT15, the source of the fifth NMOS transistor NM5 is grounded, and the current I _ REF _ T is connected to the drain of the fifth NMOS transistor NM5 and the third Schmitt triggerThe input end of the ST3, the drain of the fifth NMOS tube NM5 is grounded through a third capacitor C3; the trimming clock signal also passes through an eighth buffer BUF8 and a seventeenth inverter NOT17, and the output ends of the eighth buffer BUF8 and the seventeenth inverter NOT17 are respectively connected to the third C²The MOS circuit and the control end of a second transmission gate TG2, the output end of a third Schmitt trigger ST3 is connected with the input end of a second transmission gate TG2, and the output end of the second transmission gate TG2 is connected with a third C after passing through an eighteenth inverter NOT18²Input terminal of MOS circuit, third C²The output end of the MOS circuit is connected with the output end of the second transmission gate TG2, and meanwhile, the third C²The output end of the MOS power outputs a trimming control signal after passing through a sixteenth inverter NOT 16;

the narrow pulse detection circuit module is used for detecting a trimming clock signal input into the trimming and blowing circuit, and determining an effective trimming bit together with a trimming code output by the decoder, so that the influence of other signals on the trimming and blowing circuit is prevented, and the false blowing is prevented.

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a rear-end trimming control circuit.

Background

In the chip manufacturing process, under the influence of factors such as process deviation, circuit mismatch and the like, the parameters of the produced chip have certain deviation from the expected values of design simulation, and the deviation brings great trouble for the design of an analog circuit with high parameter requirement. In order to reduce the influence of process fluctuation, adjust circuits and match errors and improve the precision of chip key parameters, trimming (trimming) technology is widely applied to analog circuits.

However, the conventional trimming circuit employs I²C, the trimming process is controlled by the communication protocols, which needs to occupy more integrated circuit pin resources. Therefore, a novel trimming control circuit which adopts few chip pins to realize the transmission of trimming data and the control of the trimming process becomes a direction of the development of integrated circuits.

Disclosure of Invention

In order to solve the problem that a traditional trimming circuit needs more pins, the invention provides a rear-end trimming control circuit, which inputs a clock signal through the outer end of one pin, and generates the number of input clock signal pulses into corresponding effective trimming codes through the control circuit so as to realize the control of trimming.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a rear end trimming control circuit is characterized by comprising a starting circuit module, a clock signal detection circuit module, a trimming enabling generation circuit module, a trimming clock generation circuit module, a decoder module and a narrow pulse detection circuit module;

the start circuit module is used for detecting whether a clock signal is input from a clock input port, the input is the clock signal AND an enable signal, the start circuit module comprises an ESD circuit, a Delay circuit, a first power-on reset circuit POR1, a first AND gate AND1, a first OR gate OR1, a first inverter NOT1 AND a first buffer BUF1, the enable signal passes through the first buffer BUF1 AND then is connected with one input end of the first OR gate OR1, the output of the first power-on reset circuit POR1 passes through the first inverter NOT1 AND is connected with the other input end of the first OR gate OR1, the output of the first OR gate OR1 is connected with one input end of the first AND gate AND1, the clock signal input from the outer end passes through the ESD circuit AND enters the Delay circuit, the output of the Delay circuit is connected with the other input end of the first AND gate 1, AND1 outputs the start signal which is used as the enable signal of the clock signal detection circuit module;

the input of the clock signal detection circuit module is a clock signal, an enable signal and a start signal output by the start circuit module; the clock signal detection circuit module comprises a second power-on reset circuit POR2, a first C²MOS circuit, second C²The MOS circuit comprises a MOS circuit, a current mirror circuit, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a first PMOS tube PM1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a first capacitor C2, a first Schmitt trigger ST1, a second Schmitt trigger ST2, a first NAND gate 1, a second buffer BUF2, a third buffer BUF3, a fourth buffer BUF4, a fifth buffer BUF5, a second inverter NOT2, a third inverter NOT3, a fourth inverter NOT4, a fifth inverter NOT5, a sixth inverter 6, a seventh inverter NOT7, an eighth NOT8 and a ninth inverter;

the first NMOS transistor NM1 is used as ESD, the grid electrode and the source electrode are grounded, the first PMOS transistor PM1 limits the level range, and the grid electrode and the source electrode are connected with power supply voltage; the drain of the first NMOS transistor NM1 is connected to the drain of the first PMOS transistor PM1, and the drain of the first NMOS transistor NM1 is further connected to the input terminal of the second inverter NOT 2; the clock signal passes through a first resistor R1 and then is connected with the drain of a second NMOS tube NM2, the gate of the second NMOS tube is connected with one input end of a first NAND gate NAND1, the source of the second NMOS tube NM2 is connected with the other input end of the first NAND gate 1 through a second resistor R2 and a second inverter NOT2, and the source of the first NMOS tube is grounded through a third resistor R3; the output signal of the first NAND gate NAND1 is connected into the first C²One input end of the MOS circuit, a second power-on reset circuit POR2 is connected with the first C²The other input end of the MOS circuit is connected with the starting signal into the second buffer BUF2 and the third inverter NOT3, and the output signals of the second buffer BUF2 and the third inverter NOT3 are connected with the first C²Two control ports of the MOS circuit; first C²The output of the MOS circuit is connected to the drain of the third MOS transistor NM3 and one of the fourth resistors R4 through the fourth inverter NOT4The source of the third MOS transistor NM3 is connected to the other end of the fourth resistor R4, then connected to the input terminal of the first schmitt trigger ST1 through the fifth resistor R5, and the source of the third MOS transistor NM3 is also connected to the ground through the first capacitor C1; the output end of the first Schmitt trigger ST1 is connected to the drain electrode of a third MOS tube NM3 after passing through a fifth inverter NOT5, meanwhile, the output end of the fifth inverter NOT5 is connected with a third buffer BUF3, and the third buffer BUF3 outputs a qualified clock signal;

qualified clock signals are connected to a control end of the current mirror circuit after passing through a sixth inverter NOT6, an output end of the sixth inverter NOT6 is connected to a gate of a fourth NMOS tube NM4 after passing through a seventh inverter NOT7, a drain of the fourth NMOS tube NM4 is connected to one output end of the current mirror circuit, and a drain of the fourth NMOS tube NM4 is connected to an input end of a second Schmitt trigger ST2 and is grounded after passing through a second capacitor C2; the other output end signal of the current mirror circuit is defined as the current I _ REF _ T, the qualified clock signal passes through a fourth buffer BUF4 and an eighth inverter NOT8, and the outputs of the fourth buffer BUF4 and the eighth inverter NOT8 are respectively connected to a second C²Two control terminals of the MOS circuit and the first transmission gate TG 1; the output end of the second Schmitt trigger ST2 is connected with the input end of the first transmission gate TG1, the output end of the first transmission gate TG1 is connected with the second C after passing through the ninth inverter NOT9²Input terminal of MOS circuit, second C²The output end of the MOS circuit is connected with the output end of a transmission gate TG1 and the input end of a fifth buffer BUF5, and the output end of the fifth buffer BUF5 is a frequency detection signal FD;

the input signals of the trimming clock enable signal generating circuit module are enable signals, qualified clock signals and frequency detection signals; the trimming clock enabling signal generating circuit module comprises an eight-frequency dividing circuit, a delay circuit, a third power-on reset circuit POR3, a first Latch circuit Latch1, a second Latch circuit Latch2, a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, a fifth D flip-flop D5, a sixth D flip-flop D6, a second OR gate OR2, a first three-input AND gate AND1, a first four-input AND gate AND2, a tenth inverter NOT10, an eleventh inverter NOT11 AND a twelfth inverter NOT 12;

the qualified clock signal is connected to the input end of the eight-frequency dividing circuit, the enable signal is connected to the reset end of the eight-frequency dividing circuit, the output ends of the two-frequency dividing, four-frequency dividing AND eight-frequency dividing of the eight-frequency dividing circuit are connected to the input end of a first three-input AND gate AND1, a first three-input AND gate AND1 is connected to the input end of a first Latch circuit Latch1, the enable signal is connected to the control end of the first Latch circuit Latch1 after passing through a tenth inverter NOT10, the output end of the first Latch circuit Latch1 is connected to one input end of a second OR gate OR2, the qualified clock signal is connected to the other input end of a second OR gate OR2 after passing through an eleventh inverter NOT11, the output end of the second OR gate OR2 is connected to the clock ports of a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3 AND a fourth D flip-flop D4, AND the enable signal is connected to the clock ports of the first D flip-flop D1, the second D flip-flop D2, the third D flip-flop D3 AND the fourth D4D 7D flip-flop, The reset end of a fifth D flip-flop D5, the frequency detection signal are connected to the input end of a first D flip-flop D1, the output end of a first D flip-flop D1 is connected to the input end of a second D flip-flop D2, the output end of the second D flip-flop D2 is connected to the input end of a third D flip-flop D3, the output end of the third D flip-flop D3 is connected to the input end of a fourth D flip-flop D4, the output ends of the first D flip-flop D1, the second D flip-flop D2, the third D flip-flop D3 AND the fourth D flip-flop D4 are also connected to the input end of a first four-input AND gate 2 respectively, the output end of the first four-input AND gate 2 is connected to the input end of a second Latch circuit Latch2, the enable signal is connected to the control end of a second Latch circuit Latch2 after passing through a twelfth inverter NOT12, the output end of the second Latch circuit Latch2 is connected to the input end of a fifth D flip-flop D5, the qualified clock signal is connected to the output end of a sixth D599, the output end of a sixth flip-flop D599, the output end of the third power-on reset circuit POR3 is connected with the input end of the sixth D flip-flop D6, and the output of the sixth D flip-flop D6 is a trimming clock enabling signal;

the input signals of the trimming clock generation circuit module are trimming clock enabling signals, qualified clock signals AND frequency detection signals, AND the trimming clock generation circuit module comprises a second three-input AND gate AND3, a third three-input AND gate AND4, a three-input NAND gate NAND2, an AND gate AND5, a NOR gate NOR, a thirteenth inverter NOT13, a fourteenth inverter NOT14, a sixth buffer BUF6 AND a seventh buffer BUF 7;

wherein, the trimming clock enable signal is accessed to one input end of a second three-input AND gate AND3, a third three-input AND gate AND4 AND a three-input NAND gate NAND2 through a thirteenth inverter NOT13, the trimming clock enable signal is also accessed to one input end of the AND gate AND5, the qualified clock signal is accessed to the other input end of the AND gate AND5, the output of the AND gate AND5 is accessed to one input end of the second three-input AND gate AND3 AND the third three-input AND gate AND4, meanwhile, the output of the AND gate AND4 is also accessed to one input end of the three-input NAND gate NAND2, the frequency detection signal is accessed to one input end of the third three-input AND gate 4, the frequency detection signal is accessed to the other input end of the second three-input AND gate AND3 after passing through a fourteenth inverter NOT14, the output end of the second three-input AND gate AND3 is accessed to one input end of the NOR gate through a sixth buffer BUF6, the output end of the third three-input AND gate 4 is accessed to the other input end of the NOR gate through a seventh buffer BUF7, the NOR output end is connected with the other input end of the three-input NAND gate NAND2, and the output of the three-input NAND gate NAND2 is the trimming clock signal;

the decoder module inputs signals including a trimming clock signal AND an enabling signal, AND comprises a sixteen-frequency division circuit, a second four-input AND gate AND7, a third four-input AND gate AND8 … …, a seventeenth four-input AND gate AND 22; wherein, the enable signal is connected to the reset terminal of the sixteen frequency dividing circuit, the trimming clock signal is connected to the input terminal of the sixteen frequency dividing circuit, the divide-by-two forward output, divide-by-four forward output, divide-by-eight forward output, divide-by-sixteen forward output of the sixteen frequency dividing circuit are respectively connected to the input terminals of the second four-input AND gate AND7, the output trimming code DO _0 of the second four-input AND gate AND7, the divide-by-two reverse output, divide-by-four forward output, divide-by-eight forward output, divide-by-sixteen forward output of the sixteen frequency dividing circuit are respectively connected to the input terminals of the third four-input AND gate AND8, the output trimming code DO _1 of the third four-input AND gate 8, AND so on, the divide-by-two reverse output, divide-by four reverse output, divide-by eight reverse output, divide-by sixteen reverse output of the sixteen frequency dividing circuit are respectively connected to the input terminals of the seventeenth four-input AND gate AND gate 22, the output trimming code DO _15 of the seventeenth four-input AND gate 22, thus obtaining DO _ 0-DO _15, namely 16 different modifying codes;

the input signals of the narrow pulse detection circuit are a trimming clock signal and a current I _ REF _ T, and the narrow pulse detection circuit module comprises a third C²The circuit comprises a MOS circuit, a third Schmitt trigger ST3, a second transmission gate TG2, a fifteenth inverter NOT15, a sixteenth inverter NOT16, a seventeenth inverter NOT17, an eighteenth inverter NOT18, an eighth buffer BUF8, a fifth NMOS tube NM5 and a third capacitor C3; the trimming clock signal is connected to the grid electrode of a fifth NMOS tube NM5 after passing through a fifteenth inverter NOT15, the source electrode of the fifth NMOS tube NM5 is grounded, a current I _ REF _ T is connected to the drain electrode of the fifth NMOS tube NM5 and the input end of a third Schmitt trigger ST3, and the drain electrode of the fifth NMOS tube NM5 is grounded after passing through a third capacitor C3; the trimming clock signal also passes through an eighth buffer BUF8 and a seventeenth inverter NOT17, and the output ends of the eighth buffer BUF8 and the seventeenth inverter NOT17 are respectively connected to the third C²The MOS circuit and the control end of a second transmission gate TG2, the output end of a third Schmitt trigger ST3 is connected with the input end of a second transmission gate TG2, and the output end of the second transmission gate TG2 is connected with a third C after passing through an eighteenth inverter NOT18²Input terminal of MOS circuit, third C²The output end of the MOS circuit is connected with the output end of the second transmission gate TG2, and meanwhile, the third C²And the output end of the MOS power outputs a trimming control signal after passing through a sixteenth inverter NOT 16.

The narrow pulse detection circuit module is used for detecting a trimming clock signal input into the trimming and blowing circuit, and determining an effective trimming bit together with a trimming code output by the decoder, so that the influence of other signals on the trimming and blowing circuit is prevented, and the false blowing is prevented.

The invention has the advantages that clock signals are input through the outer ends of the pins, the frequency and level range of the clock signals are detected through the clock detection circuit, the generated trimming clock enable signals are used for triggering the trimming clock generation circuit module, the trimming clock generation circuit module generates trimming clock signals and inputs the trimming clock signals to the decoder module and the narrow pulse detection circuit module, trimming data output by the decoder module is determined according to the number of pulses of the trimming clock signals, the trimming clock signals detected by the narrow pulse detection circuit module prevent other signals from influencing the trimming blow circuit, and prevent mistaken blow, and trimming data output by the decoder module and the trimming enable signals output by the narrow pulse detection circuit module jointly determine trimming valid bits for finishing trimming. The transmission of trimming data and the control of the trimming process are realized through one pin, and the external pin resource of the chip is saved.

Drawings

Fig. 1 is an equivalent architecture diagram of a control circuit for back-end trimming according to the present invention;

FIG. 2 is a circuit diagram of a start-up circuit module;

FIG. 3 is a circuit diagram of a clock signal detection circuit module;

FIG. 4 is a circuit diagram of a trimming enable generation circuit module;

FIG. 5 is a circuit diagram of a trimming clock generating circuit module;

FIG. 6 is a circuit diagram of a decoder module;

FIG. 7 is a circuit diagram of a narrow pulse detection circuit;

FIG. 8 is a logic timing diagram of the control circuit.

Detailed Description

The technical scheme of the invention is described in detail below with reference to the accompanying drawings:

the invention provides a control circuit design for rear-end trimming, which is shown in a structural block diagram of fig. 1 and comprises a starting circuit module, a clock signal detection circuit module, a trimming enabling generation circuit module, a trimming clock generation circuit module, a decoder module and a narrow pulse detection circuit module.

The starting circuit module is used for detecting whether a clock signal is input into the input port or not, starting the clock signal detection circuit module when the clock signal is input into the input port, the clock signal detection circuit module is used for detecting the frequency and level range of the input clock signal, the generated trimming clock enabling signal is used for triggering the trimming clock generation circuit module, the trimming clock generation circuit module generates a trimming clock signal and inputs the trimming clock signal into the decoder module and the narrow pulse detection circuit module, and trimming data output by the decoder module and the trimming enabling signal output by the narrow pulse detection circuit module jointly determine a trimming effective bit for finishing trimming;

the start-up circuit block is shown in fig. 2. In the circuit, after power is applied to the circuit, the first power-on reset circuit POR1 constantly outputs a high potential, the enable signal is active at a high level, AND the output of the first OR gate OR1 controls the output of the first AND gate AND 1. The clock signal enters the Delay circuit through the ESD circuit, enters the first AND gate AND1, AND the first AND gate AND1 outputs a high level, which is the start signal, as the enable signal of the clock signal detection circuit module. After the trimming circuit is finished, after the clock signal port Clk _ IN is input to be at low level AND a certain time elapses, the output of the Delay circuit is inverted, the output of the first AND gate AND1 is inverted to be at low level, AND the whole trimming circuit is controlled to stop working.

The clock signal detection circuit block is shown in fig. 3. The first NMOS transistor NM1 is used as ESD, and the first PMOS transistor PM1 limits the level range, which is-0.7 v-VDD +0.7 v. When the circuit works, the second power-on reset circuit POR2 continuously outputs high level and is connected to the first C²An input terminal of the MOS circuit; the clock signal passes through a first resistor R1 and then is connected with the drain of a second NMOS tube NM2, the gate of the second NMOS tube is connected with one input end of a first NAND gate NAND1, the source of the second NMOS tube NM2 is connected with the other input end of the first NAND gate 1 through a second resistor R2 and a second inverter NOT2, and the output end of the first NAND gate 1 is connected with a first C²The other input terminal of the MOS circuit.

After the starting signal is input, the signal is used as a first C²MOS circuit control signal for controlling the first C²And outputting the MOS circuit. When the output signal LD1 of the first NAND gate NAND1 is high, the first C²The MOS circuit right pull-down branch circuit is turned on to output a low level, the third NMOS transistor NM3 is turned on, the source of the third NMOS transistor NM3 charges the first capacitor C1 through the fifth resistor R5, and the charging time constant is: tau is_{Charging device}＝R₅C₁After the voltage of the first capacitor C1 reaches the up-conversion voltage of the first schmitt trigger ST1, the schmitt trigger ST1 outputs a high level after passing through the fourth inverter NOT4 and the third buffer BUF 3; first NAND gate NANDWhen the 1 output LD1 is low, the first C²The left pull-up branch of the MOS circuit is turned on to output a high level, the third NMOS transistor NM3 is turned off, the first capacitor C1 discharges through the fourth resistor R4 and the fifth resistor R5, and the discharge time constant is: tau is_Put＝(R₄+R₅)C₁When the voltage of the first capacitor C1 reaches the lower flip-flop voltage of the schmitt trigger, the schmitt trigger ST1 outputs a low level after passing through the fourth inverter NOT4 and the third buffer BUF 3. The output signal of the third buffer BUF3 is the qualified clock signal CLK _ FA.

When the start signal is low after the start circuit stops working, the first C²MOS circuit C²The left pull-down branch of MOS1 is continuously conducted, first C²MOS circuit C²The output of the MOS1 is constantly at a low level, and the source of the third NMOS tube NM3 charges the first capacitor C1 through the fifth resistor R5, so that the output signal of the third buffer BUF3, i.e., the qualified clock signal CLK _ FA, is constantly at a high level.

The time constant τ for the charging voltage of the second capacitor C2 in the circuit to reach the flipped voltage on the second schmitt trigger ST2 is set. And the qualified clock signal passes through the sixth inverter NOT6 and then is connected to the control end of the current mirror circuit to control the current mirror to generate current. An output end signal of the current mirror is defined as a current I _ REF _ T, the other output end current is connected to the drain electrode of the fourth NMOS tube NM4 and the second capacitor C2, a qualified clock signal passes through the sixth inverter NOT6 and the seventh inverter NOT7 and then is connected to the gate electrode of the fourth NMOS tube NM4, and the charge and discharge of the second capacitor C2 are controlled through the fourth NMOS tube NM 4.

When the duty ratio of the low level of the qualified clock signal is less than tau, namely the frequency of the clock signal is more than 1/2 tau, and the qualified clock signal is at the low level, the second capacitor C2 is charged, after the charging is finished, the voltage of the second capacitor C2 does not reach the upper turning threshold voltage of the second Schmitt trigger ST2, and the low level is output. The qualified clock signal passes through the fourth buffer BUF4 and the eighth inverter NOT8, the outputs of the fourth buffer BUF4 and the eighth inverter NOT8 are connected to two control ends of the first transmission gate TG1, the transmission gate TG1 is turned on, and the output of the second schmitt trigger ST2 passes through the first transmission gate TG1 and the fifth buffer BUF5 and is output as a high level.

When the qualified clock signal is at a high level, the transmission gate TG1 is closed, the qualified clock signal passes through the fourth buffer BUF4 and the eighth inverter NOT8, and the outputs of the fourth buffer BUF4 and the eighth inverter NOT8 are connected to the second C²MOS circuit C²Control terminal of MOS2, then second C²MOS circuit C²The pull-up branch of the MOS2 is turned on and outputs a high level through the fifth buffer BUF 5. The output of the output terminal of the fifth buffer BUF5 is the frequency detection signal FD. The frequency detection signal FD is at a high level, which is a state required by the following circuit. The frequency of the outer-end input clock signal cannot be less than 1/2 tau.

When the clock signal is stopped to be input and the clock signal port Clk _ IN is at a low level, and the qualified clock signal is at a low level, the frequency detection signal FD will be at a low level after the second capacitor C2 is charged to reach the inversion voltage of the second schmitt trigger ST2, and will remain at this state until the next clock signal is input.

As shown in fig. 4, a trimming enable generation circuit block. The qualified clock signal passes through an eleventh inverter NOT11 and is then connected to one input terminal of the second OR gate OR2, the output terminal of the first Latch circuit Latch1 is connected to the other input terminal of the second OR gate OR2, and when the first Latch circuit Latch1 outputs a low level, the second OR gate OR2 outputs an inverted signal of the qualified clock signal. The qualified clock signal is connected to the input end of the eight-frequency dividing circuit, the enable signal is connected to the reset end of the eight-frequency dividing circuit, the output ends of the two-frequency dividing, four-frequency dividing AND eight-frequency dividing of the eight-frequency dividing circuit are connected to the input end of a first three-input AND gate AND1, the first three-input AND gate AND1 is connected to the input end of a first Latch circuit Latch1, when the first Latch circuit Latch1 detects that the first rising edge of the output of the first three-input AND gate AND1 is output after 4 cycles of the qualified clock signal, the first Latch circuit Latch1 latches the high level state AND keeps constant, AND the second OR gate OR2 outputs the high level constantly. The output end of the second OR gate OR2 is connected to the clock ports of the first D flip-flop D1, the second D flip-flop D2, the third D flip-flop D3 AND the fourth D flip-flop D4, AND is used as a clock signal, the enable signal is connected to the reset ends of the first D flip-flop D1, the second D flip-flop D2, the third D flip-flop D3, the fourth D flip-flop D4 AND the fifth D flip-flop D5, the frequency detection signal is connected to the input end of the first D flip-flop D1, the output end of the first D flip-flop D1 is connected to the input end of the second D flip-flop D2, the output end of the second D flip-flop D2 is connected to the input end of the third D flip-flop D3, the output end of the third D flip-flop D3 is connected to the input end of the fourth D flip-flop D4, AND the output ends of the first D1, the second D flip-flop D2, the third D flip-flop D3 AND the fourth D4 are connected to the input end of the fourth AND 2. The D flip-flop is triggered by falling edge, the first 4 falling edges of the output signal of the second OR gate OR2, AND the output of the first four-input AND gate AND2 is low level. When the output signal of the second OR gate OR2 falls 4 times later, the output of the first four-input AND gate AND2 flips to a high level, the output of the first four-input AND gate AND2 is connected to the input terminal of the second Latch circuit Latch2, AND the second Latch circuit Latch2 latches a high level state. The qualified clock signal is connected with the clock ports of the fifth D flip-flop D5 and the sixth D flip-flop D6, the output of the second Latch circuit Latch2 is connected with the fifth D flip-flop D5, the output of the fifth D flip-flop D5 is connected with the reset end of the sixth D flip-flop D6, and when the fifth D flip-flop D5 outputs a low level, the sixth D flip-flop D6 is reset and outputs a low level. When the fifth D flip-flop D5 outputs a high level, the sixth D flip-flop D6 is turned on, the output of the third power-on reset circuit POR3 is connected to the input of the sixth D flip-flop D6, and the output of the sixth D flip-flop D6 flips to a high level after 6 clocks of the qualified clock signal. The output signal of the sixth D flip-flop D6 is the modified clock enable signal CLK _ EN.

Fig. 5 shows a trimming clock generating circuit module. The trimming clock enable signal is connected to one input end of the second three-input AND gate AND3, the third three-input AND gate AND4 AND the three-input NAND gate NAND2 through a thirteenth inverter NOT13, AND is also connected to one input end of the AND gate AND 5. The frequency detection signal is connected to one input end of the third three-input AND gate AND4, AND the frequency detection signal is connected to the other input end of the second three-input AND gate AND3 after passing through the fourteenth inverter NOT 14. When the trimming clock enable signal AND the frequency detection signal jump to high level, the qualified clock signal passes through the AND gate AND5, the second three-input AND gate AND3 AND the third three-input AND gate AND4 AND is output by the three-input NAND gate NAND2, AND the three-input NAND gate NAND2 outputs the inverted signal of the qualified clock signal, namely the trimming clock signal Trim _ clk.

Fig. 6 shows a decoder module. The enabling signal is connected to the reset end of the sixteen frequency dividing circuit, the trimming clock signal is connected to the input end of the sixteen frequency dividing circuit, the binary frequency forward output, the quaternary frequency forward output, the eighth frequency forward output AND the sixteenth frequency forward output of the sixteen frequency dividing circuit are respectively connected to the input end of a second four-input AND gate 7, the trimming code DO _0 output by the second four-input AND gate 7, the binary frequency reverse output, the quaternary frequency forward output, the eighth frequency forward output AND the sixteenth frequency forward output of the sixteen frequency dividing circuit are respectively connected to the input end of a third four-input AND gate 8, the trimming code DO _1 output by the third four-input AND gate 8, AND so on, the binary frequency reverse output, the quaternary frequency reverse output, the eighth frequency reverse output AND the sixteenth frequency reverse output of the sixteen frequency dividing circuit are respectively connected to the input end of a seventeenth four-input AND gate 22, AND the seventeenth four-input AND gate 22 outputs the trimming code DO _15, by selecting different frequency division waveforms and decoding through an AND gate, different trimming codes in the DO _ 0-DO _15 and the like 16 are obtained, and corresponding code systems are selected according to trimming requirements.

Fig. 7 shows a narrow pulse detection circuit module. The output current I _ REF _ T of the clock signal detection circuit module is connected to the drain of the fifth NMOS transistor NM5 and the third capacitor C3 to charge the third capacitor C3.

The trimming clock signal is connected to the gate of the fifth NMOS tube NM5 after passing through the fifteenth inverter NOT15, and controls the on and off of the fifth NMOS tube NM5, thereby controlling the charging and discharging of the second capacitor C2. The time constant tau of the charging voltage of the third capacitor C3 in the circuit reaching the switching voltage on the third Schmitt trigger ST3 is set, and the frequency of the input trimming clock signal is larger than 1/2 tau due to the limitation of the clock signal detection circuit. The trimming clock signal also passes through an eighth buffer BUF8 and a seventeenth inverter NOT17, and the output ends of the eighth buffer BUF8 and the seventeenth inverter NOT17 are respectively connected to the third C²MOS circuit C²Control of MOS3 and second transmission gate TG2And (4) an end. Therefore, when the trimming clock is at a high level, the third capacitor C3 is charged, the transmission gate TG2 is turned on, but the capacitance value of the third capacitor C3 is set to be larger, the voltage of the third capacitor C3 cannot reach the forward threshold voltage of the third schmitt trigger ST3, and the output signal of the sixteenth inverter NOT16 is at a low level; when the trimming clock is at low level, the second transmission gate TG2 is turned off, and the third C is turned off²MOS circuit C²When the pull-up branch of the MOS3 is turned on, the output of the sixteenth inverter NOT16 remains at the previous state and remains low. When the input clock signal at the port Clk _ IN is grounded, the trimming clock continues to output a high level, the current I _ REF _ T continues to output a high level, and when the capacitance voltage of the third capacitor C3 reaches the forward threshold voltage of the third schmitt trigger ST3, the output of the sixteenth inverter NOT16 jumps to a high level. The output signal of the sixteenth inverter NOT16 is the trimming enable signal Trim _ EN. Therefore, the narrow pulse detection circuit module detects the trimming clock signal input into the trimming blow-out circuit, determines an effective trimming bit together with the trimming code DO _ X output by the decoder, prevents other signals from influencing the trimming blow-out circuit and prevents mistaken blow-out.

The overall logic timing of the back-end trimming control circuit provided by the invention is as shown in fig. 8, and is divided into four stages, namely, a start stage, a preparation stage, a data reading stage and an end stage. In the preparation stage, the external port is grounded, no clock signal exists, and the trimming data code and the trimming enable are in low level. In the preparation stage, clock signals of X +6 periods are input into an external port, and after the starting circuit detects the clock signals, the starting signals jump to high level; and entering a clock signal detection circuit module to generate a qualified clock signal, after 6 periods, changing a trimming clock enable signal into a high level to control the trimming clock signal to start outputting a signal, and enabling the circuit to enter a data stage. In the data phase, the trimming clock signal enters a decoder, and simultaneously enters a narrow pulse detection circuit. When the input clock signal is finished, the trimming clock signal outputs X periodic signals, and after the decoder circuit detects the last falling edge of the trimming clock signal, the trimming code DO _ X jumps to a high level; the narrow pulse detection circuit detects the last state of the trimming clock signal, so that the trimming enable signal becomes a high level. The trimming data output by the decoder circuit module and the trimming enabling signal output by the narrow pulse detection circuit module jointly determine the trimming effective bit, so that the change of the switch state of the trimming effective bit is realized. At the end stage, the start signal of the start circuit module jumps to low level, then the trimming clock signal changes to low level, the trimming data DO _ X and the trimming enable signal are reset, the whole control circuit stops working, and trimming is completed.