阅读说明：本技术 多晶硅层、其制作方法以及半导体器件 (Polycrystalline silicon layer, manufacturing method thereof and semiconductor device ) 是由 颜元 朱文琪 吴亮 刘修忠 于 2021-09-06 设计创作，主要内容包括：本申请提供了一种多晶硅层、其制作方法以及半导体器件。该制作方法包括：在基底上沉积非晶硅层；在预定温度下,向非晶硅层中注入预定离子,以打断非晶硅层中的Si-H键,且使得H溢出非晶硅层；对非晶硅层进行退火处理,形成多晶硅层。通过离子注入的方式打断非晶硅层中的Si-H键,使H溢出非晶硅层,减少或者避免后续在退火过程中,由于温度较高使得H聚集而导致气泡或者剥落等缺陷的产生,从而减少现有技术中的非晶硅层在退火过程中形成的缺陷。(The application provides a polycrystalline silicon layer, a manufacturing method thereof and a semiconductor device. The manufacturing method comprises the following steps: depositing an amorphous silicon layer on a substrate; injecting predetermined ions into the amorphous silicon layer at a predetermined temperature to break Si-H bonds in the amorphous silicon layer and allow H to overflow the amorphous silicon layer; and annealing the amorphous silicon layer to form a polycrystalline silicon layer. Si-H bonds in the amorphous silicon layer are broken through ion implantation, so that H overflows the amorphous silicon layer, the generation of defects such as bubbles or peeling caused by H aggregation due to high temperature in the subsequent annealing process is reduced or avoided, and the defects formed in the annealing process of the amorphous silicon layer in the prior art are reduced.)

1. A method for manufacturing a polysilicon layer is characterized by comprising the following steps:

depositing an amorphous silicon layer on a substrate;

injecting predetermined ions into the amorphous silicon layer at a predetermined temperature to break Si-H bonds in the amorphous silicon layer and allow H to overflow the amorphous silicon layer;

and annealing the amorphous silicon layer to form a polycrystalline silicon layer.

2. The method of manufacturing of claim 1, wherein the predetermined ions comprise at least one of: he. P, C, Ge are provided.

3. The method of manufacturing according to claim 1, wherein the predetermined ion is He.

4. The method of claim 1, wherein the predetermined temperature is between 300 ℃ and 500 ℃.

5. The method of claim 1, wherein the predetermined temperature is between 400 ℃ and 500 ℃.

6. A method of fabricating according to any of claims 1 to 5, wherein depositing an amorphous silicon layer on a substrate comprises:

and depositing an amorphous silicon material on the substrate at the temperature of 420-450 ℃ to form the amorphous silicon layer.

7. The method of any of claims 1 to 5, wherein annealing the amorphous silicon layer comprises at least one of:

performing the annealing treatment on the amorphous silicon layer by adopting a laser annealing method;

and carrying out annealing treatment on the amorphous silicon layer by adopting a thermal annealing method.

8. The fabrication method according to any one of claims 1 to 5, wherein the substrate includes a memory cell including a channel layer, and the polysilicon layer is located on a surface of the channel layer.

9. A polysilicon layer formed by the method of any one of claims 1 to 8.

10. A semiconductor device comprising a polysilicon layer, wherein the polysilicon layer is the polysilicon layer of claim 9.

Technical Field

The present disclosure relates to the field of semiconductors, and in particular, to a polysilicon layer, a method for fabricating the same, and a semiconductor device.

Background

In 3DNAND FLASH of the X-stacking architecture, after forming a memory cell, a channel layer of polysilicon is typically formed thereon so that the channel layer is in contact with the polysilicon in the memory cell.

In the prior art, an amorphous silicon layer is generally formed at a low temperature of 420-450 ℃; then, the amorphous silicon is converted into polysilicon through an annealing process, so that a conductive channel of the polysilicon layer is formed, and programming and erasing of the device are finally realized.

A large number of Si-H bonds can remain in the amorphous silicon layer formed by the scheme, the bonds can be broken in the subsequent annealing process, H is gathered to form bubbles, even hydrogen explosion occurs, the amorphous silicon layer is partially peeled off, and the defects of the bubbles or peeling and the like are frequently generated on the interface between the storage unit and the polycrystalline silicon layer, so that the conductivity of the device is influenced, and the performance of the device is poor.

Therefore, a solution capable of reducing defects formed during annealing of the amorphous silicon layer in the prior art is needed.

The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to a polysilicon layer, a method for fabricating the same, and a semiconductor device, so as to reduce the problem of defects formed during the annealing process of an amorphous silicon layer in the prior art.

According to an aspect of the embodiments of the present invention, there is provided a method for manufacturing a polysilicon layer, including: depositing an amorphous silicon layer on a substrate; injecting predetermined ions into the amorphous silicon layer at a predetermined temperature to break Si-H bonds in the amorphous silicon layer and allow H to overflow the amorphous silicon layer; and annealing the amorphous silicon layer to form a polycrystalline silicon layer.

Optionally, the predetermined ions comprise at least one of: he. P, C, Ge are provided.

Optionally, the predetermined ion is He.

Optionally, the predetermined temperature is between 300 and 500 ℃.

Optionally, the predetermined temperature is between 400 and 500 ℃.

Optionally, depositing an amorphous silicon layer on the substrate comprises: and depositing an amorphous silicon material on the substrate at the temperature of 420-450 ℃ to form the amorphous silicon layer.

Optionally, the annealing treatment is performed on the amorphous silicon layer, and includes at least one of: performing the annealing treatment on the amorphous silicon layer by adopting a laser annealing method; and carrying out annealing treatment on the amorphous silicon layer by adopting a thermal annealing method.

Optionally, the substrate includes a memory cell including a channel layer, and the polysilicon layer is on a surface of the channel layer.

According to another aspect of the embodiments of the present invention, there is also provided a polysilicon layer formed by any one of the above-mentioned manufacturing methods.

According to still another aspect of the embodiments of the present invention, there is also provided a semiconductor device including a polysilicon layer, the polysilicon layer being the polysilicon layer.

In the embodiment of the invention, firstly, an amorphous silicon layer is deposited on a substrate; then, implanting predetermined ions into the amorphous silicon layer at a predetermined temperature; and finally, annealing the amorphous silicon layer to form a polycrystalline silicon layer. In the method, Si-H bonds in the amorphous silicon layer are broken in an ion implantation mode, so that H overflows the amorphous silicon layer, and the generation of defects such as bubbles or peeling and the like caused by H aggregation due to high temperature in the subsequent annealing process is reduced or avoided, thereby reducing the defects formed in the annealing process of the amorphous silicon layer in the prior art.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:

fig. 1 to 3 illustrate defects of a polysilicon layer in the prior art;

FIG. 4 is a flow chart illustrating a method of fabricating a polysilicon layer according to an embodiment of the present application;

fig. 5 to 7 are schematic structural diagrams illustrating a process of fabricating a polysilicon layer according to the present application.

Wherein the figures include the following reference numerals:

10. hydrogen explosion; 11. air bubbles; 12. a substrate; 13. an amorphous silicon layer; 14. a storage unit; 15. a channel layer; 16. a polysilicon layer.

Detailed Description

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

As described in the background art, in order to reduce the problem of defects formed during annealing of an amorphous silicon layer in the related art, such as the presence of hydrogen bursts 10 and bubbles 11 in the polycrystalline silicon layer shown in fig. 1 to 3, in an exemplary embodiment of the present application, a polycrystalline silicon layer, a method of fabricating the same, and a semiconductor device are provided.

According to an embodiment of the present application, a method for fabricating a polysilicon layer is provided. Fig. 4 is a flow chart of a method of fabricating a polysilicon layer according to an embodiment of the present application. As shown in fig. 4, the method comprises the steps of:

step S101, depositing an amorphous silicon layer 13 on the substrate 12 to form the structure shown in fig. 5;

step S102, as shown in fig. 6, implanting predetermined ions into the amorphous silicon layer 13 at a predetermined temperature to break Si — H bonds in the amorphous silicon layer 13 and make H overflow the amorphous silicon layer 13;

in step S103, the amorphous silicon layer 13 is annealed to form a polysilicon layer 16, as shown in fig. 7.

In the above method, first, an amorphous silicon layer 13 is deposited on a substrate 12; then, predetermined ions are implanted into the amorphous silicon layer 13 at a predetermined temperature; finally, the amorphous silicon layer 13 is annealed to form a polycrystalline silicon layer 16. In the method, Si-H bonds in the amorphous silicon layer are broken in an ion implantation mode, so that H overflows the amorphous silicon layer, and the generation of defects such as bubbles or peeling and the like caused by H aggregation due to high temperature in the subsequent annealing process is reduced or avoided, thereby reducing the defects formed in the annealing process of the amorphous silicon layer in the prior art.

In an embodiment of the present application, the predetermined ions include at least one of: he. P, C, Ge are provided. In this embodiment, the implanted ions may be He, P, C, Ge, or a mixture of several ions, but the energy of P, C, Ge is relatively weak, the number of broken Si-H bonds in the amorphous silicon layer is small, and P, C, Ge may remain in the amorphous silicon layer at a predetermined temperature, possibly affecting other properties of the device.

In yet another embodiment of the present application, the predetermined ion is He. The energy of He ions is high, the effect of breaking Si-H bonds in the amorphous silicon layer is good, and the He ions can overflow quickly at a preset temperature, so that no residue is left in the amorphous silicon layer, and other performances of the device are not affected.

In another embodiment of the present application, the predetermined temperature is 300 to 500 ℃. Under the condition that metal exists in the substrate, if the preset temperature is higher, the metal in the semiconductor structure is melted and flows, and therefore the electrical performance of the semiconductor device is reduced.

In another embodiment of the present application, the predetermined temperature is between 400 ℃ and 500 ℃. In order to obtain the amorphous silicon layer with fewer Si-H bonds and fewer predetermined ions, in the embodiment, the predetermined temperature is controlled to be 400-500 ℃, so that a better effect of injecting the predetermined ions, namely a relatively higher concentration, can be further ensured, more Si-H bonds can be further ensured to be broken, and the formation of defects such as hydrogen explosion or bubbles caused by high temperature in the subsequent annealing process can be better reduced.

In yet another embodiment of the present application, depositing an amorphous silicon layer 13 on a substrate 12 includes depositing an amorphous silicon material on the substrate 12 at a temperature of 420-450 ℃ to form the amorphous silicon layer 13. Under the condition that metal exists in the substrate, if the deposition temperature is high, the metal in the semiconductor structure is melted and flows, and therefore the electrical performance of the semiconductor device is reduced, therefore, the temperature adopted in the embodiment is 420-450 ℃, the situation that the metal is melted and flows due to high temperature can be relieved, and the deposition effect of the amorphous silicon layer can be guaranteed to be good in the temperature range.

In another embodiment of the present application, the annealing process performed on the amorphous silicon layer 13 includes at least one of the following steps: performing the annealing process on the amorphous silicon layer 13 by using a laser annealing method; the amorphous silicon layer 13 is subjected to the annealing treatment by a thermal annealing method. In this embodiment, the amorphous silicon layer may be optionally annealed, and the polysilicon layer may be formed by controlling the conditions of the annealing process.

If laser annealing is adopted, the annealing can be finished in a short time, and particularly, the polycrystalline silicon can be controlled and formed by adjusting the intensity and the irradiation time of laser. If the thermal annealing mode is adopted, the forming of the polysilicon can be controlled by adjusting the annealing temperature and the annealing time.

In another embodiment of the present application, the substrate 12 includes a memory cell 14, the memory cell 14 includes a channel layer 15, and the polysilicon layer 16 is located on a surface of the channel layer 15. Of course, the polysilicon layer is not limited to be deposited on the memory cell, and may be deposited on other semiconductor structures, and those skilled in the art can select the polysilicon layer according to actual situations.

The memory unit further comprises a substrate, a stacking structure and a channel hole structure, wherein the stacking structure is formed on the substrate, and the preparatory stacking structure comprises insulating medium layers and gates which are alternately arranged; the stacked structure has a channel hole abutting on the surface of the substrate; and an epitaxial layer is formed in the channel hole; the channel hole is also sequentially filled with the charge blocking layer, the charge trapping layer and the charge tunneling layer.

The material of each structural layer may also be any feasible material in the prior art, for example, the charge tunneling layer may be silicon dioxide, and the channel layer may be a polysilicon layer, and of course, the material of these structural layers may also be replaced by other suitable materials, which will not be described herein again.

It should be further noted that the material of the specific charge blocking layer may be any feasible material in the prior art, such as silicon dioxide, etc., and the formation manner of the charge blocking layer may also be any feasible manner in the prior art, and a person skilled in the art may select a suitable method and a suitable material according to practical situations to form the above-mentioned charge blocking layer of the present application. The material of the charge trapping layer includes at least one of a silicon oxide compound, a silicon nitride compound, a silicon oxynitride compound, and a high-K dielectric, but the material of the charge trapping layer is not limited thereto, and may be other suitable materials.

It should be noted that each step in the above-mentioned embodiment of forming the base structure can be implemented in a feasible manner in the prior art. The substrate in the base structure may be selected according to actual requirements of devices, and may include a silicon substrate, a germanium substrate, a sige substrate, an SOI substrate, or a GOI substrate, and may also be other substrates that are feasible in the prior art.

The insulating dielectric layer may be made of a material conventional in the art, for example, the insulating dielectric layer is a silicon dioxide layer.

These structural layers described above may be formed via one or more of Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Metal Organic Vapor Phase Epitaxy (MOVPE), Hydride Vapor Phase Epitaxy (HVPE), and/or other well-known crystal growth processes.

In another exemplary embodiment of the present application, a polysilicon layer is provided, which is formed by any one of the above-mentioned fabrication methods.

The above-mentioned polycrystalline silicon layer 16 is formed by any of the above-mentioned manufacturing methods, in which, first, an amorphous silicon layer 13 is deposited on a substrate 12; then, predetermined ions are implanted into the amorphous silicon layer 13 at a predetermined temperature; finally, the amorphous silicon layer 13 is annealed to form a polycrystalline silicon layer 16. In the method, Si-H bonds in the amorphous silicon layer are broken in an ion implantation mode, so that H overflows the amorphous silicon layer, and the generation of defects such as bubbles or peeling and the like caused by H aggregation due to high temperature in the subsequent annealing process is reduced or avoided, thereby reducing the defects formed in the annealing process of the amorphous silicon layer in the prior art. Therefore, because the polycrystalline silicon layer is manufactured by the method, the defects of bubbles or peeling and the like caused by H aggregation due to higher annealing temperature in the polycrystalline silicon layer are less.

In yet another exemplary embodiment of the present application, a semiconductor device is provided, which includes a polycrystalline silicon layer, which is the polycrystalline silicon layer described above.

The semiconductor device comprises a polycrystalline silicon layer 16, wherein the polycrystalline silicon layer 16 is formed by adopting any one of the manufacturing methods, and in the manufacturing method, firstly, an amorphous silicon layer 13 is deposited on a substrate 12; then, predetermined ions are implanted into the amorphous silicon layer 13 at a predetermined temperature; finally, the amorphous silicon layer 13 is annealed to form a polycrystalline silicon layer 16. In the method, Si-H bonds in the amorphous silicon layer are broken in an ion implantation mode, so that H overflows the amorphous silicon layer, and the generation of defects such as bubbles or peeling and the like caused by H aggregation due to high temperature in the subsequent annealing process is reduced or avoided, thereby reducing the defects formed in the annealing process of the amorphous silicon layer in the prior art. Therefore, because the semiconductor device comprises the polycrystalline silicon layer and the polycrystalline silicon layer is manufactured by the method, the defects of bubbles or peeling and the like caused by H aggregation due to higher annealing temperature in the semiconductor device are less.

The semiconductor device may be a 3D NAND memory, but may be another semiconductor device including polysilicon.

In order to make the technical solutions of the present application more clearly understood by those skilled in the art, the technical solutions of the present application will be described below with reference to specific embodiments.

Examples

In this embodiment, the polysilicon layer is formed on the surface of the memory cell, and specifically, the process of manufacturing the polysilicon layer includes:

as shown in fig. 5, an amorphous silicon material is deposited on the substrate 12 including the memory cell 14 at a temperature of 420-450 ℃ to form an amorphous silicon layer 13;

as shown in fig. 6, He ions are implanted into the amorphous silicon layer 13 at 400-500 ℃ to break Si-H bonds in the amorphous silicon layer 13 and make H overflow the amorphous silicon layer 13;

the amorphous silicon layer 13 is subjected to laser annealing treatment to form a polycrystalline silicon layer 16, as shown in fig. 7.

In the polycrystalline silicon layer, because Si-H bonds in the amorphous silicon layer are broken in an ion implantation mode, H overflows the amorphous silicon layer, and the generation of defects such as bubbles or peeling and the like caused by H aggregation due to high temperature in the subsequent annealing process is reduced or avoided, so that the defects formed in the annealing process of the amorphous silicon layer in the prior art are reduced.

From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:

1) the method for manufacturing the polycrystalline silicon layer comprises the steps of firstly, depositing an amorphous silicon layer on a substrate; then, under the predetermined temperature, implant the predetermined ion into the above-mentioned amorphous silicon layer; and finally, annealing the amorphous silicon layer to form a polycrystalline silicon layer. In the method, Si-H bonds in the amorphous silicon layer are broken in an ion implantation mode, so that H overflows the amorphous silicon layer, and the generation of defects such as bubbles or peeling and the like caused by H aggregation due to high temperature in the subsequent annealing process is reduced or avoided, thereby reducing the defects formed in the annealing process of the amorphous silicon layer in the prior art.

2) The polycrystalline silicon layer is formed by adopting any manufacturing method, and in the manufacturing method, firstly, an amorphous silicon layer is deposited on a substrate; then, under the predetermined temperature, implant the predetermined ion into the above-mentioned amorphous silicon layer; and finally, annealing the amorphous silicon layer to form a polycrystalline silicon layer. In the method, Si-H bonds in the amorphous silicon layer are broken in an ion implantation mode, so that H overflows the amorphous silicon layer, and the generation of defects such as bubbles or peeling and the like caused by H aggregation due to high temperature in the subsequent annealing process is reduced or avoided, thereby reducing the defects formed in the annealing process of the amorphous silicon layer in the prior art. Therefore, because the polycrystalline silicon layer is manufactured by the method, the defects of bubbles or peeling and the like caused by H aggregation due to higher annealing temperature in the polycrystalline silicon layer are less.

3) The semiconductor device comprises a polycrystalline silicon layer, wherein the polycrystalline silicon layer is formed by adopting any one of the manufacturing methods; then, under the predetermined temperature, implant the predetermined ion into the above-mentioned amorphous silicon layer; and finally, annealing the amorphous silicon layer to form a polycrystalline silicon layer. In the method, Si-H bonds in the amorphous silicon layer are broken in an ion implantation mode, so that H overflows the amorphous silicon layer, and the generation of defects such as bubbles or peeling and the like caused by H aggregation due to high temperature in the subsequent annealing process is reduced or avoided, thereby reducing the defects formed in the annealing process of the amorphous silicon layer in the prior art. Therefore, because the semiconductor device comprises the polycrystalline silicon layer, and the polycrystalline silicon layer is manufactured by the manufacturing method, the defects of bubbles or peeling and the like caused by H aggregation due to high annealing temperature in the semiconductor device are less.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.