阅读说明：本技术 半导体器件的形成方法 (Method for forming semiconductor device ) 是由 周飞 于 2020-05-28 设计创作，主要内容包括：一种半导体器件的形成方法,包括：基底,基底包括外围区与核心区,外围区上具有若干分立排布的第一沟道柱,核心区上具有若干分立排布的第二沟道柱；在基底上形成隔离层,隔离层覆盖第一沟道柱和第二沟道柱的部分侧壁；在核心区的隔离层上及第二沟道柱的侧壁和顶部上形成牺牲层,牺牲层的刻蚀速率大于隔离层的刻蚀速率；在牺牲层上、外围区的隔离层上以及第一沟道柱的侧壁和顶部上形成第一栅氧化层；形成图形化层,图形化层暴露出牺牲层上的第一栅氧化层；去除暴露出的第一栅氧化层和位于第一栅氧化层底部的牺牲层,至暴露出核心区的隔离层的表面及第二沟道柱的顶部和侧壁表面；以提升半导体器件的性能。(A method of forming a semiconductor device, comprising: the substrate comprises a peripheral area and a core area, wherein the peripheral area is provided with a plurality of first channel columns which are distributed in a discrete mode, and the core area is provided with a plurality of second channel columns which are distributed in a discrete mode; forming an isolation layer on the substrate, wherein the isolation layer covers partial side walls of the first channel column and the second channel column; forming sacrificial layers on the isolation layer of the core region and on the side wall and the top of the second channel column, wherein the etching rate of the sacrificial layers is greater than that of the isolation layer; forming a first gate oxide layer on the sacrificial layer, the isolation layer of the peripheral region and the side wall and the top of the first channel column; forming a patterning layer, wherein the first gate oxide layer on the sacrificial layer is exposed out of the patterning layer; removing the exposed first gate oxide layer and the sacrificial layer positioned at the bottom of the first gate oxide layer until the surface of the isolation layer of the core region and the top and side wall surfaces of the second channel column are exposed; to improve the performance of the semiconductor device.)

1. A method of forming a semiconductor device, comprising:

providing a substrate, wherein the substrate comprises a peripheral area and a core area, the peripheral area is provided with a plurality of first channel columns which are distributed in a discrete mode, and the core area is provided with a plurality of second channel columns which are distributed in a discrete mode;

forming an isolation layer on the substrate, wherein the isolation layer covers partial side walls of the first channel column and the second channel column;

forming a sacrificial layer on the isolation layer of the core region and on the side wall and the top of the second channel column, wherein the etching rate of the sacrificial layer is greater than that of the isolation layer;

forming a first gate oxide layer on the sacrificial layer, on the isolation layer of the peripheral region and on the side wall and the top of the first channel column;

forming a patterning layer, wherein the first gate oxide layer on the sacrificial layer is exposed out of the patterning layer;

and removing the exposed first gate oxide layer and the sacrificial layer positioned at the bottom of the first gate oxide layer until the surface of the isolation layer of the core region and the top and side wall surfaces of the second channel column are exposed.

2. The method for forming a semiconductor device according to claim 1, wherein a ratio of an etching rate of the sacrificial layer to an etching rate of the isolation layer is 10:1 to 100: 1.

3. The method for forming a semiconductor device according to claim 1, wherein a material of the isolation layer is silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride.

4. The method for forming a semiconductor device according to claim 1, wherein a material of the sacrificial layer is SiN, SiOCN, or SiBCN.

5. The method for forming a semiconductor device according to claim 1, wherein a process of forming the first gate oxide layer is an atomic layer deposition process or a thermal oxidation process.

6. The method of forming a semiconductor device according to claim 1, wherein said patterned layer is removed after removing said exposed first gate oxide layer and said sacrificial layer at the bottom of said first gate oxide layer to expose the surface of said isolation layer of said core region and the top and sidewall surfaces of said second channel pillar.

7. The method of forming a semiconductor device of claim 1, wherein forming a sacrificial layer on the isolation layer of the core region and on sidewalls and a top of the second channel pillar comprises:

forming an initial sacrificial layer on the isolation layer, the sidewall and the top surface of the first channel pillar, and the sidewall and the top surface of the second channel pillar;

and etching to remove the initial sacrificial layer on the isolation layer of the peripheral region and the top and the side wall of the first channel column, and forming a sacrificial layer on the isolation layer of the core region and the side wall and the top of the second channel column.

8. The method of forming a semiconductor device of claim 6, wherein after removing the patterned layer, a first gate structure is formed on the first channel pillar and a second gate structure is formed on the second channel pillar.

9. The method of forming a semiconductor device according to claim 1, wherein the base includes a substrate and a source doping layer formed on the substrate, and wherein the first channel column and the second channel column are formed on the source doping layer.

10. The method of forming a semiconductor device according to claim 9, further comprising forming a protective layer on top surfaces of the first channel pillar and the second channel pillar.

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor device.

Background

A Fin field effect transistor (Fin FET) is an emerging multi-gate device, which generally includes a Fin portion protruding from a surface of a semiconductor substrate, a gate structure covering a portion of a top surface and a sidewall of the Fin portion, and source-drain doped regions in the Fin portion located at both sides of the gate structure. Compared with a planar metal-oxide semiconductor field effect transistor, the fin type field effect transistor has stronger short channel inhibition capability and stronger working current.

With the further development of semiconductor technology, the size of integrated circuit devices is smaller and smaller, and the conventional fin field effect transistor has a limitation in further increasing the operating current. Specifically, only the region near the top surface and the sidewall in the fin is used as a channel region, so that the volume of the fin used as the channel region is small, which limits the increase of the operating current of the finfet. Therefore, a gate-all-around (GAA) structure fin field effect transistor is proposed, so that the volume of the fin field effect transistor used as a channel region is increased, and the working current of the gate-all-around structure fin field effect transistor is further increased.

However, the performance of the prior art finfet with a trench gate wrap-around structure is still to be improved.

Disclosure of Invention

The invention aims to provide a method for forming a semiconductor device, which can effectively improve the performance of the finally formed semiconductor device.

In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein the substrate comprises a peripheral area and a core area, the peripheral area is provided with a plurality of first channel columns which are distributed in a discrete mode, and the core area is provided with a plurality of second channel columns which are distributed in a discrete mode; forming an isolation layer on the substrate, wherein the isolation layer covers partial side walls of the first channel column and the second channel column; forming a sacrificial layer on the isolation layer of the core region and on the side wall and the top of the second channel column, wherein the etching rate of the sacrificial layer is greater than that of the isolation layer; forming a first gate oxide layer on the sacrificial layer, on the isolation layer of the peripheral region and on the side wall and the top of the first channel column; forming a patterning layer, wherein the first gate oxide layer on the sacrificial layer is exposed out of the patterning layer; and removing the exposed first gate oxide layer and the sacrificial layer positioned at the bottom of the first gate oxide layer until the surface of the isolation layer of the core region and the top and side wall surfaces of the second channel column are exposed.

Optionally, the ratio of the etching rate of the sacrificial layer to the etching rate of the isolation layer is 10: 1-100: 1.

Optionally, the isolation layer is made of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride.

Optionally, the material of the sacrificial layer is SiN, SiOCN or SiBCN.

Optionally, a process for forming the first gate oxide layer is an atomic layer deposition process or a thermal oxidation process.

Optionally, after removing the exposed first gate oxide layer and the sacrificial layer located at the bottom of the first gate oxide layer to expose the surface of the isolation layer of the core region, the top of the second channel pillar, and the sidewall surface, the patterning layer is removed.

Optionally, the step of forming a sacrificial layer on the isolation layer of the core region and on the sidewalls and the top of the second channel pillar includes: forming an initial sacrificial layer on the isolation layer, the sidewall and the top surface of the first channel pillar, and the sidewall and the top surface of the second channel pillar; and etching to remove the initial sacrificial layers on the isolation layer of the peripheral region and on the top and the side wall of the first channel column, and forming sacrificial layers on the isolation layer of the core region and on the side wall and the top of the second channel column.

Optionally, after removing the patterned layer, a second gate oxide layer is formed on the surface of the isolation layer of the core region and on the top and sidewalls of the second channel pillar.

Optionally, the base includes a substrate and a source doping layer formed on the substrate, and the first channel pillar and the second channel pillar are formed on the source doping layer.

Optionally, a protective layer is formed, and the protective layer is located on the top surfaces of the first channel column and the second channel column.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the process of removing the exposed first gate oxide layer and the sacrificial layer positioned at the bottom of the first gate oxide layer to expose the surface of the isolation layer of the core region and the top and side wall surfaces of the second channel column, on one hand, the surface of the isolation layer of the core region cannot be damaged due to the protection effect of the sacrificial layer in the process of removing the first gate oxide layer; in addition, in the process of removing the sacrificial layer, because the etching rate of the sacrificial layer is greater than that of the isolation layer, the surface of the isolation layer in the core region can be guaranteed not to be damaged or almost not to be damaged in the etching process, the surface quality of the isolation layer in the core region is improved, and therefore the quality of the formed semiconductor device is improved.

Drawings

Fig. 1 to 4 are schematic structural views of a semiconductor device;

fig. 5 to 12 are schematic structural diagrams of steps of a method for forming a semiconductor device according to an embodiment of the present invention.

Detailed Description

The performance of the channel gate surrounding structure finfet in the prior art needs to be improved. The following detailed description will be made in conjunction with the accompanying drawings.

Referring to fig. 1, a substrate 100 is provided, where the substrate 100 includes a core region I and a peripheral region II adjacent to each other, the peripheral region II has a first channel pillar 101 thereon, and the core region I has a second channel pillar 102 thereon.

Referring to fig. 2, an isolation layer 103 is formed on the substrate 100, the isolation layer 103 covers a portion of sidewall surfaces of the first channel pillar 101 and the second channel pillar 102, and a top surface of the isolation layer 103 is lower than top surfaces of the first channel pillar 101 and the second channel pillar 102.

Referring to fig. 3, after the isolation layer 103 is formed, a first gate oxide layer 104 is formed on the isolation layer 103, on sidewalls and a top of the first channel pillar 101, and on a top and sidewalls of the second channel pillar 102.

Referring to fig. 4, after forming the first gate oxide layer 104, the first gate oxide layer 104 on the isolation layer 103 of the core region I and on the top and sidewall of the second channel pillar 102 is removed until the surface of the isolation layer 103 of the core region I and the top and sidewall surface of the second channel pillar 102 are exposed.

The inventors have found that when the first gate oxide layer 104 on the isolation layer 103 of the core region I and on the top and sidewall of the second channel pillar 102 is removed to expose the surface of the isolation layer 103 of the core region I and the top and sidewall of the second channel pillar 102, a portion of the isolation layer 103 on the core region I is removed at the same time, so that the surface of the isolation layer 103 is damaged, and thus, when a device is formed in the core region I, the performance of the device is deteriorated.

The inventor researches and discovers that in the process of removing the exposed first gate oxide layer and the sacrificial layer positioned at the bottom of the first gate oxide layer to expose the surface of the isolation layer of the core region and the top and side wall surfaces of the second channel column, on one hand, the surface of the isolation layer of the core region is not damaged in the process of removing the first gate oxide layer by utilizing the protection effect of the sacrificial layer; on the other hand, when the sacrificial layer is removed, the etching rate of the sacrificial layer is greater than that of the isolation layer, so that the surface of the isolation layer in the core region can be prevented from being damaged or hardly damaged in the etching process, the surface quality of the isolation layer in the core region is improved, and the electrical performance of the finally formed semiconductor device is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 5 to 12 are schematic structural diagrams of a process of forming a semiconductor device according to an embodiment of the present invention.

Referring to fig. 5, a substrate 200 is provided, the substrate 200 includes a peripheral region II and a core region I, the peripheral region II has a first channel pillar 201 thereon, and the core region I has a second channel pillar 202 thereon.

The base includes a substrate 203 and a source doping layer 204 formed on the substrate 203, and the first channel pillar 201 and the second channel pillar 202 are formed on the source doping layer 204.

In this embodiment, the substrate 203 is a silicon substrate; in other embodiments, the substrate may also be a semiconductor substrate such as a germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.

The source doped layer 204 is a source of the semiconductor device. The source doping layer 204 has doping ions therein, and the type of the doping ions is N-type or P-type; the N-type ions comprise phosphorus ions or arsenic ions; the P-type ions include boron ions or indium ions.

In this embodiment, the forming process of the source doping layer 204 includes an ion implantation process, and the method of the ion implantation process includes: the substrate 203 is ion-implanted to form the source doping layer 204.

In other embodiments, the formation process of the source doping layer may further adopt an in-situ doping process, and the method of the in-situ doping process includes: and forming an epitaxial layer on the substrate, and carrying out in-situ doping on the epitaxial layer to form the source doping layer.

The method for forming the first channel pillar 201 and the second channel pillar 202 includes: forming a channel material layer (not shown) on the source doping layer 204; forming a first mask layer (not shown) on the surface of the channel material layer, wherein the first mask layer exposes a part of the surface of the channel material layer; and etching the channel material layer by taking the first mask layer as a mask until the surface of the source doping layer 204 is exposed, and forming the first channel column 201 and the second channel column 202 on the source doping layer 204, wherein the first channel column 201 is positioned on the peripheral region II, and the second channel column 202 is positioned on the core region I.

In this embodiment, the process of etching the channel material layer includes a dry etching process.

In the present embodiment, the material of the first channel pillar 201 and the second channel pillar 202 includes silicon; in other embodiments, the material of the first channel pillar and the second channel pillar may further include a semiconductor material such as germanium, silicon germanium, gallium arsenide, or the like.

In this embodiment, the process of forming the channel material layer includes an epitaxial growth process; in other embodiments, the process of forming the channel material layer includes a physical vapor deposition process or an atomic layer deposition process.

In this embodiment, the material of the first mask layer includes a photoresist; in other embodiments, the material of the first mask layer comprises a hard mask material comprising silicon oxide or silicon nitride.

In this embodiment, the process of forming the first mask layer is a spin-on process.

After the first channel pillar 201 and the second channel pillar 202 are formed, the first mask layer is removed. In this embodiment, the process of removing the first mask layer includes an ashing process.

In this embodiment, a protective layer 205 is further formed on the top surfaces of the first channel pillar 201 and the second channel pillar 202.

In this embodiment, the material of the protection layer 205 is silicon nitride.

The protective layer 205 is used to protect the top surfaces of the first channel pillar 201 and the second channel pillar 202 from being damaged in a subsequent process.

In this embodiment, the finfet formed in the periphery region II is used to form an input/output circuit, and the finfet formed in the core region I is used to form a core device of an integrated circuit.

In this embodiment, the peripheral region II and the core region I are adjacent.

Referring to fig. 6, an isolation layer 206 is formed on the substrate 200, wherein the isolation layer 206 covers a portion of sidewalls of the first trench pillar 201 and the second trench pillar 202.

The isolation layer 206 is used to electrically isolate the device.

The method for forming the isolation layer 206 includes: forming an initial isolation layer (not shown) on the substrate 203, the initial isolation layer covering the top and sidewalls of the first and second channel pillars 201 and 202; planarizing the initial isolation layer until top surfaces of the first and second channel pillars 201 and 202 are exposed; after the planarization process, portions of the initial isolation layer are etched to form the isolation layer 206.

The material of the isolation layer 206 includes silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride; the process for forming the initial isolation layer comprises a chemical vapor deposition process or an atomic layer deposition process or a physical vapor deposition process.

In the present embodiment, the material of the isolation layer 206 includes silicon oxide; the process for forming the initial isolation material layer comprises a chemical vapor deposition process, particularly a flowable chemical vapor deposition process, wherein the flowable chemical vapor deposition process can form the initial isolation layer with a compact structure.

A sacrificial layer 207 is formed on the isolation layer 206 of the core region I and on the sidewalls and the top of the second channel pillar 202, and an etching rate of the sacrificial layer 207 is greater than an etching rate of the isolation layer 206.

The step of forming the sacrificial layer 207 on the isolation layer 206 of the core region and on the sidewalls and top of the second channel pillar 202 is described with reference to fig. 7-8.

Referring to fig. 7, an initial sacrificial layer 214 is formed on the isolation layer 206, the sidewalls and the top surface of the first channel pillar 201, and the sidewalls and the top surface of the second channel pillar 202.

In this embodiment, the material of the initial sacrificial layer 214 is silicon nitride; in other embodiments, the material of the initial sacrificial layer 214 may also be SiOCN or SiBCN.

In this embodiment, the process of forming the initial sacrificial layer 214 is an Atomic Layer Deposition (ALD), and specific parameters include: by SiH₂Cl₂Or NH₃The reaction gas has the flow rate of 1000 sccm-5000 sccm, the reaction temperature of 200-600 ℃, the reaction pressure of 10-150 mTorr and the reaction period of 15-100 s.

In the present embodiment, the process of forming the initial sacrificial layer 214 is an Atomic Layer Deposition (ALD) process, because the ALD process can form the initial sacrificial layer 214 with better thickness uniformity, and the formation thickness of the initial sacrificial layer 214 is better controlled.

Referring to fig. 8, the initial sacrificial layer 214 on the isolation layer 206 of the peripheral region II and on the top and sidewalls of the first channel pillar 201 is removed by etching, and a sacrificial layer 207 is formed on the isolation layer 206 of the core region I and on the sidewalls and top of the second channel pillar 202.

In this embodiment, the process of removing the initial sacrificial layer 214 on the isolation layer 206 of the peripheral region II and on the top and the sidewall of the first channel pillar 201 by etching is a wet etching process; in other embodiments, the process of etching to remove the initial sacrificial layer 214 on the isolation layer 206 of the peripheral region II and on the top and the sidewall of the first channel pillar 201 may also be a dry etching process.

In the present embodiment, the reason why the wet etching process is adopted is that the wet etching process has a higher selective etching ratio.

In this embodiment, the thickness of the sacrificial layer 207 isToWhen the thickness of the sacrificial layer 207 is less thanThe sacrificial layer 207 cannot effectively protect the second channel pillar; when the thickness of the sacrificial layer 207 is larger thanThe space between adjacent channel columns is smaller, the subsequent process window is smaller, and the process difficulty is increased.

In this embodiment, the initial sacrificial layer 214 on the isolation layer 206 of the peripheral region II and on the top and the sidewall of the first channel pillar 201 is removed by etching, and in the process of forming the sacrificial layer 207 on the isolation layer 206 of the core region I and on the sidewall and the top of the second channel pillar 202, since the etching rate of the sacrificial layer 207 is greater than that of the isolation layer 206, in the process of removing the initial sacrificial layer 214 on the isolation layer 206 of the peripheral region II and on the top and the sidewall of the first channel pillar 201, the damage to the isolation layer 206 of the peripheral region II is very small or almost zero, so as to ensure the surface quality of the isolation layer 206 of the peripheral region II, thereby preparing for forming a good-quality semiconductor device subsequently.

Referring to fig. 9, a first gate oxide layer 208 is formed on the sacrificial layer 207, on the isolation layer 206 of the peripheral region II, and on sidewalls and a top of the first channel pillar 201.

In this embodiment, a first gate oxide layer 208 is formed on the exposed top and sidewalls of the first channel pillar 201, on the isolation layer 206 of the peripheral region II, and on the sacrificial layer 207 of the core region I.

In the present embodiment, the material of the first gate oxide layer 208 includes silicon oxide.

In this embodiment, the forming process of the first gate oxide layer 208 is an atomic layer deposition process; in other embodiments, the first gate oxide layer 208 may be formed by a thermal oxidation process.

Referring to fig. 10, a patterning layer 209 is formed, and the patterning layer 209 exposes the first gate oxide layer 208 on the sacrificial layer 207.

In this embodiment, a patterning layer 209 is formed on the substrate 200, and the patterning layer 209 exposes the surface of the first gate oxide layer 208 of the core region I.

In this embodiment, the patterning layer 209 is a photoresist.

In the present embodiment, the patterning layer 209 can serve to protect the first gate oxide layer 208 on the sidewall and the top of the first channel pillar 201 and the first gate oxide layer 208 on the isolation layer 206 of the peripheral region II in a subsequent process.

Referring to fig. 11, the exposed first gate oxide layer 208 and the sacrificial layer 207 at the bottom of the first gate oxide layer 208 are removed to expose the surface of the isolation layer 206 of the core region I and the top and sidewall surfaces of the second channel pillar 202.

In this embodiment, the process of removing the exposed first gate oxide layer 208 and the sacrificial layer 207 located at the bottom of the first gate oxide layer 208 is a wet etching process.

In other embodiments, the process of removing the exposed first gate oxide layer 208 and the sacrificial layer 207 at the bottom of the first gate oxide layer 208 may also be a dry etching process.

In this embodiment, the first gate oxide layer 208 and the sacrificial layer 207 are removed in one etching process, which facilitates cost saving and etching quality control.

In this embodiment, the ratio of the etching rate of the sacrificial layer 207 to the etching rate of the isolation layer 206 is 10:1 to 100: 1.

In this embodiment, during the process of removing the exposed first gate oxide layer 208 and the sacrificial layer 207 located at the bottom of the first gate oxide layer 208, on one hand, during the process of removing the first gate oxide layer 208, since the sacrificial layer 207 is provided on the top and sidewall surfaces of the first channel pillar 201 and on the isolation layer 206 of the core region I, the surfaces of the first channel pillar 201 and the isolation layer 206 of the core region I are not damaged during the process of removing the first gate oxide layer 208; meanwhile, in the process of removing the sacrificial layer 207, since the etching rate of the sacrificial layer 207 is greater than that of the isolation layer 206, an etching reaction basically acts on the sacrificial layer 207 in the etching process, and the isolation layer 206 hardly undergoes a chemical reaction, so that the quality of the isolation layer 206 on the core region I is ensured, the surface of the isolation layer 206 is not damaged in the etching process, and the quality of a finally formed semiconductor device is improved.

In this embodiment, after removing the exposed first gate oxide layer 208 and the sacrificial layer 207 located at the bottom of the first gate oxide layer 208 to expose the surface of the isolation layer 206 of the core region I and the top and sidewall surfaces of the second channel pillar 202, the patterning layer 209 is removed.

In this embodiment, the process of removing the patterned layer 209 is an ashing process.

Referring to fig. 12, after removing the patterning layer 209, a first gate structure 210 is formed on the first channel pillar 201; a second gate structure 211 is formed over the second channel pillar 202.

The first gate structure 210 and the second gate structure 211 respectively include a gate dielectric layer 212 located on the sidewalls of the first trench pillar 201 and the second trench pillar 202, a work function layer 213 located on the surface of the gate dielectric layer, and a gate layer (not labeled) located on the surface of the work function layer.

In this embodiment, an interfacial layer (not shown) is formed on the sidewalls and top of the second channel pillar 202 before the gate dielectric layer 212 is formed.

In this embodiment, the material of the gate dielectric layer 212 includes a high-k material, and the dielectric constant of the high-k material is greater than 3.9; the high dielectric constant material comprises hafnium oxide or aluminum oxide; in other embodiments, the material of the gate dielectric layer 212 includes silicon oxide.

In this embodiment, the process of forming the gate dielectric material layer includes a chemical vapor deposition process; in other embodiments, the process of forming the gate dielectric material layer includes an atomic layer deposition process.

The material of the work function layer 213 includes titanium nitride, titanium aluminum, or tantalum nitride.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.