阅读说明：本技术 一种准垂直结构射频器件及制作方法 (Quasi-vertical structure radio frequency device and manufacturing method ) 是由 祝杰杰 马晓华 张颖聪 杨凌 侯斌 郝跃 于 2021-07-29 设计创作，主要内容包括：本发明涉及一种准垂直结构射频器件及制作方法,该器件包括基区、基极、发射区、第一钝化层、第二钝化层和发射极,其中,发射区和第一钝化层形成第二台阶；第二钝化层覆盖第一钝化层的部分表面以形成靠近第一台阶的第一台面,位于第二台阶上的第二钝化层的表面形成发射极台面；基极的底部贯穿第二钝化层且位于基区上,基极的侧面与第二台阶侧面的第二钝化层接触,基极的顶部位于第一台面上且位于发射极台面上。该器件中基极搭上发射极台面,最大限度缩小了基极与发射极台面间横向距离,降低了基极串联总电阻,实现了晶体管工作性能的提升。(The invention relates to a quasi-vertical structure radio frequency device and a manufacturing method thereof, wherein the device comprises a base region, a base electrode, an emitter region, a first passivation layer, a second passivation layer and an emitter electrode, wherein the emitter region and the first passivation layer form a second step; the second passivation layer covers part of the surface of the first passivation layer to form a first mesa close to the first step, and the surface of the second passivation layer on the second step forms an emitter mesa; the bottom of the base electrode penetrates through the second passivation layer and is located on the base region, the side face of the base electrode is in contact with the second passivation layer on the side face of the second step, and the top of the base electrode is located on the first table top and on the emitter table top. The base electrode in the device is lapped on the emitter electrode table top, so that the transverse distance between the base electrode and the emitter electrode table top is reduced to the maximum extent, the total resistance of the base electrode in series connection is reduced, and the working performance of the transistor is improved.)

1. A quasi-vertical structure radio frequency device, comprising: a base region (5), a base electrode (6), an emitter region (7), a first passivation layer (9), a second passivation layer (10) and an emitter electrode (11), wherein,

the base region (5), the emitter region (7) and the first passivation layer (9) are sequentially stacked, the base region (5) forms a first step, and the emitter region (7) and the first passivation layer (9) form a second step;

the second passivation layer (10) covers the surface of the first step and the surface of the second step, the second passivation layer (10) covers part of the surface of the first passivation layer (9) to form a first mesa close to the first step, and the surface of the second passivation layer (10) on the second step forms an emitter mesa;

the bottom of the emitter (11) penetrates through the first passivation layer (9) and the second passivation layer (10), and the top of the emitter (11) is located on the emitter mesa;

the bottom of the base electrode (6) penetrates through the second passivation layer (10) and is located on the base region (5), the side face of the base electrode (6) is in contact with the second passivation layer (10) on the side face of the second step, and the top of the base electrode (6) is located on the first table top and on the emitter table top.

2. The quasi-vertical structure radio frequency device of claim 1, further comprising: a substrate (1), an n + GaN layer (2), a collector (3) and a collector region (4), wherein,

the substrate (1), the n + GaN layer (2), the collector region (4) and the base region (5) are sequentially stacked, a collector mesa is formed on the surface of the n + GaN layer (2), and the collector region (4) and the base region (5) jointly form the first step;

the second passivation layer (10) also covers the collector mesa;

the bottom of the collector (3) penetrates through the second passivation layer (10) and is located on the collector mesa, and the top of the collector (3) is located on the second passivation layer (10) on the collector mesa;

the collector (3) is located in the center of the device, and the emitter (11) is located on the periphery of the device.

3. The quasi-vertical structure radio frequency device of claim 1, further comprising: a substrate (1), an n-type GaAs layer (2), a collector (3) and a collector region (4), wherein,

the substrate (1), the n-type GaAs layer (2), the collector region (4) and the base region (5) are sequentially stacked, a collector mesa is formed on the surface of the n-type GaAs layer (2), and the collector region (4) and the base region (5) jointly form the first step;

the second passivation layer (10) also covers the collector mesa;

the bottom of the collector (3) penetrates through the second passivation layer (10) and is located on the collector mesa, and the top of the collector (3) is located on the second passivation layer (10) on the collector mesa;

the collector (3) is positioned at the periphery of the device, and the emitter (11) is positioned at the center of the device.

4. The quasi-vertical structure radio frequency device of claim 1, further comprising: a substrate (1), a collector (3) and a collector region (4), wherein,

the substrate (1), the collector region (4) and the base region (5) are sequentially stacked, and a collector mesa is formed on the collector region (4);

the second passivation layer (10) also covers the collector mesa;

the bottom of the collector (3) penetrates through the second passivation layer (10) and is located on the collector mesa, and the top of the collector (3) is located on the second passivation layer (10) on the collector mesa;

the collector (3) is located at one end of the device and the emitter (11) is located at the other end of the device.

5. Quasi-vertical structure radio frequency device according to any of claims 1 to 4, further comprising a cap layer (8), wherein,

the cap layer (8) is located between the emitter region (7) and the first passivation layer (9), forming a second step together with the emitter region (7) and the first passivation layer (9).

6. A structure design and manufacturing method of a quasi-vertical structure radio frequency device is characterized by comprising the following steps:

s1, manufacturing a device active region electrical isolation on an epitaxial substrate, wherein the epitaxial substrate comprises a base region (5) and an emitter region (7) which are sequentially stacked;

s2, depositing a first passivation layer (9) on the emitter region (7);

s3, sequentially etching the first passivation layer (9) and the emitter region (7) in the base region pattern to enable the emitter region (7) and the first passivation layer (9) to form a second step and form a base region on the base region (5);

s4, sequentially etching the first passivation layer (9), the emitter region (7) and the base region (5) in the pattern of the collector region to enable the base region (5) to form a first step and form the collector region of the device;

s5, depositing a second passivation layer (10) on the surface of the device where the base region and the collector region are formed, wherein the second passivation layer (10) on the second step forms an emitter mesa;

s6, etching a portion of the second passivation layer (10) on the base region (5) in the base region and a portion of the second passivation layer (10) at the side of the emitter mesa, forming a base aperture such that the second passivation layer (10) covers a portion of the surface of the first passivation layer (9) to form a first mesa adjacent to the first step, and etching a portion of the second passivation layer (10) in the collector region, forming a collector aperture;

s7, etching part of the second passivation layer (10) and part of the first passivation layer (9) of the emitter mesa to form an emitter opening;

s8, simultaneously manufacturing an emitter (11), a base (6) and a collector (3) in the base opening, the collector opening and the emitter opening.

7. The method for manufacturing a quasi-vertical structure radio frequency device according to claim 6, wherein the epitaxial substrate further comprises a substrate (1), an n + GaN layer (2) and a collector region (4), the substrate (1), the n + GaN layer (2), the collector region (4) and the base region (5) are sequentially stacked, and the step S4 comprises:

sequentially etching the first passivation layer (9), the emitter region (7), the base region (5) and the collector region (4) of the collector region pattern to form a collector region on the n + GaN layer (2);

the base region (5) and the collector region (4) jointly form the first step, the collector (3) is located in the center of the device, and the emitter (11) is located on the periphery of the device.

8. The method for manufacturing a quasi-vertical structure radio frequency device according to claim 6, wherein the epitaxial substrate further comprises a substrate (1), an n-type GaAs layer (2) and a collector region (4), the substrate (1), the n-type GaAs layer (2), the collector region (4) and the base region (5) are sequentially stacked, and the step S4 comprises:

sequentially etching the first passivation layer (9), the emitter region (7), the base region (5) and the collector region (4) of the pattern of the collector region to form a collector region on the n-type GaAs layer (2);

the base region (5) and the collector region (4) jointly form the first step, the collector (3) is located on the periphery of the device, and the emitter (11) is located in the center of the device.

9. The method for manufacturing a quasi-vertical structure radio frequency device according to claim 6, wherein the epitaxial substrate further comprises a substrate (1) and a collector region (4), the substrate (1), the collector region (4) and the base region (5) are sequentially stacked, and the step S4 comprises:

sequentially etching the first passivation layer (9), the emitter region (7) and the base region (5) of the collector region pattern to form a collector region on the collector region (4);

the base region (5) forms a first step, the collector (3) is located at one end of the device, and the emitter (11) is located at the other end of the device.

10. The method for manufacturing a radio frequency device with a quasi-vertical structure according to any one of claims 6 to 9, wherein the epitaxial substrate further comprises a cap layer (8), wherein the cap layer (8) is located between the emitter region (7) and the first passivation layer (9) and forms a second step together with the emitter region (7) and the first passivation layer (9).

Technical Field

The invention belongs to the technical field of semiconductor devices, and particularly relates to a radio frequency device with a quasi-vertical structure and a manufacturing method thereof.

Background

At present, the field of High frequency devices mainly uses horizontal structure devices, such as High Electron Mobility Transistor (HEMT) devices, and the horizontal structure devices can obtain High-concentration two-dimensional electron gas due to self spontaneous polarization and piezoelectric polarization effects, so that coulomb scattering of carriers caused by a large amount of ionized donors or acceptors introduced by doping is avoided, and the mobility of the carriers is improved, and thus great development is achieved in the past. However, for power devices, in order to obtain higher current density and larger breakdown voltage, the lateral size of the device must be continuously increased, but the increase in the size of the device causes additional loss, and also causes additional difficulty for realizing large-scale integrated circuits. The transport direction of electrons in the lateral transistor is parallel to the conductive path, its inherent current gain and cut-off frequency f_TLimited by gate length and saturation velocity. In addition, horizontal structure devices currently face the problems of current collapse, enhancement, package compatibility, reliability, high voltage endurance, etc., which hinder their application and further development. Vertical structure devices have the following advantages over horizontal structures: higher breakdown voltage and forward working current without increasing chip area; better expandability and heat dissipation; is not affected by the surface state. But the vertical structure requires extremely high substrate quality due to the need to form electrode contacts at the bottom of the device.

For the above reasons, the quasi-vertical structure device combines the advantages of high concentration of two-dimensional electron gas of horizontal structure and high breakdown voltage of vertical structure, and does not require substrate material of too high quality, so that it has gained attention in recent years. The quasi-vertical structure transistor is mainly a bipolar transistor, such as a Heterojunction Bipolar Transistor (HBT) and a Bipolar Junction Transistor (BJT), because the HBTs and the BJTs are bipolar devices, the HBTs and the BJTs have substantially the same operation principle, but have a great difference in material system and doping characteristics, the BJT devices are mainly based on silicon-based materials, and the HBTs can use compound semiconductor materials, which have a larger forbidden bandwidth and higher electron mobility and electron saturation speed than silicon materials. Compared with a lateral device such as an HEMT (high electron mobility transistor), a quasi-vertical bipolar transistor such as an HBT (heterojunction bipolar transistor) has the inherent advantages of good linearity, high current, high power density and the like, is very suitable for manufacturing high-power and high-frequency microwave power devices, and the inherent delay of the quasi-vertical bipolar transistor is not limited by the electron speed.

A Thermo electronic transistor (HET) based on a compound semiconductor material is a unipolar multi-sub device with a quasi-vertical structure, the structure of which is similar to that of a bipolar transistor, the device structure of which is generally composed of an emitter region, a base region and a collector region, and the basic working principle of the HET is that high-energy hot electrons are injected from an emitter, pass through the base region in a near-ballistic transport mode, and finally reach the collector region to be collected. Since high-energy hot electrons have a high velocity (near ballistic transport) when passing through the base region, the device has a good frequency characteristic, and the thickness of the base region must be in the order of several nanometers to prevent elastic scattering and relaxation of the thermally injected electrons.

In the quasi-vertical structure device, the total base region resistance is the series combination of Rc (contact resistance) and Rsheet (surface resistance), because etching of the base region mesa causes a large transverse distance to exist between the base and the emitter region mesa, which generally causes large base region surface resistance (Rsheet), thereby causing large base region series total resistance, and the existence of the large base region resistance causes the highest oscillation frequency f of the quasi-vertical structure device_maxAnd the noise coefficient is seriously influenced, and the working performance of the device is greatly reduced.

In the prior quasi-vertical structure device, the doping concentration of a base region is mainly increased to improve the carrier concentration of the base region so as to reduce the transverse resistance; in addition, for example, a self-alignment process is adopted in the BJT device, so that the self-alignment of the emitter and the P-type base region is realized, and the lower base region resistance is achieved. The carrier mobility is reduced in bipolar transistors (HBT, BJT) by increasing the base region doping concentration, the minority carrier recombination rate is increased, the base region electron scattering effect is aggravated due to too high base region doping concentration in the HET device, and the current gain of the transistor is reduced; moreover, increasing the doping concentration is not friendly to the technology that is not mature for the doping process of compound semiconductors and the like; in addition, the process procedure of the self-alignment process is complicated, and the process difficulty in manufacturing the device is increased.

In summary, reducing the lateral distance between the base and the emitter mesa to reduce the base resistance is a key issue for achieving high frequency operation of the quasi-vertical device.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a quasi-vertical structure rf device and a manufacturing method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:

the embodiment of the invention provides a quasi-vertical structure radio frequency device, which comprises: a base region, a base electrode, an emitter region, a first passivation layer, a second passivation layer, and an emitter electrode, wherein,

the base region, the emitter region and the first passivation layer are sequentially stacked, the base region forms a first step, and the emitter region and the first passivation layer form a second step;

the second passivation layer covers the surface of the first step and the surface of the second step, the second passivation layer covers part of the surface of the first passivation layer to form a first mesa close to the first step, and the surface of the second passivation layer on the second step forms an emitter mesa;

the bottom of the emitter penetrates through the first passivation layer and the second passivation layer, and the top of the emitter is located on the emitter mesa;

the bottom of the base electrode penetrates through the second passivation layer and is located on the base region, the side face of the base electrode is in contact with the second passivation layer on the side face of the second step, and the top of the base electrode is located on the first table top and on the emitter table top.

In one embodiment of the present invention, further comprising: a substrate, an n + GaN layer, a collector, and a collector region, wherein,

the substrate, the n + GaN layer, the collector region and the base region are sequentially stacked, a collector mesa is formed on the surface of the n + GaN layer, and the collector region and the base region jointly form the first step;

the second passivation layer also covers the collector mesa;

the bottom of the collector penetrates through the second passivation layer and is positioned on the collector mesa, and the top of the collector is positioned on the second passivation layer on the collector mesa;

the collector is located at the center of the device, and the emitter is located at the periphery of the device.

In one embodiment of the present invention, further comprising: a substrate, an n-type GaAs layer, a collector, and a collector region, wherein,

the substrate, the n-type GaAs layer, the collector region and the base region are sequentially stacked, a collector mesa is formed on the surface of the n-type GaAs layer, and the collector region and the base region jointly form the first step;

the second passivation layer also covers the collector mesa;

the bottom of the collector penetrates through the second passivation layer and is positioned on the collector mesa, and the top of the collector is positioned on the second passivation layer on the collector mesa;

the collector is located at the periphery of the device, and the emitter is located at the center of the device.

In one embodiment of the present invention, further comprising: a substrate, a collector, and a collector region, wherein,

the substrate, the collector region and the base region are sequentially stacked, and a collector electrode mesa is formed on the collector region;

the second passivation layer also covers the collector mesa;

the bottom of the collector penetrates through the second passivation layer and is positioned on the collector mesa, and the top of the collector is positioned on the second passivation layer on the collector mesa;

the collector is located at one end of the device and the emitter is located at the other end of the device.

In one embodiment of the present invention, further comprising a cap layer, wherein,

the cap layer is positioned between the emitter region and the first passivation layer, and forms a second step together with the emitter region and the first passivation layer.

Another embodiment of the present invention provides a method for manufacturing a radio frequency device with a quasi-vertical structure, including the steps of:

s1, manufacturing a device active region electrical isolation on an epitaxial substrate, wherein the epitaxial substrate comprises a base region and an emitter region which are sequentially stacked;

s2, depositing a first passivation layer on the emitting region;

s3, sequentially etching the first passivation layer and the emitter region in the base region pattern to form a second step on the emitter region and the first passivation layer and form a base region on the base region;

s4, sequentially etching the first passivation layer, the emitter region and the base region in the pattern of the collector region to enable the base region to form a first step and form a collector region of the device;

s5, depositing a second passivation layer on the surface of the device where the base region and the collector region are formed, wherein the second passivation layer on the second step forms an emitter mesa;

s6, etching a part of the second passivation layer on the base region in the base region and a part of the second passivation layer on the side edge of the emitter mesa to form a base opening, enabling the second passivation layer to cover a part of the surface of the first passivation layer to form a first mesa close to the first step, and etching a part of the second passivation layer in the collector region to form a collector opening;

s7, etching part of the second passivation layer and part of the first passivation layer of the emitter mesa to form an emitter opening;

s8, simultaneously manufacturing an emitter, a base and a collector in the base opening, the collector opening and the emitter opening.

In an embodiment of the present invention, the epitaxial substrate further includes a substrate, an n + GaN layer, and a collector region, the substrate, the n + GaN layer, the collector region, and the base region are sequentially stacked, and step S4 includes:

sequentially etching the first passivation layer, the emitter region, the base region and the collector region of the collector region pattern to form a collector region on the n + GaN layer;

the base region and the collector region jointly form the first step, the collector is located in the center of the device, and the emitter is located on the periphery of the device.

In an embodiment of the present invention, the epitaxial substrate further includes a substrate, an n-type GaAs layer, and a collector region, the substrate, the n-type GaAs layer, the collector region, and the base region being sequentially stacked, and step S4 includes:

sequentially etching the first passivation layer, the emitter region, the base region and the collector region of the pattern of the collector region to form a collector region on the n-type GaAs layer;

the base region and the collector region jointly form the first step, the collector is located on the periphery of the device, and the emitter is located in the center of the device.

In an embodiment of the present invention, the epitaxial substrate further includes a substrate and a collector region, the substrate, the collector region and the base region are sequentially stacked, and step S4 includes:

sequentially etching the first passivation layer, the emitter region and the base region of the collector region pattern to form a collector region on the collector region;

the base region forms a first step, the collector electrode is located at one end of the device, and the emitter electrode is located at the other end of the device.

In one embodiment of the present invention, the epitaxial substrate further includes a cap layer, wherein the cap layer is located between the emitter region and the first passivation layer, and forms a second step together with the emitter region and the first passivation layer.

Compared with the prior art, the invention has the beneficial effects that:

1. in the quasi-vertical structure radio frequency device, one side of the top of the base electrode is positioned on the first table top and the emitter table top, so that the base electrode metal is lapped on the emitter table top, the transverse distance between the base electrode and the emitter table top is reduced to the maximum extent, the surface resistance of the base region is reduced, the total resistance of the base electrode in series connection is reduced, and the working performance of a transistor is improved on the premise of not changing the parameter design of the device and not increasing the process difficulty.

2. The manufacturing method of the invention deposits the first passivation layer first and then deposits the second passivation layer, thereby realizing that the base metal is close to the emitter mesa, reducing the total resistance of the base-region series connection to the maximum extent, having lower process difficulty and being easy to realize.

Drawings

Fig. 1 is a schematic structural diagram of a radio frequency device with a quasi-vertical structure according to an embodiment of the present invention;

fig. 2 is a schematic flowchart of a method for manufacturing a radio frequency device with a quasi-vertical structure according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a gan-based hot electron transistor device HET according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a gallium arsenide-based heterojunction bipolar transistor HBT according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a BJT according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Example one

Referring to fig. 1, fig. 1 is a schematic structural diagram of a radio frequency device with a quasi-vertical structure according to an embodiment of the present invention. The device comprises a base region 5, a base 6, an emitter region 7, a first passivation layer 9, a second passivation layer 10 and an emitter 11.

Specifically, the emitter region 7 is located on the base region 5; a first passivation layer 9 is located on the emitter region 7, the base region 5 forms a first step, and the emitter region 7 and the first passivation layer 9 form a second step.

The second passivation layer 10 covers the surface of the first step and the surface of the second step, the second passivation layer 10 covers part of the surface of the first passivation layer 9 to form a first mesa close to the first step, and the surface of the second passivation layer 10 on the second step forms an emitter mesa; that is, the second passivation layer 10 covers the upper surface of the base region 5, the side surface of the emitter region 7, and the upper surface and the side surface of the first passivation layer 9, and the surface of the second passivation layer 10 on the surface of the first passivation layer 9 and the side surface thereof forms a first mesa close to the first step, and the second passivation layer 10 on the upper surface of the first passivation layer 9 forms an emitter mesa.

The emitter 11 is in a T-shaped structure with its bottom portion penetrating the first passivation layer 9 and the second passivation layer 10 and contacting the emitter region 7, and the top portion of the emitter 11 being located on the emitter mesa.

The bottom of the base electrode 6 penetrates through the second passivation layer 10 and is located on the base region 5, one side face of the base electrode 6 is in contact with the second passivation layer 10 located on the side face of the second step, and the top of the base electrode 6 is located on the first table top and is located on the table top of the emitter electrode, so that a structure that the base electrode 6 is overlapped with the table top of the emitter electrode is formed.

In the quasi-vertical structure radio frequency device, one side of the top of the base is positioned on the first table top and on the emitter table top, so that a structure that base metal is lapped on the emitter table top is formed, the transverse distance between the base and the emitter table top is reduced to the maximum extent, the surface resistance of the base region is reduced, the total resistance of base series connection is reduced, and the improvement of the working performance of a transistor is realized on the premise that the parameter design of the device is not changed and the process difficulty is not increased.

The device structure of the embodiment is manufactured on an epitaxial substrate, and the material and the structure of the epitaxial substrate can be selected according to actual requirements. It can be understood that the structural design of the present embodiment is not limited to the gallium nitride technology, but can be applied to gallium nitride, gallium arsenide and other technologies; and is not limited to a specific device, and can be used for HET, HBT, BJT and other devices.

Example two

On the basis of the first embodiment, please refer to fig. 2, and fig. 2 is a schematic flow chart of a method for manufacturing a radio frequency device with a quasi-vertical structure according to an embodiment of the present invention, the method includes:

and S1, manufacturing a device active region on an epitaxial substrate, wherein the epitaxial substrate comprises a base region 5 and an emitter region 7 which are sequentially stacked.

S2, depositing a first passivation layer 9 on the emitter region 7.

And S3, sequentially etching the first passivation layer 9 and the emitter region 7 in the base region pattern to form a second step on the emitter region 7 and the first passivation layer 9, and forming a base region on the base region 5.

Specifically, a base region pattern is firstly photoetched on the surface of the first passivation layer 9, and then the first passivation layer 9 and the emitter region 7 in the base region pattern are etched by adopting a method combining F-based etching and Cl-based etching, so that the emitter region 7 and the first passivation layer 9 form a second step, and further a base region located on the base region 5 is formed.

And S4, sequentially etching the first passivation layer 9, the emitter region 7 and the base region 5 in the collector region pattern to form a first step on the base region 5, thereby forming a collector region of the device.

Specifically, a collector region pattern is first photo-etched on the surface of the first passivation layer 9, and then the first passivation layer 9, the emitter region 7, the base region 5 and the corresponding positions of the epitaxial substrate in the collector region pattern are etched by a method combining F-based etching and Cl-based etching, so that the base region 5 forms a first step, and further a collector region on the epitaxial substrate is formed.

S5, depositing a second passivation layer 10 on the surface of the device where the base region and the collector region are formed, wherein the second passivation layer 10 on the second step forms an emitter mesa.

S6, etching a portion of the second passivation layer 10 on the base region 5 in the base region and a portion of the second passivation layer 10 at the side of the emitter mesa to form a base opening such that the second passivation layer 10 covers a portion of the surface of the first passivation layer 9 to form a first mesa adjacent to the first step, and etching a portion of the second passivation layer 10 in the collector region to form a collector opening.

Specifically, a part of the second passivation layer 10 in the base region is etched by using an F-based etching method to form a base opening, and an emitter mesa is built on one side of the base opening region; and etching part of the second passivation layer 10 in the collector region by using an F-based etching method to form a collector opening.

And S7, etching a part of the second passivation layer 10 and a part of the first passivation layer 9 in the middle of the emitter mesa to form an emitter opening.

Specifically, an emitter opening pattern is photoetched on the surface of the second passivation layer 10, and then an emitter region opening etching is performed in an emitter opening pattern region by using an F-based etching method, wherein the etching depth is the sum of the thicknesses of the first passivation layer 9 and the second passivation layer 10.

S8, simultaneously forming emitter 11, base 6 and collector 3 in the base opening, collector opening and emitter opening.

Specifically, an electrode pattern is photoetched on the surface of the device, and then the emitter 11, the base 6 and the collector 3 are simultaneously manufactured by using an electron beam evaporation process.

In the manufacturing method of the embodiment, the first passivation layer is deposited first, and then the second passivation layer is deposited, so that the base metal is attached to the emitter mesa, the total resistance of the base-region series connection is reduced to the maximum extent, and meanwhile, the manufacturing method has lower process difficulty and is easy to realize.

EXAMPLE III

On the basis of the above embodiments, the present embodiment takes the gallium nitride based hot electron transistor device HET as an example for explanation.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a gallium nitride-based hot electron transistor device HET according to an embodiment of the present invention, where the gallium nitride-based hot electron transistor device HET selects an epitaxial substrate of a gallium nitride substrate, and includes a substrate 1, an n + GaN layer 2, a collector 3, a collector region 4, a base region 5, a base 6, an emitter region 7, a cap layer 8, a first passivation layer 9, a second passivation layer 10, and an emitter 11.

The substrate 1, the n + GaN layer 2, the collector region 4, the base region 5, the emitter region 7, the cap layer 8 and the first passivation layer 9 are sequentially stacked; the base region 5 and the collector region 4 jointly form a first step, so that a collector mesa is formed on the n + GaN layer 2 and is positioned in the center of the device; the upper surface of the base region 5 is used as a base electrode mesa; the emitter region 7, the cap layer 8 and the first passivation layer 9 together form a second step, and the second step is located at the periphery of the device.

The second passivation layer 10 covers the collector mesa, the surface of the first step and the surface of the second step, the second passivation layer 10 covers part of the surface of the first passivation layer 9 to form a first mesa close to the first step, and the surface of the second passivation layer 10 on the second step forms an emitter mesa; that is, the second passivation layer 10 covers the surface of the n + GaN layer 2, the side surface of the collector region 4, the side surface of the base region 5, the upper surface of the base region 5, the side surface of the emitter region 7, the side surface of the cap layer 8, and the upper surface and the side surfaces of the first passivation layer 9, a first mesa close to the first step is formed on the surface of the first passivation layer 9 and the surface of the second passivation layer 10 on the side surface thereof, and an emitter mesa is formed on the second passivation layer 10 on the upper surface of the first passivation layer 9.

The bottom of the collector 3 penetrates the second passivation layer 10 and is located on the collector mesa, i.e. the n + GaN layer 2, and the top of the collector 3 is located on the second passivation layer 10 on the collector mesa.

Please refer to the first embodiment for the positional relationship between the emitter 11 and the base 6, which is not described in detail in this embodiment.

In this embodiment, the device has a structure from inside to outside, which is a collector mesa, a base mesa, and an emitter mesa in sequence, so that the collector 3 is located in the center of the device, the emitter 11 is located at the periphery of the device, and the device has a groove-shaped stepped structure.

Specifically, the substrate 1 is GaN free-standingSupporting a substrate, wherein the thickness of the substrate 1 is 300-400 um; n-type doping concentration 1e of n + GaN layer 2¹⁹cm^-3～4e¹⁹cm^-3The thickness is 80nm to 100 nm; the material of the collector region 4 includes Al_yGa_1-yThe component y of N and Al is 5-10%, and the N-type doping concentration is 1e¹⁸cm^-3～5e¹⁸cm^-3The thickness is 40 nm-60 nm; the material of the base region 5 comprises GaN, the n-type doping concentration of which is 8e¹⁸cm^-3～1.5e¹⁹cm^-3The thickness is 8nm to 12 nm; the material of the emitter region 7 comprises AlxGa_1-xThe x of the N and Al components is 25 to 40 percent, and the N-type doping concentration is 1e¹⁸cm^-3～1e¹⁹cm^-3The thickness is 25 nm-40 nm; the material of the cap layer 8 comprises n + GaN with n-type doping concentration 1e¹⁹cm^-3～4e¹⁹cm^-3The thickness is 30nm to 50nm, and the first passivation layer 9 and the second passivation layer 10 are both made of SiN.

In this embodiment, a method for manufacturing HET is described by taking the following device structure as an example: thickness of GaN free-standing substrate 1 300 um; n-type doping concentration 1e of n + GaN layer 2¹⁹cm^-3The thickness is 80 nm; al (Al)_yGa_1-yThe Al component of the N collector region 4 is 5%, and the N-type doping concentration is 1e¹⁸cm^-3The thickness is 40 nm; n-type doping concentration 8e of GaN base region 5¹⁸cm^-3The thickness is 8 nm; al (Al)_xGa_1-xThe Al component of the N emitter region 7 is 25%, and the N-type doping concentration is 1e¹⁸cm^-3Thickness 25 nm; n-type doping concentration 1e of n + GaN cap layer 8¹⁹cm^-3And the thickness is 30 nm.

The preparation method of the HET comprises the following steps:

s1, capping layer 8 with n + GaN, Al_xGa_1-xN emitter region 7, GaN base region 5, Al_yGa_1-yAnd the N collector region 4 and the N + GaN layer 2 are electrically isolated from each other by manufacturing device active regions.

S11, an electrical isolation region is photoetched on the n + GaN cap layer 8.

Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min; then, coating and spin-coating the photoresist at a spin-coating speed of 3500 rpm/mim, baking the sample on a hot plate at 90 ℃ for 1min, putting the sample into a photoetching machine to expose the photoresist in the electric isolation region, putting the exposed sample into a developing solution to remove the photoresist in the electric isolation region, and washing the exposed sample with ultrapure water and drying the exposed sample with nitrogen;

and S12, etching an electric isolation area on the n + GaN cap layer 8 to form electric isolation of the active area.

Firstly, etching the n + GaN cap layer 8 and Al of the electric isolation region in sequence by utilizing an ICP (inductively coupled plasma) process_xGa_1-xN emitter region 7, GaN base region 5, Al_yGa_1-yThe N collector region 4 and the N + GaN layer 2 are used for realizing the mesa isolation of the active region, and the total etching depth is 200 nm. Then, the sample is sequentially put into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning so as to remove the photoresist outside the electric isolation area, and then the sample is rinsed by ultrapure water and dried by nitrogen.

S2, depositing a first passivation layer 9 on the n + GaN cap layer 8 of the active region.

And S21, performing surface cleaning on the device with the active region isolation completed.

Firstly, putting a sample into an acetone solution for ultrasonic cleaning for 3mim, wherein the ultrasonic intensity is 3.0; then, putting the sample into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min; then, the sample is sequentially placed into an acetone solution and an ethanol solution for ultrasonic cleaning for 3min, and the ultrasonic intensity is 3.0; finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.

S22, depositing a first passivation layer 9 on the n + GaN cap layer 8 by using a PECVD process.

On the n + GaN cap layer 8 of the active region, a PECVD process is used to grow SiN with a thickness of 200nm to form a first passivation layer 9, and the growth process conditions are as follows: by NH₃And SiH₄As the reaction gas, the substrate temperature was 250 ℃, the reaction chamber pressure was 600mTorr, and the RF power was 22W.

S3, sequentially etching the first passivation layer 9, the n + GaN cap layer 8 and the emitter region 7 in the base region pattern, so that the first passivation layer 9, the n + GaN cap layer 8 and the emitter region 7 form a second step, and a base region located on the base region 5 is formed.

And S31, photoetching a base region pattern.

Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min; then, glue coating and spin coating of the stripping glue are carried out on the n + GaN cap layer 8, the spin coating thickness is 0.35 mu m, and the sample is placed on a hot plate at 200 ℃ to be baked for 5 min; then, gluing and spinning photoresist on the stripper with the thickness of 0.77 μm, and baking the sample on a hot plate at 90 deg.C for 1 min; then, putting the sample which is subjected to gluing and whirl coating into a photoetching machine to expose the photoresist in the base region; and finally, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the base region, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist and the stripping glue to form a base region pattern.

And S32, etching the base region.

Firstly, using F-based ICP etching process, and taking CF as reaction gas₄And O₂And etching the first passivation layer 9 on the n + GaN cap layer 8 in the base region pattern under the conditions that the pressure of the reaction chamber is 10mTorr and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, wherein the etching depth is 200 nm.

Then, the n + GaN cap layer 8 and the AlxGa in the base region graph are etched in sequence by utilizing a Cl-based etching process_1-xAnd an N emitting region 7, wherein the total etching depth is 55 nm.

And finally, sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the etching area, washing the sample with ultrapure water, and drying with nitrogen to form the base region.

S4, sequentially etching the first passivation layer 9, the n + GaN cap layer 8, the emitter region 7, the base region 5 and the collector region 4 in the pattern of the collector region, so that the base region 5 and the collector region 4 form a first step to form the collector region of the device.

And S41, photoetching a collector region pattern.

Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min; then, glue coating and spin coating of a stripping glue are carried out on the n + GaN cap layer 8 and the etched base region, the spin coating thickness is 0.35 mu m, and the sample is placed on a hot plate at 200 ℃ and baked for 5 min; then, gluing and spinning photoresist on the stripper with the thickness of 0.77 μm, and baking the sample on a hot plate at 90 deg.C for 1 min; then, putting the sample subjected to gluing and whirl coating into a photoetching machine to expose the photoresist in the collector region; and finally, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the collector region, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist and the stripping glue to form a collector region pattern.

And S42, etching the collector region.

Firstly, using F-based ICP etching process to make the reaction gas be CF₄And O₂And etching the first passivation layer 9 on the n + GaN cap layer 8 under the conditions that the pressure of the reaction chamber is 10mTorr and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, wherein the etching depth is 200 nm.

Then, the n + GaN cap layer 8 and Al in the collector region are etched in sequence by using a Cl-based etching process_xGa_1-xN emitter region 7, GaN base region 5, Al_yGa_1-yAnd the total etching depth of the N collector region 4 is 103 nm.

And finally, sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the etching area, washing the sample with ultrapure water and drying the sample with nitrogen to form a collector electrode area.

S5, depositing a second passivation layer 10 on the surface of the device where the base region and the collector region are formed, wherein the second passivation layer 10 on the upper surface of the first passivation layer 9 forms an emitter mesa.

And S51, cleaning the surface of the etched device.

Firstly, putting a sample into an acetone solution for ultrasonic cleaning for 3mim, wherein the ultrasonic intensity is 3.0; then, putting the sample into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min; then, the sample is sequentially placed into an acetone solution and an ethanol solution for ultrasonic cleaning for 3min, and the ultrasonic intensity is 3.0; finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.

S52, growing the second passivation layer 10 by using a PECVD process.

On the surface of the etched deviceAnd growing SiN with the thickness of 60nm by using a PECVD process to form a second passivation layer 10, wherein the growing process conditions are as follows: by NH₃And SiH₄As the reaction gas, the substrate temperature was 250 ℃, the reaction chamber pressure was 600mTorr, and the RF power was 22W.

S6, etching a portion of the second passivation layer 10 on the base region 5 in the base region and a portion of the second passivation layer 10 at the side of the emitter mesa to form a base opening such that the second passivation layer 10 covers a portion of the surface of the first passivation layer 9 to form a first mesa adjacent to the first step, and etching a portion of the second passivation layer 10 in the collector region to form a collector opening.

And S61, photoetching a base electrode opening region pattern on the n + GaN cap layer 8 and the GaN base region 5, and photoetching a collector electrode opening region pattern on the n + GaN layer 2.

Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min; then, glue spreading and spin coating of the stripping glue are carried out on the n + GaN cap layer 8, the GaN base region 5 and the n + GaN layer 2, the thickness of the spin coating is 0.35 mu m, and the sample is placed on a hot plate at 200 ℃ to be baked for 5 min; then, gluing and spinning photoresist on the stripper with the thickness of 0.77 μm, and baking the sample on a hot plate at 90 deg.C for 1 min; then, putting the sample subjected to gluing and whirl coating into a photoetching machine to expose the photoresist in the base electrode and collector electrode regions; and finally, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the base electrode region and the collector electrode region, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist and the stripping glue to form a base electrode open pore region pattern and a collector electrode open pore region pattern.

And S62, performing base opening etching and collector opening etching by using an F-based etching process, wherein the etching depth is 60nm, and one side of the base opening is lapped with an emitter mesa.

By utilizing ICP etching process, the reaction gas is CF₄And O₂Etching off the n + GaN cap layer 8, a part of the second passivation layer 10 on the GaN base region 5 and a part of the second passivation layer 10 on the n + GaN layer 2 under the conditions that the pressure of the reaction chamber is 10mTorr and the radio frequency powers of the upper electrode and the lower electrode are 100W and 10W respectively, manufacturing an electrode groove region, and forming a base electrode opening and a collector electrode opening. Then, the sample is sequentially placed into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning so as to remove the photoresist outside the open pore area, and the sample is rinsed with ultrapure water and dried by nitrogen.

And S7, etching a part of the second passivation layer 10 and a part of the first passivation layer 9 in the middle of the emitter mesa to form an emitter opening, wherein the emitter opening is positioned on the periphery of the device.

S71, patterning the emitter opening region on n + GaN cap layer 8.

Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min; then, glue spreading and spin coating of the stripping glue are carried out on the n + GaN cap layer 8, the GaN base region 5 and the n + GaN layer 2, the thickness of the spin coating is 0.35 mu m, and the sample is placed on a hot plate at 200 ℃ to be baked for 5 min; then, gluing and spinning photoresist on the stripper with the thickness of 0.77 μm, and baking the sample on a hot plate at 90 deg.C for 1 min; then, putting the sample subjected to gluing and whirl coating into a photoetching machine to expose the photoresist in the base electrode and collector electrode regions; and finally, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the base electrode region and the collector electrode region, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist and the stripping glue to form an emitter opening region pattern.

S72, utilizing ICP etching process to make the reaction gas be CF₄And O₂And etching off a part of the second passivation layer 10 and the first passivation layer 9 on the n + GaN cap layer 8 under the conditions that the pressure of the reaction chamber is 10mTorr and the radio frequency powers of the upper electrode and the lower electrode are 100W and 10W respectively, wherein the etching depth is 260nm, and manufacturing an electrode groove region to form an emitter opening.

And finally, sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the open pore area, washing the sample with ultrapure water and drying with nitrogen.

S8, the emitter 11, the base 6 and the collector 3 are simultaneously formed in the base opening, the collector opening and the emitter opening by an electron beam evaporation process.

S81, an emitter region and a base region are etched on the n + GaN cap layer 8 and GaN base region 5, and a collector region is etched on the n + GaN layer 2.

Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min; then, glue spreading and spin coating of the stripping glue are carried out on the n + GaN cap layer 8, the GaN base region 5 and the n + GaN layer 2, the thickness of the spin coating is 0.35 mu m, and the sample is placed on a hot plate at 200 ℃ to be baked for 5 min; then, gluing and spinning photoresist on the stripper with the thickness of 0.77 μm, and baking the sample on a hot plate at 90 deg.C for 1 min; then, putting the sample subjected to gluing and whirl coating into a photoetching machine to expose the photoresist in the emitter region, the base region and the collector region; and finally, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the emitter region, the base region and the collector region, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist and the stripping glue to form the emitter region, the base region and the collector region.

S82, placing the sample into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 x 10^{- 6}And after the Torr is carried out, evaporating a metal layer with a stack structure consisting of three layers of Ni, Au and Ni sequentially from bottom to top on the n + GaN cap layer 8, the GaN base region 5 and the n + GaN layer 2 in the emitter, base and collector regions and the photoresist outside the emitter, base and collector regions.

And S83, stripping the sample after the evaporation of the metal of the emitter, the base and the collector is finished to remove the metal, the photoresist and the stripping glue outside the areas of the emitter, the base and the collector, washing the sample with ultrapure water and drying the sample with nitrogen to form the emitter 11, the base 6 and the collector 3.

And finally, cleaning the sample subjected to electrode manufacturing, flushing the sample with ultrapure water, and drying the sample with nitrogen to finish device manufacturing.

Example four

In addition to the above embodiments, the present embodiment takes a gallium arsenide-based heterojunction bipolar transistor HBT as an example for explanation.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a gaas-based heterojunction bipolar transistor HBT according to an embodiment of the present invention.

The gallium arsenide-based heterojunction bipolar transistor HBT adopts an epitaxial substrate of a sapphire substrate and comprises a substrate 1, an n-type GaAS layer 2, a collector 3, a collector region 4, a base region 5, a base electrode 6, an emitter region 7, a cap layer 8, a first passivation layer 9, a second passivation layer 10 and an emitter 11.

Specifically, a substrate 1, an n-type GaAS layer 2, a collector region 4, a base region 5, an emitter region 7, a cap layer 8 and a first passivation layer 9 are sequentially stacked; the base region 5 and the collector region 4 jointly form a first step, so that a collector mesa is formed on the n-type GaAS layer 2 and is positioned on the periphery of the device; the upper surface of the base region 5 is used as a base electrode mesa; the emitter region 7, the cap layer 8, and the first passivation layer 9 together form a second step, which is located at the center of the device.

The second passivation layer 10 covers the collector mesa, the surface of the first step and the surface of the second step, the second passivation layer 10 covers part of the surface of the first passivation layer 9 to form a first mesa close to the first step, and the surface of the second passivation layer 10 on the second step forms an emitter mesa; that is, the second passivation layer 10 covers the surface of the n-type GaAS layer 2, the side surface of the collector region 4, the side surface of the base region 5, the upper surface of the base region 5, the side surface of the emitter region 7, the side surface of the cap layer 8, and the upper surface and the side surfaces of the first passivation layer 9, a first mesa close to the first step is formed on the surface of the first passivation layer 9 and the surface of the second passivation layer 10 on the side surface thereof, and an emitter mesa is formed on the second passivation layer 10 on the upper surface of the first passivation layer 9.

The bottom of the collector 3 penetrates the second passivation layer 10 and is located on the collector mesa, i.e. the n-type GaAS layer 2, and the top of the collector 3 is located on the second passivation layer 10 on the collector mesa.

In this embodiment, the device has an emitter mesa, a base mesa, and a collector mesa in sequence from inside to outside, so that the emitter 11 is located in the center of the device, the collector 3 is located at the periphery of the device, and the device has an island-shaped stepped structure.

Specifically, the substrate 1 is a sapphire substrate, and the thickness of the substrate 1 is 300-400 um; n-type doping concentration 1e of n-type GaAS layer 2¹⁹cm^-3～4e¹⁹cm^-3The thickness is 80nm to 100 nm; the material of the collector region 4 includes Al_yGa_1-yAs, Al component y is 5Percent to 10 percent, and n-type doping concentration is 1e¹⁸cm^-3～5e¹⁸cm^-3The thickness is 40 nm-60 nm; the material of the base region 5 comprises P-type GaAS with a P-type doping concentration of 8e¹⁸cm^-3～1.5e¹⁹cm^-3The thickness is 30 nm-80 nm; the material of the emitter region 7 comprises Al_xGa_1-xAs and Al components x is 25-40%, and n-type doping concentration is 1e¹⁸cm^-3～1e¹⁹cm^-3The thickness is 25 nm-40 nm; the material of the cap layer 8 comprises n-type GaAs with n-type doping concentration 1e¹⁹cm^-3～4e¹⁹cm^-3The thickness is 30nm to 50nm, and the first passivation layer 9 and the second passivation layer 10 are both made of SiN.

In this embodiment, a method for manufacturing an HBT is described with the following device structure as an example: the thickness of the sapphire substrate 1 is 300 um; n-type doping concentration 2e of n-type GaAs layer 2¹⁹cm^-3The thickness is 80 nm; al (Al)_yGa_1-yAl component of As collector region 4 is 7%, and n-type doping concentration is 3e¹⁸cm^-3The thickness is 50 nm; p-type doping concentration 1e of P-type GaAs base region 5¹⁹cm^-3The thickness is 50 nm; AlxGa_{1- x}Al component of As emitter region 7 is 30%, and n-type doping concentration is 3e¹⁸cm^-3The thickness is 60 nm; n-type doping concentration 3e of n-type GaAS cap layer 8¹⁹cm^-3And the thickness is 80 nm.

The preparation method of the HBT comprises the following steps:

s1, forming an n-type GaAS cap layer 8, and forming AlxGa_1-xAs emitter region 7, P-type GaAs base region 5, and Al_yGa_1-yAnd the As collector region 4 and the n-type GaAs layer 2 are provided with device active regions which are electrically isolated.

S11, an electrically isolated region is photo-etched on the n-type GaAS cap layer 8.

Please refer to step S11 of the third embodiment.

S12, forming an n-type GaAS cap layer 8, and forming AlxGa_1-xAs emitter region 7, P-type GaAs base region 5, and Al_yGa_1-yAnd etching an electric isolation region on the As collector region 4 and the n-type GaAs layer 2 to form electric isolation of the active region.

First, the electrical isolation is etched in sequence by utilizing an ICP processN-type GaAS cap layer 8 of the region, Al_xGa_1-xAs emitter region 7, P-type GaAS base region 5, Al_yGa_1-yThe As collector region 4 and the n-type GaAS layer 2 are used for realizing the mesa isolation of the active region, and the total etching depth is 320 nm; then, the sample is sequentially put into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning so as to remove the photoresist outside the electric isolation area, and then the sample is rinsed by ultrapure water and dried by nitrogen.

S2, depositing a first passivation layer 9 on the n-type GaAS cap layer 8 of the active region.

Please refer to step S2 of the third embodiment.

S3, etching the first passivation layer 9, the n-type GaAS cap layer 8 and the Al in the base region pattern in sequence_xGa_1-xAn As emitter region 7, a first passivation layer 9, an n-type GaAS cap layer 8 and AlxGa_1-xThe As emitter region 7 forms a second step forming a base region located above the base region 5.

And S31, photoetching a base region pattern.

Please refer to step S31 of the third embodiment.

And S32, etching the base region.

Firstly, using F-based ICP etching process, and taking CF as reaction gas₄And O₂And etching the first passivation layer 9 on the n-type GaAS cap layer 8 under the conditions that the pressure of the reaction chamber is 10mTorr and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, wherein the etching depth is 200 nm.

Then, the n-type GaAS cap layer 8 of the base region and Al are etched in sequence by using a Cl-based etching process_xGa_1-xAn As emitting region 7 with a total etching depth of 140 m;

and finally, sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the etching area, washing the sample with ultrapure water and drying with nitrogen.

S4, etching the first passivation layer 9, the n-type GaAS cap layer 8 and the Al in the pattern of the collector region in sequence_xGa_1-xAs emitter region 7, P-type GaAs base region 5 and Al_yGa_1-yAs collector region 4, such thatAnd forming a first step on the base region 5 and the collector region 4 to form a collector region of the device.

And S41, photoetching a collector region pattern.

Please refer to step S41 of the third embodiment.

And S42, etching the collector region.

Firstly, using F-based ICP etching process to make the reaction gas be CF₄And O₂And etching the first passivation layer 9 on the n-type GaAS cap layer 8 under the conditions that the pressure of the reaction chamber is 10mTorr and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, wherein the etching depth is 200 nm.

Then, the n-type GaAS cap layer 8 and Al in the collector region are etched in sequence by using a Cl-based etching process_xGa_1-xAs emitter region 7, P-type GaAs base region 5 and Al_yGa_1-yAnd the total etching depth of the As collector region 4 is 240 nm.

And finally, sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the etching area, washing the sample with ultrapure water and drying the sample with nitrogen to form a collector electrode area.

S5, depositing a second passivation layer 10 on the surface of the device where the base region and the collector region are formed, wherein the second passivation layer 10 on the upper surface of the first passivation layer 9 forms an emitter mesa.

Please refer to step S5 of the third embodiment.

S6, etching a portion of the second passivation layer 10 on the base region 5 in the base region and a portion of the second passivation layer 10 at the side of the emitter mesa to form a base opening such that the second passivation layer 10 covers a portion of the surface of the first passivation layer 9 to form a first mesa adjacent to the first step, and etching a portion of the second passivation layer 10 in the collector region to form a collector opening.

And S61, photoetching a base opening region pattern on the n-type GaAs cap layer 8 and the P-type GaAs base region 5, and photoetching a collector opening region pattern on the n-type GaAs layer 2.

Please refer to step S61 of the third embodiment.

And S62, performing base opening etching and collector opening etching by using an F-based etching process, wherein the etching depth is 60nm, and one side of the base opening is lapped with an emitter mesa.

By utilizing ICP etching process, the reaction gas is CF₄And O₂Under the conditions that the pressure of the reaction chamber is 10mTorr and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, the n-type GaAS cap layer 8, the second passivation layer 10 on the upper portion of the P-type GaAs base region 5 and the second passivation layer 10 on the upper portion of the n-type GaAs layer 2 are etched, an electrode groove region is manufactured, and base openings and collector openings are formed. Then, the sample is sequentially placed into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning so as to remove the photoresist outside the open pore area, and the sample is rinsed with ultrapure water and dried by nitrogen.

And S7, etching a part of the second passivation layer 10 and a part of the first passivation layer 9 in the middle of the emitter mesa to form an emitter opening, wherein the emitter opening is positioned on the periphery of the device.

S71, patterning the emitter opening region on n-type GaAS cap layer 8.

Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min; then, glue spreading and spin coating of a stripping glue are carried out on the n-type GaAS cap layer 8, the P-type GaAs base region 5 and the n-type GaAs layer 2, the spin coating thickness is 0.35 mu m, and the sample is placed on a hot plate at 200 ℃ to be baked for 5 min; then, gluing and spinning photoresist on the stripper with the thickness of 0.77 μm, and baking the sample on a hot plate at 90 deg.C for 1 min; then, putting the sample subjected to gluing and whirl coating into a photoetching machine to expose the photoresist in the base electrode and collector electrode regions; and finally, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the base electrode region and the collector electrode region, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist and the stripping glue to form an emitter opening region pattern.

S72, utilizing ICP etching process to make the reaction gas be CF₄And O₂Etching off part of the second passivation layer 10 and the first passivation layer 9 on the n-type GaAS cap layer 8 under the conditions that the pressure of the reaction chamber is 10mTorr and the radio frequency powers of the upper electrode and the lower electrode are 100W and 10W respectively, wherein the etching depth is 260nm, and manufacturingAnd forming an emitter opening in the electrode groove region.

And finally, sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the open pore area, washing the sample with ultrapure water and drying with nitrogen.

S8, the emitter 11, the base 6 and the collector 3 are simultaneously formed in the base opening, the collector opening and the emitter opening by an electron beam evaporation process.

S81, photoetching emitter and base regions on the n-type GaAS cap layer 8 and P-type GaAS base region 5, and photoetching collector region on the n-type GaAS layer 2.

Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min; then, glue spreading and spin coating of a stripping glue are carried out on the n-type GaAS cap layer 8, the P-type GaAs base region 5 and the n-type GaAs layer 2, the spin coating thickness is 0.35 mu m, and the sample is placed on a hot plate at 200 ℃ to be baked for 5 min; then, gluing and spinning photoresist on the stripper with the thickness of 0.77 μm, and baking the sample on a hot plate at 90 deg.C for 1 min; then, putting the sample subjected to gluing and whirl coating into a photoetching machine to expose the photoresist in the emitter region, the base region and the collector region; and finally, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the emitter region, the base region and the collector region, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist and the stripping glue to form the emitter region, the base region and the collector region.

S82, placing the sample into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 x 10^{- 6}And after Torr, evaporating a metal layer with a stack structure consisting of three metals of Ni, Au and Ni from bottom to top on the photoresist outside the emitter, base and collector regions, namely the n-type GaAS cap layer 8, the P-type GaAs base region 5 and the n-type GaAs layer 2, and the emitter, base and collector regions.

And S83, stripping the sample after the evaporation of the metal of the emitter, the base and the collector is finished to remove the metal, the photoresist and the stripping glue outside the areas of the emitter, the base and the collector, washing the sample with ultrapure water and drying the sample with nitrogen to form the emitter 11, the base 6 and the collector 3.

And finally, cleaning the sample subjected to electrode manufacturing, flushing the sample with ultrapure water, and drying the sample with nitrogen to finish device manufacturing.

EXAMPLE five

Based on the above embodiments, the present embodiment takes a silicon-based bipolar transistor BJT as an example for explanation.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a silicon-based bipolar transistor BJT according to an embodiment of the present invention, where the silicon-based bipolar transistor BJT includes a substrate 1, a collector 3, a collector region 4, a base region 5, a base 6, an emitter region 7, a first passivation layer 9, a second passivation layer 10, and an emitter 11.

Specifically, a substrate 1, a collector region 4, a base region 5, an emitter region 7, a cap layer 8 and a first passivation layer 9 are sequentially stacked; the base regions 5 together form a first step, so that a collector mesa is formed on the collector region 4, and the collector mesa is positioned at one end of the device; the upper surface of the base region 5 is used as a base electrode mesa; the emitter region 7, the first passivation layer 9 form a second step at the other end of the device.

The second passivation layer 10 covers the collector mesa, the surface of the first step and the surface of the second step, the second passivation layer 10 covers part of the surface of the first passivation layer 9 to form a first mesa close to the first step, and the surface of the second passivation layer 10 on the second step forms an emitter mesa; that is, the second passivation layer 10 covers the surface of the collector region 4, the side surface of the base region 5, the upper surface of the base region 5, the side surface of the emitter region 7, and the upper surface and the side surface of the first passivation layer 9, a first mesa close to the first step is formed on the surface of the second passivation layer 10 on the surface of the first passivation layer 9 and the side surface thereof, and an emitter mesa is formed on the second passivation layer 10 on the upper surface of the first passivation layer 9.

The bottom of the collector 3 extends through the second passivation layer 10 and is located on the collector mesa, i.e. on the collector region 4, and the top of the collector 3 is located on the second passivation layer 10 on the collector mesa.

Please refer to the first embodiment for the positional relationship between the emitter 11 and the base 6, which is not described in detail in this embodiment.

In this embodiment the collector mesa is located at one end of the device and the emitter mesa is located at the other end of the device, so that the collector 3 is located at one end of the device and the emitter 11 is located at the other end of the device, thereby forming a stepped structure.

Specifically, the substrate 1 is a silicon substrate, and the thickness of the substrate 1 is 300-400 um; the material of collector region 4 comprises n-type Si with n-type doping concentration 5e¹⁵cm^-3～5e¹⁶cm^-3The thickness is 5um to 8 um; the material of the base region 5 comprises P-type Si with a doping concentration of 1e¹⁶cm^-3～8e¹⁷cm^-3The thickness is 1um to 1.5 um; the material of the emitter region 7 comprises n-type Si with n-type doping concentration 1e¹⁹cm^-3～6e¹⁹cm^-3And the thickness is 2um to 5um, and the materials of the first passivation layer 9 and the second passivation layer 10 are both SiN.

In this embodiment, a method for manufacturing a BJT is described by taking the following device structure as an example: the thickness of the silicon substrate 1 is 300-400 um; n-type doping concentration 6e of n-type Si collector region 4¹⁵cm^-3And the thickness is 5 um; n-type doping concentration 7e of P-type Si base region 5¹⁶cm^-31um in thickness; n-type doping concentration 2e of n-type Si emitter region 7¹⁹cm^-3And the thickness is 3um.

The preparation method of the BJT comprises the following steps:

and S1, manufacturing device active regions in the n-type Si collector region 4, the P-type Si base region 5 and the n-type Si emitter region 7 to be electrically isolated.

S11, electrically isolating regions are lithographically formed on the n-type Si emitter 7.

Please refer to step S11 of the third embodiment.

And S12, etching an electric isolation region on the n-type Si collector region 4, the P-type Si base region 5 and the n-type Si emitter region 7 to form electric isolation of the active region.

Firstly, etching an n-type Si emitter region 7, a P-type Si base region 5 and an n-type Si collector region 4 of an electrical isolation region in sequence by utilizing an ICP (inductively coupled plasma) process to realize mesa isolation of an active region, wherein the total etching depth is 6 microns; then, the sample is sequentially put into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning so as to remove the photoresist outside the electric isolation area, and then the sample is rinsed by ultrapure water and dried by nitrogen.

S2, a first passivation layer 9 is deposited on the n-type Si emitter region 7 of the active region.

Please refer to step S2 of the third embodiment.

S3, sequentially etching the first passivation layer 9 and the n-type Si emitter region 7 in the base region pattern, so that the first passivation layer 9 and the n-type Si emitter region 7 form a second step to form a base region on the P-type Si base region 5.

And S31, photoetching a base region pattern.

Please refer to step S31 of the third embodiment.

And S32, etching the base region.

Firstly, using ICP etching process to make reaction gas be CF₄And O₂And etching the first passivation layer 9 on the n-type Si emitter region 7 under the conditions that the pressure of the reaction chamber is 10mTorr and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, wherein the etching depth is 200 nm.

Then, the n-type Si emitter region 7 of the base region is sequentially etched by a Cl-based etching process, with a total etching depth of 3um.

And finally, sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the etching area, washing the sample with ultrapure water, and drying with nitrogen to form the base region.

S4, sequentially etching the first passivation layer 9, the n-type Si emitter region 7, the PP-type Si base region 5 and the n-type Si collector region 4 in the pattern of the collector region, so that the base region 5 and the collector region 4 form a first step to form a collector region of the device.

And S41, photoetching a collector region pattern.

Please refer to step S41 of the third embodiment.

And S42, etching the collector region.

Firstly, using F-based ICP etching process to make the reaction gas be CF₄And O₂Etching off the n-type Si emitter region 7 under the conditions that the pressure of the reaction chamber is 10mTorr and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectivelyAnd the first passivation layer 9 is etched to a depth of 200 nm.

And then, sequentially etching the n-type Si emitter region 7 and the P-type Si base region 5 of the collector region by using a Cl-based etching process, wherein the total etching depth is 4 um.

And finally, sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the etching area, washing the sample with ultrapure water and drying the sample with nitrogen to form a collector electrode area.

S5, depositing a second passivation layer 10 on the surface of the device where the base region and the collector region are formed, wherein the second passivation layer 10 on the upper surface of the first passivation layer 9 forms an emitter mesa.

Please refer to step S5 of the third embodiment.

S6, etching a portion of the second passivation layer 10 on the base region 5 in the base region and a portion of the second passivation layer 10 at the side of the emitter mesa to form a base opening such that the second passivation layer 10 covers a portion of the surface of the first passivation layer 9 to form a first mesa adjacent to the first step, and etching a portion of the second passivation layer 10 in the collector region to form a collector opening.

S61, a base open area pattern is etched on the P-type Si base region 5 and a collector open area pattern is etched on the n-type Si collector region 4.

Please refer to step S61 of the third embodiment.

And S62, performing base opening etching and collector opening etching by using an F-based etching process, wherein the etching depth is 60nm, and one side of the base opening is lapped with an emitter mesa.

By utilizing ICP etching process, the reaction gas is CF₄And O₂Under the conditions that the pressure of the reaction chamber is 10mTorr and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, etching off the n-type Si emitter region 7, a part of the second passivation layer 10 on the P-type Si base region 5 and a part of the second passivation layer 10 on the n-type Si collector region 4, manufacturing an electrode groove region, and forming a base electrode opening and a collector electrode opening. Then, the sample is sequentially put into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning so as to remove the open poresAnd (4) rinsing the sample by using ultrapure water and drying by using nitrogen.

S7, etching a portion of the second passivation layer 10 and a portion of the first passivation layer 9 in the middle of the emitter mesa to form an emitter opening, the collector opening being at one end of the device and the emitter opening being at the other end of the device.

S71, patterning the emitter open area on n-type Si emitter 7.

Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min; then, glue spreading and spin coating of a stripping glue are carried out on the n-type Si emitter region 7, the P-type Si base region 5 and the n-type Si collector region 4, the spin coating thickness is 0.35 mu m, and the sample is placed on a hot plate at 200 ℃ to be baked for 5 min; then, gluing and spinning photoresist on the stripper with the thickness of 0.77 μm, and baking the sample on a hot plate at 90 deg.C for 1 min; then, putting the sample subjected to gluing and whirl coating into a photoetching machine to expose the photoresist in the base electrode and collector electrode regions; and finally, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the base electrode region and the collector electrode region, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist and the stripping glue to form an emitter opening region pattern.

S72, utilizing ICP etching process to make the reaction gas be CF₄And O₂Etching off a part of the second passivation layer 10 and the first passivation layer 9 on the n-type Si emitter region 7 under the conditions that the pressure of the reaction chamber is 10mTorr and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, wherein the etching depth is 260nm, manufacturing an electrode groove region, and forming an emitter opening.

And finally, sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the open pore area, washing the sample with ultrapure water and drying with nitrogen.

S8, the emitter 11, the base 6 and the collector 3 are simultaneously formed in the base opening, the collector opening and the emitter opening by an electron beam evaporation process.

S81, photo-etching emitter and base regions on the n-type Si emitter region 7 and the P-type Si base region 5, and photo-etching collector region on the n-type Si collector region 4.

Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min; then, glue spreading and spin coating of a stripping glue are carried out on the n-type Si emitter region 7, the P-type Si base region 5 and the n-type Si collector region 4, the spin coating thickness is 0.35 mu m, and the sample is placed on a hot plate at 200 ℃ to be baked for 5 min; then, gluing and spinning photoresist on the stripper with the thickness of 0.77 μm, and baking the sample on a hot plate at 90 deg.C for 1 min; then, putting the sample subjected to gluing and whirl coating into a photoetching machine to expose the photoresist in the emitter region, the base region and the collector region; and finally, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the emitter region, the base region and the collector region, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist and the stripping glue to form the emitter region, the base region and the collector region.

S82, placing the sample into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 x 10^{- 6}And after Torr, evaporating a metal layer with a stack structure consisting of three layers of Ni, Au and Ni sequentially from bottom to top on photoresist outside the emitter region, the base region and the collector region, namely the n-type Si emitter region 7, the P-type Si base region 5 and the n-type Si collector region 4.

And S83, stripping the sample after the evaporation of the metal of the emitter, the base and the collector is finished to remove the metal, the photoresist and the stripping glue outside the areas of the emitter, the base and the collector, washing the sample with ultrapure water and drying the sample with nitrogen to form the emitter 11, the base 6 and the collector 3.

And finally, cleaning the sample subjected to electrode manufacturing, flushing the sample with ultrapure water, and drying the sample with nitrogen to finish device manufacturing.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.