阅读说明：本技术 薄膜晶体管阵列基板及其制作方法 (Thin film transistor array substrate and manufacturing method thereof ) 是由 卓毅 于 2021-08-25 设计创作，主要内容包括：本申请公开一种薄膜晶体管阵列基板及其制作方法。薄膜晶体管阵列基板包括衬底、设置在衬底上的平台层。氧化物有源层包括沟道部及两导体部。沟道部的顶面所在的水平面高度高于任一导体部的顶面所在的水平面高度。栅极绝缘层设置在氧化物有源层上栅极设置在栅极绝缘层上,且栅极在衬底上的正投影覆盖平台层及沟道部在衬底上的正投影。源极和漏极与导体部电连接。本申请薄膜晶体管阵列基板延长了氧化物有源层的导体化扩散路径,保证有效沟道长度,利于实现薄膜晶体管器件尺寸的缩小。(The application discloses a thin film transistor array substrate and a manufacturing method thereof. The thin film transistor array substrate comprises a substrate and a platform layer arranged on the substrate. The oxide active layer includes a channel portion and two conductor portions. The height of the horizontal plane on which the top surface of the channel portion is located is higher than the height of the horizontal plane on which the top surface of any one of the conductor portions is located. The gate insulating layer is arranged on the oxide active layer, the gate is arranged on the gate insulating layer, and the orthographic projection of the gate on the substrate covers the orthographic projection of the terrace layer and the channel part on the substrate. The source and drain electrodes are electrically connected to the conductor portion. The thin film transistor array substrate prolongs the conductor diffusion path of the oxide active layer, ensures the effective channel length and is beneficial to realizing the reduction of the size of a thin film transistor device.)

1. A thin film transistor array substrate, comprising:

a substrate;

a mesa layer disposed on the substrate;

an oxide active layer disposed on the substrate and above the mesa layer, the oxide active layer including a channel portion and conductor portions on opposite sides of the channel portion, wherein a height of a horizontal plane on which a top surface of the channel portion is located is higher than a height of a horizontal plane on which a top surface of any one of the conductor portions is located,

a gate insulating layer disposed on the oxide active layer

A gate disposed on the gate insulating layer, wherein an orthographic projection of the gate on the substrate covers an orthographic projection of the mesa layer and the channel portion on the substrate; and

a source electrode and a drain electrode electrically connected to the conductor portion.

2. The thin film transistor array substrate of claim 1, further comprising a buffer layer disposed on the substrate and covering the mesa layer, wherein a material of the mesa layer is an insulating material or a metal oxide.

3. The thin film transistor array substrate of claim 2, wherein the buffer layer includes a boss, and the channel portion is disposed on the boss and covers the entire boss.

4. The thin film transistor array substrate of claim 1, wherein the channel portion includes two sloped sides, one end of each of the sloped sides is connected to the corresponding conductor portion, and the sloped sides are inclined in a direction away from the channel portion and toward the corresponding conductor portion.

5. The thin film transistor array substrate of claim 4, wherein the mesa layer includes first and second end surfaces that are respectively inclined outward, and an orthographic projection of the channel portion on the substrate covers an orthographic projection of the mesa layer on the substrate.

6. The thin film transistor array substrate of claim 5, wherein the gate insulating layer comprises two offset portions disposed oppositely, the offset portions being defined at portions between end edges of the gate insulating layer corresponding to the gate and corresponding end edges of the gate insulating layer, wherein orthographic projections of the two offset portions on the substrate respectively cover orthographic projections of the first end surface and the second end surface of the mesa layer and the sloping edge of the channel portion on the substrate.

7. The thin film transistor array substrate of claim 1, further comprising an interlayer insulating layer covering the oxide active layer, the gate insulating layer, and the gate electrode, and the interlayer insulating layer including a plurality of via holes, wherein the source and drain electrodes are disposed on the interlayer insulating layer and electrically connected to the conductor part through the plurality of via holes.

8. A manufacturing method of a thin film transistor array substrate is characterized by comprising the following steps:

depositing a terrace layer on a substrate, wherein the material of the terrace layer is an insulating material or a metal oxide;

forming an oxide active layer on a substrate, and forming a channel part and conductor regions positioned at two opposite sides of the channel part by utilizing a photoetching process;

depositing a gate insulating layer on the oxide active layer;

depositing a grid metal layer on the grid insulating layer;

patterning the layer of gate metal layer by using a photolithography process to form a gate, and self-aligning and etching the gate insulating layer to expose the conductor region of the oxide active layer, wherein the orthographic projection of the gate on the substrate covers the terrace layer and the orthographic projection of the channel part on the substrate;

conducting whole-surface plasma treatment to enable the conductor region of the oxide active layer to be conductive and form a conductor part, wherein the height of the horizontal plane where the top surface of the channel part is located is higher than that of the top surface of any one conductor part;

depositing an interlayer insulating layer to cover the oxide active layer, the gate insulating layer and the gate electrode, and patterning the interlayer insulating layer to form a plurality of via holes; and

and depositing a source/drain metal layer, and patterning to form a source and a drain, wherein the source and the drain are electrically connected with the conductor part of the oxide active layer through the via holes.

9. The method of fabricating the thin film transistor array substrate of claim 8, wherein the step of forming an oxide active layer on the substrate further comprises: depositing a buffer layer on the substrate to cover the platform layer, and forming a boss positioned right above the platform layer by the buffer layer through a photoetching process, wherein the channel part is arranged on the boss and covers the whole boss.

10. The method according to claim 9, wherein the channel portion includes two sloped sides, one end of each sloped side is connected to the corresponding conductor portion, and the sloped sides are inclined away from the channel portion and toward the corresponding conductor portion, wherein the gate insulating layer includes two offset portions disposed opposite to each other, the offset portions are formed at portions of the gate insulating layer between the end edges of the gate electrode and the corresponding end edges of the gate insulating layer, and orthogonal projections of the two offset portions on the substrate respectively cover orthogonal projections of the two opposite end surfaces of the mesa layer and the sloped sides of the channel portion on the substrate.

Technical Field

The invention relates to the technical field of display, in particular to a thin film transistor array substrate and a manufacturing method thereof.

Background

With the development of display technology, flat panel displays have become the mainstream displays at present. Commonly used flat panel displays include Liquid Crystal Displays (LCDs) and Active Matrix driven organic electroluminescent displays (AMOLEDs).

In a flat panel display, a Thin-Film Transistor (TFT) array substrate is a main driving element and is an essential structure of a high-performance flat panel display device. The thin film transistor array substrate includes a plurality of thin film transistors arranged in an array, which includes different types such as a bottom gate type thin film transistor (bottom gate) or a Top gate type thin film transistor (Top gate). The top gate type thin film transistor has lower parasitic capacitance and better ductility because the source electrode, the drain electrode and the grid electrode are not overlapped, and can reduce delay in the signal transmission process. In the technology of the metal oxide thin film transistor with the top gate structure, in order to reduce the resistance of the region outside the channel, a self-aligned (self-aligned) etching process is often adopted, namely, a photoetching process is used for simultaneously defining a gate pattern and etching a gate insulating layer and a conductor of a non-channel region, so that the formation of high-resistance regions at two sides of the channel caused by alignment deviation can be effectively avoided. However, the diffusion of the conductor effect on both sides of the channel causes a low resistance region to exist on both ends of the channel, that is, the effective channel length becomes short, which is not advantageous for the reduction in size of the TFT device.

Disclosure of Invention

The invention provides a thin film transistor and a manufacturing method thereof, and aims to solve the technical problems that the diffusion of the conductor effect at two sides of a channel of a traditional film transistor causes low-resistance areas at two ends of the channel, so that the effective channel length is shortened, and the size of a thin film transistor device is not favorably shortened.

In order to solve the above problems, the technical scheme provided by the invention is as follows:

the embodiment of the invention provides a thin film transistor array substrate, which comprises a substrate; the gate electrode comprises a terrace layer, an oxide active layer, a gate insulating layer, a grid electrode and an orthographic projection, wherein the terrace layer is arranged on the substrate, the oxide active layer is arranged on the substrate and is positioned above the terrace layer, the oxide active layer comprises a channel part and conductor parts positioned on two opposite sides of the channel part, the horizontal plane height of the top surface of the channel part is higher than the horizontal plane height of the top surface of any conductor part, the grid electrode insulating layer is arranged on the oxide active layer, the grid electrode is arranged on the grid electrode insulating layer, and the orthographic projection of the grid electrode on the substrate covers the orthographic projection of the terrace layer and the channel part on the substrate; and a source electrode and a drain electrode electrically connected to the conductor portion.

Further, the thin film transistor array substrate further comprises a buffer layer disposed on the substrate and covering the mesa layer, wherein the mesa layer is made of an insulating material or a metal oxide.

Further, the buffer layer comprises a boss, and the channel part is arranged on the boss and covers the whole boss.

Further, the channel portion includes two slope sides, one end of each slope side is connected with the corresponding conductor portion, and the slope sides are inclined in the direction away from the channel portion and towards the corresponding conductor portion.

Further, the terrace layer comprises a first end face and a second end face which are respectively inclined outwards, and the orthographic projection of the channel part on the substrate covers the orthographic projection of the terrace layer on the substrate.

Further, the gate insulating layer includes two offset portions disposed oppositely, the offset portions are defined at portions between end edges of the gate insulating layer corresponding to the gate and corresponding end edges of the gate insulating layer, wherein orthographic projections of the two offset portions on the substrate respectively cover orthographic projections of the first end surface and the second end surface of the terrace layer and the sloping edge of the channel portion on the substrate.

Further, the thin film transistor array substrate further includes an interlayer insulating layer covering the oxide active layer, the gate insulating layer, and the gate electrode, and the interlayer insulating layer includes a plurality of via holes, wherein the source electrode and the drain electrode are disposed on the interlayer insulating layer and electrically connected to the conductor part through the plurality of via holes.

The embodiment of the invention also provides a manufacturing method of the thin film transistor array substrate, which comprises the steps of depositing a layer of platform layer on the substrate, wherein the platform layer is made of insulating materials or metal oxide; forming an oxide active layer on a substrate, and forming a channel part and conductor regions positioned at two opposite sides of the channel part by utilizing a photoetching process; depositing a gate insulating layer on the oxide active layer; depositing a grid metal layer on the grid insulating layer; patterning the layer of gate metal layer by using a photolithography process to form a gate, and self-aligning and etching the gate insulating layer to expose the conductor region of the oxide active layer, wherein the orthographic projection of the gate on the substrate covers the terrace layer and the orthographic projection of the channel part on the substrate; conducting whole-surface plasma treatment to enable the conductor region of the oxide active layer to be conductive and form a conductor part, wherein the height of the horizontal plane where the top surface of the channel part is located is higher than that of the top surface of any one conductor part; depositing an interlayer insulating layer to cover the oxide active layer, the gate insulating layer and the gate electrode, and patterning the interlayer insulating layer to form a plurality of via holes; and depositing a source/drain metal layer, and patterning to form a source and a drain, wherein the source and the drain are electrically connected with the conductor part of the oxide active layer through the via holes.

Further, the step of forming an oxide active layer on the substrate may be preceded by the steps of: depositing a buffer layer on the substrate to cover the platform layer, and forming a boss positioned right above the platform layer by the buffer layer through a photoetching process, wherein the channel part is arranged on the boss and covers the whole boss.

Further, the channel portion includes two slope sides, one end of each slope side is connected to the corresponding conductor portion, and the slope sides are inclined in a direction away from the channel portion and toward the corresponding conductor portion, wherein the gate insulating layer includes two offset portions which are oppositely arranged, each offset portion is formed at a portion between an end edge of the gate insulating layer corresponding to the gate and the corresponding end edge of the gate insulating layer, and orthographic projections of the two offset portions on the substrate respectively cover opposite end surfaces of the terrace layer and orthographic projections of the slope sides of the channel portion on the substrate.

The invention has the beneficial effects that: the embodiment of the application provides a thin film transistor and a manufacturing method thereof, wherein a film layer structure above the thin film transistor forms a gradual slope-shaped offset part by utilizing the arrangement of a platform layer and the angle regulation and control of a first end face and a second end face of the platform layer, wherein the orthographic projections of two offset parts on a substrate cover the orthographic projections of a slope edge of a channel part on the substrate and respectively fall on the first end face and the second end face of the platform layer. By means of the arrangement of the offset part, the conductive diffusion path of the oxide active layer is prolonged, the length of a low-resistance region formed by diffusing two ends of the channel part into the channel part after self-aligned etching is reduced, the shortening of the effective channel length is effectively regulated or restrained, the effective channel length is guaranteed, the size reduction of a thin film transistor device is facilitated, and the technical problems that the low-resistance regions exist at two ends of the channel due to the fact that the diffusion of the conductive effect on two sides of the channel of a traditional thin film transistor device causes the shortening of the effective channel length and is not beneficial to the shortening of the size of the thin film transistor device are effectively solved.

Drawings

In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic cross-sectional view of a thin film transistor array substrate according to an embodiment of the present application.

Fig. 2 is a schematic cross-sectional view of a thin film transistor array substrate according to another embodiment of the present disclosure.

Fig. 3 is a flowchart of a method for manufacturing a thin film transistor array substrate according to an embodiment of the present disclosure.

Fig. 4 to 11 are schematic diagrams of film structures of thin film transistors manufactured in steps of a method for manufacturing a thin film transistor array substrate according to an embodiment of the present application.

Detailed Description

The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals. In the drawings, the thickness of some layers and regions are exaggerated for clarity of understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily illustrated, but the present invention is not limited thereto.

The embodiment of the application provides a thin film transistor which can be arranged in an array and prepared into a thin film transistor array substrate. The thin film transistor array substrate is provided with a plurality of grid scanning lines and a plurality of data lines, the grid scanning lines and the data lines define a plurality of pixel units, and the thin film transistor and the pixel electrode are arranged in each pixel unit. The thin film transistor array substrate can be used as a driving substrate of a liquid crystal display or an organic light emitting diode display.

Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a thin film transistor array substrate 1 according to an embodiment of the present disclosure. As shown in fig. 1, the thin film transistor array substrate 1 provided in the embodiment of the present application includes a substrate 10, a terrace layer 11, an oxide active layer 13, a gate insulating layer 14, a gate electrode 15, an interlayer insulating layer 16, source and drain electrodes 17, a passivation layer 18, and a pixel electrode 19, which are sequentially disposed. The material of the substrate 10 may be glass or transparent plastic, and is preferably glass. The surface of the substrate 10 is provided with a terrace layer 11. Specifically, a mesa layer thin film is deposited using an insulating material, and patterned by a photolithography process to form the mesa layer 11. The mesa layer 11 includes a top surface and first and second end surfaces 111 and 112. The first end surface 111 and the second end surface 112 are respectively disposed at two opposite ends of the mesa layer 11, and the first end surface 111 and the second end surface 112 are respectively inclined outward from the top surface of the mesa layer 11 toward the substrate 10. Preferably, the first end surface 111 forms an angle of 40 to 80 with the substrate 10, and the second end surface 112 forms an angle of 40 to 80 with the substrate 10. In one embodiment, the angle between the first end surface 111 and the substrate 10 is the same as the angle between the second end surface 112 and the substrate 10. It is noted that the above-mentioned angle range is set according to the process capability range of the etching process, and can promote the upper film layer to form the corresponding inclined configuration.

As shown in fig. 1, the oxide active layer 13 is disposed on the substrate 10, and the material of the oxide active layer 13 may be a metal oxide semiconductor of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), or Indium Gallium Zinc Tin Oxide (IGZTO). The oxide active layer 13 includes a channel portion 131 and conductor portions 132 positioned at opposite sides of the channel portion 131, wherein the channel portion 131 is positioned directly above the mesa layer 11. Note that, since the terrace layer 11 is provided on the surface of the substrate 10, the height of the channel portion 131 is raised accordingly, so that the channel portion 131 and the conductor portion 132 are located at different horizontal positions, respectively. That is, the top surface of the channel portion 131 is located at a level higher than that of the top surface of any one of the conductor portions 132. Specifically, the channel portion 131 includes two slopes 133, one end of each slope 133 is connected to the corresponding conductor portion 132, and the other end extends from the channel portion 131, wherein the slopes 133 are inclined away from the channel portion 131 and toward the corresponding conductor portion 132.

Referring to fig. 1, a gate insulating layer 14 is disposed on the oxide active layer 13. The gate electrode 15 is disposed on the gate insulating layer 14. The gate electrode 15 is formed by patterning a metal layer through a photolithography process, and self-aligned etching the gate insulating layer 14 to expose the conductor region 130 of the oxide active layer 13 (as shown in fig. 6), and then performing a plasma (plasma) process to make the conductor region 130 of the oxide active layer 13 conductive to form the conductor portion 132. Further, the gate insulating layer 14 is subjected to the photolithography process and the self-aligned etching to form two offset portions 141. The two offset portions 141 are disposed at opposite ends of the gate insulating layer 14, and each offset portion 141 is disposed along the slope edge 133 of the channel portion 131 and covers the slope edge 133. Specifically, each offset 141 is defined at a portion between an edge of the gate insulating layer 14 corresponding to the gate 15 and a corresponding edge of the gate insulating layer 14. Note that the mesa layer 11 has a length smaller than that of the channel portion 131 and substantially the same as that of the gate 15. That is, an orthographic projection of the gate 15 on the substrate 10 covers an orthographic projection of the mesa layer 11 and the channel portion 131 on the substrate 10. In this embodiment, the difference in length between the mesa layer 11 and the gate 15 is less than 2 microns. As can be seen from the schematic cross-sectional structure of the thin film transistor array substrate 1 in fig. 1, the first end surface 111 and the second end surface 112 of the mesa layer 11 respectively extend out of the length range of the gate 15 in the vertical cross-section. That is, the orthographic projection of each offset 141 on the substrate 10 covers the orthographic projection of the first end face 111 or the second end face 112 of the mesa layer 11 on the substrate 10 of 1.

As shown in fig. 1, an interlayer insulating layer 16 is deposited on the substrate 10 to cover the oxide active layer 13, the gate insulating layer 14 and the gate electrode 15, and the interlayer insulating layer 16 is patterned to form a plurality of via holes 160. The source and drain electrodes 17 are disposed on the interlayer insulating layer 16 and electrically connected to the conductor portions 132 of the oxide active layer 13 through the respective vias 160. In addition, a passivation layer 18 is further formed on the interlayer insulating layer 16, and the material thereof may be nitride (silicon nitride, etc.), oxide (silicon oxide, silicon dioxide), or a multi-layered structure film. In another embodiment, a planarization layer (not shown) is further disposed on the passivation layer 18, and the planarization layer can provide further protection for the underlying film layer and provide better planarization. A pixel electrode 19 is formed on the passivation layer 18 or on the planarization layer. The pixel electrode 19 is formed via a patterned metal layer and electrically connects the source and drain electrodes 17 through the through-hole 180. According to all the above components, the present embodiment provides a top gate type thin film transistor array substrate 1, which can be used as a driving substrate for a subsequent liquid crystal display or an organic light emitting diode display.

Please refer to fig. 2, which is a schematic cross-sectional view of a thin film transistor array substrate 1 according to another embodiment of the present application. The embodiment shown in fig. 2 is different from that shown in fig. 1 in that the thin film transistor array substrate 1 shown in fig. 2 is further provided with a buffer layer 12 (described in detail later), and other similar components are not described in detail herein. As shown in fig. 2, the thin film transistor array substrate 1 provided in the embodiment of the present invention includes a substrate 10, a terrace layer 11, a buffer layer 12, an oxide active layer 13, a gate insulating layer 14, a gate electrode 15, an interlayer insulating layer 16, source and drain electrodes 17, a passivation layer 18, and a pixel electrode 19, which are sequentially disposed. Specifically, a mesa layer thin film is deposited using an insulating material or a metal oxide material, and patterned by a photolithography process to form the mesa layer 11.

Referring to fig. 2, a buffer layer 12 is deposited on the substrate 10 to cover the mesa layer 11. Specifically, the material of the buffer layer 12 may be nitride (silicon nitride, etc.), oxide (silicon oxide, silicon dioxide), or a multi-layer film. The buffer layer 12 formed by deposition has a mesa 121 at a corresponding lower mesa. It should be noted that, in the embodiment shown in fig. 1, the terrace layer 11 is made of an insulating material, and therefore, the buffer layer 12 may not be provided, but in order to increase the adhesion between the glass substrate and each active layer on the surface thereof and provide the function of blocking impurities inside the glass substrate from diffusing into each active layer in the process, the thin film transistor array substrate 1 of the embodiment of the present application is provided with the buffer layer 12 on the substrate 10.

As shown in fig. 2, an oxide active layer 13 is deposited on the buffer layer 12. The oxide active layer 13 includes a channel portion 131 and conductor portions 132 on opposite sides of the channel portion 131. It is particularly noted that the channel portion 131 and the conductor portions 132 are located at different horizontal levels, i.e., the top surface of the channel portion 131 is located at a higher level than the top surface of any one of the conductor portions 132. Specifically, the channel portion 131 is disposed on the mesa 121 of the buffer layer 12 and covers the entire mesa 121. It should be noted that the channel portion 131 includes two slopes 133, one end of each slope 133 is connected to the corresponding conductor portion 132, and the other end extends from the channel portion 131, wherein the slope 133 is inclined away from the channel portion 131 and toward the corresponding conductor portion 132. As shown in fig. 2, the buffer layer 12 is disposed between the oxide active layer 13 and the substrate 10 and the mesa layer 11.

Referring to fig. 2, the gate insulating layer 14 is disposed on the oxide active layer 13. The gate electrode 15 is disposed on the gate insulating layer 14. Further, the gate insulating layer 14 is subjected to a photolithography process and a self-aligned etching process to form two offset portions 141. The two offset portions 141 are disposed at opposite ends of the gate insulating layer 14, and each offset portion 141 is disposed along the slope edge 133 of the channel portion 131 and covers the slope edge 133. Specifically, each offset 141 is defined at a portion between an edge of the gate insulating layer 14 corresponding to the gate 15 and a corresponding edge of the gate insulating layer 14. It should be noted that the length of the mesa layer 11 is smaller than the length of the channel portion 131 and is substantially the same as the length of the gate 15, that is, the orthographic projection of the channel portion 131 on the substrate 10 covers the orthographic projection of the mesa layer 11 on the substrate 10. In addition, an orthographic projection of the gate electrode 15 on the substrate 10 covers an orthographic projection of the terrace layer 11 and the channel portion 131 on the substrate 10. In this embodiment, the difference in length between the mesa layer 11 and the gate 15 is less than 2 microns. As can be seen from the schematic cross-sectional structure of the tft array substrate 1 in fig. 1, the first end surface 111 and the second end surface 112 of the mesa layer 11 are inclined at an angle of 40 ° to 80 °, such that the first end surface 111 and the second end surface 112 respectively extend out of the gate 15 in a vertical cross-section. That is, an orthographic projection of each offset 141 on the substrate 10 is located on the first end surface 111 or the second end surface 112 of the mesa layer 11.

As shown in fig. 2, an interlayer insulating layer 16 is deposited on the buffer layer 12 to cover the oxide active layer 13, the gate insulating layer 14 and the gate electrode 15, and the interlayer insulating layer 16 is patterned to form a plurality of via holes 160. The source and drain electrodes 17 are disposed on the interlayer insulating layer 16 and electrically connected to the conductor portions 132 of the oxide active layer 13 through the respective vias 160. In addition, a passivation layer 18 is further formed on the interlayer insulating layer 16. In another embodiment, a planarization layer (not shown) is further disposed on the passivation layer 18. A pixel electrode 19 is formed on the passivation layer 18 or on the planarization layer. The pixel electrode 19 electrically connects the source and drain electrodes 17 through the through hole 180. In accordance with all the above components, the present embodiment provides a top gate type thin film transistor array substrate 1. Accordingly, the thin film transistor array substrate 1 of the embodiment of the present application can be used as a driving substrate for a subsequent liquid crystal display or an organic light emitting diode display.

As described above, in the thin film transistor array substrate 1 of the embodiment of the present application, by the arrangement of the mesa layer 11 and the angle adjustment of the first end surface 111 and the second end surface 112 of the mesa layer 11, the upper film structure forms the gradually sloping offset portion 141, wherein the orthographic projections of the two offset portions 141 on the substrate 10 cover the orthographic projections of the sloping edge 133 of the channel portion 131 on the substrate 10, and fall on the first end surface 111 and the second end surface 112 of the mesa layer 11, respectively. By means of the arrangement of the offset part 141, a conductor diffusion path of the oxide active layer 13 is prolonged, and the length of a low-resistance region formed by diffusion from two ends of the channel part 131 into the channel part 131 after self-aligned etching is reduced, so that the shortening of the effective channel length is effectively regulated or restrained, the effective channel length is ensured, and the reduction of the size of a thin film transistor device is favorably realized.

The present embodiment further provides a method for manufacturing a thin film transistor array substrate, that is, a method for manufacturing the thin film transistor array substrate 1 of the above embodiment.

Please refer to fig. 3 and fig. 4 to 11. Fig. 3 is a flowchart of a method for manufacturing the thin film transistor array substrate 1 according to an embodiment of the present disclosure. Fig. 4 to 11 are schematic diagrams of film structures of the thin film transistor array substrate 1 manufactured in the steps of the method for manufacturing the thin film transistor array substrate 1 according to the embodiment of the present application.

As shown in fig. 3, the method for manufacturing the thin film transistor array substrate 1 according to the embodiment of the present application includes steps S10 to S80:

step S10: a mesa layer is deposited on the substrate. Specifically, as shown in fig. 4, the mesa layer 11 on the substrate 10 has a thickness of 100 angstroms (angstroms,)-and includes a first end surface 111 and a second end surface 112 respectively inclined outward, and the material of the terrace layer 11 is an insulating material or a metal oxide.

If the mesa layer 11 is made of an insulating material, the thin film transistor array substrate shown in fig. 1 may not have a buffer layer.

In another embodiment, a buffer layer may be further deposited on the substrate 10 in order to increase the adhesion between the glass substrate and the active layers on the surface of the glass substrate and provide a function of blocking the diffusion of impurities inside the glass substrate into the active layers during the process. Specifically, as shown in fig. 5, the manufacturing method further includes step S101: depositing a buffer layer on the substrate to cover the mesa layer. The buffer layer 12 is made of silicon oxide, silicon nitride orA film of a multilayer structure, and havingWherein the buffer layer 12 forms the mesa 121 directly above the mesa layer 11 by a photolithography process.

Step S20: an oxide active layer is provided on a substrate, and a channel portion and conductor regions on opposite sides of the channel portion are formed using a photolithography process. Specifically, as shown in fig. 6, the oxide active layer 13 is made of a metal oxide semiconductor of IGZO, IZTO, or IGZTO, and hasIs measured. The channel portion 131 includes two sloped sides 133, one end of each sloped side 133 is connected to the corresponding conductive region 130, and each sloped side 133 is inclined away from the channel portion 131 and toward the corresponding conductive region 130. Wherein the channel portion 131 is disposed on the boss 121 and covers the entire boss 121.

Step S30: and depositing a gate insulating layer on the oxide active layer. Specifically, as shown in fig. 7, the gate insulating layer 14 may be made of silicon oxide, silicon nitride or a multi-layer film and hasIs measured.

Step S40: and depositing a gate metal layer on the gate insulating layer. Specifically, as shown in fig. 8, the gate metal layer 150 may be made of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), manganese (Mn), etc., or an alloy thereof, and haveIs measured.

Step S50: and patterning the layer of gate metal layer by utilizing a photoetching process to form a gate, and etching the gate insulating layer in a self-alignment manner to expose the conductor region of the oxide active layer, wherein the orthographic projection of the gate on the substrate covers the terrace layer and the orthographic projection of the channel part on the substrate. . Specifically, as shown in fig. 8, the gate metal layer 150 is patterned by a photolithography process using a mask 110 to form the gate electrode 15, and the gate insulating layer 14 is self-aligned etched to expose the conductor region 130 of the oxide active layer 13. As shown in fig. 9, the gate insulating layer 14 is subjected to the photolithography process and the self-aligned etching to form two offset portions 141, the two offset portions 141 respectively cover the slope sides 133 of the channel portion 131, and orthographic projections of the two offset portions 141 on the substrate 10 are located on the first end surface 111 or the second end surface 112 of the mesa layer 11. Meanwhile, the orthographic projections of the offset portions 141 on the substrate 10 cover the orthographic projections of the first end face 111 and the second end face 112 of the terrace layer 11 on the substrate 10 and the orthographic projections of the slope sides 133 of the channel portions 131 on the substrate 10, respectively.

Step S60: and conducting whole surface plasma (plasma) treatment to make the conductor region of the oxide active layer conductive and form a conductor part, wherein the height of the horizontal plane where the top surface of the channel part is higher than that of the top surface of any one conductor part. Specifically, as shown in fig. 9, for the oxide active layer 13 without the photoresist/gate insulating layer 14/metal protection thereon, the resistance is significantly reduced after the process, the N + -type conductor portion 132 is formed, and the conductive diffusion paths corresponding to the offset portions 141 on the first end surface 111 and the second end surface 112 of the mesa layer 11 are extended.

Step S70: depositing an interlayer insulating layer to cover the oxide active layer, the gate insulating layer and the gate, and patterning the interlayer insulating layer to form a plurality of via holes. Specifically, as shown in FIG. 10, the interlayer insulating layer 16 may be made of silicon oxide, silicon nitride or a multi-layered film, and hasIs measured. The interlayer insulating layer 16 is patterned to expose source/drain contact regions of the oxide active layer 13 and to form a plurality of via holes 160.

Step S80: and depositing a source/drain metal layer, and patterning to form a source and a drain, wherein the source and the drain are electrically connected with the conductor part of the oxide active layer through the via holes. Specifically, as shown in fig. 11, the interlayer insulating layer 16 depositing a source/drain metal layer, wherein the source/drain metal layer is made of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), manganese (Mn), etc., or an alloy thereof, and hasIs measured. The source and drain electrodes 17 are formed by the patterned source/drain metal layers, and are electrically connected to the conductor portions 132 of the oxide active layer 13 through the vias 160.

In addition, as shown in fig. 1 and 2, a passivation layer 18, which may be made of silicon oxide, silicon nitride or a multi-layered structure film and has a structure of silicon oxide, silicon nitride or a multi-layered structure film, is further formed on the interlayer insulating layer 16And the passivation layer 18 is formed with a through hole 180 by a photolithography process. In another embodiment, a planarization layer (not shown) may also be disposed on the passivation layer 18. Finally, a pixel electrode layer is formed under the basic film structure, and the pixel electrode layer is patterned to form a pixel electrode 19, and the pixel electrode 19 is electrically connected to the source and the drain 17 through the through hole 180. Accordingly, the thin film transistor array substrate 1 of the present application can be used as a driving substrate for a subsequent liquid crystal display or an organic light emitting diode display.

In summary, in the thin film transistor array substrate and the method for manufacturing the same according to the embodiments of the present application, the mesa layer is disposed, and the angles of the first end surface and the second end surface of the mesa layer are adjusted, so that the upper film structure forms the gradually sloping offset portion, where orthographic projections of the two offset portions on the substrate cover orthographic projections of the slope edge of the channel portion on the substrate, and the two offset portions respectively fall on the first end surface and the second end surface of the mesa layer. By means of the arrangement of the offset part, the conductive diffusion path of the oxide active layer is prolonged, the length of a low-resistance region formed by diffusing two ends of the channel part into the channel part after self-aligned etching is reduced, the shortening of the effective channel length is effectively regulated or restrained, the effective channel length is guaranteed, the size reduction of a thin film transistor device is facilitated, and the technical problems that the low-resistance regions exist at two ends of the channel due to the fact that the diffusion of the conductive effect on two sides of the channel of a traditional thin film transistor device causes the shortening of the effective channel length and is not beneficial to the shortening of the size of the thin film transistor device are effectively solved.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The above embodiments of the present application are described in detail, and specific examples are applied in the present application to explain the principles and implementations of the present application, and the description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.