阅读说明：本技术 一种扩散型高压快速软恢复二极管及其制造方法 (Diffusion type high-voltage fast soft recovery diode and manufacturing method thereof ) 是由 张磊 陈黄鹂 赵卫 赵涛 张琦 周杰 周哲 何杉 于 2021-08-19 设计创作，主要内容包括：本发明公开了一种扩散型高压快速软恢复二极管及其制造方法。以N-基区为衬底,N-基区上方的阳极侧交替设置了P+/P掺杂区,分别通过硼预沉积和AL扩散形成；N-为耐压区；在阳极P+区与N-区之间设置了P缓冲层；阴极侧交替设置了高浓度的N+区和稍低浓度的P+区；在阴极侧的N+/P+区与N-区之间设置了中等掺杂浓度的N缓冲层。阳极区上方设有阳极,阴极区下方设有阴极。本发明还公开了该种扩散性高压快速软恢复二极管的制备方法。本发明的高压快速软恢复二极管具有反向恢复速度快、软度大,工艺简单,成本低的优点。(The invention discloses a diffusion type high-voltage fast soft recovery diode and a manufacturing method thereof. Taking an N-base region as a substrate, and alternately arranging P +/P doped regions on the anode side above the N-base region, wherein the P +/P doped regions are respectively formed by boron pre-deposition and AL diffusion; n-is a voltage-resistant area; a P buffer layer is arranged between the anode P + region and the N-region; high-concentration N + regions and slightly low-concentration P + regions are alternately arranged on the cathode side; an N buffer layer with medium doping concentration is arranged between the N +/P + region and the N-region on the cathode side. An anode is arranged above the anode region, and a cathode is arranged below the cathode region. The invention also discloses a preparation method of the diffusible high-voltage fast soft recovery diode. The high-voltage fast soft recovery diode has the advantages of high reverse recovery speed, high softness, simple process and low cost.)

1. The utility model provides a quick soft recovery diode of diffusion type high pressure which characterized in that: an N-region (3) is taken as a substrate, and a P + region (21) and a P region (22) are alternately arranged on the anode side above the N-region (3) and are respectively formed by boron pre-deposition and AL diffusion; the N-area (3) is a pressure-resistant area; a P buffer layer (22) is arranged between the anode P + region (21) and the N-region (3); high-concentration N + regions (42) and slightly low-concentration P + regions (23) are alternately arranged on the cathode side; an N buffer layer (41) with medium doping concentration is arranged above an N + region (42) and a P + region (23) on the cathode side, an anode A (1) is arranged above an anode region, and a cathode K (5) is arranged below a cathode region.

2. A diffused high voltage fast soft recovery diode as claimed in claim 1, wherein: the anode side P + region (21) and the cathode side P + region (23) have the same size, the anode and cathode positions are corresponding, the ratio of the width of the P + region to the width of the anode and cathode is 1/4-1/3, and the doping concentration of the anode and cathode P + regions is 5 x 10¹⁸cm^-3～1×10¹⁹cm^-3The depth is 2 to 5 μm.

3. A manufacturing method of a diffusion type high-voltage fast soft recovery diode is characterized by comprising the following steps:

(1) selecting an original defect-free dislocation-free high-resistance zone-melting neutron monocrystalline silicon wafer as a substrate material of an N-zone;

(2) after cleaning a silicon wafer, pre-depositing aluminum on two surfaces of the silicon single crystal wafer at 900-1100 ℃ to form shallow junction P⁺N^-P⁺Structure;

(3) marking the silicon wafer in the step (2) to distinguish the anode and the cathode, and then corroding aluminum pre-deposited on the cathode surface to a depth of 5-10 mu m to form shallow junction P⁺N^-Structure;

(4) oxidizing the silicon wafer in the step (3) at the temperature of 900-1200 ℃ for 2-5 h, wherein the generated silicon dioxide layer is used as a masking layer for subsequent phosphorus diffusion and has the thickness of 1-2 mu m;

(5) coating photoresist on the silicon wafer obtained in the step (4), exposing and developing to protect the anode silicon dioxide layer, and removing the cathode silicon dioxide layer;

(6) performing low-temperature phosphorus pre-deposition on the cathode surface of the silicon wafer in the step (5) at the temperature of 1000-1150 ℃, and then performing oxidation high-temperature diffusion at the temperature of 1150-1250 ℃ to form deep-junction PN^-An N structure, wherein the junction depth of an N-type layer is 20-40 mu m;

(7) photoetching a P + diffusion window on the anode of the silicon wafer in the step (6), removing a cathode silicon dioxide layer, and pre-etching the silicon wafer on the two sides at low temperatureDepositing boron at 900-1100 ℃ for 40-200 min to form low-concentration boron with the junction depth of 2-5 mu m and obtain P⁺PN^-NP⁺Structure;

(8) carrying out low-temperature oxidation on the silicon wafer in the step (7) at 900-1100 ℃ for 5-10 h, and forming a silicon dioxide layer on the surface of the silicon wafer to serve as a masking layer for subsequent phosphorus diffusion;

(9) photoetching an N + diffusion window on the silicon wafer cathode in the step (8), pre-depositing phosphorus at 1000-1150 ℃ for 1-2 h, wherein boron basically does not diffuse into the silicon wafer at the temperature and the time, and the high-concentration phosphorus completely compensates the boron in the step (7) by utilizing the impurity solid solubility and the diffusion coefficient of the phosphorus higher than those of the boron, wherein the depth of the phosphorus is 5-15 mu m, and the impurity concentration is 5 multiplied by 10¹⁹cm^-3～5×10²⁰cm^-3Boron has a depth of 2 to 5 μm and a concentration of 5X 10¹⁸cm^-3～1×10¹⁹cm^-3So that a regularly staggered P + N + structure is obtained on the cathode side;

(10) evaporating aluminum on the two sides of the silicon wafer obtained in the step (9) to obtain aluminum with the thickness of 10-20 microns, and then metalizing the silicon wafer at the temperature of 400-600 ℃;

(11) performing laser circle cutting on the silicon wafer obtained in the step (10), cutting the silicon wafer into a wafer with the diameter of 38-125 mm, molding the table top, corroding and gluing for protection, forming a complete chip, and completing initial measurement of reverse blocking voltage;

(12) performing electron irradiation on the chip obtained in the step (11), and adjusting reverse recovery time t_rr2 to 10 mu s, reverse recovery charge Q_rr4000-10000 mu As, and finally carrying out final measurement.

Technical Field

The invention belongs to the technical field of power semiconductor device manufacturing, and relates to a diffusion type high-voltage fast soft recovery diode and a manufacturing method thereof.

Background

With the development of a direct-current power grid in the directions of high efficiency, high density, high reliability and low cost, the crimping type IGBT and the IGCT for medium and high-voltage direct-current power transmission are further developed, which puts higher requirements on the performance of a large-size wafer freewheeling diode connected in anti-parallel with the crimping type IGBT and the IGCT. It is required to have high withstand voltage, low leakage current, fast soft recovery characteristics and high resistance to dynamic avalanche.

In order to improve the fast soft recovery characteristics of the high voltage diode, the anode P +/P and cathode N +/P + region structures are combined, as shown in fig. 1. During reverse recovery, the P + region injects holes into the NN-junction, maintaining the tail current at the end of reverse recovery. Generally, the cathode structure with the P + region is applied to a small-sized, square diode, and the N + region and the P + region are selectively formed by an ion implantation process, which is relatively high in cost. If a selective P + region is formed in a large-sized, wafer high-voltage diode, not only an additional photolithography process is required, but also the energy of ion implantation is required to be high, and a long-time annealing is required to reach a corresponding junction depth. Therefore, the process is complicated and the cost is high. The development of high-performance and low-cost high-voltage fast soft recovery diodes is urgently needed.

Disclosure of Invention

The invention aims to provide a diffusion type high-voltage fast soft recovery diode and a manufacturing method thereof. The defects of poor reverse recovery characteristic, complex process and high cost of the high-voltage diode in the prior art are overcome.

The invention has the technical scheme that a diffusion type high-voltage rapid soft recovery diode takes an N-base region as a substrate, and a P + region and a P region are alternately arranged on the anode side above the N-base region and are respectively formed by boron pre-deposition and AL diffusion; the N-area is a voltage-resistant area; a P buffer layer is arranged between the anode P + region and the N-region; high-concentration N + regions and slightly low-concentration P + regions are alternately arranged on the cathode side; an N buffer layer of medium doping concentration is provided over the N + and P + regions on the cathode side. An anode A is arranged above the anode area, and a cathode K is arranged below the cathode area.

The sizes of the anode side P + region and the cathode side P + region are completely the same, the anode and cathode positions are corresponding, the ratio of the width of the P + region to the width of the anode and cathode is 1/4-1/3, and the doping concentrations of the anode and cathode P + regions are both 5 multiplied by 10¹⁸cm^-3～1×10¹⁹cm^-3The depth is 2 to 5 μm.

A manufacturing method of a diffusion type high-voltage fast soft recovery diode is implemented according to the following steps:

(1) selecting an original defect-free dislocation-free high-resistance zone-melting neutron monocrystalline silicon wafer as a substrate material of an N-zone;

(2) after cleaning a silicon wafer, pre-depositing aluminum on two surfaces of the silicon single crystal wafer at 900-1100 ℃ to form shallow junction P⁺N^-P⁺Structure;

(3) marking the silicon wafer in the step (2) to distinguish the anode and the cathode, and then corroding aluminum pre-deposited on the cathode surface to a depth of 5-10 mu m to form shallow junction P⁺N^-Structure;

(4) oxidizing the silicon wafer in the step (3) at the temperature of 900-1200 ℃ for 2-5 h, wherein the generated silicon dioxide layer is used as a masking layer for subsequent phosphorus diffusion and has the thickness of 1-2 mu m;

(5) coating photoresist on the silicon wafer obtained in the step (4), exposing and developing to protect the anode silicon dioxide layer, and removing the cathode silicon dioxide layer;

(6) performing low-temperature phosphorus pre-deposition on the cathode surface of the silicon wafer in the step (5) at the temperature of 1000-1150 ℃, and then performing oxidation high-temperature diffusion at the temperature of 1150-1250 ℃ to form deep-junction PN^-An N structure, wherein the junction depth of an N-type layer is 20-40 mu m;

(7) photoetching a P + diffusion window on the anode of the silicon wafer in the step (6), removing a cathode silicon dioxide layer, and then pre-depositing boron on two sides at a low temperature of 900-1100 ℃ for 40-200 min to form low-concentration boron, wherein the junction depth is 2-5 mu m, and P is obtained⁺PN^-NP⁺Structure;

(8) carrying out low-temperature oxidation on the silicon wafer in the step (7) at 900-1100 ℃ for 5-10 h, and forming a silicon dioxide layer on the surface of the silicon wafer to serve as a masking layer for subsequent phosphorus diffusion;

(9) photoetching an N + diffusion window on the silicon wafer cathode in the step (8), pre-depositing phosphorus at 1000-1150 ℃ for 1-2 h, wherein boron basically does not diffuse into the silicon wafer at the temperature and the time, and the high-concentration phosphorus completely compensates the boron in the step (7) by utilizing the impurity solid solubility and the diffusion coefficient of the phosphorus higher than those of the boron, wherein the depth of the phosphorus is 5-15 mu m, and the impurity concentration is 5 multiplied by 10¹⁹cm^-3～5×10²⁰cm^-3Boron has a depth of 2 to 5 μm and a concentration of 5X 10¹⁸cm^-3～1×10¹⁹cm^-3So that a regularly staggered P + N + structure is obtained on the cathode side;

(10) evaporating aluminum on the two sides of the silicon wafer obtained in the step (9) to obtain aluminum with the thickness of 10-20 microns, and then metalizing the silicon wafer at the temperature of 400-600 ℃;

(11) performing laser circle cutting on the silicon wafer obtained in the step (10), cutting the silicon wafer into a wafer with the diameter of 38-125 mm, molding the table top, corroding and gluing for protection, forming a complete chip, and completing initial measurement of reverse blocking voltage;

(12) performing electron irradiation on the chip obtained in the step (11), and adjusting reverse recovery time t_rr2 to 10 mu s, reverse recovery charge Q_rr4000-10000 mu As, and finally carrying out final measurement.

Compared with the conventional large-size wafer diode structure, the invention has the following beneficial effects:

(1) the P + region on the surface of the anode a corresponds to the P + region of the cathode K, and the P region on the surface of the anode a corresponds to the N + region of the cathode K, so as to improve the fast soft recovery characteristic of the high voltage diode, as shown in fig. 1.

(2) By reasonably designing diffusion process conditions and utilizing higher impurity solid solubility and diffusion coefficient of phosphorus, boron of the cathode is compensated, so that the diffusion junction depth of the phosphorus is greater than that of the boron. The process complexity is reduced, and the stepwise selective injection of boron and phosphorus adopted by the common process is avoided, so that the process error caused by the alignment precision is avoided, the use of a photoetching plate is reduced, and the manufacturing cost is reduced.

(3) The anode and the cathode simultaneously pre-deposit boron at low temperature, and the boron doping concentration of the anode is further reduced by utilizing the segregation effect of boron impurities in the silicon dioxide layer through a long-time low-temperature oxidation process, so that the hole injection efficiency of the anode is better controlled, and the characteristics of quick and soft recovery are obtained.

Drawings

Fig. 1 is a cross-sectional view of a high voltage fast soft recovery diode made in accordance with the present invention.

Fig. 2 is a schematic diagram of the doping profile of a high voltage fast soft recovery diode manufactured by the present invention.

Fig. 3 illustrates the steps of the high voltage fast soft recovery diode manufacturing process according to the present invention.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

The structure of the high-voltage fast soft recovery diode is shown in figure 1, an N-region 3 is used as a substrate, and a P + region 21 and a P region 22 are alternately arranged on the anode side above the N-region 3 and are respectively formed by boron pre-deposition and AL diffusion; the N-area 3 is a voltage-resistant area; a P buffer layer 22 is arranged between the anode P + region 21 and the N-region 3; the cathode side is alternately provided with high-concentration N + regions 42 and slightly low-concentration P + regions 23; an N buffer layer 41 of medium doping concentration is provided over the N + region 42 and the P + region 23 on the cathode side. An anode A1 is arranged above the anode region, and a cathode K5 is arranged below the cathode region.

The sizes of the anode side P + region 21 and the cathode side P + region 23 of the high voltage fast soft recovery diode shown in FIG. 1 are completely the same, the anode and the cathode correspond to each other, and the ratio of the width of the P + region to the width of the anode and the cathode is 1/4-1/3. Because the anode and cathode P + regions are formed by the same process, the doping concentration is 5 multiplied by 10¹⁸cm^-3～1×10¹⁹cm^-3The depth is 2 to 5 μm.

Fig. 2 is a schematic view of the doping profile at the corresponding CC 'and DD' cuts of fig. 1. The total thickness of the device is 500-1000 mu m. The junction depth of the anode P region is far greater than that of P + junction, and the depth range is 60-120 mu m; junction depths of the anode P + region and the cathode P + region are both 2-5 mu m; the N buffer layer is 20-40 mu m; the cathode N + junction depth is 5-15 μm.

The working principle of the high-voltage fast soft recovery diode is as follows:

the cathode adopts an alternate P +/N + structure, and holes are injected into a P + region at the end stage of reverse recovery, so that better reverse recovery softness is obtained. Under the anode P + region, the hole injection is stronger, so that the cathode P + region is arranged under the anode side P + region, and better softness is obtained; and under the anode P region, hole injection is weak, and self-soft, so that the cathode N + region is arranged under the anode P region. The design can simultaneously take account of surge characteristics and reverse recovery characteristics.

The invention provides a manufacturing method of a high-voltage fast soft recovery diode, which is implemented according to the following steps, and FIG. 3 is a schematic diagram of a corresponding process manufacturing flow.

(1) Selecting an original defect-free dislocation-free high-resistance zone-melting neutron monocrystalline silicon wafer as a substrate material of an N-zone;

(2) after cleaning a silicon wafer, pre-depositing aluminum on two surfaces of the silicon single crystal wafer at 900-1100 ℃ to form shallow junction P⁺N^-P⁺Structure;

(3) marking the silicon wafer in the step (2) to distinguish the anode and the cathode, and then corroding aluminum pre-deposited on the cathode surface to a depth of 5-10 mu m to form shallow junction P⁺N^-Structure;

(4) oxidizing the silicon wafer in the step (3) at the temperature of 900-1200 ℃ for 2-5 h, wherein the generated silicon dioxide layer is used as a masking layer for subsequent phosphorus diffusion and has the thickness of 1-2 mu m;

(5) coating photoresist on the silicon wafer obtained in the step (4), exposing and developing to protect the anode silicon dioxide layer, and removing the cathode silicon dioxide layer;

(6) performing low-temperature phosphorus pre-deposition on the cathode surface of the silicon wafer in the step (5) at the temperature of 1000-1150 ℃, and then performing oxidation high-temperature diffusion at the temperature of 1150-1250 ℃ to form deep-junction PN^-An N structure, wherein the junction depth of an N-type layer is 20-40 mu m;

(7) photoetching a P + diffusion window on the anode of the silicon wafer in the step (6)Removing the cathode silicon dioxide layer, then pre-depositing boron on the two sides at low temperature of 900-1100 ℃ for 40-200 min to form low-concentration boron, wherein the junction depth is 2-5 mu m, and obtaining P⁺PN^-NP⁺Structure;

(8) carrying out low-temperature oxidation on the silicon wafer in the step (7) at 900-1100 ℃ for 5-10 h, and forming a silicon dioxide layer on the surface of the silicon wafer to serve as a masking layer for subsequent phosphorus diffusion;

(9) photoetching an N + diffusion window on the silicon wafer cathode in the step (8), pre-depositing phosphorus at 1000-1150 ℃ for 1-2 h, wherein boron basically does not diffuse into the silicon wafer at the temperature and the time, and the high-concentration phosphorus completely compensates the boron in the step (7) by utilizing the impurity solid solubility and the diffusion coefficient of the phosphorus higher than those of the boron, wherein the depth of the phosphorus is 5-15 mu m, and the impurity concentration is 5 multiplied by 10¹⁹cm^-3～5×10²⁰cm^-3Boron has a depth of 2 to 5 μm and a concentration of 5X 10¹⁸cm^-3～1×10¹⁹cm^-3So that a regularly staggered P + N + structure is obtained on the cathode side;

(10) evaporating aluminum on the two sides of the silicon wafer obtained in the step (9) to obtain aluminum with the thickness of 10-20 microns, and then metalizing the silicon wafer at the temperature of 400-600 ℃;

(11) performing laser circle cutting on the silicon wafer obtained in the step (10), cutting the silicon wafer into a wafer with the diameter of 38-125 mm, molding the table top, corroding and gluing for protection, forming a complete chip, and completing initial measurement of reverse blocking voltage;

(12) performing electron irradiation on the chip obtained in the step (11), and adjusting reverse recovery time t_rr2 to 10 mu s, reverse recovery charge Q_rr4000-10000 mu As, and finally carrying out final measurement.