阅读说明：本技术 一种压摆率自适应调节的多级放大器结构与方法 (Multistage amplifier structure and method with adaptive slew rate adjustment ) 是由 张明 漆星宇 刘焕双 李肖飞 于 2021-09-13 设计创作，主要内容包括：本发明提出一种压摆率自适应调节的多级放大器结构与方法。所述结构包括第一差分放大级、第二误差放大级、第三数字比较级和输出反馈级；输出反馈级连接多位状态寄存器；输出反馈级生成状态值,将所述状态值按照时序存储至多位状态寄存器；第一差分放大级接收所述输出反馈级生成的反馈调节信号,基于所述反馈调节信号调节所述第一差分放大级的输入,从而通过输入控制电路调节所述放大器结构的压摆率。所述方法包括若多位状态寄存器中出现连续存储的第一状态值,或者出现连续存储的第二状态值,则生成反馈调节信号,调节输入端的偏置电路输出的偏置电流大小。本发明能够实现多级放大器结构的压摆率自适应调节。(The invention provides a multistage amplifier structure and a method for adaptively adjusting a slew rate. The structure comprises a first differential amplification stage, a second error amplification stage, a third digital comparison stage and an output feedback stage; the output feedback stage is connected with the multi-bit state register; the output feedback stage generates a state value, and the state value is stored to a multi-bit state register according to a time sequence; the first differential amplifier stage receives a feedback adjustment signal generated by the output feedback stage, and adjusts an input of the first differential amplifier stage based on the feedback adjustment signal, thereby adjusting a slew rate of the amplifier structure via an input control circuit. The method comprises the steps that if a continuously stored first state value or a continuously stored second state value appears in the multi-bit state register, a feedback adjusting signal is generated, and the magnitude of a bias current output by a bias circuit at an input end is adjusted. The invention can realize the self-adaptive regulation of the slew rate of the multistage amplifier structure.)

1. A slew rate adaptively adjusted multi-stage amplifier architecture comprising a first differential amplifier stage and a second error amplifier stage,

the method is characterized in that:

the second error amplification stage is connected with a third digital comparison stage;

the first differential amplification stage and the third digital comparison stage are connected by an output feedback stage;

the output feedback stage is connected with the multi-bit state register;

the output feedback stage receives the comparison output signal of the third digital comparison stage, generates a state value based on the comparison output signal, and stores the state value to the multi-bit state register according to a time sequence;

the first differential amplification stage receives a feedback adjustment signal generated by the output feedback stage, and adjusts the input of the first differential amplification stage based on the feedback adjustment signal;

the feedback adjustment signal is determined based on the state value that the multi-bit state register has stored.

2. A slew rate adaptive regulated multi-stage amplifier architecture as defined in claim 1, wherein:

the multi-bit state register is a time control transient memory;

the state value stored by the time control transient memory is only valid within a preset time period, and the size of the preset time period is adjustable.

3. A slew rate adaptively adjusted multistage amplifier architecture as defined in claim 2, wherein:

the multi-bit status register comprises N time-controlled transient memories, wherein N is an integer greater than 1;

the preset time interval of the ith time control transient state memory is not less than the preset time interval of the jth time control transient state memory, and j is more than or equal to 1 and less than or equal to N.

4. A slew rate adaptive regulated multi-stage amplifier architecture as defined in claim 1, wherein:

the comparison output signal is a logic value of 0 or a logic value of 1;

when the comparison output signal of the third digital comparison stage received by the output feedback stage is 1, generating a first state value and storing the first state value to an m-th time control transient memory; the m satisfies the following condition:

m is more than or equal to 1 and less than N; the state of the mth clocked transient memory is empty and the state of the (m + 1) th clocked transient memory is also empty.

5. A slew rate adaptive regulated multi-stage amplifier architecture as defined in claim 1, wherein:

the comparison output signal is a logic value of 0 or a logic value of 1;

when the comparison output signal of the third digital comparison stage received by the output feedback stage is 0, generating a second state value to be stored in an nth time control transient memory; the n satisfies the following condition: n >2, the state of the nth clocked transient memory is empty and the state of the (n-1) th clocked transient memory is non-empty.

6. A slew rate adaptively adjusted multistage amplifier architecture as defined in claim 4 or 5, wherein:

the determining of the feedback adjustment signal based on the state value already stored by the multi-bit state register specifically includes:

if a first state value is present that is stored consecutively in the multi-bit state register, or a second state value is present that is stored consecutively,

the feedback adjustment signal is generated.

7. A slew rate adaptively adjusted multistage amplifier architecture as defined in claim 4 or 5, wherein:

the input of the first differential amplifier stage comprises a bias circuit;

the first differential amplifier stage receives a feedback adjustment signal generated by the output feedback stage, and adjusts an input of the first differential amplifier stage based on the feedback adjustment signal, and the method specifically includes:

and adjusting the bias current output by the bias circuit of the input end based on the feedback adjusting signal.

8. A slew rate adaptive adjustment method of a multi-stage amplifier, the multi-stage amplifier comprising a first differential amplifier stage, a second error amplifier stage, a third digital comparison stage and an output feedback stage,

the method comprises the following steps:

the output feedback stage receives the comparison output signal output by the third digital comparison stage, generates a state value based on the comparison output signal, and stores the state value to a multi-bit state register according to a time sequence;

generating a feedback adjustment signal based on successive states of state values stored by a multi-bit state register;

adjusting an input signal of the first differential amplification stage based on the feedback adjustment signal.

9. The slew rate adaptive adjustment method of a multistage amplifier as defined in claim 8, wherein:

the comparison output signal is a logic value of 0 or a logic value of 1;

when the comparison output signal of the third digital comparison stage received by the output feedback stage is 1, generating a first state value and storing the first state value into a multi-bit state register;

and when the comparison output signal of the third digital comparison stage received by the output feedback stage is 0, generating a second state value to be stored in a multi-bit state register.

10. The slew rate adaptive adjustment method of a multistage amplifier according to claim 8 or 9, wherein:

and if the continuously stored first state value or the continuously stored second state value appears in the multi-bit state register, generating the feedback adjusting signal.

Technical Field

The invention belongs to the technical field of circuits, and particularly relates to a multistage amplifier structure and a multistage amplifier method capable of adaptively adjusting slew rate.

Background

The SLEW Rate (SLEW Rate), also called SLEW Rate, abbreviated as SR, has three units of V/s, V/ms and V/mus, and reflects the response capability of the operational amplifier to a rapidly changing signal. The reason for this is that when the negative feedback operational amplifier circuit is in an amplifying state, the potentials of the positive and negative terminals are always equal (virtual short), but when the input signal changes too fast, the amplifier performance may not achieve a fast response of the output signal and may not follow the input signal rate to change rapidly. The virtual short is now destroyed and the amplifier input stage is no longer balanced, which naturally distorts the output signal.

The slew rate is a parameter for measuring the working speed of the operational amplifier under the action of a large-amplitude signal. When the absolute value of the change slope of the input signal is smaller than SR, the output voltage changes according to a linear rule. That is, if the input signal changes too quickly and the slew rate of the selected signal is too low, the output will be distorted; however, the larger the slew rate is, the better the slew rate is, and in many cases, the slew rate of the actuator is limited.

The slew rate and bandwidth of the differential amplifier determine the speed at which the comparator operates. Charging/discharging rate of load according to slew rateIt can be seen that the factors that influence the slew rate are the bias current and the load capacitance of the differential amplifier, and the slew rate of the comparator can be reduced by adjusting the bias current and the bandwidth of the amplifier.

Chinese patent application CN113196663A proposes that a High Voltage (HV) compound switch may include coupling circuitry to help provide better slew rate (dV/dt) control, such as to limit electromagnetic energy radiation that may cause undesirable EMI during switching. The narrow-pulse high-current constant current source and the control method thereof proposed by CN112486232A get rid of the limitation of the operational amplifier slew rate on the narrow-pulse transition process by setting the short-circuit branch, and realize the narrow-pulse high-current constant current control similar to the ideal waveform by setting the multi-path parallel and clamping circuits.

However, in practical applications, slew rate control and adjustment for multi-stage operational amplifiers cannot be adaptively adjusted and fed back.

Disclosure of Invention

In order to solve the above technical problems, the present invention provides a multi-stage amplifier structure and method for adaptively adjusting slew rate.

In a first aspect of the invention, a slew rate adaptively adjusted multi-stage amplifier architecture is presented, the architecture comprising a first differential amplifier stage and a second error amplifier stage.

On the basis, the second error amplification stage is connected with a third digital comparison stage; the first differential amplification stage and the third digital comparison stage are connected by an output feedback stage; the output feedback stage is connected with the multi-bit state register; the output feedback stage receives the comparison output signal of the third digital comparison stage, generates a state value based on the comparison output signal, and stores the state value to the multi-bit state register according to a time sequence; the first differential amplification stage receives a feedback adjustment signal generated by the output feedback stage, and adjusts the input of the first differential amplification stage based on the feedback adjustment signal; the feedback adjustment signal is determined based on the state value that the multi-bit state register has stored.

Further, as a further improved introduction, in the above technical solution, after the state values are stored to the multi-bit state register according to a time sequence, the feedback adjustment signal may be generated based on a continuous state of the state values stored by the multi-bit state register; adjusting an input signal of the first differential amplification stage based on the feedback adjustment signal.

More specifically, preferably, the feedback adjustment signal is generated if a first state value stored continuously occurs in the multi-bit state register or a second state value stored continuously occurs in the multi-bit state register.

The first state value and the second state value are both determined based on a logic value of a comparison output signal of the third digital comparison stage;

as a further preferred solution, the multi-bit status register is a time-controlled transient memory;

the state value stored by the time control transient memory is only valid within a preset time period, and the size of the preset time period is adjustable.

When the comparison output signal of the third digital comparison stage received by the output feedback stage is 1, generating a first state value to be stored in the time control transient memory;

and when the comparison output signal of the third digital comparison stage received by the output feedback stage is 0, generating a second state value to be stored in the time control transient memory.

As a specific adjustment mode, the input end of the first differential amplification stage comprises a bias circuit and an input control circuit;

the first differential amplifier stage receives a feedback adjustment signal generated by the output feedback stage, and adjusts an input of the first differential amplifier stage based on the feedback adjustment signal, and the method specifically includes:

and adjusting the bias current output by the bias circuit of the input end through the input control circuit based on the feedback adjusting signal.

In a second aspect of the present invention, a method for adaptive slew rate adjustment of a multi-stage amplifier is provided, the multi-stage amplifier comprising a first differential amplifier stage, a second error amplifier stage, a third digital comparator stage, and an output feedback stage.

The method specifically comprises the following steps:

the output feedback stage receives the comparison output signal output by the third digital comparison stage, generates a state value based on the comparison output signal, and stores the state value to a multi-bit state register according to a time sequence;

generating a feedback adjustment signal based on successive states of state values stored by a multi-bit state register;

adjusting an input signal of the first differential amplification stage based on the feedback adjustment signal.

Wherein the comparison output signal is a logic value of 0 or a logic value of 1;

when the comparison output signal of the third digital comparison stage received by the output feedback stage is 1, generating a first state value and storing the first state value into a multi-bit state register;

and when the comparison output signal of the third digital comparison stage received by the output feedback stage is 0, generating a second state value to be stored in a multi-bit state register.

If a first state value continuously stored or a second state value continuously stored appears in the multi-bit state register, generating the feedback regulation signal;

and based on the feedback adjusting signal, adjusting the magnitude of the bias current output by the bias circuit at the input end through an input control circuit.

According to the technical scheme, the slew rate influence of the output end of the current amplifier can be evaluated through the continuity of the state value generated by the logic output of the digital comparator, so that the corresponding regulating and controlling signal is generated to change the bias current of the input end, the slew rate is adaptively changed through the change of the opening and closing state of the switching circuit of the input control circuit, the quick response is realized, and the simplicity and the high efficiency are realized through the modularized structure.

Further advantages of the invention will be apparent in the detailed description section in conjunction with the drawings attached hereto.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a block diagram of a slew rate adaptive regulated multi-stage amplifier architecture according to an embodiment of the present invention

FIG. 2 is a memory schematic of a multi-bit status register used with the multi-stage amplifier architecture of FIG. 1

FIG. 3 is a schematic diagram of a hierarchical amplification structure of the multi-stage amplifier structure of FIG. 1

FIG. 4 is a schematic diagram of the connection of the components of the input control circuit and the bias circuit of the multi-stage amplifier configuration of FIG. 1

FIG. 5 is a flow chart of a method for slew rate adjustment for the multi-stage amplifier configuration of FIG. 1

FIG. 6 is a flow chart of a further preferred embodiment of the method of FIG. 5

Detailed Description

The invention is further described with reference to the following drawings and detailed description.

Referring to fig. 1, there is shown an architecture diagram of a slew rate adaptively adjusted multi-stage amplifier structure according to an embodiment of the present invention.

In fig. 1, the multi-stage amplifier architecture includes a first differential amplification stage, a second error amplification stage, a third digital comparison stage, and an output feedback stage.

The second error amplification stage is connected to a third digital comparison stage in a connection configuration; the first differential amplification stage and the third digital comparison stage are connected by an output feedback stage; the output feedback stage is connected to a multi-bit state register.

The output feedback stage receives the comparison output signal of the third digital comparison stage, generates a state value based on the comparison output signal, and stores the state value to the multi-bit state register in a time sequence.

The specific structure of the multi-bit status register of fig. 1 can be seen in the schematic diagram of fig. 2. Fig. 2 shows three storage states of the multi-bit state register, which are divided into an upper diagram, a middle diagram and a lower diagram.

In the upper diagram of fig. 2, the initial state of the multi-bit state register is shown.

The multi-bit status register may be a contiguous memory space of N transient registers, each memory space storing only one status value, and writing cannot continue when a memory space already stores a status value.

In each embodiment of the present invention, the generated state values are sequentially stored to a storage space of which a certain state of the multi-bit state register is empty according to a generation timing sequence, and are searched according to the sequence of the N consecutive storage spaces, where the first state is empty.

In a specific embodiment, N is a positive integer power of 2, i.e., N is 2^kK is a positive integer greater than 1;

taking the upper diagram in fig. 2 as an example, N is 2⁴16, the multi-bit status register is a continuous memory space consisting of 16 transient registers, in order of 1-16.

In the upper diagram of fig. 2, the initial state of the multi-bit status register indicates that the status of the continuous memory space formed by 16 transient registers is empty, i.e., NULL (or NULL).

The lower and upper diagrams of fig. 2 store state values in a portion of the 16 transient registers, and subsequent embodiments will be described in detail.

After the state values are stored to the multi-bit state register according to a time sequence, the output feedback stage generates a feedback regulation signal;

the first differential amplifier stage receives a feedback adjustment signal generated by the output feedback stage and adjusts an input of the first differential amplifier stage based on the feedback adjustment signal.

The feedback adjustment signal is determined based on the state value that the multi-bit state register has stored.

Specifically, if a first state value continuously stored or a second state value continuously stored appears in the multi-bit state register, the feedback adjustment signal is generated.

Next, the generation of the state values will be further described with reference to the lower diagram and the middle diagram of fig. 2.

In fig. 1, the comparison output signal has a logic value of 0 or a logic value of 1; when the comparison output signal of the third digital comparison stage received by the output feedback stage is 1, generating a first state value and storing the first state value into a multi-bit state register;

and when the comparison output signal of the third digital comparison stage received by the output feedback stage is 0, generating a second state value to be stored in a multi-bit state register.

For ease of description, in the embodiment of fig. 2, the first state value and the second state value directly correspond to a logical value of the comparison output signal.

When the comparison output signal of the third digital comparison stage received by the output feedback stage is 1, generating a first state value 1 to be stored in a multi-bit state register;

and when the comparison output signal of the third digital comparison stage received by the output feedback stage is 0, generating a second state value of 0 to be stored in the multi-bit state register.

As a more specific example, when the comparison output signal of the third digital comparison stage received by the output feedback stage is 1, a first state value 1 is generated and stored in a storage space of a state register, where a certain state is empty;

as another more specific example, when the comparison output signal of the third digital comparison stage received by the output feedback stage is 0, a second state value is generated to store 0 to a storage space where a certain state is empty.

In the present embodiment, the length of the multi-bit status register is limited, and in order to ensure that the whole adaptive adjustment process can be always smooth, in the above embodiment, each storage space of the multi-bit status register is a transient storage space.

The usual meaning of transient is that data disappears after power is turned off;

in this example, to further save space, it is further preferred that the multi-bit status register is a clocked transient memory; the state value stored by the time control transient memory is only valid within a preset time period, and the size of the preset time period is adjustable.

That is, in a further preferred embodiment of the present invention, each storage space does not need to wait until power is off to make data disappear (initialized), but a data storage period may be preset, and the data storage period is automatically initialized after the storage period is exceeded.

In the preferred embodiment, correspondingly, if the multi-bit status register includes N clocked transient memories, N is an integer greater than 1; the preset time period of the ith time-controlled transient memory is not less than the preset time period of the jth time-controlled transient memory, and j is greater than or equal to 1 and less than or equal to N. This setting obviously takes into account the definition of the slew rate itself and the timing of the storage of the state values.

In contrast, in the preferred embodiment,

when the comparison output signal of the third digital comparison stage received by the output feedback stage is 1, generating a first state value and storing the first state value to an m-th time control transient memory; the m satisfies the following condition:

m is more than or equal to 1 and less than N; the state of the mth clocked transient memory is empty and the state of the (m + 1) th clocked transient memory is also empty.

When the comparison output signal of the third digital comparison stage received by the output feedback stage is 0, generating a second state value to be stored in an nth time control transient memory; the n satisfies the following condition:

n >2, the state of the nth clocked transient memory is empty and the state of the (n-1) th clocked transient memory is non-empty.

The determining of the feedback adjustment signal based on the state value already stored by the multi-bit state register specifically includes:

the feedback adjustment signal is generated if a first state value (consecutive 1-1 of the diagram in fig. 2) is present in the multi-bit state register that is stored consecutively, or if a second state value (consecutive 0-0 of the diagram in fig. 2) is present that is stored consecutively.

Reference is next made to fig. 3. The multi-stage amplifying structure can be divided into functional modules of differential amplification, error amplification, digital comparison, output feedback and the like, wherein the output feedback module is connected with the state register module and corresponds to the first differential amplifying stage, the second error amplifying stage and the third digital comparison stage respectively to output the feedback stage and the multi-bit state register.

In fig. 3, as one exemplary structure of a specific feedback regulation, the input terminal of the first differential amplification stage includes a bias circuit;

the first differential amplifier stage receives a feedback adjustment signal generated by the output feedback stage, and adjusts an input of the first differential amplifier stage based on the feedback adjustment signal, and the method specifically includes:

and adjusting the bias current output by the bias circuit of the input end based on the feedback adjusting signal.

That is, in this embodiment, the bias circuit size is changed based on the feedback adjustment signal, thereby adjusting the slew rate.

More specific feedback regulation circuit control structure can be seen in fig. 4.

In fig. 4, not all components of the multi-stage amplifying structure are marked for space, and not every component is labeled and explained, however, the structure diagram and the component symbols of fig. 4 both follow the conventional expressions in the art, and the specific parameters, dimensions, and the like thereof can be determined according to the actual situation in the specific design, and do not affect the specific implementation of the present invention.

With respect to fig. 4, the differential input (Vin +/Vin-), the output (Vout), the bias circuit (Ibias) and the input control circuit (connected to the reference voltage Vdd) of the multi-stage amplification structure are highlighted.

Based on fig. 4, the regulation may be achieved by changing the switching state of the input control circuit after the feedback regulation signal is derived.

Specifically, in fig. 4, the input control circuit includes a plurality of switching devices S1, S2, … … connected in parallel (the dashed line segment in fig. 4 includes that a similar combination structure also exists, that is, the circled portion in fig. 4 can be repeated for a plurality of times), and the on-off state of each switching device Si is mapped with the continuous state value corresponding to the feedback adjustment signal.

The mapping relationship is exemplified as follows:

assuming that there are successive state values 1-1-1 in the 4 th-6 th bit storage space of the 16-bit state register, the respective switches S2, S4, S6 are in the closed (open) state in the input control circuit.

Of course, the specific mapping relationship may be determined experimentally according to the parameter values and adjustment requirements of the actual circuit, and the above examples of the present invention are merely illustrative.

Of course, the input control circuit may be set in other forms as long as there is a mapping relationship between the state of the switching device and the continuous state value corresponding to the feedback adjustment signal, and the magnitude of the bias current of the bias circuit may be adjusted, and similar switching circuit structures may refer to existing prior art circuits.

Referring next to fig. 5-6, different level embodiments of the method of slew rate adjustment of the multi-stage amplifier architecture of fig. 1 are presented, respectively.

A slew rate self-adaptive adjustment method of a multi-stage amplifier comprises a first differential amplification stage, a second error amplification stage, a third digital comparison stage and an output feedback stage

In fig. 5, the main flow of the method includes:

the output feedback stage receives the comparison output signal output by the third digital comparison stage, generates a state value based on the comparison output signal, and stores the state value to a multi-bit state register according to a time sequence;

generating a feedback adjustment signal based on successive states of state values stored by a multi-bit state register;

adjusting an input signal of the first differential amplification stage based on the feedback adjustment signal.

In fig. 6, the state values are stored in a multi-bit state register in time series, and the following determination is made:

and if the continuously stored first state value or the continuously stored second state value appears in the multi-bit state register, generating the feedback adjusting signal.

If the input control circuit described in fig. 4 is used, the following steps are continuously included in fig. 6:

and changing the switching state of the input control circuit through the mapping relation between the continuous state value corresponding to the feedback adjusting signal and the plurality of switching devices of the input notification circuit, so as to adjust the magnitude of the bias current output by the bias circuit at the input end.

The hardware structure of the method corresponds to the foregoing embodiments of fig. 1 to 4, specifically, the comparison output signal is a logic value 0 or a logic value 1;

when the comparison output signal of the third digital comparison stage received by the output feedback stage is 1, generating a first state value and storing the first state value into a multi-bit state register;

and when the comparison output signal of the third digital comparison stage received by the output feedback stage is 0, generating a second state value to be stored in a multi-bit state register.

The same multi-bit state register is a time control transient memory; the state value stored by the time control transient memory is only valid within a preset time period, and the size of the preset time period is adjustable.

When the multi-bit status register comprises N clocked transient memories, N being an integer greater than 1;

the preset time interval of the ith time control transient state memory is not less than the preset time interval of the jth time control transient state memory, and j is more than or equal to 1 and less than or equal to N.

The comparison output signal is a logic value of 0 or a logic value of 1;

when the comparison output signal of the third digital comparison stage received by the output feedback stage is 1, generating a first state value and storing the first state value to an m-th time control transient memory; the m satisfies the following condition:

m is more than or equal to 1 and less than N; the state of the mth clocked transient memory is empty and the state of the (m + 1) th clocked transient memory is also empty.

When the comparison output signal of the third digital comparison stage received by the output feedback stage is 0, generating a second state value to be stored in an nth time control transient memory; the n satisfies the following condition:

n >2, the state of the nth clocked transient memory is empty and the state of the (n-1) th clocked transient memory is non-empty.

The multi-bit status register may be a contiguous memory space of N transient registers, each memory space storing only one status value, and writing cannot continue when a memory space already stores a status value.

In each embodiment of the present invention, the generated state values are sequentially stored to a storage space of which a certain state of the multi-bit state register is empty according to a generation timing sequence, and are searched according to the sequence of the N consecutive storage spaces, where the first state is empty.

According to the invention, the slew rate influence of the output end of the current amplifier is evaluated through the continuity of the state value generated by the logic output of the digital comparator, so that the corresponding regulating and controlling signal is generated to change the bias current of the input end, the on-off state of the switching circuit of the input control circuit is changed, the slew rate is adaptively changed, the response is quick, and the simplicity and the high efficiency are realized through the modular structure.

The present invention is not limited to the specific module structure described in the prior art. The prior art mentioned in the background section can be used as part of the invention to understand the meaning of some technical features or parameters. The scope of the present invention is defined by the claims.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.