阅读说明：本技术 参考电压管理 (Reference voltage management ) 是由 E·博兰里那 F·贝代斯基 于 2020-03-18 设计创作，主要内容包括：本发明描述用于例如在关键操作(例如感测操作)期间维持存储器装置中的稳定电压差的技术。待维持的电压差可为跨存储器单元的读取电压或与参考电压相关联的差,以及其它实例。组件(例如本地电容器)可在所述操作之前与偏置到第一电压(例如全局参考电压)的节点耦合以在电路系统相对安静(例如无噪声)时对所述第一电压与第二电压之间的电压差进行采样。所述组件可在所述操作之前与所述节点解耦,使得可允许所述组件的节点(例如电容器)在所述操作期间浮动。跨所述组件的所述电压差可在所述第二电压的变化期间保持稳定,且可在所述操作期间提供稳定电压差。(Techniques are described for maintaining a stable voltage difference in a memory device, such as during critical operations (e.g., sensing operations). The voltage difference to be maintained can be a read voltage across the memory cell or a difference associated with a reference voltage, among other examples. A component (e.g., a local capacitor) may be coupled with a node biased to a first voltage (e.g., a global reference voltage) prior to the operation to sample a voltage difference between the first voltage and a second voltage when circuitry is relatively quiet (e.g., noise-free). The component may be decoupled from the node prior to the operation such that a node (e.g., a capacitor) of the component may be allowed to float during the operation. The voltage difference across the components may remain stable during variations of the second voltage and may provide a stable voltage difference during the operation.)

1. A method, comprising:

coupling a first capacitor with a first node biased to a first voltage, wherein the first capacitor is coupled with a second node associated with establishing a conductive path between a digit line and a sense component of a memory cell;

storing, using the first capacitor, a voltage difference between the first voltage and a second voltage associated with a plate line of the memory cell;

decoupling the first capacitor from the first node;

accessing the memory cell after decoupling the first capacitor from the first node; and

coupling the first capacitor with the first node after accessing the memory cell.

2. The method of claim 1, further comprising:

sensing a state stored by the memory cell using the sensing component while the first capacitor is decoupled from the first node.

3. The method of claim 1, wherein:

coupling the first capacitor with the first node includes activating a switching component.

4. The method of claim 1, wherein:

decoupling the first capacitor from the first node includes deactivating a switching component.

5. The method of claim 1, wherein:

decoupling the first capacitor from the first node includes increasing a resistance associated with a switching component.

6. The method of claim 1, wherein the first capacitor is coupled with the first node when the sensing component is inactive.

7. The method of claim 1, wherein the second node is located at a gate of a cascode amplifier.

8. The method of claim 1, wherein:

coupling the first capacitor with the first node couples the first capacitor with a second capacitor, wherein the second capacitor is coupled between the first node and a voltage supply that provides the first voltage.

9. The method of claim 1, wherein:

accessing the memory cell includes asserting a word line signal associated with the memory cell.

10. A memory device, comprising:

a memory cell coupled with a digit line;

a switching component configured to couple the digit line and a sensing component;

a first capacitor having a first node coupled with the switching component;

a first voltage supply coupled with a plate line of the memory cell and with a second node of the first capacitor, the first voltage supply configured to supply a first voltage; and

a controller operable to cause the memory device to:

coupling the first capacitor with a third node biased to a second voltage prior to accessing a memory cell;

decoupling the first capacitor from the third node,

accessing the memory cell based at least in part on decoupling the first capacitor from the third node, an

Coupling the first capacitor and the third node after accessing the memory cell.

11. The memory device of claim 10, further comprising:

a second switching component selectively coupling the first capacitor and the third node, wherein the controller is operable to cause the memory device to:

activating the second switching component to couple the first capacitor to the third node.

12. The memory device of claim 11, wherein the controller is further operable to cause the memory device to:

deactivating the second switching component to decouple the first capacitor from the third node.

13. The memory device of claim 11, wherein the controller is further operable to cause the memory device to:

adjusting a resistance of the second switching component to decouple the first capacitor from the third node.

14. The memory device of claim 10, further comprising:

a second capacitor coupled with the second switching component and with a second voltage supply configured to supply the second voltage.

15. The memory device of claim 10, wherein the controller is further operable to cause the memory device to:

activating the sensing component, wherein accessing the memory cell comprises activating the sensing component.

16. The memory device of claim 10, wherein the switching component comprises a cascode amplifier, and wherein the first node is associated with a gate of the cascode amplifier.

17. The memory device of claim 10, wherein the controller is operable to cause the memory device to:

sensing a state stored by the memory cell using the sensing component while the first capacitor is decoupled from the third node.

18. A method, comprising:

coupling the first and second capacitors with a first node biased to a first voltage;

decoupling the first capacitor and the first node at a first time to store a first difference between the first voltage and a second voltage associated with a plate line of a memory cell;

decoupling the second capacitor from the first node at a second time after the first time to store a second difference between the first voltage and the second voltage;

coupling a second node of the first capacitor and the second capacitor associated with establishing a conductive path between a digit line and a sense component of the memory cell at a third time after the second time; and

the memory cell is accessed when the first and second capacitors are coupled with the second node.

19. The method of claim 18, wherein coupling the first and second capacitors with the second node comprises:

a third capacitor coupling the first capacitor and the second capacitor with the second node.

20. The method of claim 18, wherein the first and second capacitors are coupled with a second voltage supply configured to supply the second voltage.

21. A memory device, comprising:

a memory cell coupled with a digit line;

a cascode amplifier for coupling the digit line and a sensing component;

a first capacitor and a second capacitor;

a first voltage supply coupled with a plate line of the memory cell and with a first node of the first capacitor and a first node of the second capacitor and configured to supply a first voltage; and

a controller operable to cause the memory device to:

coupling the first capacitor and the second capacitor with a second node biased to a second voltage;

decoupling the first capacitor from the second node at a first time to store the first voltage and the second voltage

A first difference between the second voltages is provided,

decoupling the second capacitor from the second node at a second time after the first time to store a second difference between the first voltage and the second voltage, an

Coupling the first and second capacitors with a gate of the cascode amplifier at a third time after the second time to provide an average of the first and second differences to the gate of the cascode amplifier.

22. The memory device of claim 21, wherein the controller is further operable to cause the device to:

accessing the memory cell when the first and second capacitors are coupled with the gate of the cascode amplifier.

23. The memory device of claim 21, further comprising:

a first switching component for coupling the first capacitor with the second node; and

a second switching component for coupling the second capacitor with the second node.

24. The memory device of claim 21, where the controller is further operable to cause the memory device to:

a third capacitor coupling the first and second capacitors and the cascode amplifier at the third time, wherein coupling the first and second capacitors and the gate of the cascode amplifier comprises coupling the first and second capacitors and the third capacitor.

25. The memory device of claim 21, wherein the first capacitor has a smaller capacitance than the second capacitor such that the second difference is weighted more than the first difference.

Background

The following generally relates to systems that may include at least one memory device, and more specifically, to apparatus and techniques for reference voltage management in a memory device.

Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, typically represented by a logic 1 or a logic 0. In other devices, more than two states may be stored. To access the stored information, components of the device may read or sense at least one storage state in the memory device. To store information, components of a device may write or program states in a memory device.

There are various types of memory devices, including magnetic hard disks, Random Access Memory (RAM), Read Only Memory (ROM), dynamic RAM (dram), synchronous dynamic RAM (sdram), ferroelectric RAM (feram), magnetic RAM (mram), resistive RAM (rram), flash memory, Phase Change Memory (PCM), and others. The memory devices may be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for long periods of time, even in the absence of an external power source. Volatile memory devices, such as DRAMs, lose their memory state when disconnected from an external power source. Ferams are capable of achieving densities similar to volatile memories, but may be non-volatile due to the use of ferroelectric capacitors as storage devices.

Drawings

FIG. 1 illustrates an example of a system that supports reference voltage management in a memory device in accordance with examples disclosed herein.

FIG. 2 illustrates an example of a memory array supporting reference voltage management in a memory device according to examples disclosed herein.

FIG. 3 illustrates an example of a hysteresis curve supporting reference voltage management in a memory device according to examples disclosed herein.

FIG. 4 illustrates an example of a memory device supporting reference voltage management in accordance with examples disclosed herein.

FIG. 5 illustrates a timing diagram of memory cell voltages in a system supporting reference voltage management according to an example disclosed herein.

FIG. 6 illustrates an example of a circuit supporting reference voltage management in accordance with examples disclosed herein.

FIG. 7 illustrates an example of a memory device supporting reference voltage management in accordance with examples disclosed herein.

FIG. 8 illustrates an example of a circuit supporting reference voltage management in accordance with examples disclosed herein.

Fig. 9 illustrates an example of a timing diagram supporting reference voltage management in accordance with examples disclosed herein.

FIG. 10 illustrates a block diagram of a memory controller supporting reference voltage management in accordance with examples disclosed herein.

FIG. 11 illustrates a method of supporting reference voltage management in accordance with examples disclosed herein.

Fig. 12 illustrates a method of supporting reference voltage management in accordance with examples disclosed herein.

Detailed Description

The performance of sensing components (e.g., sense amplifiers) in a memory device may be affected by Power Delivery Network (PDN) capabilities (e.g., noise suppression capabilities). For example, depending on the read path and sensing architecture, the accuracy of the sensing operation may be affected by noise associated with voltages used to bias the memory cell (e.g., read voltage) or used to determine a state stored on the memory cell (e.g., reference voltage). Techniques for improving reference voltage management are desired.

A memory device may include a memory cell and a sensing component. The sense component can be coupled with a digit line associated with the memory cell and can be used to sense a state stored by the memory cell during a read operation. Some types of memory cells, such as ferroelectric memory cells, may include a cell capacitor for storing a state of the memory cell. During an operation, such as a read operation, the memory cell may be biased by applying a voltage to one or both plates of the cell capacitor, which may cause the cell capacitor to share charge with the digit line during the read operation. For example, the resulting amount of charge (or corresponding voltage or current) on the digit line can be used by the sensing component to determine the state stored by the memory cell, such as by comparing the voltage of the digit line to a reference voltage, which can be defined in terms of the voltage difference between the voltage of the reference line and a ground voltage.

In some cases, the voltage across the memory cell (e.g., the read voltage), such as the difference between the voltages applied to the top and bottom plates of the cell capacitor, or the voltage difference associated with the reference voltage may be affected by noise within the PDN. For example, during a read operation, the voltage applied to one plate of a capacitor in a memory cell may change due to parasitic capacitance or electrical coupling within the PDN. In this case, the voltage across the cell capacitor may also vary; for example, the read voltage may be unstable, which may affect the amount of charge shared by the memory cell and the digit line during a read operation.

In some cases, if the read voltage is not sufficiently well controlled (e.g., stabilized) during portions (e.g., critical portions) of the read operation (e.g., when the sense component is activated and senses the voltage or current on the digit line), the sense component may not be able to accurately determine the state stored by the memory cell. Similarly, if the voltage difference between the reference voltage and another voltage (e.g., ground) is not sufficiently well controlled (e.g., stabilized) during the sensing operation, the accuracy of the sensing operation may be adversely affected. Accordingly, it is desirable to identify techniques for managing (e.g., controlling) such voltage differences during read operations.

In some cases, the digit lines of the memory cells may be coupled with the sensing elements via cascode amplifiers (or other types of switching components). For example, the cascode may establish a conductive path between the digit line and the sense component. In this case, the read voltage of the memory cell (e.g., the voltage across the cell capacitor) may be affected by the voltage at the gate of the cascode.

In some cases, the gate voltage may be provided by one or more components (e.g., a peripheral regulator) and may be stabilized (e.g., maintained) using other components (e.g., global capacitors in various locations on the chip). Therefore, the gate voltage can be relatively stable. However, the plate line voltage (e.g., a voltage applied to another plate of the cell capacitor) may be provided by a plate line driver and may be affected by current injected into the circuitry from other components in the memory device. For example, when the sense component is activated during a read operation, it can inject current into the plate line and change the voltage of the plate line, thereby changing the read voltage across the memory cell because the gate voltage is not similarly affected. The variation in the read voltage across the memory cell caused by current injection from the active sense component can be particularly problematic because it occurs at a critical time in a read operation when the sense component is attempting to determine the state of the memory cell. Similarly, the reference voltage may be affected by the current injected into the circuit during a read operation.

Thus, in some cases, a memory device may include components such as local capacitors to help maintain a stable read voltage during a read operation. For example, one node of the local capacitor may be coupled with the plate line voltage and a second node of the local capacitor may be coupled with the cascode gate. The second node of the local capacitor may also be coupled with a node biased to the gate voltage prior to activating the sensing component during a read operation, and thereby the voltage difference between the plate line voltage and the gate voltage may be sampled and stored when the sensing component is idle and the circuitry is relatively quiet (e.g., noise free).

During a critical portion of a read operation (e.g., when the sense component is activated to sense the state of the memory cell), the local capacitor may be decoupled from the gate voltage and may be allowed to float. In this case, a change in the plate line voltage (e.g., due to activation of the sensing component) may correspondingly change the voltage at the transistor gate through the local capacitor, thereby causing the voltage at the gate of the cascode to track the plate line voltage and maintain a stable read voltage across the memory cell when the sensing component is activated. Similar techniques may be used to maintain stability of the reference voltage during one or more operations (e.g., critical operations).

In some cases, multiple local capacitors may be used to sample the difference between the board voltage and the gate voltage at different times before the sensing component is activated. The set of local capacitors may be used to provide one or more time measurements (e.g., an average or moving average) of the voltage difference to the transistor gates, as described in more detail herein.

In some cases, the techniques described herein may reduce or eliminate the need for local repeaters to maintain a stable voltage difference during critical operations, and may help compensate for higher voltage drops across a PDN. Although these techniques are discussed primarily in the context of maintaining a stable read voltage or reference voltage, similar approaches may be used to stabilize various other performance characteristics in a memory device, including but not limited to voltage differences.

Features of the present disclosure are first described in the context of memory systems and memory arrays. The features of the present disclosure are described in the context of a hysteresis curve that supports reference voltage management. These and other features of the present disclosure are further illustrated by and described with reference to memory devices, circuits, timing diagrams, and flow diagrams related to reference voltage management.

Fig. 1 illustrates an example of a system 100 utilizing one or more memory devices in accordance with examples disclosed herein. System 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling external memory controller 105 and memory device 110. System 100 may include one or more memory devices, but for ease of description, one or more memory devices may be described as a single memory device 110.

The system 100 may include features of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. The system 100 may be an example of a portable electronic device. The system 100 may be an example of a computer, laptop, tablet, smartphone, cell phone, wearable device, internet connected device, or the like. Memory device 110 may be a component of a system that is configured to store data for one or more other components of system 100. In some examples, system 100 is configured for two-way wireless communication with other systems or devices using a base station or access point. In some examples, system 100 enables Machine Type Communication (MTC), inter-machine (M2M) communication, or inter-device (D2D) communication.

At least part of the system 100 may be an instance of a host device. Such a host device may be an example of a device that uses memory to perform a process, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cell phone, a wearable device, an internet-connected device, some other fixed or portable electronic device, or the like. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof, that implements the functionality of external memory controller 105. In some cases, external memory controller 105 may be referred to as a host or a host device.

In some cases, memory device 110 may be a stand-alone device or component configured to communicate with other components of system 100 and provide physical memory addresses/space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to work with at least one or more different types of systems 100. Signaling between components of the system 100 and the memory device 110 may be operable to support modulation schemes for modulating signals, different pin designs for communicating signals, dissimilar packaging of the system 100 and the memory device 110, clock signaling and synchronization between the system 100 and the memory device 110, timing conventions, and/or other factors.

The memory device 110 may be configured to store data for components of the system 100. In some cases, memory device 110 may act as a slave to system 100 (e.g., to respond to and execute commands provided by system 100 through external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. Memory device 110 may include two or more memory dies 160 (e.g., memory chips) to support a desired or specified data storage capacity. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

The system 100 may further include a processor 120, a basic input/output system (BIOS) component 125, one or more peripheral components 130, and an input/output (I/O) controller 135. The components of system 100 may be in electronic communication with each other using a bus 140.

The processor 120 may be configured to control at least a portion of the system 100. The processor 120 may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In such cases, processor 120 may be an example of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a General Purpose Graphics Processing Unit (GPGPU), or a system on a chip (SoC), among other examples.

The BIOS component 125 may be a software component that may include a BIOS operating as firmware, which may initialize and run various hardware components of the system 100. The BIOS component 125 may also manage data flow between the processor 120 and various components of the system 100, such as peripheral components 130, I/O controllers 135, and the like. The BIOS component 125 may include programs or software stored in Read Only Memory (ROM), flash memory, or any other non-volatile memory.

Peripheral component 130 may be any input or output device or interface for such a device that may be integrated into system 100 or integrated with system 100. Examples may include disk controllers, sound controllers, graphics controllers, ethernet controllers, modems, Universal Serial Bus (USB) controllers, serial or parallel ports, or peripheral card slots, such as Peripheral Component Interconnect (PCI) or dedicated graphics ports. The peripheral components 130 may be other components understood by those of skill in the art as peripheral devices.

The I/O controller 135 may manage data communications between the processor 120 and peripheral components 130, input devices 145, or output devices 150. I/O controller 135 may manage peripheral devices that are not integrated into system 100 or integrated with system 100. In some cases, I/O controller 135 may represent a physical connection or port to an external peripheral component.

Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or components thereof. This may include a user interface or interfacing with or between other devices. In some cases, input 145 may be a peripheral that interfaces with system 100 via one or more peripheral components 130, or may be managed by I/O controller 135.

The output 150 may represent a device or signal external to the system 100 that is configured to receive an output from the system 100 or any of its components. Examples of output 150 may include a display, an audio speaker, a printing device, or another processor on a printed circuit board, and so forth. In some cases, output 150 may be a peripheral that interfaces with system 100 via one or more peripheral components 130, or may be managed by I/O controller 135.

The components of system 100 may be comprised of general purpose or special purpose circuitry designed to perform their functions. This may include various circuit elements configured to implement the functions described herein, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements.

Memory device 110 can include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and/or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and/or memory array 170-N). The memory array 170 may be a collection (e.g., a grid) of memory cells, where each memory cell is configured to store at least one bit of digital data. Features of the memory array 170 and/or memory cells are described in more detail with reference to FIG. 2.

Memory device 110 may be an example of a two-dimensional (2D) array of memory cells, or may be an example of a three-dimensional (3D) array of memory cells. For example, a 2D memory device may include a single memory die 160. The 3D memory device can include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and/or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other or next to each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a level, a hierarchy, a tier, or a die. The 3D memory device can include any number of stacked memory dies 160-N (e.g., more than 2, more than 3, more than 4, more than 5, more than 6, more than 7, more than 8). This may increase the number of memory cells that may be positioned on the substrate compared to a single 2D memory device, which in turn may reduce production costs or improve performance of the memory array, or both. In some 3D memory devices, different levels may share at least one common access line, such that some levels may share at least one of a word line, a digit line, and/or a plate line.

Device memory controller 155 may include circuitry or components configured to control the operation of memory device 110. As such, device memory controller 155 may include hardware, firmware, and software that enable memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information related to memory device 110. Device memory controller 155 may be configured to communicate with external memory controller 105, one or more memory dies 160, or processor 120. In some cases, memory device 110 may receive data and/or commands from external memory controller 105.

For example, memory device 110 may receive a write command indicating that memory device 110 is to store certain data on behalf of a component of system 100 (e.g., processor 120), or receive a read command indicating that memory device 110 is to provide certain data stored in memory die 160 to a component of system 100 (e.g., processor 120). In some cases, device memory controller 155 may control the operations of memory device 110 described herein in conjunction with local memory controller 165 of memory die 160. Examples of components included in device memory controller 155 and/or local memory controller 165 may include a receiver for demodulating signals received from external memory controller 105, a decoder, logic, decoder, amplifier, filter, or the like for modulating and transmitting signals to external memory controller 105.

A local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. Further, local memory controller 165 may be configured to communicate (e.g., receive and transmit data and/or commands) with device memory controller 155. Local memory controller 165 may support device memory controller 155 in controlling the operation of memory device 110 as described herein. In some cases, memory device 110 does not include device memory controller 155, and local memory controller 165 or external memory controller 105 may perform the various functions described herein. Thus, local memory controller 165 may be configured to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 105 or processor 120.

In the disclosed technology, local memory controller 165 (e.g., local to memory die 160) can cause memory device 100 to perform operations specific to maintaining a stable read voltage during a read operation of a memory cell. Specifically, local memory controller 165 may cause memory device 100 to couple a local capacitor with a first node biased to a first voltage. The first capacitor may also be coupled with a second node associated with establishing a conductive path between a digit line (e.g., digit line 215) and a sensing component (e.g., sensing component 250) of the memory cell. The memory device 100 may store a voltage difference between a first voltage and a second voltage associated with a plate line of a memory cell using a local capacitor. The memory device 100 may decouple the local capacitor from the first node and access the memory cell after decoupling the local capacitor from the first node. The local capacitor helps stabilize the read voltage during an access operation. The memory device 100 may re-couple the first capacitor and the first node after accessing the memory cell.

External memory controller 105 may be configured to be able to transfer information, data, and/or commands between components of system 100, such as processor 120, and memory device 110. The external memory controller 105 may act as a contact between the components of the system 100 and the memory device 110 such that the components of the system 100 need not be aware of the details of the operation of the memory device. Components of system 100 may make requests (e.g., read commands or write commands) to external memory controller 105 that external memory controller 105 satisfies. The external memory controller 105 may translate or translate communications exchanged between components of the system 100 and the memory device 110. In some cases, external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

In some cases, external memory controller 105 or other components of system 100 or functions thereof described herein may be implemented by processor 120. For example, external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by processor 120 or other components of system 100. Although external memory controller 105 is depicted as being external to memory device 110, in some cases, external memory controller 105 or its functions described herein may be implemented by memory device 110. For example, external memory controller 105 may be hardware, firmware, or software implemented by device memory controller 155 or one or more local memory controllers 165, or some combination thereof. In some cases, external memory controller 105 may be distributed across processor 120 and memory device 110 such that portions of external memory controller 105 are implemented by processor 120 and other portions are implemented by device memory controller 155 or local memory controller 165. Likewise, in some cases, one or more functions attributed herein to device memory controller 155 or local memory controller 165 may in some cases be performed by external memory controller 105 (separate from processor 120 or included in processor 120).

Components of system 100 may exchange information with memory device 110 using multiple channels 115. In some examples, channel 115 may enable communication between external memory controller 105 and memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, the channel 115 may include a first terminal that includes one or more pins or pads at the external memory controller 105 and one or more pins or pads at the memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be configured to serve as part of a channel. In some cases, the pins or pads of the terminals may be part of the signal path of the channel 115. The additional signal paths may be coupled with terminals of channels used to route signals within components of system 100. For example, memory device 110 may include signal paths (e.g., signal paths internal to memory device 110 or components thereof, such as within memory die 160) that route signals from terminals of channels 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

The channels 115 (and associated signal paths and terminals) may be dedicated to conveying particular types of information. In some cases, channel 115 may be an aggregated channel and thus may include multiple individual channels. For example, the data channel 190 may be x4 (e.g., including 4 signal paths), x8 (e.g., including 8 signal paths), x16 (including 16 signal paths), and so on.

Signals transmitted over the channel may use a Double Data Rate (DDR) timing scheme. For example, some symbols of a signal may register on a rising edge of a clock signal and other symbols of the signal may register on a falling edge of the clock signal. Signals transmitted over a channel may use Single Data Rate (SDR) signaling. For example, one symbol of a signal may be registered per clock cycle.

In some cases, the channels 115 may include one or more Command and Address (CA) channels 186. The CA channel 186 may be configured to transfer commands between the external memory controller 105 and the memory devices 110, including control information (e.g., address information) associated with the commands. For example, the CA channel 186 may include a read command with an address of the desired data. In some cases, CA channel 186 may register on rising clock signal edges and/or falling clock signal edges. In some cases, CA channel 186 may include any number of signal paths to decode address and command data (e.g., 8 or 9 signal paths).

In some cases, the channel 115 may include one or more clock signal (CK) channels 188. The CK channel 188 may be configured to transfer one or more common clock signals between the external memory controller 105 and the memory device 110. Each clock signal may be configured to oscillate between a high state and a low state and coordinate the actions of external memory controller 105 and memory device 110. In some cases, the clock signals may be differential outputs (e.g., CK _ t and CK _ c signals), and the signal path of CK channel 188 may be configured accordingly. In some cases, the clock signal may be single ended. The CK channel 188 may include any number of signal paths. In some cases, the clock signal CK (e.g., the CK _ t signal and the CK _ c signal) may provide a timing reference for command and addressing operations for the memory device 110 or for other system-wide operations of the memory device 110. The clock signal CK may thus be variously referred to as a control clock signal CK, a command clock signal CK, or a system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors, or the like).

In some cases, channel 115 may include one or more Data (DQ) channels 190. Data channel 190 may be configured to transfer data and/or control information between external memory controller 105 and memory device 110. For example, the data channel 190 may transfer information written to the memory device 110 (e.g., bi-directional) or read from the memory device 110. The data channel 190 may carry signals that may be modulated using various different modulation schemes (e.g., NRZ, PAM 4).

In some cases, the channel 115 may include one or more other channels 192 that may be dedicated for other purposes. These other channels 192 may include any number of signal paths.

The channel 115 may couple the external memory controller 105 and the memory device 110 using a variety of different architectures. Examples of various architectures may include a bus, a point-to-point connection, a crossbar switch, a high-density interposer (e.g., a silicon interposer), or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may at least partially include a high density interposer, such as a silicon interposer or a glass interposer.

The signals transmitted over channel 115 may be modulated using a variety of different modulation schemes. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate signals communicated between external memory controller 105 and memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to 2. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logical 1 or a logical 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), unipolar coding, bipolar coding, manchester coding, Pulse Amplitude Modulation (PAM) with two symbols (e.g., PAM2), and/or others.

In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals communicated between external memory controller 105 and memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to 3. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., a symbol may represent logic 00, logic 01, logic 10, or logic 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM4, PAM8, and the like, Quadrature Amplitude Modulation (QAM), Quadrature Phase Shift Keying (QPSK), and/or others. The multi-symbol signal or PAM4 signal may be a signal modulated using a modulation scheme that may include at least three levels to encode more than one information bit. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher order modulation schemes and symbols.

FIG. 2 illustrates an example of a memory die 200 according to examples disclosed herein. The memory die 200 may be an example of the memory die 160 described with reference to FIG. 1. In some cases, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die 200 may include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 is programmable to store two or more states. For example, memory cell 205 may be configured to store one digital logic bit (e.g., logic 0 and logic 1) at a time. In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one digital logic bit (e.g., logic 00, logic 01, logic 10, or logic 11) at a time.

Memory cell 205 may store a state (e.g., a polarization state or a dielectric charge) that represents digital data. In a FeRAM architecture, memory cell 205 may include a capacitor, which may include a ferroelectric material to store a charge and/or polarization representing a programmable state. In a DRAM architecture, memory cells 205 may include capacitors, which may include a dielectric material to store charge representing programmable states.

Operations such as reads and writes may be performed on memory cells 205 by activating or selecting access lines such as word lines 210, digit lines 215, and/or plate lines 220. In some cases, digit lines 215 may also be referred to as bit lines. References to access lines, word lines, digit lines, plate lines, or the like may be interchanged without loss of understanding or operation. Activating or selecting a word line 210, digit line 215, or plate line 220 may include applying a voltage to the respective line.

The memory die 200 can include access lines (e.g., word lines 210, digit lines 215, and plate lines 220) arranged in a grid-like pattern. Memory cells 205 may be located at the intersections of word lines 210, digit lines 215, and/or plate lines 220. By biasing the word line 210, the digit line 215, and the plate line 220 (e.g., applying voltages to the word line 210, the digit line 215, and the plate line 220), a single memory cell 205 may be accessed at its intersection.

Access to memory cells 205 may be controlled by a row decoder 225, a column decoder 230, and a plate driver 235. For example, the row decoder 225 may receive a row address from the local memory controller 265 and activate the word line 210 based on the received row address. Column decoder 230 receives a column address from local memory controller 265 and activates digit lines 215 based on the received column address. The board driver 235 may receive a board address from the local memory controller 265 and activate the board line 220 based on the received board address. For example, memory die 200 may include a plurality of word lines 210 labeled WL _1 to WL _ M, a plurality of digit lines 215 labeled DL _1 to DL _ N, and a plurality of plate lines labeled PL _1 to PL _ P, where M, N and P depend on the size of the memory array. Thus, by activating word line 210, digit line 215, and plate line 220 (e.g., WL _1, DL _3, and PL _1), memory cell 205 at its intersection can be accessed. The intersection of a word line 210 and a digit line 215 in a two-dimensional or three-dimensional configuration may be referred to as an address of a memory cell 205. In some cases, the intersection of word line 210, digit line 215, and plate line 220 may be referred to as an address of memory cell 205.

Memory cell 205 may include logic storage components, such as capacitor 240 and switching component 245. The capacitor 240 may be an example of a ferroelectric capacitor. A first node of the capacitor 240 may be coupled with the switching component 245 and a second node of the capacitor 240 may be coupled with the plate line 220. The switching component 245 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between the two components.

Selecting or deselecting memory cell 205 may be accomplished by activating or deactivating switching component 245. The capacitor 240 may be in electronic communication with the digit line 215 using a switching component 245. For example, capacitor 240 may be isolated from digit line 215 when switching component 245 is deactivated, and capacitor 240 may be coupled with digit line 215 when switching component 245 is activated. In some cases, switching component 245 is a transistor and its operation is controlled by applying a voltage to the transistor gate, where the voltage difference between the transistor gate and the transistor source is greater than or less than the threshold voltage of the transistor. In some cases, switching component 245 may be a p-type transistor or an n-type transistor. The word line 210 may be in electronic communication with the gate of the switching component 245, and the switching component 245 may be activated/deactivated based on a voltage applied to the word line 210.

The word line 210 may be a conductive line in electronic communication with the memory cell 205 that may be used to perform an access operation on the memory cell 205. In some architectures, the word line 210 may be in electronic communication with the gate of the switching component 245 of the memory cell 205 and may be configured to control the switching component 245 of the memory cell. In some architectures, the word line 210 may be in electronic communication with a node of a capacitor of the memory cell 205, and the memory cell 205 may not include a switching component.

The digit line 215 can be a conductive line connecting the memory cell 205 and the sense component 250. In some architectures, memory cells 205 may be selectively coupled with digit lines 215 during portions of an access operation. For example, the word line 210 and the switching component 245 of the memory cell 205 may be configured to selectively couple and/or isolate the capacitor 240 of the memory cell 205 and the digit line 215. In some architectures, memory unit 205 may be in electronic communication (e.g., persistent) with digit line 215.

The plate line 220 may be a conductive line in electronic communication with the memory cells 205 that may be used to perform access operations on the memory cells 205. Plate line 220 may be in electronic communication with a node of capacitor 240 (e.g., the bottom of the cell). The plate line 220 may be configured to cooperate with the digit line 215 to bias the capacitor 240 during an access operation of the memory cell 205. In some cases, it may be beneficial to manage or control the voltages of plate line 220 and digit line 215 (or other voltages that may affect the voltage of digit line 215) to provide a stable read voltage across capacitor 240 during a read operation.

The sensing component 250 may be configured to detect a state (e.g., a polarization state or charge) stored on the capacitor 240 of the memory cell 205 and determine a logic state of the memory cell 205 based on the detected state. In some cases, the charge stored by memory cell 205 may be very small. Thus, the sensing component 250 may include one or more sense amplifiers to amplify the signal output of the memory cell 205. In some cases, sense component 250 may include or be coupled with a cascode amplifier that couples digit line 215 with the sense amplifier. The sense amplifier may detect small changes in the charge of the digit line 215 during a read operation and may generate a signal corresponding to a logic 0 or a logic 1 based on the detected charge. During a read operation, the capacitor 240 of the memory cell 205 may output a signal (e.g., discharge) to its corresponding digit line 215. The signal may cause the voltage of the digit line 215 to change.

Sensing component 250 can be configured to compare a signal received from memory cell 205 across digit line 215 to a reference signal 255 (e.g., a reference voltage). The sensing component 250 may determine the storage state of the memory cell 205 based on the comparison.

For example, in binary signaling, if digit line 215 has a voltage higher than reference signal 255, sensing component 250 may determine that the storage state of memory cell 205 is a logic 1, and if digit line 215 has a voltage lower than reference signal 255, sensing component 250 may determine that the storage state of memory cell 205 is a logic 0. The sensing component 250 may include various transistors or amplifiers to detect and amplify the signal difference. The detected logic state of memory cell 205 may be output as output 260 through column decoder 230. In some cases, sensing component 250 may be part of another component (e.g., column decoder 230, row decoder 225). In some cases, sensing component 250 can be in electronic communication with row decoder 225, column decoder 230, and/or plate driver 235.

Local memory controller 265 may control the operation of memory cells 205 through various components, such as row decoder 225, column decoder 230, plate driver 235, and sense component 250. Local memory controller 265 may be an example of local memory controller 165 described with reference to FIG. 1. In some cases, one or more of row decoder 225, column decoder 230, and plate driver 235 and sensing component 250 may be co-located with local memory controller 265. Local memory controller 265 may be configured to receive one or more commands and/or data from external memory controller 105 (or device memory controller 155 described with reference to FIG. 1), translate the commands and/or data into information usable by memory die 200, perform one or more operations on memory die 200, and transfer data from memory die 200 to external memory controller 105 (or device memory controller 155) in response to performing the one or more operations.

The local memory controller 265 may generate row, column and/or plate line address signals to activate the target word line 210, the target digit line 215 and the target plate line 220. The local memory controller 265 can also generate and control various voltages or currents used during operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein can be adjusted or varied or can be different for the various operations discussed in operating the memory die 200.

In some cases, the local memory controller 265 can be configured to perform a precharge operation on the memory die 200. The precharge operation may include precharging one or more components and/or access lines of the memory die 200 to one or more predetermined voltage levels. In some examples, memory cells 205 and/or portions of memory die 200 may be precharged between different access operations. In some examples, the digit lines 215 and/or other components may be precharged prior to a read operation.

In some cases, the local memory controller 265 can be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. Local memory controller 265 may identify the target memory unit 205 for which a write operation is performed. The local memory controller 265 may identify a target word line 210, a target digit line 215, and/or a target plate line 220 in electronic communication with a target memory cell 205, such as an address of the target memory cell 205.

The local memory controller 265 may activate the target word line 210, the target digit line 215, and/or the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. During a write operation, local memory controller 265 may apply a particular signal (e.g., a voltage) to digit line 215 and a particular signal (e.g., a voltage) to plate line 220 to store a particular state in capacitor 240 of memory cell 205, the particular state indicating a desired logic state.

In some cases, the local memory controller 265 can be configured to perform read operations (e.g., sense operations) on one or more memory cells 205 of the memory die 200. During a read operation, the logic state stored in memory cells 205 of memory die 200 can be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. Local memory controller 265 may identify the target memory cell 205 on which to perform a read operation. The local memory controller 265 may identify a target word line 210, a target digit line 215, and/or a target plate line 220 in electronic communication with a target memory cell 205, such as an address of the target memory cell 205.

The local memory controller 265 may activate the target word line 210, the target digit line 215, and/or the target plate line 220 (e.g., apply a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. The target memory cell 205 may transfer a signal to the sense component 250 in response to biasing the access line. The sensing component 250 may amplify the signal. Local memory controller 265 may trigger sense component 250 (e.g., a latching sense component) and thereby compare a signal received from memory cell 205 to reference signal 255. Based on the comparison, the sensing component 250 can determine the logic state stored on the memory cell 205. As part of a read operation, local memory controller 265 may transfer the logic states stored on memory cells 205 to external memory controller 105 (or a device memory controller).

In some cases, memory cell 205 can be coupled with digit line 215, a switching component for coupling digit line 215 and sensing component 250, and a first capacitor having a first node coupled with the switching component. A first capacitor having a first node may be biased to a first voltage. A first voltage supply supplying a first voltage may be coupled with a plate line of the memory cell 205 and a second node of the first capacitor. The memory die 200 can also include a controller that causes the memory die 200 to couple a first node of the first capacitor and a third node biased to a second voltage to store a voltage difference between the second voltage and the first voltage using the first capacitor. The controller may decouple the first capacitor and the third node and access the memory cell 205 after decoupling the first capacitor and the third node. Accessing memory cell 205 may include performing a critical operation (e.g., a read operation). After accessing the memory cell 205, the first capacitor may be recoupled with the third node after accessing the memory cell 205.

In some memory architectures, accessing memory cell 205 may reduce or destroy the logic state stored in memory cell 205. For example, a read operation performed on a ferroelectric memory cell may destroy the logic state stored in the ferroelectric capacitor. In another example, a read operation performed in a DRAM architecture may partially or completely discharge the capacitor of a target memory cell. Local memory controller 265 may perform a rewrite operation or a refresh operation to return the memory cells to their original logic states. Local memory controller 265 may rewrite the logic state to the target memory cell after a read operation. In some cases, the rewrite operation may be considered part of a read operation. In addition, activating a single access line, such as word line 210, may disturb the state stored in some memory cells in electronic communication with the access line. Thus, a rewrite operation or a refresh operation may be performed on one or more memory cells that may not be accessed.

Figure 3 illustrates an example of nonlinear electrical properties of ferroelectric memory cells having hysteresis curves 300-a and 300-b, according to various examples of the present disclosure. Hysteresis curves 300-a and 300-b illustrate example ferroelectric memory cell write and read processes, respectively. The hysteresis curves 300-a and 300-b depict the charge Q stored on a ferroelectric capacitor, such as the capacitor 240 described with reference to fig. 2, as a function of the voltage difference V.

Ferroelectric materials are characterized by spontaneous polarization, i.e., they maintain a non-zero electrical polarization in the absence of an electric field. Example ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconium titanate (PZT), and Strontium Bismuth Tantalate (SBT). The ferroelectric capacitors described herein may include these or other ferroelectric materials. Electrical polarization within the ferroelectric capacitor results in a net charge at the surface of the ferroelectric material and an opposite charge is attracted through the capacitor terminals. Thus, charge is stored at the interface of the ferroelectric material and the capacitor terminals. Since electrical polarization can be maintained for relatively long periods of time (even indefinitely) in the absence of an externally applied electric field, charge leakage can be significantly reduced over, for example, capacitors used in DRAM arrays. This may reduce the need to perform refresh operations.

The hysteresis curves 300-a and 300-b can be understood from a single terminal perspective of the capacitor. By way of example, if the ferroelectric material has a negative polarization, positive charges accumulate at the terminals. Likewise, if the ferroelectric material has a positive polarization, negative charges accumulate at the terminals. In addition, the voltages in the hysteresis curves 300-a and 300-b represent the voltage difference across the capacitors and are directional. For example, a positive voltage may be achieved by applying a positive voltage to the relevant terminal (e.g., cell plate) and maintaining the second terminal (e.g., cell bottom) at ground (or substantially zero volts (0V)). A negative voltage may be applied by maintaining the associated terminal at ground and applying a positive voltage to the second terminal, e.g., a positive voltage may be applied to negatively polarize the associated terminal. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages may be applied to the appropriate capacitor terminals to generate the voltage differences shown in the hysteresis curves 300-a and 300-b.

As depicted in the hysteresis curve 300-a, the ferroelectric material can maintain positive or negative polarization with zero voltage difference, resulting in two possible charge states: charge state 305 and charge state 310. According to the example of fig. 3, charge state 305 represents a logic 0 and charge state 310 represents a logic 1. In some examples, the logic values of the respective charge states may be inverted to accommodate other schemes for operating the memory cells.

By applying a voltage, a logic 0 or 1 can be written to the memory cell by controlling the electrical polarization of the ferroelectric material and thus the charge on the capacitor terminals. For example, applying a net positive voltage 315 across the capacitor results in charge accumulation until the charge state 305-a is reached. After removing voltage 315, charge state 305-a follows path 320 until it reaches charge state 305 at zero voltage. Similarly, the charge state 310 is written by applying a net negative voltage 325, which results in charge state 310-a. After the negative voltage 325 is removed, the charge state 310-a follows path 330 until it reaches the charge state 310 at zero voltage. The charge states 305-a and 310-a may also be referred to as remnant polarization (Pr) values, such as the polarization (or charge) that remains after the external bias (e.g., voltage) is removed. Coercive voltage is a voltage where the charge (or polarization) is zero.

To read or sense the memory state of the ferroelectric capacitor, a voltage may be applied across the capacitor. In response, the stored charge Q changes, and the degree of change depends on the initial charge state, e.g., whether the final stored charge (Q) depends on the initial stored charge state 305-b or 310-b. For example, the hysteresis curve 300-b illustrates two possible stored charge states 305-b and 310-b. A voltage 335 may be applied across the capacitor 240 as discussed with reference to fig. 2. In other cases, a fixed voltage may be applied to the cell plate, and although depicted as a positive voltage, voltage 335 may be negative. In response to voltage 335, charge state 305-b may follow path 340. Likewise, if charge state 310-b is initially stored, it follows path 345. The final positions of the charge states 305-c and 310-c depend on one or more factors, including the particular sensing scheme and circuitry.

The voltage applied across the capacitor of the memory cell during a read operation may be referred to as a read voltage, and the accuracy of the read operation may depend in part on the stability of the read voltage, e.g., on the stability of the voltages applied to the cell plate (e.g., via the plate line) and the cell bottom (e.g., via the digit line) of the capacitor. In some cases, a stable read voltage across the cell capacitor may be maintained during a read operation using a (separate) local capacitor, as described herein.

In some cases, the final charge may depend on the intrinsic capacitance of the digit line connected to the memory cell. For example, if a capacitor is electrically connected to the digit line and a voltage 335 is applied, the voltage of the digit line may rise due to its intrinsic capacitance. The voltage measured at the sensing component may not equal the voltage 335, but may depend on the voltage of the digit line. Thus, the location of the final charge states 305-c and 310-c on the hysteresis curve 300-b may depend on the capacitance of the digitline and may be determined by load line analysis, e.g., the charge states 305-c and 310-c may be defined with respect to the digitline capacitance. Thus, the voltage of the capacitor (voltage 350 or voltage 355) may be different and may depend on the initial state of the capacitor.

By comparing the digital line voltage to a reference voltage, the initial state of the capacitor can be determined. The digital line voltage may be the difference between voltage 335 and the final voltage across the capacitor (voltage 350 or voltage 355), such as the difference between voltage 335 and voltage 350 or the difference between voltage 335 and voltage 355. The reference voltage may be generated such that its magnitude is between two possible voltages of the two possible digital line voltages to determine whether to store a logic state, e.g., to determine whether the digital line voltage is above or below the reference voltage. After the comparison by the sense component, the sensed digit line voltage can be determined to be above or below the reference voltage, and the stored logic value (e.g., logic 0 or 1) of the ferroelectric memory cell can be determined.

In some cases, the ferroelectric memory cell may maintain an initial logic state after a read operation. For example, if charge state 305-b is stored, during a read operation, the charge state may follow path 340 to charge state 305-c, and after voltage 335 is removed, the charge state may return to the initial charge state 305-b by following path 340 in the opposite direction. In some cases, a ferroelectric memory cell may lose its initial logic state after a read operation. For example, if charge state 310-b is stored, during a read operation, the charge state may follow path 345 to charge state 305-c, and after voltage 335 is removed, the charge state may be alleviated to charge state 305-b by following path 340.

Hysteresis curve 300-b illustrates an example of reading a memory cell configured to store charge state 305-b and charge state 310-b. For example, the read voltage 335 may be applied as a voltage difference via the digit line 215 and the plate line 220, as described with reference to FIG. 2. The hysteresis curve 300-b may illustrate a read operation in which the read voltage 335 is a negative voltage difference Vcap (e.g., in which Vsubtom-Vplate is negative). The negative read voltage across the capacitor may be referred to as a "plate high" read operation, where plate line 220 is initially placed at a high voltage and digit line 215 is initially at a low voltage (e.g., ground). Although the read voltage 335 is shown as a negative voltage across the ferroelectric capacitor 240, in an alternative operation, the read voltage may be a positive voltage across the ferroelectric capacitor 240, which may be referred to as a "plate-low" read operation.

When memory cell 205 is selected (e.g., by activating switching component 245, as described with reference to fig. 2), a read voltage 335 may be applied across ferroelectric capacitor 240. After a read voltage 335 is applied to ferroelectric capacitor 240, charge may flow into or out of ferroelectric capacitor 240 via digit line 215 and plate line 220, and a different charge state may be generated depending on whether ferroelectric capacitor 240 is in charge state 305-a (e.g., a logic 1) or charge state 310-a (e.g., a logic 0).

FIG. 4 illustrates an example of a memory device 400 that supports reference voltage management in accordance with examples disclosed herein. Memory device 400 may include memory cells 205-a that may be coupled with Digit Lines (DL) 215-a. For example, memory cell 205-a may include a cell capacitor 240-a, such as a ferroelectric capacitor or another type of capacitor. Memory cell 205-a may include a cell selector 245-a (e.g., a switching component) for selecting memory cell 205-a by activating a signal on Word Line (WL) 210-a. The memory cell 205-a, word line 210-a, and digit line 215-a may be examples of the memory cell 205, word line 210, and digit line 215 discussed with reference to FIG. 2.

Cell plate 497 of cell capacitor 240-a may be coupled with plate line 220-a. The plate line 220-a may be coupled with a voltage source 460, and the voltage source 460 may supply a plate line voltage Vplate to the plate line 220-a. In some cases, for example, Vplate may be set to the VSS voltage, which may be the ground voltage. In some cases, Vplate may be set to another voltage.

Digit line 215-a may be coupled with sense amplifier 405 via switching component 485. That is, switching component 485 may be used to establish a conductive path between digit line 215-a and sense amplifier 405. In some cases, switching component 485 may be a cascode amplifier or another type of switching component that may include one or more transistors. In some cases, sense amplifier 405 may be part of a sensing component (e.g., sensing component 250 described with reference to FIG. 2) and may be used to sense a logic state stored on memory cell 205-a by sensing a voltage, current, or charge on digit line 215-a.

Memory device 400 may include a local capacitor 475. The first node 455 of the local capacitor 475 is coupled to the switching element 470 and the node 480, and the node 480 may be a node associated with the gate 490 of the switching element 485. The second node of the local capacitor 475 is coupled to a voltage source 460, the voltage source 460 may supply the board line voltage Vplate. That is, in some cases, the second node 410 of the local capacitor 475 may be biased to the plate line voltage.

In some cases, due to transient effects in the memory device 400, the Vplate seen by the plate line 220-a and the second node 410 of the local capacitor 475 can change relative to the actual voltage supplied by the voltage source 460. That is, Vplate at plate line 220-a and second node 410 of local capacitor 475 can be a local Vplate that may not be fully stable.

In some cases, the voltage at node 480 may activate switching component 485 to couple digit line 215-a and sense amplifier 405. The switching component 485 (e.g., a transistor of the switching component) may be associated with a threshold voltage Vth that may cause a voltage difference between a voltage at the gate 490 of the switching component 485 and a voltage of the digit line 215-a. In some cases, Vth may be the minimum voltage used to activate switching component 485, for example, and may represent the voltage difference from the gate of switching component 485 to the source of switching component 485.

Thus, in some cases, the voltage on the digit line 215-a, and thus the voltage on the cell bottom of the capacitor 240-a, may be approximately equal to the voltage at node 480 (e.g., the gate voltage) minus the threshold voltage Vth. Because of this relationship, the voltage at gate 490 of switching component 485 (e.g., at node 480) may be used to bias memory cell 205-a.

Local capacitor 475 may be selectively coupled to node 435 by activating switching component 470. Node 435 may be biased to a voltage supplied by voltage source 450, such as via global capacitor 495. In some cases, the voltage at node 435 may be referred to as the VCASC voltage (e.g., the voltage used to bias the cascode amplifier). For example, a global capacitor 495 may be included in the memory device 400 to help maintain stability of the VCASC voltage at node 435. In some cases, the global capacitor 495 may represent a single discrete capacitor. In other cases, the global capacitor 495 may represent one or more discrete capacitors as well as parasitic capacitances associated with circuitry in the memory device 400.

When switching component 470 is activated, local capacitor 475 may generate a voltage across local capacitor 475 that is based on the voltage of node 435 (e.g., the VCASC voltage) and the voltage provided by voltage source 460 (e.g., Vplate). That is, when switching component 470 is activated, local capacitor 475 may generate a voltage difference across local capacitor 475 that is equal to VCASC-Vplate.

The first node 455 of the local capacitor 475 may be coupled with node 435 (which is biased to VCASC) when the sensing component is idle. This may cause local capacitor 475 to store a voltage difference between the voltage at node 435 (VCASC) and the plate-line voltage (Vplate) when the circuitry is relatively quiet. During this period, the voltage at node 480 may be substantially equal to the voltage at node 435.

As previously discussed, the read operation may include activating a sense component (e.g., including sense amplifier 405) to determine the state stored by memory cell 205-a. However, prior to activating the sense amplifier 405, the first node of the local capacitor 475 may be decoupled from the node 435 by deactivating the switching component 470, allowing the first node 455 of the local capacitor 475 (and the node 480 associated with the gate 490) to float. At this point, the voltage at node 480 may be referred to as the local VCASC voltage because it is based on the (global) VCASC voltage at node 435, but is allowed to drift based on the voltage variation of Vplate at node 410. After deactivating the switching component 470, the memory cell 205-a may be accessed and the sense amplifier 405 may be activated to determine the state stored by the memory cell 205-a.

As previously mentioned, when the sense component (e.g., including sense amplifier 405) is activated, it may inject a current into plate line 220-a, causing the plate line voltage (Vplate) to change. Accordingly, the plate line voltage at the second node 410 of the local capacitor 475 may change during a read operation. Because the first node 455 of the capacitor 475 is floating (e.g., it is not controlled by or coupled with the voltage supply), changes in the plate-line voltage at the second node 410 of the local capacitor 475 result in corresponding voltage changes at the first node 455 of the local capacitor 475, thereby also changing the voltage at the node 480. In this manner, local capacitor 475 allows the local VCASC voltage at node 480 (at gate 490 of switching component 485) to track the voltage variation of the plate line voltage Vplate, thereby maintaining a stable voltage difference (e.g., read voltage) across memory cell 205-a during a critical portion of a read operation, such as when sense amplifier 405 is activated.

After the sense portion of the read operation is complete, the sense amplifier 405 may be deactivated (e.g., the sense amplifier 405 may become idle), and the first node 455 of the local capacitor 475 may be recoupled with the node 435 to recharge the local capacitor 475 to the voltage difference between the node 435 (e.g., VCASC) and the node 410 (e.g., Vplate) before the next access of the memory cell 205-a follows.

In some cases, the switching component 470 may be deactivated by opening the switching component 470 such that there may be no electrical connection between the node 435 and the first node 455 (and the node 480). In this case, when the switching component 470 is deactivated, the resistance of the switching component 470 may be considered infinite.

In some cases, the switching component 470 may be deactivated by adjusting (e.g., increasing) the resistance of the switching component 470 without fully opening the switching component 470. For example, the open-circuit switching components may be replaced with resistive connections to maintain a weak connection between the global VCASC voltage (at node 435) and the local VCASC voltage (at node 480). In this case, a small amount of current may still flow through the switching component 470.

FIG. 5 illustrates an example of a timing diagram 500 of voltages that may occur during a read operation of a memory cell in a memory device supporting reference voltage management in accordance with examples disclosed herein.

As previously discussed, in some cases, the read voltage across the memory cell (e.g., the difference between the voltages applied to the top and bottom plates of the cell capacitor) may be affected by noise within the PDN. The read voltage can be expressed as:

Vcell＝VCASC-Vth-Vplate

where VCASC may be a local VCASC voltage at node 480, such as at gate 490 of switching component 485 (e.g., a transistor or cascode amplifier). Vth may be a threshold voltage associated with switching component 485 and Vplate may be a plate voltage applied to the cell plate of cell capacitor 240-a.

As previously discussed, it is desirable to maintain a stable read voltage Vcell during a read operation of memory cell 205-a, particularly during the critical portion of a read operation in which a sense amplifier (e.g., sense amplifier 405) is activated and determines the state stored by memory cell 205-a. However, in some cases, when the sense amplifier is activated, it may cause the voltage of the plate line (Vplate) to rise, thus potentially lowering the read voltage Vcell, which may adversely affect the accuracy of the read operation.

Thus, as discussed with reference to fig. 4, the local capacitor 475 may be used to maintain a stable read voltage Vcell during read operations. In particular, local capacitor 475 may be coupled with node 435, which may be biased to a voltage (e.g., VCASC). Local capacitor 475 may be coupled with node 435 during inactive phase 505 (e.g., when the sense amplifier is inactive) to sample and store the voltage difference between Vplate and VCASC when the circuit is relatively quiet. Then, switching component 470 may be deactivated to decouple local capacitor 475 from node 435 and allow node 480 to float with a voltage based on the voltage across local capacitor 475 prior to activating the sense amplifier. Because first node 455 of local capacitor 475 is floating and second node 410 of local capacitor 475 is coupled with Vplate, the voltage at node 480 may track the voltage variation of Vplate, thereby maintaining a stable read voltage Vcell during active phase 510 of performing critical operations, as depicted in timing diagram 500.

That is, as depicted in fig. 5, when the plate line voltage Vplate rises during the active phase 510 (e.g., due to activating the sense amplifier to sense the state of the memory cell), the local VCASC at node 480 (and thus the local VCASC-Vth) rises by an equal amount, thereby maintaining a stable read voltage Vcell across the memory cell 205-a during the active phase 510. The voltages depicted in timing diagram 500 are approximations and are intended to illustrate general behavior and not specific voltages.

Fig. 6 illustrates an example of a circuit 600 supporting reference voltage management in accordance with examples disclosed herein. The circuit 600 may be similar to the circuitry depicted in the memory device 400, but may be used to more generally maintain a stable voltage difference between a general reference signal and another voltage (e.g., a VSS voltage or a ground voltage). For example, such a voltage difference may be used as a reference voltage used by a sense amplifier to determine the state stored by the memory cell (as described with reference to FIG. 2), or may be used for another type of reference.

The circuit 600 may include a local capacitor 605 having a first node 610 coupled with a voltage source 615. For example, the voltage source 615 may supply a first voltage. The first voltage may be a VSS voltage, a ground voltage, or another voltage. Local capacitor 605 has a second node 620 coupled to node 625. For example, node 625 may be a node that provides a local reference voltage (local REF) to other circuitry, such as a sensing component.

For example, the second node 620 of the local capacitor 605 may be selectively coupled with the node 630 by activating the switching component 635. Node 630 may be biased to a global reference voltage (global REF).

For example, during certain critical operations of the memory device, the circuit 600 may be used within the memory device to provide a stable voltage difference between a local reference voltage at node 625 and the voltage supplied by the voltage source 615. Such critical operations may include a portion of a read operation during which the local reference voltage is used to determine the state of the memory cell, or during another type of operation in which it is desired to maintain a steady voltage difference between the local reference voltage and the voltage supplied by the voltage source 615.

In some cases, the switching component 635 may be activated (e.g., during an inactive or idle phase when certain components of the memory device (e.g., a sensing component) are inactive) to couple the node 620 and the node 630 of the local capacitor 605. For example, the switching component 635 may be activated prior to critical operations, such as prior to the sensing component being activated and using a local reference voltage at node 625 to determine the state stored by the memory cell. The switching component 635 can then be deactivated to store the voltage difference between node 630 and node 610 on the local capacitor 605. Then, a critical operation (such as a sense operation during an access of memory cell 205-a or another type of operation) may be performed when switching component 635 is deactivated and node 625 floats. In some cases, switching component 635 may be activated again after the critical operation is completed to recharge capacitor 605 prior to a subsequent memory access.

FIG. 7 illustrates an example of a memory device 700 that supports reference voltage management in accordance with examples disclosed herein. In some cases, the circuitry depicted in memory device 700 may help provide a stable read voltage by sampling and storing the difference between, for example, the plate line voltage Vplate and the global cascode voltage VCASC, multiple times using the plurality of local capacitors 475 and switching components 470 before critical operations (e.g., when the sense amplifier is activated). Multiple samples of the voltage difference may then be used to determine (e.g., provide) a moving average voltage difference.

In some cases, transient noise may be present in the circuit (e.g., in the PDN) when storing the difference between the plate line voltage Vplate and the cascode voltage VCASC (e.g., when the switching component 470 is open to cause the local capacitor 475 to store the voltage difference, as described with reference to fig. 4). In this case, the voltage difference stored on local capacitor 475 may be different than the voltage difference between Vplate and VCASC that is closer to the time that the sense amplifier is activated, thereby potentially reducing subsequent tracking of the local VCASC voltage with the Vplate voltage when the switching component is turned on. In this case, the read voltage (e.g., Vcell) during critical operations may be less stable due to transient voltage differences that occur before the time that the switching component 470 is deactivated.

Thus, rather than using a single local capacitor 475 that samples at a given time as described with reference to FIG. 4, memory device 700 may include multiple local capacitors 475-a, 475-b, 475-c and corresponding switching components 470-a, 470-b, 470-c, which may be used to store the voltage difference between VCASC and Vplate at multiple (different) times prior to a critical operation (e.g., when a sense amplifier is activated), as depicted in FIG. 7. Multiple local capacitors 475 may then be coupled to one another via switching components 705-a, 705-b, 705-c to enable charge sharing across local capacitors 475, thereby providing a moving average of the difference between VCASC and Vplate, for example. The moving average may, in turn, enable the memory device 700 to provide a more stable read voltage during critical operations, as described in more detail below.

Memory device 700 may include memory cells 205-b that may be coupled with Digit Lines (DL) 215-b. Memory cell 205-a may include a cell capacitor 240-b and a cell selector 245-b for selecting memory cell 205-b by activating a signal on the Word Line (WL) 210-b. The memory cell 205-b, word line 210-b, and digit line 215-b may be examples of the memory cells 205, 205-a, word lines 210, 210-a, and digit lines 215, 215-a discussed with reference to FIGS. 2 and 4.

The cell plate of cell capacitor 240-b may be coupled with plate line 220-b. Plate line 220-b may be coupled to voltage source 460-a, which voltage source 460-a may supply plate line voltage Vplate to plate line 220-a.

The digit line 215-b may be coupled with the sense amplifier 405-a via one or more switching elements (e.g., switching element 485-a). That is, switching component 485-a may be used to establish a conductive path between digit line 215-b and sense amplifier 405-a. Switching component 485-a may be an example of switching component 485 described with reference to fig. 4, and may be, for example, a cascode amplifier.

As discussed above, the memory device 700 may include a plurality of local capacitors 475. Multiple local capacitors 475 may be used to sample the difference between the board voltage Vplate and the global VCASC voltage at different times before the sense amplifier 405-a is activated. This set of local capacitors 475 may be used to provide a moving average voltage to node 480-a, which may be located at gate 490-a of switching element 485-a.

Each local capacitor 475 may be selectively coupled with node 435-a (e.g., with the global VCASC voltage) by activating a corresponding switching component 470. For example, node 435-a may be biased to a voltage provided by voltage source 450-a via global capacitor 495-a. In some cases, node 435-a may be biased to the global VCASC voltage. By way of example, in some cases, first capacitor 475-a and second capacitor 475-b may be coupled with node 435-a by activating switching components 470-a and 470-b, respectively.

In some cases, for example, the first node 455 of each local capacitor 475 may be selectively coupled with node 435-a as described above, and the second node 410 of each local capacitor 475 may be coupled with the plate line voltage Vplate provided by voltage source 460-a. In some cases, for example, the plate line voltage Vplate may also be applied to the bottom plate of the cell capacitor 240-b.

In some cases, the first node 455 of each local capacitor 475 may be coupled with node 435-a (e.g., by activating the corresponding switching component 470) during a time period in which the sense amplifier 405-a is inactive. During this time period, the switching elements 705-a, 705-b, 705-c may be deactivated, e.g., they may be turned on. Thus, local capacitor 475 may generate a voltage across local capacitor 475, which may be the difference between the voltage at node 435-a (e.g., global VCASC) and the voltage supplied by voltage source 460-a (e.g., Vplate).

At a first time, the switching component 470-a may be deactivated, causing the local capacitor 475-a to decouple from the node 435-a and storing a first difference between the voltage at the node 435-a and the voltage supplied by the voltage source 460-a.

At a second time (e.g., after the first time), the switching component 470-b may be deactivated, causing the local capacitor 475-b to decouple from the node 435-a and storing a second voltage difference between the voltage at the node 435-a and the voltage supplied by the voltage source 460-a. The second voltage difference may be different from the first voltage difference (e.g., stored by local capacitor 475-a) due to transient changes in VCASC, Vplate, or both.

At a third time (e.g., after the second time), the switching component 470-c may be deactivated, causing the local capacitor 475-c to decouple from the node 435-a and storing a third difference between the voltage at the node 435-a and the voltage supplied by the voltage source 460-a. This third voltage difference may be different than the first and/or second voltage differences stored by local capacitors 475-a and 475-b, respectively, due to transient voltage changes of VCASC, Vplate, or both.

At a fourth time (e.g., after the third time), local capacitors 475-a, 475-b, 475-c may be coupled with node 480-a by activating corresponding switching components 705-a, 705-b, 705-c. For example, node 480-a may be located at gate 490-a of switching component 485-a. When switching component 705 is activated, the set of local capacitors 475 may share charge with one another, thereby providing a moving average VCASC voltage (e.g., an average of the voltage differences stored by local capacitors 475 at the first time, the second time, and the third time) to node 480-a.

For example, after the switching component 705 is activated, the sense amplifier 405-a may be activated to determine the state stored by the memory cell 205-b. Because the first node 455 of each of the local capacitors 475 is decoupled from node 435-a and thus floats during this critical portion of the read operation, the voltage at node 480-a can track the voltage variation of the plate line (Vplate) and provide a more stable read voltage across the memory cell 205-b when, for example, the sense amplifier is activated.

Although the memory device 700 depicts three local capacitors (475-a, 475-b, 475-c) and corresponding switching components (470-a, 470-b, 470-c, 705-a, 705-b, 705-c), it should be appreciated that the memory device may use more or fewer local capacitors and switching components without departing from the scope of the present disclosure.

Optionally, memory device 700 may include an additional local capacitor 710 that may be used to store the moving average voltage provided by local capacitor 475 and provide the moving average voltage to node 480-a.

In some cases, it is desirable to have the voltage difference stored by the local capacitor 475 weighted differently according to the moving average voltage. For example, a voltage difference stored at a later time (e.g., a voltage difference stored by local capacitor 475-c at a third time) may be more relevant to maintaining a stable read voltage than a voltage difference stored at an earlier time (e.g., a voltage difference stored by local capacitor 475-a at a first time). Because a larger capacitor may have a greater relative impact on the overall average voltage when all capacitors are coupled together, the voltage difference may be stored using the larger capacitor at the most relevant time (e.g., at the last time the voltage difference was sampled).

Thus, in some cases, each local capacitor 475 may have a different capacitance depending on the desired weighting of the voltage difference stored by the local capacitor 475. As an example, local capacitor 475-a may have a smaller capacitance than local capacitor 475-b, which in turn may have a smaller capacitance than local capacitor 475-c. Other size combinations are also possible.

Additional details regarding the timing and operation of the moving average circuitry (e.g., including the set of local capacitors 475 and corresponding switching components) of the memory device 700 are discussed with reference to fig. 8 and 9.

Fig. 8 illustrates an example of a circuit 800 supporting reference voltage management in accordance with examples disclosed herein. The circuit 800 may be referred to as a moving average circuit and may be similar to the moving average circuitry depicted in the memory device 700, but may be used more generally to maintain a steady voltage difference (Δ V) between a general reference signal (e.g., a local reference signal) and another voltage (e.g., a VSS voltage or a ground voltage) during critical operations using techniques similar to those described with reference to FIG. 7. Such a reference signal may include a reference voltage, such as used by a sense amplifier to determine the state stored by the memory cell described with reference to FIG. 2, or may be another type of reference signal. For example, the critical operation may be an operation during which maintaining a stable difference between the local reference signal and the second voltage is very important.

The circuit 800 may include a set of multiple local capacitors 805. Local capacitor 805 can be used to sample and store the voltage difference between a global reference voltage (global REF) at node 820 and a second voltage, such as a voltage supplied by voltage source 830, at different times before critical operations are performed. The local capacitor 805 may be used to provide a moving average voltage difference to a node 825, and the node 825 may provide a local reference signal (local REF) to other circuitry (e.g., sensing components) in the memory device.

As described with respect to circuitry in memory device 700, each local capacitor 805 can be selectively coupled with node 820 by activating a corresponding switching component 810. In some cases, for example, a first node of each local capacitor 805 may be selectively coupled with the node 820, and a second node of each local capacitor 805 may be coupled with the voltage source 830.

In some cases, when the circuit is relatively quiet, the local capacitor 805 may be coupled with the node 820 (e.g., by activating the corresponding switching component 810) for a period of time prior to critical operation. During this time period, the switching elements 815-a, 815-b, 815-c may be deactivated, e.g., may be turned on. Thus, the local capacitor 805 may generate a voltage across the local capacitor 805, which may be a voltage difference Δ V between the voltage at the node 820 and the voltage supplied by the voltage source 830.

At a first time, the switching component 810-a may be deactivated, causing the local capacitor 805-a to decouple from the node 820 and storing a first voltage difference between the voltage at the node 820 and the voltage supplied by the voltage source 830.

At a second time (e.g., after the first time), the switching component 810-b may be deactivated, causing the local capacitor 805-b to decouple from the node 820 and store a second voltage difference between the voltage at the node 820 and the voltage supplied by the voltage source 830. The second voltage difference may be different than the first voltage difference (e.g., as stored by local capacitor 805-a) due to transient variations in the global reference voltage at node 820, the local voltage supplied by voltage source 830, or both.

At a third time (e.g., after the second time), the switching component 810-c may be deactivated, causing the local capacitor 805-c to decouple from the node 820 and storing a third difference between the voltage at the node 820 and the voltage supplied by the voltage source 830. This third voltage difference may be different than the first and/or second voltage differences stored by local capacitors 805-a and 805-b, respectively, due to transient variations in the global reference voltage at node 820, the local voltage supplied by voltage source 830, or both.

At a fourth time (e.g., after the third time), the local capacitors 805-a, 805-b, 805-c may be coupled with the node 825 and with each other by activating the corresponding switching components 815-a, 815-b, 815-c. The node 825 may provide a local reference signal (local REF) to other circuitry (e.g., sense components) in the memory device. When the switching component 815 is activated, the local capacitors 805 may share charge with each other, thereby providing a moving average of the voltage differences stored at the first time, the second time, and the third time to the node 825. Because node 825 is floating, the voltage at node 825 can track the voltage variation of the local voltage supplied by voltage source 830, thereby providing a steady voltage difference (e.g., a steady local REF) at node 825.

After switching component 815 is activated and node 825 is allowed to float, critical operations may be performed. In some cases, during critical operations, the voltage difference Δ V between the local reference signal at node 825 and the voltage supplied by voltage source 830 may remain relatively stable because the voltage at node 825 may track voltage variations associated with voltage source 830 through local capacitor 805.

In some cases, for example, after performing a critical operation, the local capacitor 805 may be decoupled from the node 825 (e.g., by deactivating the switching component 815) and recoupled with the node 820 (e.g., by activating the switching component 810) in preparation for the next critical operation.

Other aspects of the operation of the circuit 800 are described in more detail with reference to FIG. 9, the circuit 800 may be general case for the circuitry depicted in the memory device 700.

FIG. 9 illustrates an example of a timing diagram 900 of voltages that may occur during various operations in a memory device supporting reference voltage management in accordance with examples disclosed herein.

As previously discussed, in some cases, it is desirable to maintain a stable voltage difference av between a local reference voltage and another voltage (e.g., a VSS voltage, a ground voltage, or other voltage) during certain critical operations. Such critical operations may include, for example, sensing operations during read operations of the memory cells or other critical operations during which stability of the voltage difference Δ V is desired.

The timing diagram 900 depicts various voltages associated with the circuit 800 during operation of a memory device that may include the circuit 800.

Timing diagram 900 may include a global reference voltage 905, which may be, for example, a voltage associated with node 820 of circuit 800 (e.g., global REF). That is, in some cases, node 820 may be biased to a global reference voltage 905, which may be, for example, a reference voltage for sensing operations or a VCASC voltage.

The timing diagram may include a local supply voltage 910, which may be a voltage associated with the voltage supply 830. That is, in some cases, local supply voltage 910 may be supplied by voltage supply 830, for example, but may experience variations based on various electrical effects in the memory device, such as when current is injected by an active sense amplifier. For example, the local supply voltage 910 may be (or may be based on) a VSS voltage or a plate line voltage (Vplate) supplied by the voltage supply 830.

Timing diagram 900 may include a local reference voltage 915, which may be the voltage at node 825 of circuit 800 (e.g., a local REF). In some cases, the local reference voltage 915 may be a reference voltage used by the sense amplifier to determine the state stored by the memory cell, or may be a gate voltage such as a voltage used to bias the memory cell (e.g., a voltage at a gate of a cascode amplifier). The voltages depicted in timing diagram 900 are approximations and are intended to illustrate general electrical behavior rather than specific voltages.

Prior to time 920, switching components 810 and 815 may be activated (e.g., "on"). Accordingly, the local reference voltage 915 may be substantially equal to the global reference voltage 905 (and thus may not be visible in the timing diagram 900) because the node 825 is coupled with the node 820. The voltage across each of the local capacitors 805 may be the difference between the global reference voltage 905 and the local supply voltage 910 (which may be slightly different from the voltage of the voltage supply 830 due to various transients or parasitics in the memory device).

At time 920, the switching components 815 may be deactivated (e.g., "turned off") to decouple each of the local capacitors 805 from the node 825 (e.g., the local reference voltage 915). In addition, switching component 810-a may be deactivated to decouple local capacitor 805-a from node 820 (e.g., global reference voltage 905). Thus, at time 920, local capacitor 805-a may store a first voltage difference Δ V1 between global reference voltage 905 at node 820 and local supply voltage 910. At time 920, local capacitors 805-b and 805-c may remain coupled with node 820, i.e., switching components 810-b, 810-c may remain "on".

At time 925, switching component 810-b may be deactivated to decouple local capacitor 805-b from node 820 (e.g., global reference voltage 905). Thus, at time 925, local capacitor 805-b may store a second voltage difference Δ V2 between global reference voltage 905 at node 820 and local supply voltage 910. At time 925, local capacitor 805-c may remain coupled with node 820, i.e., switching component 810-c may remain "on".

At time 930, switching component 810-c may be deactivated to decouple local capacitor 805-c from node 820 (e.g., global reference voltage 905). Thus, at time 930, local capacitor 805-c may store a third voltage difference Δ V3 between global reference voltage 905 at node 820 and local supply voltage 910.

Also at (or near) time 930, switching component 815 may be activated ("turned on") so that local capacitors 805 may be coupled to each other and to node 825, and may begin to share charge. Accordingly, the voltage at the node 825 (e.g., the local reference voltage 915) may be biased to a voltage such that the voltage difference between the local reference voltage 915 and the local supply voltage 910 is an average of the voltage differences Δ V1, Δ V2, Δ V3 across the local capacitor 805. Because Δ V1, Δ V2, Δ V3 are each stored at different times, this average may be considered a moving average.

As previously discussed, in some cases, the size of the local capacitor 805 may be different such that the voltage at the node 825 may provide a weighted average of the voltage differences Δ V1, Δ V2, Δ V3 across the local capacitor 805.

At (or after) time 930, critical operations (e.g., activity phases) may begin. For example, a critical operation may include activating a sense amplifier to sense a voltage on a digit line during a read operation of a memory cell. For example, the critical operation may be based on (e.g., may use or rely on) a voltage difference 940 between the local reference voltage 915 and the local supply voltage 910.

During critical operations (which may occur between time 930 and time 935), the voltage difference 940 between the local reference voltage 915 and the local supply voltage 910 may remain relatively stable even though the local supply voltage 910 may change because the local capacitor 805 is decoupled from the global reference voltage 905, e.g., it is floating, thereby enabling the voltage at node 825 (e.g., the local reference voltage 915) to track voltage variations of the local supply voltage 910 and maintain the stable voltage difference 940.

At time 935, the critical operation may end. At or after time 935, the switching component 810 (and possibly 815) may be reactivated by re-coupling the local capacitor 805 with the node 820 in preparation for the next operation.

Fig. 10 shows a block diagram 1000 of a controller 1005 supporting reference voltage management in accordance with an example disclosed herein. The controller 1005 may be an example of a feature of a local memory controller, a device memory controller, or an external memory controller of the memory device described with reference to fig. 1 and 2. Controller 1005 may include a switch manager 1010, an access operation manager 1015, a sense manager 1020, and a storage manager 1025. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses, conductive lines, etc.).

The switching manager 1010 may couple the first capacitor with a first node biased to a first voltage. The first capacitor can be coupled with a second node associated with establishing a conductive path between a digit line and a sense component of the memory cell.

In some examples, the switching manager 1010 may decouple the first capacitor from the first node, e.g., before accessing the memory cell and performing a critical operation. In some examples, the switching manager 1010 may couple (e.g., re-couple) the first capacitor with the first node after accessing the memory cell.

In such examples, the switching manager 1010 may couple the first and second capacitors with a first node biased to a first voltage. The switching manager 1010 may decouple the first capacitor and the first node at a first time to store a first representation of a difference between the first voltage and a second voltage associated with a plateline of the memory cell. The switching manager 1010 may decouple the second capacitor from the first node at a second time after the first time to store a second representation of a difference between the first voltage and the second voltage. The switching manager 1010 can couple the first capacitor and the second capacitor at a second time after the first time and a second node associated with establishing a conductive path between a digit line and a sense component of the memory cell.

The switching manager 1010 may couple the first capacitor with the first node by activating the switching component. The switching manager 1010 may decouple the first capacitor from the first node by deactivating the switching component. The switching manager 1010 may decouple the first capacitor from the first node by adjusting (e.g., increasing) a resistance associated with the switching component. In some cases, coupling the first capacitor with the first node couples the first capacitor with a second capacitor, where the second capacitor is coupled between the first node and a voltage supply that provides the first voltage.

The switching manager 1010 may couple the first capacitor and a third capacitor where the second capacitor is coupled with the second node.

In some cases, the first capacitor is coupled with the first node when the sensing component is inactive. In some cases, the first capacitor is coupled with a gate of the cascode amplifier. In some cases, the first capacitor and the second capacitor are coupled with a second voltage supply configured to supply a second voltage.

The access operation manager 1015 may access the memory cell after the first capacitor is decoupled from the first node. In some examples, the access operation manager 1015 may access the memory cell when the first capacitor and the second capacitor are coupled with the second node. In some examples, the access operation manager 1015 may access the memory cells by asserting word line signals associated with the memory cells.

Storage manager 1025 may store a voltage difference between a first voltage and a second voltage associated with a plate line of a memory cell using a first capacitor.

The sensing manager 1020 may sense a state stored by the memory cell using the sensing component when the first capacitor is decoupled from the first node.

FIG. 11 shows a flow diagram illustrating one or several methods 1100 of supporting reference voltage management in accordance with examples disclosed herein. The operations of method 1100 may be implemented by a memory device or components thereof described herein. For example, the operations of method 1100 may be performed by the memory device described with reference to FIG. 1. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

At 1105, a memory device may couple a first capacitor with a first node biased to a first voltage. The first capacitor can be coupled with a second node associated with establishing a conductive path between a digit line and a sense component of the memory cell. Operation 1105 may be performed according to the methods described herein. In some examples, aspects of operation 1105 may be performed by a handoff manager, as described with reference to fig. 10.

At 1110, the memory device may store a voltage difference between a first voltage and a second voltage associated with a plate line of the memory cell using a first capacitor. Operation 1110 may be performed according to the methods described herein. In some examples, aspects of operation 1110 may be performed by a storage manager, as described with reference to fig. 10.

At 1115, the memory device may decouple the first capacitor from the first node. Operation 1115 may be performed in accordance with the methods described herein. In some examples, aspects of operation 1115 may be performed by a handoff manager, as described with reference to fig. 10.

At 1120, the memory device may access the memory cell after decoupling the first capacitor from the first node. Operation 1120 may be performed according to the methods described herein. In some examples, the features of operation 1120 may be performed by an access operation manager, as described with reference to fig. 10.

At 1125, the memory device can couple the first capacitor and the first node after accessing the memory cell. Operation 1125 may be performed according to the methods described herein. In some examples, the features of operation 1125 may be performed by a handoff manager, as described with reference to fig. 10.

In some examples, an apparatus described herein may perform one or several methods, such as method 1100. An apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for coupling a first capacitor with a first node biased to a first voltage, where the first capacitor is coupled with a second node associated with establishing a conductive path between a digit line of a memory cell and a sense component. The apparatus may include features, means or instructions for: storing, using a first capacitor, a voltage difference between a first voltage and a second voltage associated with a plate line of a memory cell; decoupling the first capacitor from the first node; accessing the memory cell after decoupling the first capacitor from the first node; and coupling the first capacitor and the first node after accessing the memory cell.

Some examples of the method 1100 and apparatus described herein may further include operations, features, means, or instructions for sensing a state stored by a memory cell using the sensing component when the first capacitor is decoupled from the first node.

In some examples of the method 1100 and apparatus described herein, coupling the first capacitor with the first node may include operations, features, means, or instructions for activating a switching component.

In some examples of the method 1100 and apparatus described herein, decoupling the first capacitor from the first node may include operations, features, means, or instructions for deactivating the switching component.

In some examples of the method 1100 and apparatus described herein, decoupling the first capacitor from the first node may include operations, features, means, or instructions for increasing a resistance associated with the switching component.

In some examples of the method 1100 and apparatus described herein, the first capacitor may be coupled with the first node when the sensing component may be inactive.

In some examples of the method 1100 and apparatus described herein, the first capacitor may be coupled with a gate of the cascode amplifier.

Some examples of the method 1100 and apparatus described herein may further include operations, features, means, or instructions for coupling the first capacitor with a first node (which couples the first capacitor with a second capacitor), wherein the second capacitor may be coupled between the first node and a voltage supply that provides the first voltage.

In some examples of the method 1100 and apparatus described herein, accessing a memory cell may include an operation, feature, means, or instruction for asserting a word line signal associated with the memory cell.

FIG. 12 shows a flow diagram illustrating one or several methods 1200 of supporting reference voltage management in accordance with features of the present disclosure. The operations of method 1200 may be implemented by the memory devices described herein or components thereof. For example, the operations of method 1200 may be performed by the memory device described with reference to fig. 1. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform the features of the described functions.

At 1205, the memory device may couple the first capacitor and the second capacitor with a first node biased to a first voltage. Operation 1205 may be performed according to the methods described herein. In some examples, the features of operation 1205 may be performed by a handoff manager, as described with reference to fig. 10.

At 1210, the memory device may decouple the first capacitor and the first node at a first time to store a first representation of a difference between a first voltage and a second voltage associated with a plate line of the memory cell. Operation 1210 may be performed according to the methods described herein. In some examples, the features of operation 1210 may be performed by a handover manager, as described with reference to fig. 10.

At 1215, the memory device may decouple the second capacitor from the first node at a second time after the first time to store a second representation of a difference between the first voltage and the second voltage. Operation 1215 may be performed in accordance with the methods described herein. In some examples, the features of operation 1215 may be performed by a handoff manager, as described with reference to fig. 10.

At 1220, the memory device may couple the first capacitor and the second capacitor at a second time after the second time and a second node associated with establishing a conductive path between a digit line and a sense component of the memory cell. Operation 1220 may be performed according to the methods described herein. In some examples, the features of operation 1220 may be performed by a handoff manager, as described with reference to fig. 10.

At 1225, the memory device can access the memory cell when the first capacitor and the second capacitor are coupled with the second node. Operation 1225 may be performed according to the methods described herein. In some examples, the features of operation 1225 may be performed by an access operation manager, as described with reference to fig. 10.

In some examples, an apparatus described herein may perform one or several methods, such as method 1200. The apparatus may include features, means, or instructions (e.g., non-transitory computer-readable medium storage instructions executable by a processor) for: coupling the first and second capacitors with a first node biased to a first voltage; at a first time, decoupling a first capacitor from a first node to store a first representation of a difference between a first voltage and a second voltage associated with a plateline of a memory cell; decoupling the second capacitor from the first node at a second time after the first time to store a second representation of a difference between the first voltage and the second voltage; at a third time after the second time, coupling the first and second capacitors to a second node associated with establishing a conductive path between a digit line of the memory cell and the sense component; and accessing the memory cell while the first capacitor and the second capacitor are coupled with the second node.

In some examples of the method 1200 and apparatus described herein, coupling the first and second capacitors with the second node may include operations, features, means, or instructions for coupling the first and second capacitors with a third capacitor that may be coupled with the second node.

In some examples of the methods 1200 and apparatus described herein, the first capacitor and the second capacitor may be coupled with a second voltage supply configured to supply a second voltage.

It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Further, features from two or more of the methods may be combined. Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, one of ordinary skill in the art will appreciate that the signals may represent a signal bus, where the bus may have various bit widths.

The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports signal flow between the components. Components may be considered to be in electronic communication with each other (or in conductive contact, connection, or coupling with each other) if there are any conductive paths between the components that may support signal flow between the components at any time.

At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with or connected or coupled to each other) may be open or closed based on the operation of the device that may include the connected components. The conductive path between connected components may be a direct conductive path between components, or the conductive path between connected components may be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some cases, signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

The term "coupled" refers to a condition that transitions from an open-circuit relationship between components (where signals cannot currently be conveyed between components through conductive paths) to a closed-circuit relationship between components (where signals can be conveyed between components through conductive paths). When a component, such as a controller, couples other components together, the component causes a change that allows a signal to flow between the other components through a conductive path that previously did not allow the signal to flow.

The term "isolation" refers to the relationship between components in which a signal cannot currently flow between the components. If there is an open circuit between the components, they are isolated from each other. For example, when a switch positioned between two components is open, the components separated by the switch are isolated from each other. When the controller isolates the two components from each other, the controller causes a change that prevents signals from flowing between the components using the conductive path that previously allowed the signals to flow.

The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as a silicon-on-glass (SOG) or silicon-on-Sapphire (SOP) or another epitaxial layer of semiconductor material on a substrate. The conductivity of the substrate or sub-regions of the substrate may be controlled by doping with various chemical species, including but not limited to phosphorous, boron or arsenic. The doping may be performed during initial formation or growth of the substrate by ion implantation or by any other doping method.

The switching elements or transistors discussed herein may represent Field Effect Transistors (FETs) and include three terminal devices including sources, drains, and gates. The terminals may be connected to other electronic components through conductive materials (e.g., metals). The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (e.g., majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (e.g., majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulated gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor may be "off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

The description set forth herein in connection with the appended drawings describes example configurations and is not intended to represent all examples that may be practiced or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" rather than "preferred" or "superior to other instances. The detailed description includes specific details for the purpose of providing an understanding of the described technology. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the drawings, similar components or features may have the same reference numerals. Further, various components of the same type may be distinguished by following the reference label by a dashed line and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any one of the similar components having the same first reference label, regardless of the second reference label.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and the following claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or a combination of any of these. Features that implement a function may also be physically located at various locations, including portions that are distributed such that the function is implemented at different physical locations. Further, as used herein (including in the claims), "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of …" or "one or more of …") indicates an inclusive list such that, for example, a list of at least one of A, B or C means a or B or C or AB or AC or BC or ABC (i.e., a and B and C). Further, as used herein, the phrase "based on" should not be construed as referring to a set of closed conditions. For example, exemplary steps described as "based on condition a" may be based on both condition a and condition B without departing from the scope of the present disclosure. In other words, the phrase "based on" as used herein should be interpreted in the same manner as the phrase "based at least in part on".

The description herein is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.