阅读说明：本技术 非易失性存储器的温度计采样和保持设计 (Thermometer sample and hold design for non-volatile memory ) 是由 郭晓江 施伟华 于 2019-05-27 设计创作，主要内容包括：用于非易失性存储器的温度测量的采样和保持方案可以使温度读出延迟显著减少。在一个示例中,温度计电路以刷新速率而被启用,以使以定期的时间间隔对温度进行感测和锁存。通过在后台以刷新速率而不是按需执行温度读取,温度可在几乎没有延迟的情况下为命令提供服务。(A sample and hold scheme for temperature measurement of non-volatile memory may allow for a significant reduction in temperature readout delay. In one example, the thermometer circuit is enabled at a refresh rate such that the temperature is sensed and latched at periodic intervals. By performing temperature readings in the background at a refresh rate rather than on demand, the temperature can service commands with little delay.)

1. A non-volatile memory device, comprising:

a non-volatile memory array;

a thermal sensor to detect a temperature of the non-volatile memory device; and

circuitry for:

sampling the temperature of the non-volatile memory device at regular time intervals,

storing the temperature of the sample, an

The stored temperature is output in response to receiving the command.

2. The non-volatile memory device of claim 1, wherein:

the circuit is configured to sample and store the temperature at regular intervals, independent of receiving a command.

3. The non-volatile memory device of claim 1, wherein:

the circuit is configured to sample and store the temperature prior to receiving the command and output the stored temperature without resampling the temperature.

4. The non-volatile memory device of claim 1, wherein:

the commands include program, read, erase, read status or get feature commands.

5. The non-volatile memory device of claim 1, wherein:

the circuit for sampling the temperature comprises: an oscillator for generating a clock signal, wherein the periodic time intervals at which the temperature is to be sampled are based on the clock signal.

6. The non-volatile memory device of claim 5, wherein:

the circuit for sampling the temperature further comprises: a frequency divider to receive the clock signal and output a signal to turn on a thermometer circuit.

7. The non-volatile memory device of claim 6, wherein:

the circuit for sampling the temperature further comprises: a pulse generator to receive the output of the frequency divider and generate a pulse to trigger sampling of the temperature.

8. The non-volatile memory device of claim 1, wherein:

the circuit for storing the sampled temperature includes a latch.

9. The non-volatile memory device of claim 1, wherein:

the non-volatile memory array comprises a three-dimensional (3D) NAND array; and is

The thermal sensor comprises an on-die thermal sensor on a 3D NAND die.

10. The non-volatile memory device of claim 1, wherein:

the periodic time intervals at which the temperature is sampled are based on values stored in one or more registers.

11. A three-dimensional (3D) NAND die, comprising:

a 3D NAND memory array;

a thermal sensor to detect a temperature of the 3D NAND die; and

circuitry to:

sampling the temperature of the 3D NAND die at regular intervals,

storing the temperature of the sample, an

The stored temperature is output in response to receiving the command.

12. The 3D NAND die of claim 11, wherein:

the circuit is configured to sample and store the temperature at regular intervals, independent of receiving a command.

13. The 3D NAND die of claim 11, wherein:

the circuit is configured to sample and store the temperature prior to receiving the command and output the stored temperature without resampling the temperature.

14. The 3D NAND die of claim 11, wherein:

the commands include program, read, erase, read status or get feature commands.

15. The 3D NAND die of claim 11, wherein:

the circuit for sampling the temperature comprises: an oscillator for generating a clock signal, wherein the periodic time intervals at which the temperature is to be sampled are based on the clock signal.

16. The 3D NAND die of claim 15, wherein:

the circuit for sampling the temperature further comprises: a frequency divider to receive the clock signal and output a signal to turn on a thermometer circuit.

17. The 3D NAND die of claim 16, wherein:

the circuit for sampling the temperature further comprises: a pulse generator to receive the output of the frequency divider and generate a pulse to trigger sampling of the temperature.

18. The 3D NAND die of claim 11, wherein:

the circuit for storing the sampled temperature includes a latch.

19. A system, comprising:

a processor; and

a non-volatile memory device, comprising:

a non-volatile memory array;

a thermal sensor to detect a temperature of the non-volatile memory device; and

circuitry for:

sampling the temperature of the non-volatile memory device at regular time intervals,

storing the temperature of the sample, an

Outputting the stored temperature in response to receiving a command from the processor.

20. The system of claim 19, wherein:

the circuit is configured to sample and store the temperature at regular intervals of time, independent of receiving a command from the processor.

Technical Field

The present description generally relates to non-volatile storage media such as NAND flash memory.

Background

A flash memory device such as a NAND flash memory is a non-volatile storage medium. The nonvolatile memory device refers to a memory device having a certain state even if power of the apparatus is interrupted. Three-dimensional (3D) NAND flash refers to NAND flash in which a NAND string (NAND string) can be vertically constructed such that Field Effect Transistors (FETs) of the string are stacked on top of each other. 3D NAND and other 3D architectures are attractive, in part, because significantly higher bit densities can be achieved relative to two-dimensional (2D) architectures. Thus, flash memory devices are increasingly being used in mobile, client and enterprise sector units. In addition to high bit density, other metrics, such as low latency, are required for memory technology.

Drawings

The following description includes a discussion of figures having illustrations given by way of example of implementations of embodiments of the invention. The drawings should be understood by way of example and not by way of limitation. As used herein, references to one or more "embodiments" or "examples" should be understood to describe a particular feature, structure, and/or characteristic included in at least one implementation of the invention. Thus, phrases such as "in one embodiment" or "in one example" appearing herein describe various embodiments and implementations of the invention, and do not necessarily all refer to the same embodiment. However, they are also not necessarily mutually exclusive.

FIG. 1 depicts an example portion of a NAND flash array in which a thermometer sample and hold circuit may be implemented.

FIG. 2 depicts an example system.

Fig. 3 shows an example of a sample and hold scheme.

FIG. 4 shows an example of a thermometer system in a non-volatile memory die or device.

FIG. 5 shows an example of a sample and hold (S/H) circuit for a memory thermometer system.

Fig. 6 shows a control sequence of the S/H circuit.

Fig. 7 shows an example of a sample and hold oscillator.

Fig. 8 is a timing diagram illustrating handshaking of a sample and hold scheme during chip initialization.

FIG. 9 is a flow chart of an example of a background temperature measurement method for a non-volatile memory device.

FIG. 10 provides an exemplary depiction of a computing system in which the thermometer sample and hold techniques described may be implemented.

The following is a description of certain details and implementations, including: description of the figures may depict some or all of the embodiments described below, as well as a discussion of other potential embodiments or implementations of the inventive concepts presented herein.

Detailed Description

A thermometer sample and hold circuit for a non-volatile memory is described.

The non-volatile memory die includes an on-die thermometer for detecting temperature. The detected temperature may be used to perform temperature compensation for array operation or to provide the temperature to a controller (e.g., a controller in a memory device) in response to a request. The thermometer sample and hold circuit enables the thermometer to sense (sample) the temperature and latch the temperature (hold) in the background for a short period of time. At a certain refresh rate, the thermometer may be periodically enabled to refresh the temperature stored in the latch on the memory die. When the memory die receives a request that requires a temperature read, the temperature can then be read out of the latch without resampling the temperature to support a near zero read delay.

FIG. 1 depicts an example portion of a NAND flash array 100 in which a thermometer sample and hold circuit may be implemented in the NAND flash array 100. The NAND flash memory array 100 includes a plurality of non-volatile memory cells 102A through 102F (abbreviated 102) arranged in columns, such as series strings 104A and 104B (abbreviated 104). In one example, memory cell 102 includes a transistor with a replacement gate. Cells with replacement gates typically have a low resistance gate (e.g., a tungsten gate) and a charge extraction layer between the gate and the channel where charge is extracted or stored to represent one or more bit values. In another example, the memory cell 102 may include a transistor having a floating gate (e.g., a high resistance poly gate) that stores charge indicative of one or more bit values. Other architectures are possible. In the series string 104, the drain region of a cell 102 (except the top cell) is coupled to the source region of another cell 102.

The array 100 also includes word lines 106A-106C. Word lines 106A-106C may span multiple series strings 104 (e.g., a word line may be coupled to one memory cell of each series string 104) and are connected to the control gates of each memory cell 102 in a row of array 100 and serve to bias the control gates of the memory cells 102 in the row. Bit lines 108A and 108B (abbreviated as 108) are each coupled to the series string 104 through a drain select gate 114 and sense circuits 120A and 120B, the sense circuits 120A and 120B detecting the state of each cell by sensing the voltage or current on a particular bit line 108.

Multiple series strings 104 of memory cells are coupled to a source line 110 by source select gates 112A and 112B (abbreviated 112) and to a single bit line 108 by drain select gates 114A and 114B (abbreviated 114). Source select gate 112 is controlled by source select gate control line 116 and drain select gate 114 is controlled by drain select gate control line 118.

In some examples, each memory cell 102 may be programmed according to various encoding schemes (e.g., SLC (single level cell), MLC (multi-level cell), TLC (three level cell), QLC (four level cell), or other encoding schemes). The threshold voltage (Vt) of each cell represents the data stored in the cell.

In one example, a cell state that is set to store multiple bits may form part of multiple different pages, where each bit of the cell corresponds to a different page. For example, for a cell to enter a state storing 2 bits (e.g., using an MLC encoding scheme), one bit may correspond to an Upper Page (UP) and another bit may correspond to a Lower Page (LP). For cells to enter a state storing 3 bits (i.e., using a TLC encoding scheme), one bit may correspond to LP, one bit may correspond to UP, and another bit may correspond to an Extra Page (Extra Page, XP). For a cell to store 4 bits (i.e., using a QLC encoding scheme), one bit may correspond to LP, another bit may correspond to UP, another bit may correspond to XP, and the last bit may correspond to the Top Page (TP). Each page (e.g., LP, UP, XP, or TP) may include a respective set of bits stored by a plurality of different cells of a wordline.

The programming sequence for a set of cells may include programming all desired pages into the set of cells. The programming sequence may include one or more programming procedures. A programming process (which may include one or more programming cycles) may program one or more pages. The programming process may include applying one or more valid programming voltages to the cells to be programmed and then applying one or more verify voltages to the cells in order to determine which cells have completed programming (subsequent programming processes typically do not apply valid programming voltages and/or verify voltages to cells that have completed programming). Applying the effective programming voltage to the cell may include varying a voltage difference between a control gate and a channel of the cell in order to vary a threshold voltage of the cell. Thus, the voltage of the word line (coupled to the control gate of the target cell) and/or the channel of the cell can be set in order to enable the application of an effective programming voltage. Since a program voltage generally refers to a voltage applied to a word line, an effective program voltage may be a voltage difference between a control gate and a channel of a cell (which may be synonymous with a program voltage in the case where the channel is held at 0V).

FIG. 2 depicts an example system. The system includes a host 250 and a memory device 200. The host 250 and the memory device 200 may be examples of systems that exist within the packaging of a computer (e.g., within a laptop/notebook, server, or other computer). In other examples, the memory device 200 may also be accessed via a larger network, such as a local area network (e.g., ethernet) or a wide area network (e.g., wireless cellular network, internet, etc.). Such an example may conform to a standard such as NVMe-od (non-volatile memory express over fabric) architecture. The host 250 includes one or more processors 252, a memory 254, and other components that are omitted from the figure for clarity.

The memory device includes a memory medium 202 for storing data. Memory medium 202 may be a memory or storage medium that may store one or more bits in one or more arrays 209 of memory cells. For example, the memory medium 202 may include non-volatile and/or volatile types of memory. In one example, the memory medium 202 includes one or more non-volatile memory dies. In some examples, the memory medium 202 may comprise a block-addressable memory device, such as NAND technology. In one example, the memory medium 202 comprises a NAND flash memory array, such as the array in fig. 1. The memory medium 202 may also include a non-volatile type of memory such as 3D cross point memory (3DxP) or other byte addressable non-volatile memory. Other technologies (e.g., some NOR flash memories) may byte address reads and/or writes while block address erases. The memory medium 202 may include a memory device using a chalcogenide phase change material (e.g., chalcogenide glass), multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), Magnetoresistive Random Access Memory (MRAM) memory employing memristor technology, or spin transfer torque MRAM (STT-MRAM), or a combination of any of the above, or other memory types. Memory medium 202 may include Single Level Cell (SLC) NAND memory devices, multi-level cell (MLC) NAND memory devices, Triple Level Cell (TLC) NAND memory devices, quad-level cell (QLC) memory devices.

According to some examples, the volatile types of memory included in memory medium 202 may include, but are not limited to, Random Access Memory (RAM), dynamic RAM (D-RAM), double data rate synchronous dynamic RAM (DDR SDRAM), Static Random Access Memory (SRAM), thyristor RAM (T-RAM), or zero-capacitance RAM (Z-RAM). The volatile type of MEMORY may be compatible with a variety of MEMORY technologies, such as DDR4(DDR version 4, an initial specification published by JEDEC in 9 months 2012), LPDDR4 (LOW POWER DOUBLE DATA RATE (LPDDR)) version 4, JESD209-4, originally published by JEDEC in 8 months 2014), WIO2(Wide I/O2 (WideIO2), JESD229-2, originally published by JEDEC in 8 months 2014), HBM (high BANDWIDTH MEMORY dram), JESD235, originally published by JEDEC in 10 months 2013), DDR5(DDR version 5, currently discussed by JEDEC), LPDDR5(LPDDR version 5, currently discussed by JEDEC), HBM2(HBM version 2, currently discussed by JEDEC), and/or other derived or extended technologies based on such specifications.

The memory device 200 may communicate with the host system 250 using respective interfaces 220 and 256. In one example, interface 256 is part of a Peripheral Control Hub (PCH). In the example shown, controller 204 is coupled with a computing platform (e.g., host 250) using interface 220. In one example, the controller 204 is an ASIC (application specific integrated circuit). In one example, the interface conforms to a standard such as PCI Express (PCIe), serial Advanced Technology Attachment (ATA), parallel ATA, Universal Serial Bus (USB), and/or other interface protocols. The controller 204 may communicate with elements of the computing platform to read data from the memory medium 202 or write data to the memory medium 202. Although in this disclosure, the term "host" refers to a system (e.g., host 250) having a processor (or other device that sends a request to access data stored in non-volatile memory) and an interface to communicate with the NAND, some implementations may refer to the controller 204 as a "host" with respect to the non-volatile memory medium 202.

The controller 204 may be configured to receive requests from the host 250 and generate and execute commands related to the use of the storage medium 202 (e.g., commands to read data, write data, or erase data). Other commands may include, for example, a command to read status, a command to change configuration settings, a reset command, and the like. The controller may be implemented in hardware (e.g., logic circuitry), software, firmware, or a combination of hardware, software, and firmware. Examples of logic circuitry include dedicated hard-wired logic circuitry (including, for example, one or more state machine logic circuits), programmable logic circuitry (e.g., Field Programmable Gate Arrays (FPGAs) and Programmable Logic Arrays (PLAs)). In one example, the logic is designed to execute some form of program code, such as SSD firmware (e.g., an embedded processor, an embedded controller, etc.). The memory device also typically includes a memory 217 coupled to the logic 211, which may be used to cache NVM data and store firmware executed by the controller 204. The term "control logic" may be used to refer to logic circuitry, firmware, software, or a combination of both. For example, control logic may refer to control logic 211, firmware, or both.

The controller 204 is coupled with the memory medium 202 to control or command the memory to cause operations to occur (e.g., read, program, erase, suspend, resume, and other operations). Communication between the memory medium 202 and the controller 204 may include writing to and/or reading from particular registers (e.g., registers 208). Such registers may reside in the controller 204, in the memory medium 202, or external to the controller 204 and the memory medium 202. The registers or memory within the memory medium 202 may be accessed by the controller 204 through, for example, an internal interface of the memory device 200 (e.g., an Open NAND Flash Interface (ONFI) interface, a proprietary interface, or other interface) that exists between the controller 204 and the memory medium 202 to communicatively couple the controller 204 and the memory medium 202. Input/output (I/O) pins and signal lines communicatively couple the controller 204 with the memory medium 202 to enable transfer of read and write data between the controller 204 and the memory medium 202. The I/O pins may also be used to transfer other data, such as status information. The memory medium 202 may also include other pins, such as command pins (e.g., Command Latch Enable (CLE), Address Latch Enable (ALE), chip enable (CE #), read enable (RE #), and write enable (WE #), power and ground pins (e.g., Vcc, Vss, etc.). In one example, the memory medium includes a pin to indicate a ready/busy status. However, in implementations where there are many memory dies in one package, it is often impractical to use a dedicated ready/busy pin for each die. Instead, in some examples, the status may be output on an I/O pin of the die in response to a request to read the status.

The controller 204 may be coupled to the word lines of the memory medium 202 to select one of the word lines, apply a read voltage, apply a program voltage combined with a bit line potential level, or apply an erase voltage. The controller 204 may be coupled to the bit lines of the memory medium 202 to read data stored in the memory cells, determine the state of the memory cells during a programming operation, and control the potential levels of the bit lines to promote or inhibit programming and erasing. Other circuitry may be used to apply the selected read voltage and other signals to the memory media 202.

In the example shown, the non-volatile storage medium further includes a thermometer system 207. The thermometer system includes a thermal sensor for sensing or detecting the temperature of the memory media 202. In one such example, each memory die includes a sensor to detect the temperature of the die. In other examples, one thermal sensor may be used for multiple dies, or may include multiple (e.g., 2 or more) thermal sensors for each die. In one example, the thermal sensor is on-die (e.g., internal to the die). The thermometer system also includes logic (circuitry, firmware, or both) to control the thermal sensor.

In conventional NAND devices, the temperature of the die is measured in response to a request. For example, NAND devices measure temperature to perform array operations (e.g., program, read, verify, and erase operations). The NAND device also measures temperature in response to a specific request from the controller to read the temperature (e.g., read status or "get feature" command).

With respect to NAND array operations, temperature is typically read before the operation is performed, since the threshold of a NAND cell is a function of temperature. In a read or verify operation, the NAND die modulates the Word Line (WL) and/or Bit Line (BL) voltages with temperature information to obtain similar string currents at different temperatures. This process may be referred to as tempco (temperature coefficient) compensation. Typical 3D NAND flash products employ an on-die thermometer to detect temperature and apply certain algorithms for temperature compensation to meet cross-temperature performance. When the device is activated and receives array operation commands (including read, program, and erase), the NAND thermometer system is enabled and begins sensing temperatures. The delay in acquiring the temperature may greatly affect the performance of the array operation. For example, according to a thermometer architecture, the process of enabling and sensing temperature may take several microseconds (e.g., 4 to 5us or more) after receiving an array operation command. The NAND on-die firmware can latch the temperature after it is ready and use it for temperature compensation.

Further, the system may send a command to the NAND flash to read the device temperature. The system also needs to wait for this delay after the command is issued. Thus, significant delays in both array operation and command to read device temperature occur due to delays in sensing die temperature.

In contrast, a sample and hold scheme may be used to reduce temperature readout delay. The memory medium 202 further includes: a sample and hold circuit 203 for controlling when and how often temperature readings are taken; and a latch 205 for storing the temperature reading. In one example, the sample and hold circuit 203 includes a standby oscillator (e.g., a sample and hold (S/H) oscillator) that remains on in the background to monitor time. At some predetermined refresh rate, a temperature sensor circuit (e.g., the circuitry of the thermometer system 207) is enabled and senses temperature. Once the temperature is read, the temperature bit is latched in latch 205 and stored on memory 202 (e.g., on a NAND die). If the system issues a temperature sensing command, the memory can issue a latched temperature bit, thereby reducing the temperature sensing delay to almost zero.

Fig. 3 shows an example of a sample and hold scheme. In the example shown in FIG. 3, a sample and hold (S/H) circuit 302 generates one or more signals to sample the temperature of the non-volatile memory device at regular intervals with a thermometer system 304 and cause the sampled temperature to be stored in a latch 306. Thermometer system 304 includes at least one thermometer, which may also be referred to as a thermal sensor or temperature sensor. In one example, the thermal sensor is internal to the memory die (e.g., an on-die thermal sensor internal to the NAND die).

Unlike conventional systems that read temperature only in response to a command, the scheme shown in fig. 3 periodically measures temperature in the background at some predetermined frequency. Measuring the temperature at regular intervals in the background allows reliable temperature readings to be obtained with minimal delay. As described above, for NAND systems, it is desirable to obtain NAND temperature as early as possible so that on-die firmware can internally set the temperature compensated voltage/current target. Reducing the thermometer delay can greatly improve NAND performance. It would also be beneficial to system performance if we could reduce this delay. While a conventional thermal sensor on a NAND die is used to sense the temperature of that particular NAND die, it is also possible to use a NAND thermometer to sense the system temperature (e.g., by removing a dedicated system temperature sensor and relying on a NAND thermometer, system cost may be reduced). For example, if the NAND memory has a sufficiently accurate temperature sensor, then a system-level temperature sensor (e.g., a dedicated temperature sensor of the system of fig. 2) may be eliminated and the host may obtain a temperature reading from the NAND rather than a dedicated system-level temperature sensor. In such systems, it would be more important to reduce the delay in temperature sensing.

FIG. 4 shows an example of a thermometer system in a non-volatile memory die or device. The thermometer system is one example of the thermometer system 304 of FIG. 3.

The thermometer system shown in fig. 4 comprises a bandgap reference generator (BG)402 for generating a temperature independent voltage reference vbgr. The voltage reference vbgr becomes the input to a digital-to-analog converter (DAC) 404. The DAC may generate a number of different temperature independent reference voltages (vdacs). In the example shown, the DAC generates vdac1 and vdac 2. These voltage references are widely used in NAND chips to generate bias voltages.

In one example, the thermometer is designed with a resistive ladder ADC. In one such example, one of the vdac reference voltages is used to create an analog voltage (reft) at the top of the resistor ladder 414. The voltage between the resistors in the resistor ladder is input to selector 415. For thermometers, an analog signal related to temperature may be used. In one example, in an ideal case, a signal linearly related to temperature is used. In one example, the bandgap reference generator generates an analog voltage vbe that may be used for purposes of an analog signal related to temperature. In one example, Vbe is given by the following equation:

Vbe＝VGO-VT[(γ-α)lnT-ln(EG)]

where α, γ, E, G are temperature-independent parameters. Vbe is therefore inversely proportional to temperature, with a temperature range of-40 ℃ to 130 ℃, which is a typical range for NAND dies.

By applying gain (e.g., with gain amplifier 406) and inversion (e.g., with inverter 408) to Vbe, "termolev" is generated, which scales linearly with temperature. In one example, Vtermolev is given by the following equation:

the thermometer in the illustrated example then employs SAR ADC architecture 409 to convert "termolev" to a temperature bit, which can then be latched after SAR logic 410 completes the conversion. The random offset is eliminated using an auto-zero and chopping technique on the operational amplifier and comparator 412 of the SAR ADC. The auto-zeroing and chopping techniques can greatly improve the accuracy of the thermometer system. After the thermometer system is enabled, it is necessary to wait a period of time for the temperature to be ready. The time delays include, for example, active bandgap settling time, DAC settling time, "termolev" settling time, and thermometer SAR ADC conversion time. In one such example, the delay in temperature readiness is at least 4 to 5 us. It is difficult to further reduce this time delay without sacrificing accuracy or increasing power consumption.

The thermometer system of FIG. 4 is one example of a system that can sample in the background at regular intervals. The sample and hold scheme may be implemented with any thermometer system in which temperature is sensed and stored (e.g., in a latch or other storage element).

FIG. 5 shows an example of a sample and hold (S/H) circuit for a memory thermometer system. In one such example, the circuit 500 is a NAND thermometer sample and hold system (e.g., the S/H circuit 302) that outputs a signal to the memory thermometer system 304.

In the example shown in fig. 5, the sample and hold circuit includes an S/H oscillator 502, a frequency divider 504, and a pulse generator 506. In the example shown, the oscillator 502 receives an Enable (EN) signal and a TRIM signal. The enable signal enables or disables the oscillator according to the asserted logic value. In one example, the oscillator 502 is on (enabled) even in a low power or standby mode. Thus, the oscillator 502 remains on in the background and generates the S/H system clock CLK _ SH. The TRIM signal adjusts the clock frequency (cycle time) of the clock signal CLK _ SH. In one example, CLK _ SH is designed to have an adjustable range of 30us to 60 us. In the example where the thermometer delay is 4 to 5us, one CLK _ SH clock cycle is sufficient to complete the internal operation of the thermometer. In one example, the TRIM signal is based on a value stored in a register.

The system clock CLK SH enters the divider 504 and generates the signal "term SH start" within an adjustable (e.g., programmable or adjustable) period. In one example, the frequency of the term _ SH _ start signal is half of the CLK _ SH signal. The signal "term _ sh _ start" is a sample/hold on signal that triggers the sample _ hold _ on signal to enable the circuitry required for thermal sensing. Other inputs to the divider 504 include "TRIM for tper" that can adjust the trigger frequency of the sample/hold on signal (term _ sh _ start) and an Enable (EN) for enabling the divider.

The sample/hold on signal is input to the pulse generator 506, which pulse generator 506 triggers the termo _ sh _ on signal to turn on the thermometer circuit, as described above. The pulse generator also generates a Tcomp en sh signal to indicate to the latch that the temperature is ready to latch. In addition to the term _ sh _ start signal, other inputs to the pulse generator include the TRIM set, Clk _ term, and Enable (EN) signals. The TRIM setting controls how long the hot sample/hold (term _ sh _ on) signal stays (e.g., asserts a logical value to turn on the thermometer circuit). In one example, when termo _ sh _ on is high, the system may consume more power because more circuit blocks are enabled. In the example shown, the pulse generator also receives the CLK _ term signal, which is the clock on which the temperature sensor depends. In one such example, the term _ sh _ on signal is based on both the TRIM setting (TRIM setting) and the CLK _ term signal. The enable signal enables the pulse generator 506. In one example, the same enable signal enables the oscillator 502, the frequency divider 504, and the pulse generator 506.

Fig. 6 shows a control sequence of the S/H circuit shown in fig. 5. In the example shown, a clock clk _ sh (e.g., generated by the oscillator 502 of fig. 5) triggers a pulse term _ sh _ start. For example, the rising edge of clk _ sh triggers the term _ sh _ start signal. In the example shown, the pulse of the signal termo _ sh _ start is one clock cycle of clk _ sh. However, the pulse of term _ sh _ start may be shorter or longer than one clock cycle of clk _ sh (e.g., 0.75 or 2 clock cycles of clk _ sh). In one example, each pulse of term _ sh _ on is 30 to 60 μ s within a preset period, which can be adjusted based on the fine setting. In the example shown, the term _ sh _ on signal enters a pulse generator (e.g., pulse generator 506 of fig. 5) to generate a thermometer control signal. For example, the control signal "term _ sh _ on" enables the thermometer system (e.g., turns on the thermometer system). The control signal "tcomp _ en _ sh" is used to latch the temperature bit (e.g., after Successive Approximation Register (SAR) analog-to-digital converter (ADC) conversion). In the example shown, there is a delay between the rising edge of the term _ sh _ on and tcomp _ en _ sh pulses. Specifically, there is a "tana" (time analog) delay that represents the time to enable the analog circuitry of the thermometer system (e.g., a bandgap reference generator (BG), digital-to-analog converter (DAC), or other analog circuitry). The delay "t 3 conv" represents the time to convert the sensed temperature from an analog value to a latchable digital value. After a delay to ensure that the temperature is ready to be latched, the tcomp _ en _ sh pulse causes the next temperature reading to be latched (t (n)).

This process continues in each clock cycle so that the temperature reading in the latch is periodically updated in the background. In one example, as the sample and hold system operates in the background (including during standby), the temperature reading is ready when needed. In one example, the temperature is refreshed at some predetermined rate by: the temperature sensor circuit is enabled, the temperature is sensed, and then the temperature is latched. Once the temperature is latched, the thermometer circuit may be disabled to save power. If the system issues a temperature sense command (e.g., by a NAND controller), the NAND need only issue the latched temperature bit. Therefore, the temperature readout delay is almost zero. For NAND array operations, the on-die firmware may directly retrieve the stored temperature bits at the start of the operation without waiting for a delay. Thus, the sample and hold temperature scheme may reduce or eliminate thermometer bottlenecks for NAND performance.

One possible disadvantage of having the thermometer circuit run in the background is the increased standby current (Iccs). In one example, to minimize the effects of standby current, most thermometer dependent circuits are disabled after the temperature sample/hold operation is completed. In one such example, the only circuit that remains enabled is the sample/hold oscillator. The standby Icc for this scheme can be calculated as:

where Icc (active block) represents the active current from the block supporting thermometer operation, Ttermo _ on represents the enable time for thermometer settling and latching, and Tsh _ cyc represents the cycle time of the sample/hold operation. Icc (osc _ sh) is the current of the sample/hold oscillator.

Some circuits need to be enabled for thermometer operation. In one example, the active bandgap, iref generator, DAC and thermometer are enabled to sense temperature. In one such example, an active vcc regulator (avdc) and a state machine oscillator that clock the thermometer SAR ADC are also enabled to sample the temperature. In one such example, the total ICC from the blocks when activated is about 1 mA.

The sample/hold refresh rate (rate at which temperature is sensed) may be determined based on the temperature drift rate of the NAND system. In NAND systems, temperature drift is typically a slow event (e.g., the temperature drift of a typical NAND system is on the order of hundreds of milliseconds per degree of temperature change). The thermometer circuit only needs to be activated during the refresh window. In one example, the thermometer is enabled once every X milliseconds, where X is a value based on one or more factors (including register settings). In one such example, when the thermometer is enabled, it remains on for some predetermined period of time to enable sensing and latching of the temperature. The S/H oscillator can be carefully designed to minimize Icc so that the thermometer sample/hold system has very little effect on the overall standby current of the NAND.

Fig. 7 shows an example of a sample and hold oscillator. The oscillator shown in FIG. 7 is one example of an S/H oscillator (e.g., oscillator 502 of FIG. 5) used to generate a clock in the sample and hold scheme of the thermometer system.

From the above standby current impact analysis, the design of the S/H oscillator may be crucial to keep the standby current within an acceptable range. In one example, a thermometer sample and hold system is not required to have a high precision oscillator, but a low power design is desired. The oscillator in fig. 7 is an example of a simple and low power design. In the example shown in fig. 7, a source follower (also referred to as a common drain amplifier) 702 is used to create a lower internal power source vcc _ int. In one such example, the internal voltage is 1/2 to 1/5 times greater than the external voltage VCC. In one such example, the internal voltage is about 1.3V, and VCC is 3 to 5V. In the example shown, the voltage Vref comes from a NAND standby bandgap circuit (e.g., BG 402 of fig. 4) that is enabled at all times (e.g., during operation and standby). In one such example, the voltage Vref is about 1.25V. In one such example, a zero Vt NMOS is used as the source follower, which generates an internal power supply of about 1.3V. The oscillator design shown is based on a ring oscillator architecture. The oscillator shown includes a NAND gate followed by two inverters 706A AND 706B. Other oscillator designs may include more than two inverters. Assuming that at a given turn-on time t0, the enable signal (en) is initially low (logic 0) and the voltage at point 710 is high (logic 1), the initial output of the NAND gate 712 is logic 1 and the voltage at point 708 is low. The output of NAND gate 712 transitions to logic 0 when the enable transitions to logic 1 and remains at logic 1 during operation and standby. Thus, the transition of the enable signal from a logic 0 to a logic 1 causes the outputs at points 708-710 to switch after the gate delay associated with inverters 706A and 706B. When the feedback signal 714 is a logic 0, the output of the NAND gate 712 is a logic 1, and when the feedback signal 714 is a logic 1, the output of the NAND gate 712 is a logic 0. Because the output of the NAND gate 712 depends on the feedback signal 714, the switching of the outputs at points 708 and 710 results in an oscillating output clk _ sh. Trim logic 704 is added to support feedback to close the loop of the ring oscillator. For example, trim logic 704 may cause feedback voltage 714 to be the voltage at point 708 or the voltage at point 710 using, for example, a multiplexer. The select signal of such a multiplexer may be to change the frequency of clk _ sh based on the value stored in one or more register bits. By selecting different feedback points, different clock periods can be selected. The Icc from this oscillator can be calculated as follows:

Icc＝C*V，f

where C is the total capacitance of the ring oscillator, V is the internal Vcc (Vcc _ int), and f is the target frequency of clk _ sh. In one example, the total Icc from the oscillator is about 0.7 uA.

FIG. 8 is a timing diagram showing handshaking of a sample and hold scheme of a NAND thermometer system during chip initialization. During power-up of the chip, the sample and hold circuit (e.g., S/H circuit 302 of FIG. 3) of the thermometer system need not be enabled. During chip initialization, the temperature may be read out by means of firmware (e.g., NAND firmware). The temperature read during initialization (e.g., at time t1) may not be very accurate because no trim has been loaded. In one example, the NAND reads out the on-chip trim during chip initialization and then loads it into the corresponding trim register. The signal "reg _ romfuse _ en" will go high at time t2 after the chip initialization period to indicate that the correct trim has been loaded so that an accurate thermometer sensing operation can be performed. When the thermometer sample-and-hold scheme is in the default mode, "rom _ term _ sh _ en" will go high after "Reg _ romfuse _ en" goes high. In one example, the sample/hold clock system is designed to have one thermometer sample-and-hold event at this time. After a delay (e.g., 50us or so), the term _ sh _ on signal will go high at time t3, which will trigger a more accurate temperature to be sampled and latched at time t 4. Thus, at the completion of chip initialization, the NAND will have the correct temperature latched in the sample/hold temperature latch on the die. The temperature will then be resampled at a predetermined refresh rate. In the example shown, after one refresh cycle, termo _ sh _ on goes high again at time t5 to trigger the next temperature read.

FIG. 9 is a flow chart of an example of a temperature measurement method for a non-volatile memory device. The operations of the method may be performed by hardware, firmware, software, or a combination of hardware, firmware, and/or software. In one implementation, all operations of the method are performed by hardware (e.g., circuitry). For example, these operations may be performed by S/H circuits, latches, and thermometer circuits, as shown in FIGS. 3, 4, 5, and 7.

The method begins at operation 902 by periodically sampling the temperature of a memory device or die at periodic predefined time intervals. For example, a sample and hold system (such as that shown in FIG. 5) may generate pulses such that temperature is sensed at regular intervals. In one example, the periodic time intervals at which the temperature is sensed are independent of any commands that traditionally trigger temperature readings. For example, the circuit senses temperature whether a read, get feature, etc. command is received. The sensing of the temperature is not triggered by a command, but is sampled periodically in the background. Then, at operation 904, the sampled temperature is stored. For example, the sampled temperature is stored in a latch or other storage element so that the temperature may be obtained when the request is received.

Then, at operation 906, the method involves providing the stored temperature in response to receiving the command without resampling the temperature. Providing the temperature may involve, for example, outputting the temperature on a pin of the memory die, storing the temperature in a register, or sending the temperature as an input to internal control circuitry. For example, if the NAND die receives a command from the NAND controller to read a temperature, the NAND die can output the temperature stored in the latch on the I/O pin without obtaining a new temperature reading. For example, a system (e.g., a NAND ASIC controller) can issue a "get feature" command to read out the NAND temperature. The NAND does not need to enable the thermometer after receiving the temperature read command, since the correct temperature is already latched in the thermometer sample/hold latch. Instead, the NAND sends the most recently latched temperature from the sample/hold latch to the system. Thus, the temperature sensing delay is greatly reduced.

In another example, if a command (e.g., a program, read, or erase command) is received to perform an array operation, a latched temperature may be provided on an input of the internal circuitry to generate an appropriate voltage to perform the array operation. As described above, in typical NAND array operation, temperature is used for internal temperature compensation. At the beginning of a read, program, or erase sequence, the NAND controller (e.g., a controller internal to the NAND die) will take the temperature bit from the sample/hold latch and provide it to a set of dedicated latches and use that temperature to complete the entire algorithmic operation. Since the thermometer sample/hold operation is enabled, there may be a thermometer sample/hold event in the middle of the algorithm operation. However, in one such example, the NAND controller will not acquire this new temperature. Even if the temperature bit stored in the latch is updated during a NAND operation, it should not be a problem in general, since the longest NAND array operation need not take a long time (e.g., only a few milliseconds). In such an example, the new temperature stored in the latch will be used in the next operation.

Fig. 10 provides an exemplary depiction of a computing system 1000 (e.g., a smartphone, a tablet, a laptop, a desktop, a server computer, etc.). As observed in fig. 10, the system 1000 may include one or more processors or processing units 1001. Processor(s) 1001 may include one or more Central Processing Units (CPUs), each of which may include, for example, a plurality of general purpose processing cores. The processor(s) 1001 may also or alternatively include one or more Graphics Processing Units (GPUs) or other processing units. Processor(s) 1001 may include memory management logic (e.g., a memory controller) and I/O control logic. The processor(s) 1001 may be similar to the processor 252 of fig. 2 or the same as the processor 252 of fig. 2.

System 1000 also includes memory 1002 (e.g., system memory), non-volatile storage 1004, communication interfaces 1006, and other components 1008, which may also be similar or identical to components of host 250 of fig. 2. Other components may include, for example, a display (e.g., touchscreen, tablet), a power source (e.g., battery or other power source), sensors, power management logic, or other components. Communication interface 1006 may include logic and/or features to support a communication interface. For these examples, communications interfaces 1006 may include one or more of the following: one or more communication interfaces that operate according to various communication protocols or standards to communicate over direct or network communication links or channels. Direct communication may occur via use of a communication protocol or standard described in one or more industry standards (including progeny and variants), such as associated with the PCIe specification. Network communication may occur via use of a communication protocol or standard, such as those described in one or more standards promulgated by the IEEE. For example, one such ethernet standard may include IEEE 802.3. Network communication may also occur according to one or more OpenFlow specifications, such as the OpenFlow switch specification. Other examples of communication interfaces include, for example, a local wired point-to-point link (e.g., USB) interface, a wireless local area network (e.g., WiFi) interface, a wireless point-to-point link (e.g., bluetooth) interface, a global positioning system interface, and/or other interfaces.

The computing system also includes non-volatile storage 1004, which may be a mass storage component of the system. The non-volatile storage 1004 may be similar to or the same as the memory device 200 of FIG. 2 described above. Non-volatile storage 1004 includes one or more non-volatile memory (storage) arrays. The non-volatile storage 1004 may include a Solid State Drive (SSD), dual in-line memory module (DIMM), or other non-volatile storage. The non-volatile memory device 1004 may include a byte or block addressable type of non-volatile memory having a 3-dimensional (3D) cross-point memory structure that includes a chalcogenide phase change material (e.g., chalcogenide glass), hereinafter referred to as a "3D cross-point memory. The non-volatile type of memory may also include other types of byte or block addressable non-volatile memory, such as, but not limited to, multi-threshold level NAND flash memory (e.g., 3D NAND flash memory), NOR flash memory, single or multi-level Phase Change Memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), Magnetoresistive Random Access Memory (MRAM) employing memristor technology, spin transfer torque MRAM (STT-MRAM), or a combination of any of the above. In one example, non-volatile storage 1004 may include mass storage consisting of one or more SSDs. The SSD may be composed of flash memory chips implementing a sample and hold thermometer scheme as described above.

Thermometer sample and hold schemes and implementation techniques are discussed above. In one example, a low power oscillator is enabled in the background to count time. The thermometer is periodically enabled to sample (sense) and latch the temperature. In this way, the temperature is always ready when needed. For example, the NAND controller can acquire temperature at the beginning of array operation to perform temperature compensation. The NAND controller can also take the temperature and send it to the system as soon as a temperature sensing command is received. A near zero thermometer delay can be achieved by this scheme.

An example of a thermometer sample and hold scheme and technique is as follows. In one example, a non-volatile memory device includes: a non-volatile memory array; a thermal sensor for detecting a temperature of the non-volatile memory device; and circuitry to: the method includes sampling a temperature of the non-volatile memory device at regular intervals, storing the sampled temperature, and outputting the stored temperature in response to receiving a command. In one example, the circuit is used to sample and store the temperature at regular intervals, independent of receiving the command. In one example, the circuit is to sample and store a temperature prior to receiving the command and output the stored temperature without resampling the temperature. In one example, the command includes a program, read, erase, read status or get feature command. In one example, a circuit for sampling a temperature includes an oscillator for generating a clock signal, wherein a periodic time interval at which the temperature is to be sampled is based on the clock signal. In one example, the circuit for sampling temperature further comprises: a frequency divider to receive the clock signal and output a signal to turn on the thermometer circuit. In one example, the circuit for sampling temperature further comprises: a pulse generator for receiving the output of the frequency divider and generating a pulse to trigger sampling of the temperature. In one example, the circuit for storing the sampled temperature includes a latch. In one example, the non-volatile memory array comprises a three-dimensional (3D) NAND array and the thermal sensor comprises an on-die thermal sensor on a 3D NAND die. In one example, the periodic time intervals at which the temperature is sampled are based on values stored in one or more registers.

In one example, a three-dimensional (3D) NAND die comprises: a 3D NAND memory array; a thermal sensor to detect a temperature of the 3D NAND die; and circuitry to: the method includes sampling a temperature of the 3D NAND die at regular time intervals, storing the sampled temperature, and outputting the stored temperature in response to receiving a command. In one example, the system includes a processor and a non-volatile memory device according to the above examples.

Embodiments of the invention may include various processes as described above. The processes may be embodied in machine-executable instructions. These instructions may be used to cause a general-purpose or special-purpose processor to perform certain processes. Alternatively, the processes may be performed by specific/custom hardware components that contain hardwired or programmable logic circuits (e.g., FPGAs, PLDs) for performing the processes, or by any combination of programmed computer components and custom hardware components.

Elements of the present invention may also be provided as a machine-readable medium for storing the machine-executable instructions. The machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs, and magneto-optical disks, FLASH memory, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, propagation media or other type of media/machine-readable medium suitable for storing electronic instructions. For example, the present invention may be downloaded as a computer program which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem or network connection).

The flow diagrams illustrated herein provide examples of sequences of various process actions. The flow diagrams may indicate operations performed by software or firmware routines and physical operations. In one example, the flow diagram may show the state of a Finite State Machine (FSM), which may be implemented in hardware, software, or a combination. Although shown in a particular order or sequence, the order of the acts may be modified unless otherwise specified. Thus, the illustrated embodiment should be understood only as an example, the process may be performed in a different order, and some actions may be performed in parallel. Moreover, one or more acts may be omitted in various examples; thus, not all acts may be required in every embodiment. Other flows are also possible.

Within the scope of various operations or functions described herein, they may be described or defined as software code, instructions, configurations, data, or combinations. The content may be directly executable ("object" or "executable" form), source code, or difference code ("delta" or "patch" code). The software content of the embodiments described herein may be provided via an article of manufacture having content stored thereon or via a method of operating a communication interface to transmit data via the communication interface. A machine-readable storage medium may cause a machine to perform the functions or operations described, and includes any mechanism for storing information in a form accessible by a machine (e.g., a computing device, an electronic system, etc.), such as recordable/non-recordable media (e.g., Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism for interfacing with any of a hardwired, wireless, optical, etc. medium to communicate with another device, such as a memory bus interface, a processor bus interface, an internet connection, a disk controller, etc. The communication interface may be configured by providing configuration parameters or sending signals or both to prepare the communication interface to provide data signals describing the software content. The communication interface may be accessed via sending one or more commands or signals to the communication interface.

The various components described herein may be means for performing the operations or functions described. Each component described herein includes software, hardware, or a combination of these items. These components may be implemented as software modules, hardware modules, dedicated hardware (e.g., application specific hardware, Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), etc.), embedded controllers, hardwired circuitry, and so forth.

In addition to those described herein, various modifications may be made to the disclosed embodiments and implementations of the invention without departing from the scope thereof. Accordingly, the illustrations and examples herein should be construed in an illustrative, and not a restrictive, sense. The scope of the invention should be measured solely by reference to the claims that follow.