阅读说明：本技术 薄膜晶体管及其制备方法、阵列基板、显示装置 (Thin film transistor, preparation method thereof, array substrate and display device ) 是由 罗超 关峰 王治 杜建华 吕杨 强朝辉 李超 于 2020-03-27 设计创作，主要内容包括：一种薄膜晶体管,包括：栅极、栅绝缘层、有源层、离子化非晶硅层、源极和漏极；所述栅绝缘层覆盖于所述栅极上；所述有源层设置于所述栅绝缘层远离所述栅极一侧；所述离子化非晶硅层设置于所述有源层远离所述栅极一侧,所述离子化非晶硅层与所述栅绝缘层接触；所述源极和所述漏极设置于所述离子化非晶硅层远离所述栅绝缘层一侧,所述源极和所述漏极通过所述离子化非晶硅层与所述有源层耦接。(A thin film transistor, comprising: the gate electrode, the gate insulating layer, the active layer, the ionized amorphous silicon layer, the source electrode and the drain electrode; the grid insulating layer covers the grid electrode; the active layer is arranged on one side, far away from the grid electrode, of the grid insulating layer; the ionized amorphous silicon layer is arranged on one side, away from the grid electrode, of the active layer and is in contact with the grid insulating layer; the source electrode and the drain electrode are arranged on one side, far away from the gate insulating layer, of the ionized amorphous silicon layer, and the source electrode and the drain electrode are coupled with the active layer through the ionized amorphous silicon layer.)

A thin film transistor, comprising:

a gate electrode;

a gate insulating layer covering the gate electrode;

the active layer is arranged on one side, far away from the grid electrode, of the grid insulating layer;

the ionized amorphous silicon layer is arranged on one side, far away from the grid electrode, of the active layer and is in contact with the grid insulating layer;

and the source electrode and the drain electrode are arranged on one side, far away from the gate insulating layer, of the ionized amorphous silicon layer and are coupled with the active layer through the ionized amorphous silicon layer.

The thin film transistor of claim 1, wherein the gate insulating layer has a density that is less than a density of the active layer.

The thin film transistor according to claim 1 or 2, wherein a material of the gate insulating layer comprises silicon oxide.

The thin film transistor according to claim 1 or 2, wherein the gate insulating layer includes a first gate insulating sublayer and a second gate insulating sublayer that are provided in a stacked arrangement;

the material of the first gate insulating sublayer comprises silicon dioxide; the material of the second gate insulating sublayer comprises silicon nitride;

the first gate insulating sublayer is close to the ionized amorphous silicon layer relative to the second gate insulating sublayer.

The thin film transistor of claim 4, wherein the first gate insulator layer has a thickness ofThe second gate insulating sublayer has a thickness of

The thin film transistor according to any one of claims 1 to 5, wherein the active layer comprises a polysilicon pattern and an amorphous silicon pattern on at least one side of the polysilicon pattern;

at least one of the source electrode and the drain electrode is coupled with the amorphous silicon pattern.

The thin film transistor of claim 6, wherein the amorphous silicon pattern surrounds the polysilicon pattern in a direction parallel to a plane in which the thin film transistor is located, and the source and drain are coupled to the amorphous silicon pattern.

The thin film transistor of claim 7, wherein portions of the amorphous silicon pattern on opposite sides of the polysilicon pattern are equal in width.

The thin film transistor according to claim 7 or 8, wherein a width of a portion of the amorphous silicon pattern on one side of the polysilicon pattern in a direction parallel to a plane in which the thin film transistor is located and a line connecting the source electrode and the drain electrode is 2 μm to 5 μm.

The thin film transistor according to any one of claims 1 to 9, further comprising:

the barrier layer is arranged on one side of the active layer, which is far away from the grid electrode;

the edge of the ionized amorphous silicon layer close to the active layer is lapped on the surface of one side of the barrier layer far away from the grid electrode.

The thin film transistor of claim 10, wherein in a case where the active layer includes a polysilicon pattern and an amorphous silicon pattern, an orthographic projection of the blocking layer on a plane of the thin film transistor covers an orthographic projection of the polysilicon pattern on a plane of the thin film transistor, and an edge of the orthographic projection of the blocking layer on the plane of the thin film transistor coincides with an edge of the orthographic projection of the active layer on the plane of the thin film transistor.

The thin film transistor of any of claims 10 or 11, wherein the barrier layer has a thickness of

The thin film transistor of any one of claims 1 to 12, wherein the ionised amorphous silicon layer comprises an ion doped sub-layer and an amorphous silicon sub-layer;

the ion-doped sublayer is remote from the gate relative to the amorphous silicon sublayer.

The thin film transistor of claim 13, wherein the amorphous silicon sublayer has a thickness ofThe ion-doped sublayer has a thickness of

An array substrate, comprising: the thin film transistor according to any one of claims 1 to 14.

A display device, comprising: the array substrate of claim 15.

A method for preparing a thin film transistor comprises the following steps:

forming a gate electrode of a thin film transistor on a substrate;

forming a gate insulating layer covering the gate on one side of the gate away from the substrate;

forming an active layer on one side of the gate insulating layer far away from the gate electrode;

forming an ionized amorphous silicon layer on one side of the active layer, which is far away from the gate insulating layer, wherein the ionized amorphous silicon layer is in contact with the gate insulating layer;

and forming a source electrode and a drain electrode on one side of the ionized amorphous silicon layer far away from the gate insulating layer, wherein the source electrode and the drain electrode are coupled with the active layer through the ionized amorphous silicon layer.

The manufacturing method according to claim 17, wherein forming the active layer includes:

depositing an amorphous silicon material on one side of the gate insulating layer far away from the gate to form a first amorphous silicon film;

crystallizing the first amorphous silicon film by adopting a localized laser annealing process to form a polycrystalline silicon pattern;

depositing a material to be formed into a barrier layer on the crystallized first amorphous silicon film to form a barrier film;

patterning the blocking film and the crystallized first amorphous silicon film by adopting a first mask plate, removing the blocking film and the crystallized first amorphous silicon film except for the region where the active layer is to be formed, and forming a blocking layer and an amorphous silicon pattern to obtain the active layer comprising the polycrystalline silicon pattern and the amorphous silicon pattern.

The manufacturing method according to claim 17 or 18, wherein forming the gate insulating layer, the ionized amorphous silicon layer, the source electrode, and the drain electrode includes:

depositing a silicon nitride material on one side of the grid electrode, which is far away from the substrate, and forming a second grid insulation sublayer;

depositing a silicon dioxide material on one side of the second gate insulating sublayer, which is far away from the substrate, to form a first gate insulating sublayer, so as to obtain the gate insulating layer comprising the first gate insulating sublayer and the second gate insulating sublayer;

after the active layer is formed, depositing an amorphous silicon material on one side of the active layer, which is far away from the grid electrode, by adopting a vapor deposition process to form a second amorphous silicon film, wherein the second amorphous silicon film is in contact with the first grid insulator layer;

ion doping is carried out on one side, far away from the first gate insulating sublayer, of the second amorphous silicon thin film;

depositing a material to be formed into a source electrode and a drain electrode on one side of the ion-doped second amorphous silicon film, which is far away from the first gate insulating sublayer, so as to form a conductive film;

and patterning the conductive thin film and the ion-doped second amorphous silicon thin film by adopting a second mask plate to form the source electrode, the drain electrode and the ionized amorphous silicon layer.