阅读说明：本技术 像素电路及其驱动方法、显示装置 (Pixel circuit, driving method thereof and display device ) 是由 吴小玲 于 2021-08-04 设计创作，主要内容包括：一种像素电路及其驱动方法以及显示装置,其中像素电路包括数据写入单元,第一控制单元,第一发光控制单元,第二发光控制单元,第二控制单元,存储单元以及驱动单元,所述驱动单元与所述数据写入单元、所述第一控制单元、所述第一发光控制单元、所述第二发光控制单元、所述第二控制单元以及所述存储单元连接。(A pixel circuit comprises a data writing unit, a first control unit, a first light-emitting control unit, a second control unit, a storage unit and a driving unit, wherein the driving unit is connected with the data writing unit, the first control unit, the first light-emitting control unit, the second control unit and the storage unit.)

1. A pixel circuit disposed on a display substrate, comprising:

the data writing unit is accessed to the scanning signal and the data signal and is connected with the first node;

the first control unit is connected with a reference voltage and is connected with the first node;

the first light-emitting control unit is connected with a light-emitting signal and a first power supply voltage;

the second light-emitting control unit is connected with the light-emitting signal and is connected with the second node and the light-emitting unit;

a second control unit connected to the second node;

a storage unit connected to the first node and the second node; and

a driving unit connected to the first light emitting control unit, the first node, and the second node;

after the light-emitting signal outputs the low potential, the scanning signal outputs the high potential to write the data signal into the data writing unit, and before the light-emitting signal returns to the high potential, the scanning signal outputs the low potential to close the data writing unit and then turns on the first light-emitting control unit and the second light-emitting control unit to enable the driving unit to drive the light-emitting unit to emit light.

2. The pixel circuit according to claim 1, wherein the data cell comprises a first transistor, a gate of the first transistor is coupled to the scan signal, a source of the first transistor is coupled to the data signal, and a drain of the first transistor is coupled to the first node.

3. The pixel circuit according to claim 1, wherein the first control unit comprises a second transistor, a gate of the second transistor is connected to the first control signal, a source of the second transistor is connected to the reference voltage, and a drain of the second transistor is connected to the first node.

4. The pixel circuit according to claim 1, wherein the first light emission control unit comprises a third transistor, a source of the third transistor is connected to the first power voltage, a gate of the third transistor is connected to the light emission signal, and a drain of the third transistor is connected to the driving unit.

5. The pixel circuit according to claim 1, wherein the second light emission control unit comprises a fourth transistor, a gate of the fourth transistor is connected to the light emission signal, a drain of the fourth transistor is connected to the light emission unit, and a source of the fourth transistor is connected to the second node.

6. The pixel circuit according to claim 1, wherein the second control unit comprises a fifth transistor, a gate of the fifth transistor is connected to the second control signal, a source of the fifth transistor is connected to the threshold voltage, and a drain of the fifth transistor is connected to the second node.

7. The pixel circuit according to claim 1, wherein the driving unit comprises a driving transistor, a source of the driving transistor is connected to the first light emission control unit, a drain of the driving transistor is connected to the second node, and a gate of the driving transistor is connected to the first node.

8. The pixel circuit according to claim 1, wherein the storage cell comprises a storage capacitor, a first terminal of the storage capacitor is connected to the first node, and a second terminal of the storage capacitor is connected to the second node.

9. A driving method of a pixel circuit, comprising the pixel circuit as claimed in any one of claims 1 to 8, wherein the driving method of the pixel circuit sequentially comprises a reset stage, a threshold detection stage, a data writing stage, a sustain stage and a light emitting stage;

in the reset phase, the light-emitting signal maintains a high level, the second control signal rises to a high level, and the first control signal rises to the high level after the second control signal rises to the high level, wherein the first control unit discharges the first node to the reference voltage based on the first control signal, and the second control unit controls the second node to discharge to the starting voltage based on the second control signal;

in the threshold detection stage, the light-emitting signal and the first control signal are maintained at a high potential, the second control signal is reduced to a low potential, and the second node is charged to a first compensation voltage;

in the data writing phase, the first control signal is lowered to a low potential, the light-emitting signal is subsequently lowered to a low potential, the scanning signal is raised to a high potential after the light-emitting signal is lowered to the low potential, and the data writing unit writes the data signal into the first node based on the scanning signal;

in the maintaining phase, the scanning signal is reduced to a low potential; and

in the light-emitting stage, the light-emitting signal rises to a high potential, and the driving unit drives the light-emitting unit to emit light.

10. A display device comprising a display substrate, a plurality of pixel circuits as claimed in any one of claims 1 to 9 disposed on the display substrate, a scan driving circuit for providing the scan signal, a data driving circuit for providing the data signal, and a clock control circuit for providing the light emitting signal, the first control signal, and the second control signal.

[ technical field ] A method for producing a semiconductor device

The invention relates to the technical field of display, in particular to a pixel circuit, a driving method thereof and a display device.

[ background of the invention ]

In the manufacturing process of the display panel, due to the deviation of the actual manufacturing conditions, the threshold voltages (Vth) of different driving transistors in the panel may be different, which causes the driving currents flowing through different driving transistors to be different, affects the uniformity of the display image, and causes the problem of non-uniform display.

Fig. 1 is a circuit diagram of a pixel circuit of the related art, and fig. 2 is a timing diagram of the pixel circuit of the related art, in which a scan signal Vsel and a data signal Vdata output a high potential at the same time, and the second transistor T2 outputs the data signal Vdata to the first transistor according to the scan signal Vsel, but a light emitting current output from the first transistor T1 to the light emitting unit is inevitably affected by a threshold voltage Vth of the first transistor.

Therefore, it is desirable to provide a pixel circuit, a driving method thereof and a display device, so as to solve the problem of uneven display of the display device caused by the influence of the threshold voltage on the light emitting current output by the driving transistor in the prior art.

[ summary of the invention ]

In order to solve the above problems, the present invention provides a pixel circuit, a driving method thereof and a display device, so as to improve the problem of uneven display on the display device.

To achieve the above object, the present invention provides a pixel circuit disposed on a display substrate, including:

the data writing unit is accessed to the scanning signal and the data signal and is connected with the first node;

the first control unit is connected with a reference voltage and is connected with the first node;

the first light-emitting control unit is connected with a light-emitting signal and is connected with a first power voltage;

the second light-emitting control unit is connected with the light-emitting signal and is connected with the second node and the light-emitting unit;

a second control unit connected to the second node;

a storage unit connected to the first node and the second node; and

a driving unit connected to the first light emitting control unit, the first node, and the second node;

after the light-emitting signal outputs the low potential, the scanning signal outputs the high potential to write the data signal into the data writing unit, and before the light-emitting signal returns to the high potential, the scanning signal outputs the low potential to close the data writing unit and then turns on the first light-emitting control unit and the second light-emitting control unit to enable the driving unit to drive the light-emitting unit to emit light.

In one embodiment of the present invention, the data unit includes a first transistor, a gate of the first transistor is connected to the scan signal, a source of the first transistor is connected to the data signal, and a drain of the first transistor is connected to the first node.

In an embodiment of the invention, the first control unit includes a second transistor, a gate of the second transistor is connected to the first control signal, a source of the second transistor is connected to the reference voltage, and a drain of the second transistor is connected to the first node.

In an embodiment of the invention, the first light emitting control unit includes a third transistor, a source of the third transistor is connected to the first power voltage, a gate of the third transistor is connected to the light emitting signal, and a drain of the third transistor is connected to the driving unit.

In an embodiment of the invention, the second light-emitting control unit includes a fourth transistor, a gate of the fourth transistor is connected to the light-emitting signal, a drain of the fourth transistor is connected to the light-emitting unit, and a source of the fourth transistor is connected to the second node.

In an embodiment of the invention, the second control unit includes a fifth transistor, a gate of the fifth transistor is connected to the second control signal, a source of the fifth transistor is connected to the threshold voltage, and a drain of the fifth transistor is connected to the second node.

In an embodiment of the invention, the driving unit includes a driving transistor, a source of the driving transistor is connected to the first light-emitting control unit, a drain of the driving transistor is connected to the second node, and a gate of the driving transistor is connected to the first node.

In one embodiment of the present invention, the storage unit includes a storage capacitor, a first end of the storage capacitor is connected to the first node, and a second end of the storage capacitor is connected to the second node.

In order to achieve the above object, the present invention further provides a driving method of a pixel circuit, including the above pixel circuit, the driving method includes a reset phase, a threshold detection phase, a data writing phase, a sustain phase and a light emitting phase;

in the reset phase, the light-emitting signal maintains a high level, the second control signal rises to a high level, and the first control signal rises to the high level after the second control signal rises to the high level, wherein the first control unit discharges the first node to the reference voltage based on the first control signal, and the second control unit controls the second node to discharge to the starting voltage based on the second control signal;

in the threshold detection stage, the light-emitting signal and the first control signal are maintained at a high potential, the second control signal is reduced to a low potential, and the second node is charged to a first compensation voltage;

in the data writing phase, the first control signal is lowered to a low potential, the light-emitting signal is subsequently lowered to a low potential, the scanning signal is raised to a high potential after the light-emitting signal is lowered to the low potential, and the data writing unit writes the data signal into the first node based on the scanning signal;

in the maintaining phase, the scanning signal is reduced to a low potential; and

in the light-emitting stage, the light-emitting signal rises to a high potential, and the driving unit drives the light-emitting unit to emit light.

In order to achieve the above object, the present invention further provides a display device, which includes a plurality of pixel circuits as described above, a scan driving circuit, a data driving circuit and a clock control circuit, wherein the scan driving circuit is configured to provide the scan signal, the data driving circuit is configured to provide the data signal, and the clock control circuit is configured to provide the light emitting signal, the first control signal and the second control signal.

The pixel circuit, the driving method thereof and the display device disclosed by the invention enable the second node to be charged to the first compensation voltage through the threshold detection stage, and the influence of the threshold voltage of the driving transistor on the pixel circuit is reduced. The scanning signal is reduced to a low potential before the light-emitting unit emits light through the maintaining stage before the light-emitting stage, so that the influence of the scanning signal on the driving transistor is reduced, and the display effect is improved.

[ description of the drawings ]

FIG. 1 is a circuit schematic of a prior art pixel circuit;

FIG. 2 is a timing diagram of a prior art pixel circuit;

FIG. 3 is a block diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 4 is a block diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 5 is a block diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 6 is a block diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 7 is a block diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 8 is a block diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 9 is a block diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 10 is a block diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 11 is a circuit diagram of one embodiment of a pixel circuit of the present invention;

FIG. 12 is an equivalent circuit diagram of one embodiment of a pixel circuit of the present invention;

FIG. 13 is a flow chart of a pixel circuit driving method according to the present invention;

FIG. 14 is a timing diagram illustrating a driving method of a pixel circuit according to the present invention;

FIG. 15 is another timing diagram illustrating a driving method of a pixel circuit according to the present invention;

fig. 16 is a schematic cross-sectional view of a display device of the present invention.

[ detailed description ] embodiments

The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention.

In the drawings, elements having similar structures are denoted by the same reference numerals.

Referring to fig. 3, fig. 3 is a block diagram of a pixel circuit according to an embodiment of the invention. The pixel circuit PXL provided by the present invention is disposed on a display substrate, and includes a data writing unit 10, a first control unit 20, a first light emission control unit 30, a second light emission control unit 40, a second control unit 50, a storage unit 60, a driving unit 70, and a light emission unit L1. The data writing unit 10 receives the scan signal Sc and the data signal Vdata, and is connected to the first node P1. The first control unit 20 is connected to a reference voltage Vref and is connected to the first node P1. The first light emission control unit 30 receives the light emission signal EM and the first power voltage VDD. The second emission control unit 40 is connected to the emission signal EM and is connected to the second node P2 and the emission unit L1. One end of the light-emitting unit L1 is connected to the second power supply voltage VSS, and the other end is connected to the second light-emission control unit 40. The second control unit 50 is connected to the second node P2. The memory cell 60 is connected to the first node P1 and the second node P2. The driving unit 70 is connected with the first light emitting control unit 30, the first node P1, and the second node P2. Specifically, the driving unit 70 is connected to the data writing unit 10, the first control unit 20, and the storage unit 60 through the first node P1. The second node P2 is connected to the second lighting control unit 40 and the second control unit 50.

The driving unit 70 is isolated by the data writing unit 10, the first control unit 20, the first light emission control unit 30, the second light emission control unit 40, and the second control unit 50, and does not directly receive an external signal. The first node P1 and the second node P2, which are connected to two terminals of the driving unit 70, are also connected to two terminals of the memory cell 60. When the driving unit 70 outputs a driving current for driving the light emitting unit L1, the memory cell 60 stabilizes the potential difference between the first node P1 and the second node P2, and reduces the influence of external elements, pixel circuit arrangement positions, array wirings, and the like on the driving current for driving the light emitting unit L1. Referring to fig. 14, after the emission signal EM outputs a low potential, the scan signal Sc outputs a high potential to write the Data signal Data into the Data writing unit 10, and before the emission signal EM returns to the high potential, the scan signal Sc outputs a low potential to turn off the Data writing unit 10, and then the first emission control unit 30 and the second emission control unit 40 are turned on to make the driving unit DTFT drive the emission unit L1 to emit light. That is, the driving unit 70 maintains a stable on state by the potential difference between the first node P1 and the second node P2 stabilized by the memory cell 60 and provides the output driving current to the light emitting cell L1. When the driving unit DTFT is isolated by the data writing unit 10, the first control unit 20, the first light emission control unit 30, the second light emission control unit 40, and the second control unit 50, the scan signal Sc is already pulled to a low potential, which alleviates the influence of the parasitic capacitance of the data writing unit 10 and the parasitic capacitance of the light emitting unit L1 on the potential of the first node P1.

Specifically, the data writing unit 10 is turned ON (ON) based ON the control of the potential value of the scan signal Sc, and writes the data signal Vdata into the first node P1. Referring to fig. 4, fig. 4 is a block diagram of a pixel circuit according to an embodiment of the invention, in which the data unit 10 is composed of a first transistor T1, a gate of the first transistor T1 is connected to the scan signal Sc, a source of the first transistor T1 is connected to the data signal Vdata, and a drain of the first transistor T1 is connected to the first node P1. When the scan signal Sc is higher than the turn-on potential of the first transistor T1, the first node P1 is charged to the potential of the data signal Vdata, and when the scan signal Sc is lower than the turn-on potential of the first transistor T1, the data unit 10 turns off the charging of the first node P1.

Specifically, the first control unit 20 is turned ON (ON) based ON the control of the potential value of the first control signal Rst1, and switches the reference voltage Vref in to the first node P1. Referring to fig. 5, fig. 5 is a block diagram of a pixel circuit according to an embodiment of the invention, wherein the first control unit 20 is composed of a second transistor T2, a gate of the second transistor T2 is connected to the first control signal Rst1, a source of the second transistor T2 is connected to the reference voltage Vref, and a drain of the second transistor T2 is connected to the first node P1. When the potential of the first control signal Rst1 is higher than the turn-on potential of the second transistor T2, the first node P1 is discharged to be equal to the reference voltage Vref, and when the potential of the first control signal Rst1 is lower than the turn-on potential of the second transistor T2, the discharge of the first node P1 by the first control unit 20 is turned off. In the present embodiment, the reference voltage Vref is a constant voltage potential.

Specifically, the first light emission control unit 30 determines whether to output the first power supply voltage VDD to the driving unit 70 based on the potential value of the light emission signal EM. Referring to fig. 6, fig. 6 is a block diagram illustrating a pixel circuit according to an embodiment of the invention. The first light emitting control unit 30 is composed of a third transistor T3, a source of the third transistor T3 is connected to the first power voltage VDD, a gate of the third transistor T3 is connected to the light emitting signal EM, a drain of the third transistor T3 is connected to the driving unit 70, and when a potential value of the light emitting signal EM is higher than an on potential of the third transistor T3, the first power voltage VDD is connected to the driving unit 70 through the third transistor T3.

Specifically, the second emission control unit 40 determines whether to connect the emission current output from the driving unit 70 to the emission unit L1 based on the potential value of the emission signal EM. Referring to fig. 7, fig. 7 is a block diagram illustrating a pixel circuit according to an embodiment of the invention. The second emission control unit 40 is formed by a fourth transistor T4, a gate of the fourth transistor T4 is connected to the emission signal EM, a drain of the fourth transistor T4 is connected to the emission unit L1, a source of the fourth transistor T4 is connected to the second node P2, and when a potential value of the emission signal EM is higher than an on potential of the fourth transistor T4, the fourth transistor T4 is turned on so that an emission current of the driving unit 70 flows through the second emission control unit 40 and flows to the emission unit L1.

The light emitting unit L1 is connected to the second light emission control unit 40, and when a driving current for driving the light emitting unit L1 flows through the second light emission control unit 40 and the light emitting unit L1, the light emitting unit L1 emits light according to the driving current.

Specifically, the second control unit 50 controls the potential of the second node P2 to decrease to the threshold voltage Vini according to the potential value of the second control signal Rst 2. Referring to fig. 8, fig. 8 is a block diagram illustrating a pixel circuit according to an embodiment of the invention. In the embodiment of fig. 8, the second control unit 50 is composed of a fifth transistor T5, a gate of the fifth transistor T5 is connected to the second control signal Rst2, a source of the fifth transistor T5 is connected to the voltage Vini, and a drain of the fifth transistor T5 is connected to the second node P2. When the potential value of the second control signal Rst2 is higher than the turn-on voltage of the fifth transistor T5, the second node P2 continues to discharge toward the voltage Vini until the second node P2 is equal to the voltage Vini, and when the potential value of the second control signal Rst2 is lower than the turn-on voltage of the fifth transistor T5, the second node P2 stops discharging toward the voltage Vini.

Specifically, the memory cell 60 stabilizes the potentials of the first node P1 and the second node P2. Referring to fig. 9, fig. 9 is a block diagram of a pixel circuit according to an embodiment of the present invention, wherein the storage unit 60 is composed of a storage capacitor Cs, a first terminal of the storage capacitor Cs is connected to the first node P1, and a second terminal of the storage capacitor Cs is connected to the second node P2.

Specifically, the driving unit 70 controls the magnitude of the driving current according to the potential difference between the first node P1 and the second node P2. Referring to fig. 10, fig. 10 is a block diagram illustrating a pixel circuit according to an embodiment of the invention. The driving unit 70 is composed of a driving transistor DTFT, a source of the driving transistor DTFT is connected to the first light emission control unit 30, a drain of the driving transistor DTFT is connected to the second node P2, and a gate of the driving transistor DTFT is connected to the first node P1. As the driving current formula of the driving transistor DTFT:the potential difference between the first node P1 and the second node P2 is Vgs of the driving transistor DTFT, and determines the driving current output by the driving transistor DTFT.

Referring to fig. 11, fig. 11 is a circuit diagram of a pixel circuit according to an embodiment of the invention. In the pixel circuit PXL disclosed in fig. 11, the data unit 10, the first control unit 20, the first light-emitting control unit 30, the second light-emitting control unit 40, the second control unit 50, the storage unit 60 and the driving unit 70 are respectively formed by a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a storage capacitor Cs and a driving transistor DTFT.

It should be noted that Vgs of the driving transistor DTFT is also affected by capacitive coupling and feedback (feedback), where feedback is Δ V (Vscan _ H-Vscan _ L) × Cgs/Σ C, which is the sum of equivalent parasitic capacitances associated with the gate of the driving transistor DTFT, including the internal capacitance of the light emitting unit L1. In the pixel circuit PXL of fig. 11, after the first transistor T1 charges the first node P1 according to the scan signal Sc control data signal Vdata, the scan signal Sc does not fall to the low level, so the parasitic capacitance of the first transistor T1 contributes to the equivalent parasitic capacitance sum Σ C. The internal capacitance of the light emitting cell L1 can be isolated by turning off the fourth transistor T4. The parasitic capacitance of the first transistor T1 can be reduced by the scan signal Sc being lowered to a low level. Therefore, the influence of the feed through (feed through) on the gate potential of the driving transistor DTFT can be effectively reduced by the isolation of the first transistor T1 and the fourth transistor T4.

To further clearly illustrate the pixel circuit PXL, please refer to fig. 12, wherein fig. 12 is a schematic diagram illustrating an equivalent circuit of the pixel circuit PXL according to an embodiment of the present invention, in which the equivalent resistance R indicates that the pixel circuit PXL at different positions has different equivalent resistance R from the power input terminal due to different positions from the power input terminal, so that the value of the equivalent second voltage source Vss 'is different, but the storage capacitor Cs maintains the potential difference between the first node P1 and the second node P2, so as to prevent the potential of the second node P2 from being influenced by the variations of the equivalent resistance R and the equivalent second voltage source Vss' and causing the variation of the light emitting current output by the driving transistor DTFT.

Preferably, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the driving transistor DTFT in the pixel circuit PXL are all N-type transistors.

Preferably, the light emitting unit is any one of an Organic Light Emitting Diode (OLED), a submillimeter light emitting diode (Mini-LED), a Micro-light emitting diode (Micro-LED) or a Light Emitting Diode (LED).

In the above description, the embodiments of different circuit architectures of the pixel circuit PXL are described, and the present invention further provides a driving method of the pixel circuit PXL:

referring to fig. 13, fig. 13 is a flowchart illustrating a driving method of a pixel circuit according to an embodiment of the present invention, wherein the driving method of the pixel circuit includes a reset phase I, a threshold detection phase II, a data writing phase III, a sustain phase IV, and an emission phase V. When the pixel circuits PXL continuously operate in a continuous timing, the reset phase I is continuously executed after the light-emitting phase V is finished.

Referring to fig. 14, fig. 14 is a timing diagram illustrating a driving method of a pixel circuit according to the present invention:

in the reset phase I, the first control unit 20 discharges the first node P1 to the reference voltage Vref based on the first control signal Rst1, and the second control unit 50 controls the second node P2 to discharge to the starting voltage Vini based on the second control signal Rst 2.

In the reset phase I, the second control signal Rst2 rises to the high potential to discharge the second node P2 to the threshold voltage Vini, and the emission control signal EM still maintains the high potential to enable the light emitting unit L1 to still connect to VSS. The voltage across the light emitting cell L1 is: Vini-VSS < Voled, where Voled is the activation voltage of the light emitting cell L1, and thus, the light emitting cell L1 is turned off not to emit light. Then, the first control signal Rst1 rises to a high level, discharging the first node P1 to the reference voltage Vref, and therefore, the two terminals of the memory cell 60: the potentials of the first node P1 and the second node P2 are set to: the reference voltage Vref and the starting voltage Vini.

In the threshold detection stage II, the emission signal EM and the first control signal Rst1 are maintained at a high level, the second control signal Rst2 is lowered to a low level, and the first emission control unit 30 continuously inputs the first power voltage VDD to the driving transistor DTFT in response to the control of the emission signal EM. After the second control signal Rst2 is lowered to the low level, the second control unit 50 is turned off, and the potential of the second node P2 is charged from the starting voltage Vini to the first compensation voltage. Specifically, the first control signal Rst1 is maintained at a high level, and at this time, the first control unit 20 continues to charge the first node P1, the first node P1 is maintained at the reference voltage Vref, and the second control signal Rst2 is lowered to a low level, so that the second node P2 is no longer connected to the starting voltage Vini. Wherein the reference voltage Vref and the threshold voltage Vini are set to: vref > Vini and Vref-Vini > Vth, which is the threshold voltage of the driving transistor DTFT. Accordingly, the driving transistor DTFT is turned on at this time, and then, the voltage Vp2 (i.e., Vs) of the second node P2 rises because of the input of the first power voltage VDD until the gate-source potential difference Vgs of the driving transistor DTFT becomes Vref-Vp2 ≦ Vth, at which time the driving transistor DTFT is turned off. Accordingly, the second node P2 is charged and maintains the first compensation voltage Vref-Vth.

At this time, a voltage difference between the first node P1 and the second node P2, i.e., a gate-source potential difference Vgs of the driving transistor DTFT, is Vth, i.e., a voltage difference between both ends of the storage unit 60 is Vth.

It should be noted that, in the threshold detection phase II, since the reference voltage Vref is set as: Vref-Vth-VSS is less than Voled, so light emitting unit L1 will not emit light during the threshold detection phase II.

In the data writing phase III, the first control signal Rst1 falls to the low potential, and the first control unit 20 is turned off. The emission signal EM is then lowered to a low level, and both the first emission control unit 30 and the second emission control unit 40 are turned off. The source, gate and drain of the driving transistor DTFT are isolated, and at this time, the scan signal SC rises to a high potential after the emission signal EM falls to a low potential, and the data writing unit 10 writes the data signal Vdata into the first node P1 based on the scan signal SC.

Before the scan signal Sc is raised to the high potential, the emission signal EM is first lowered to the low potential, so that the second emission control unit 40 is turned off, and the gate potential of the driving transistor DTFT is prevented from being affected by the breakdown of the driving transistor DTFT caused by the light emitting device L1. The scan signal Sc is raised to a high level before the data signal Vdata, i.e. the data unit 10 is turned on early, so as to prevent the data unit 10 from being not turned on and being unable to be read completely due to RC delay of the scan signal Sc.

In a preferred embodiment, when the data unit 10 is the first transistor T1, the time difference between the scan signal Sc being raised to the high level and the data signal Vdata being raised to the high level is the on-time from the first transistor T1 receiving the high level scan signal Sc to overcome the capacitive-resistive load (RC loading) to be fully turned on, so as to prevent the data signal Vdata from being affected by the capacitive-resistive load (RC loading) and being unable to be fully transmitted to the first node P1, and the first node P1 is charged to the same potential as the data signal Vdata in the data writing phase III; meanwhile, since the memory cell 60 maintains the voltage level, the voltage level of the second node P2 is not affected by the data signal Vdata of the first node P1 and is maintained at the first compensation voltage Vref-Vth.

In the sustain phase IV, the first node P1 and the second node P2 are respectively maintained as the data voltage Vdata and the first compensation voltage Vref-Vth through the memory cell 60.

In the sustain phase IV, the scan signal Sc is lowered to the low level, and the data writing unit 10 turns off and stops writing the data signal into the first node P1 based on the scan signal Sc. The data signal Vdata is lowered to the low potential after the scan signal Sc is lowered to the low potential, so that the data signal Vdata can continue to be outputted to the first node P1 through the data unit 10 during the time period when the data unit 10 starts to turn off but is not completely turned off, so as to maintain the potential of the first node P1.

In the light emission period V, the first and second light emission control units 30 and 40 are turned on in response to the control of the light emission signal EM, and a first power voltage VDD is input to the driving transistor DTFT, which is responsive to the electricity of the first node P1And the second light-emitting control unit 40 outputs a driving current to the light-emitting unit L1 to drive the light-emitting unit L1 to emit light. In the light emitting period V, the scan signal Sc, the first control signal Rst1 and the second control signal Rst2 are lowered to low levels, and the potentials of the first node P1 and the second node P2 are the data voltage Vdata and the first compensation voltage Vref-Vth, respectively, according to the driving current formula of the driving transistor DTFT:in which the gate-source potential difference Vgs of the driving transistor DTFT is Vg-Vs Vdata- (Vref-Vth), so that the driving current I is 1/2 uC W/L (Vgs-Vth)²＝(uCW)/(2L)*(Vdata-(Vref-Vth)-Vth)²＝(uCW)/(2L)*(Vdata-Vref+Vth-Vth)²＝(uCW)/(2L)*(Vdata-Vref)². That is, the influence of the threshold voltage Vth on the driving transistor DTFT is canceled by the potential Vref-Vth of the second node, and therefore, the driving current of the driving transistor DTFT is independent of the threshold voltage Vth of the driving transistor DTFT, eliminating the influence of the difference in threshold voltage of the driving transistor DTFT of different pixel circuits PXL, which causes the display luminance of different light emitting cells to be non-uniform.

Referring to fig. 15, fig. 15 is another timing diagram illustrating the driving method of the pixel circuit according to the present invention, wherein in the sustain phase IV, the scan signal Sc is lowered to an overdrive low potential lower than the scan signal Sc, and then returned to the low potential of the scan signal Sc to speed up the turn-off of the data unit 10. The data signal Vdata is lowered to the low potential after the scan signal Sc is lowered to the scan signal Sc overdriving the low potential, so that the data signal Vdata can still be continuously outputted to the first node P1 through the data unit 10 during the time period when the data unit 10 starts to be turned off but is not completely turned off.

Referring to fig. 16, fig. 16 is a schematic cross-sectional view of a display device according to the present invention. The display device 100 includes any one of the pixel circuits PXL, the scan driving circuit GD, the data driving circuit DD and the clock control circuit Tcon, wherein the scan driving circuit GD is configured to provide the scan signal Sc, the data driving circuit DD is configured to provide the data signal Vdata, and the clock control circuit Tcon is configured to provide the emission signal EM, the first control signal Rst1, the second control signal Rst2, the first power voltage VDD, the second power voltage VSS, the reference voltage Vref and the start voltage Vini. The timing operation of the pixel circuit driving method of the present invention, the operations from stage I to stage V, may also be: the first control signal Rst1 and the second control signal Rst2 are global signals and are provided at the beginning of one frame. I.e. phase I and phase II for all pixels are performed at the beginning of a frame. The scan signal Sc, the data signal Vdata, and the emission signal EM are line-by-line driving signals. That is, Vth detection of each pixel in the whole panel is performed first, and then, Vdata is written row by row in the stages III to V.

The display device may be an Organic Light Emitting Diode (OLED) display panel, a submillimeter light emitting diode (Mini-LED) display panel, a Micro light emitting diode (Micro-LED) display panel, or a Light Emitting Diode (LED) display panel.

By the pixel circuit, the driving method thereof and the display device, the influence of the threshold voltage of the driving transistor on the pixel circuit is reduced, and the display effect is improved.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and improvements can be made without departing from the principle of the present invention, and these modifications and improvements should also be considered as the protection scope of the present invention.