阅读说明：本技术 一种阻抗转换比可调的两路功率合成片上变压器 (Two-path power synthesis on-chip transformer with adjustable impedance conversion ratio ) 是由 李智群 李振南 王晓伟 陈伯凡 于 2021-08-09 设计创作，主要内容包括：本发明公开了一种阻抗转换比可调的两路功率合成片上变压器,包括第一初级线圈Lp1、第二初级线圈Lp2、次级线圈Ls、调谐线圈Lt、第一调谐电容Ct1及第二调谐电容Ct2,第一初级线圈Lp1的第一端口作为第一路功率输入的负端,第二端口作为第二路功率输入的正端；第二初级线圈Lp2的第一端口作为第一路功率输入的正端,第二端口作为第二路功率输入的负端；次级线圈Ls的第一端口作为合成功率输出的正端,第二端口作为合成功率输出的负端；调谐线圈Lt的第一端口连接第一调谐电容Ct1的正极,第一调谐电容的负极接地,调谐线圈的第二端口连接第二调谐电容的正极,第二调谐电容的负极接地。本发明的变压器的阻抗转换比可调。(The invention discloses a two-path power synthesis on-chip transformer with adjustable impedance conversion ratio, which comprises a first primary coil Lp1, a second primary coil Lp2, a secondary coil Ls, a tuning coil Lt, a first tuning capacitor Ct1 and a second tuning capacitor Ct2, wherein a first port of the first primary coil Lp1 is used as a negative end of a first path of power input, and a second port is used as a positive end of a second path of power input; a first port of the second primary coil Lp2 is used as a positive end of the first path of power input, and a second port is used as a negative end of the second path of power input; a first port of the secondary coil Ls is used as a positive end of the synthesized power output, and a second port is used as a negative end of the synthesized power output; the first port of the tuning coil Lt is connected to the positive electrode of the first tuning capacitor Ct1, the negative electrode of the first tuning capacitor Ct is grounded, the second port of the tuning coil Lt is connected to the positive electrode of the second tuning capacitor Ct, and the negative electrode of the second tuning capacitor Ct is grounded. The impedance conversion ratio of the transformer is adjustable.)

1. A transformer on two paths of power synthesis chips with adjustable impedance conversion ratio is characterized in that: comprising a first primary coil L_p1A second primary coil L_p2Secondary coil L_sTuning coil L_tA first tuning capacitor C_t1And a second tuning capacitor C_t2(ii) a Wherein:

the first primary coil L_p1The first port IN 1-is used as the negative terminal of the first power input, and the second port IN2+ is used as the positive terminal of the second power input;

the second primary coil L_p2The first port IN1+ is used as the positive terminal of the first power input, and the second port IN 2-is used as the negative terminal of the second power input;

the secondary coil L_sThe first port OUT + of the first power amplifier is used as the positive end of the synthesized power output, and the second port OUT-is used as the negative end of the synthesized power output;

the tuning coil L_tFirst port L of_{t_1}Connecting a first tuning capacitor C_t1The first tuning capacitor C_t1The negative electrode of (2) is grounded;

the tuning coil L_tSecond port L of_{t_2}Connecting a second tuning capacitor C_t2Positive pole of (2), second tuning capacitor C_t2The negative electrode of (2) is grounded.

2. The two-way power combiner on-chip transformer with adjustable impedance conversion ratio of claim 1, wherein: the first tuning capacitor C_t1And a second tuning capacitor C_t2Exactly the same, wherein the first tuning capacitor C_t1Comprising a first capacitor C₀A second capacitor C₁A third capacitor C₂A fourth capacitor C₃And a first NMOS switch transistor NM0, a second NMOS switch transistor NM1, a third NMOS switch transistor NM2 and a fourth NMOS switch transistor NM3, the first capacitor C₀A second capacitor C₁A third capacitor C₂A fourth capacitor C₃Positive electrode of (2)Positive poles P shorted together as first tuning capacitors₁First capacitor C₀The negative electrode of the first NMOS switch tube NM0 is connected to the drain of the first NMOS switch tube NM0, the gate of the first NMOS switch tube NM0 is connected to the control voltage Vb0, and the source of the first NMOS switch tube NM0 is grounded; second capacitor C₁The negative electrode of the second NMOS switch tube NM1 is connected to the drain of the second NMOS switch tube NM1, the gate of the second NMOS switch tube NM1 is connected to the control voltage Vb1, and the source of the second NMOS switch tube NM1 is grounded; third capacitor C₂The negative electrode of the third NMOS switch tube NM2 is connected to the drain of the third NMOS switch tube NM2, the gate of the third NMOS switch tube NM2 is connected to the control voltage Vb2, and the source of the third NMOS switch tube NM2 is grounded; fourth capacitor C₃The negative electrode of the fourth NMOS switch tube NM3 is connected to the drain of the fourth NMOS switch tube NM3, the gate of the fourth NMOS switch tube NM3 is connected to the control voltage Vb3, and the source of the fourth NMOS switch tube NM3 is grounded.

3. The two-way power combiner on-chip transformer with adjustable impedance conversion ratio of claim 2, wherein: the first capacitor C₀A second capacitor C₁A third capacitor C₂A fourth capacitor C₃The size relationship of (A) is as follows: c₃＝2C₂＝4C₁＝8C₀。

4. The two-way power combiner on-chip transformer with adjustable impedance conversion ratio of claim 2, wherein: the first NMOS switch tube NM0, the second NMOS switch tube NM1, the third NMOS switch tube NM2 and the fourth NMOS switch tube NM3 have the same size.

5. The two-way power combiner on-chip transformer with adjustable impedance conversion ratio of claim 1, wherein: the transformer comprises five winding coils, namely a first coil, a second coil, a third coil, a fourth coil and a fifth coil from the center of the transformer from inside to outside, wherein the first coil and the fourth coil are connected in series to form a tuning coil L_tEstablishing a rectangular coordinate system with the center of the transformer as an origin, and tuning a coil L_tSymmetrical along the X-axis, with two ports L_{t_1}And L_{t_2}At a variable voltageLeft side of the device, port L_{t_1}Located above the X-axis, port L_{t_2}Is positioned below the X axis; the second coil is divided into two symmetrical halves along the Y axis, and the left half is the first primary coil L_p1And the right half is a second primary coil L_p2And a first primary coil L_p1And a second primary coil L_p2Is symmetrical along the X axis; wherein, the upper left port is a first primary coil L_p1And the first port IN 1-is used as the negative terminal of the first power input, and the lower left port is the first primary coil L_p1And a second port IN2+ as a positive terminal for the second power input, the upper right port being the second primary winding L_p2And the first port IN1+ is used as the positive end of the first power input, and the lower right port is the second primary coil L_p2And as a negative terminal for the second power input, and a second port IN 2-; the third coil and the fifth coil are connected in parallel to form a secondary coil L_sSecondary winding L_sAnd the two ports OUT + and OUT-are positioned on the right side of the transformer along the X axis, the port OUT + is positioned above the X axis and is used as a positive end of the synthesized power output, and the port OUT-is positioned below the X axis and is used as a negative end of the synthesized power output.

6. The two-way power combiner on-chip transformer with adjustable impedance conversion ratio of claim 1, wherein: the on-chip transformer adopts a metal layer stacking structure of a 22nm CMOS process.

7. The two-way power combiner on-chip transformer with adjustable impedance conversion ratio of claim 6, wherein: the 22nm CMOS process metal layer stacking structure sequentially comprises the following steps from bottom to top: substrate, first layer metal M1, second layer metal M2, third layer metal M3, fourth layer metal M4, fifth layer metal M5, sixth layer metal M6, seventh layer metal M7, eighth layer metal M8 and top layer metal AP.

8. The two-way power combiner on-chip transformer with adjustable impedance conversion ratio of claim 7, wherein: all coils of the transformer are of an octagonal structure, the first coil and the fourth coil are made of top-layer metal AP, the second coil is made of seventh-layer metal M7, and the third coil and the fifth coil are made of eighth-layer metal M8.

Technical Field

The invention relates to a technology of a transformer on two paths of power synthesis chips with adjustable impedance conversion ratio, belonging to the technical field of integrated circuits.

Background

The on-chip transformer is commonly used for a power amplifier module in a radio frequency transceiving system, is a critical part in the design of the power amplifier, can realize impedance conversion, power synthesis and distribution, and has the advantages of small area, high power transmission efficiency, broadband matching characteristic and the like. Besides power amplifiers, on-chip transformers are also commonly used in circuit modules such as broadband amplifiers, low noise amplifiers, voltage-controlled oscillators, etc., which play a crucial role in the field of radio frequency and microwave millimeter wave integrated circuits.

A conventional on-chip transformer consists of a primary coil and a secondary coil, the primary and secondary coils having fixed inductance values and fixed impedance conversion ratios for a given frequency. Although the conventional on-chip transformer can realize impedance conversion, power synthesis or distribution, the impedance conversion ratio is fixed and not adjustable, so that the conventional on-chip transformer is not suitable for application scenarios requiring impedance modulation, for example, the optimal load impedance of the power amplifier varies with the output power level of the power amplifier, and when the power amplifier operates in a power back-off region, the load impedance needs to be modulated to improve the back-off efficiency of the power amplifier.

Disclosure of Invention

The invention aims to provide a two-path power synthesis on-chip transformer with an adjustable impedance conversion ratio, so as to realize the flexible adjustment of the impedance conversion ratio of the transformer according to the circuit design requirement and overcome the defect that the impedance conversion ratio of the traditional on-chip transformer is fixed and cannot be adjusted.

In order to realize the purpose of the invention, the technical solution is as follows:

a transformer with adjustable impedance conversion ratio on two power synthesis chips comprises a first primary coil L_p1A second primary coil L_p2Secondary coil L_sTuning coil L_tA first tuning capacitor C_t1And a second tuning capacitor C_t2(ii) a Wherein:

the first primary coil L_p1The first port IN 1-is used as the negative terminal of the first power input, and the second port IN2+ is used as the positive terminal of the second power input;

the second primary coil L_p2First port IN of1+ is used as the positive end of the first path of power input, and a second port IN 2-is used as the negative end of the second path of power input;

the secondary coil L_sThe first port OUT + of the first power amplifier is used as the positive end of the synthesized power output, and the second port OUT-is used as the negative end of the synthesized power output;

the tuning coil L_tFirst port L of_{t_1}Connecting a first tuning capacitor C_t1The first tuning capacitor C_t1The negative electrode of (2) is grounded;

the tuning coil L_tSecond port L of_{t_2}Connecting a second tuning capacitor C_t2Positive pole of (2), second tuning capacitor C_t2The negative electrode of (2) is grounded.

The first tuning capacitor C_t1And a second tuning capacitor C_t2Exactly the same, wherein the first tuning capacitor C_t1Comprising a first capacitor C₀A second capacitor C₁A third capacitor C₂A fourth capacitor C₃And a first NMOS switch transistor NM0, a second NMOS switch transistor NM1, a third NMOS switch transistor NM2 and a fourth NMOS switch transistor NM3, the first capacitor C₀A second capacitor C₁A third capacitor C₂A fourth capacitor C₃Are shorted together as the positive pole P of the first tuning capacitor₁First capacitor C₀The negative electrode of the first NMOS switch tube NM0 is connected to the drain of the first NMOS switch tube NM0, the gate of the first NMOS switch tube NM0 is connected to the control voltage Vb0, and the source of the first NMOS switch tube NM0 is grounded; second capacitor C₁The negative electrode of the second NMOS switch tube NM1 is connected to the drain of the second NMOS switch tube NM1, the gate of the second NMOS switch tube NM1 is connected to the control voltage Vb1, and the source of the second NMOS switch tube NM1 is grounded; third capacitor C₂The negative electrode of the third NMOS switch tube NM2 is connected to the drain of the third NMOS switch tube NM2, the gate of the third NMOS switch tube NM2 is connected to the control voltage Vb2, and the source of the third NMOS switch tube NM2 is grounded; fourth capacitor C₃The negative electrode of the fourth NMOS switch tube NM3 is connected to the drain of the fourth NMOS switch tube NM3, the gate of the fourth NMOS switch tube NM3 is connected to the control voltage Vb3, and the source of the fourth NMOS switch tube NM3 is grounded.

The first capacitor C₀A second capacitor C₁A third capacitor C₂The fourth electricityContainer C₃The size relationship of (A) is as follows: c₃＝2C₂＝4C₁＝8C₀。

The first NMOS switch tube NM0, the second NMOS switch tube NM1, the third NMOS switch tube NM2 and the fourth NMOS switch tube NM3 have the same size.

The transformer comprises five winding coils, namely a first coil, a second coil, a third coil, a fourth coil and a fifth coil from the center of the transformer from inside to outside, wherein the first coil and the fourth coil are connected in series to form a tuning coil L_tEstablishing a rectangular coordinate system with the center of the transformer as an origin, and tuning a coil L_tSymmetrical along the X-axis, with two ports L_{t_1}And L_{t_2}On the left side of the transformer, port L_{t_1}Located above the X-axis, port L_{t_2}Is positioned below the X axis; the second coil is divided into two symmetrical halves along the Y axis, and the left half is the first primary coil L_p1And the right half is a second primary coil L_p2And a first primary coil L_p1And a second primary coil L_p2Is symmetrical along the X axis; wherein, the upper left port is a first primary coil L_p1And the first port IN 1-is used as the negative terminal of the first power input, and the lower left port is the first primary coil L_p1And a second port IN2+ as a positive terminal for the second power input, the upper right port being the second primary winding L_p2And the first port IN1+ is used as the positive end of the first power input, and the lower right port is the second primary coil L_p2And as a negative terminal for the second power input, and a second port IN 2-; the third coil and the fifth coil are connected in parallel to form a secondary coil L_sSecondary winding L_sAnd the two ports OUT + and OUT-are positioned on the right side of the transformer along the X axis, the port OUT + is positioned above the X axis and is used as a positive end of the synthesized power output, and the port OUT-is positioned below the X axis and is used as a negative end of the synthesized power output.

The on-chip transformer adopts a metal layer stacking structure of a 22nm CMOS process.

The 22nm CMOS process metal layer stacking structure sequentially comprises the following steps from bottom to top: substrate, first layer metal M1, second layer metal M2, third layer metal M3, fourth layer metal M4, fifth layer metal M5, sixth layer metal M6, seventh layer metal M7, eighth layer metal M8 and top layer metal AP.

All coils of the transformer are of an octagonal structure, the first coil and the fourth coil are made of top-layer metal AP, the second coil is made of seventh-layer metal M7, and the third coil and the fifth coil are made of eighth-layer metal M8.

Has the advantages that: compared with the traditional on-chip transformer, the invention has the following remarkable advantages: 1) the invention introduces a tuning coil L_tAnd a tuning capacitor C_t1、C_t2The equivalent inductance value of the secondary coil of the transformer can be flexibly adjusted by adjusting the size of the tuning capacitor, and the working bandwidth of the transformer is expanded; 2) the transformer can flexibly adjust the equivalent inductance value of the secondary coil of the transformer, so that the transformer is more suitable for a power amplifier, the impedance conversion ratio of the transformer can be changed aiming at different working frequency points or different output power levels, the efficiency of the power amplifier is improved, and the transformer has better portability and better effect in practical application; 3) the transformer has the advantages of simple structure, low insertion loss and high power synthesis efficiency.

Drawings

Fig. 1 is a schematic structural diagram of a transformer on a two-way power combining sheet with adjustable impedance conversion ratio in an embodiment of the invention;

FIG. 2 shows a first tuning capacitor C according to an embodiment of the present invention_t1A schematic diagram of a circuit;

FIG. 3 is a schematic diagram of a stacked structure of lower metal layers based on a 22nm CMOS process according to an embodiment of the present invention;

fig. 4 is a simulation result diagram of the variation of the inductance and the impedance transformation ratio of the primary and secondary coils with the tuning capacitance in the embodiment of the present invention.

Detailed Description

In order that the objects and advantages of the invention will be more clearly understood, the invention will now be described in further detail with reference to the following examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only for explaining the technical principle of the present invention, and do not limit the scope of the present invention.

It should be noted that in the description of the present invention, terms of directions or positional relationships indicated by "upper", "lower", "left", "right", "inside", "outside", and the like are based on directions or positional relationships shown in the drawings, which are merely for convenience of description, and do not indicate that the described elements or wirings must have a specific orientation, and thus, cannot be construed as limiting the present invention.

In one embodiment, as shown in fig. 1, a two-way power combiner on-chip transformer with adjustable impedance conversion ratio comprises a first primary winding L_p1A second primary coil L_p2Secondary coil L_sTuning coil L_tA first tuning capacitor C_t1And a second tuning capacitor C_t2(ii) a Wherein:

first primary coil L_p1The first port IN 1-is used as the negative terminal of the first power input, and the second port IN2+ is used as the positive terminal of the second power input;

second primary coil L_p2The first port IN1+ is used as the positive terminal of the first power input, and the second port IN 2-is used as the negative terminal of the second power input;

secondary coil L_sThe first port OUT + of the first power amplifier is used as the positive end of the synthesized power output, and the second port OUT-is used as the negative end of the synthesized power output;

tuning coil L_tFirst port L of_{t_1}Connecting a first tuning capacitor C_t1The first tuning capacitor C_t1The negative electrode of (2) is grounded;

tuning coil L_tSecond port L of_{t_2}Connecting a second tuning capacitor C_t2Positive pole of (2), second tuning capacitor C_t2The negative electrode of (2) is grounded.

First tuning capacitor C_t1And a second tuning capacitor C_t2Exactly the same, wherein the first tuning capacitor C_t1Comprising a first capacitor C₀A second capacitor C₁A third capacitor C₂The first stepFour capacitors C₃A first NMOS switch tube NM0, a second NMOS switch tube NM1, a third NMOS switch tube NM2, a fourth NMOS switch tube NM3, a first capacitor C₀A second capacitor C₁A third capacitor C₂A fourth capacitor C₃Are shorted together as the positive pole P of the first tuning capacitor₁First capacitor C₀The negative electrode of the first NMOS switch tube NM0 is connected to the drain of the first NMOS switch tube NM0, the gate of the first NMOS switch tube NM0 is connected to the control voltage Vb0, and the source of the first NMOS switch tube NM0 is grounded; second capacitor C₁The negative electrode of the second NMOS switch tube NM1 is connected to the drain of the second NMOS switch tube NM1, the gate of the second NMOS switch tube NM1 is connected to the control voltage Vb1, and the source of the second NMOS switch tube NM1 is grounded; third capacitor C₂The negative electrode of the third NMOS switch tube NM2 is connected to the drain of the third NMOS switch tube NM2, the gate of the third NMOS switch tube NM2 is connected to the control voltage Vb2, and the source of the third NMOS switch tube NM2 is grounded; fourth capacitor C₃The negative electrode of the fourth NMOS switch tube NM3 is connected to the drain of the fourth NMOS switch tube NM3, the gate of the fourth NMOS switch tube NM3 is connected to the control voltage Vb3, and the source of the fourth NMOS switch tube NM3 is grounded. Wherein, C₃＝2C₂＝4C₁＝8C₀The first NMOS switch NM0, the second NMOS switch NM1, the third NMOS switch NM2 and the fourth NMOS switch NM3 have the same size.

In one embodiment, the transformer comprises five winding coils, namely a first coil, a second coil, a third coil, a fourth coil and a fifth coil from the center of the transformer from inside to outside, wherein the first coil and the fourth coil are connected in series to form a tuning coil L_tA rectangular coordinate system is established by taking the center of the transformer as an origin, and a coil L is tuned_tSymmetrical along the X-axis, with two ports L_{t_1}And L_{t_2}On the left side of the transformer, port L_{t_1}Located above the X-axis, port L_{t_2}Is positioned below the X axis; the second coil is divided into two symmetrical halves along the Y axis, and the left half is the first primary coil L_p1And the right half is a second primary coil L_p2And a first primary coil L_p1And a second primary coil L_p2Is symmetrical along the X axis; wherein, the upper left port is a first primary coil L_p1And as the first work, and the first port IN1The negative end of the rate input, the lower left end, is the first primary coil L_p1And a second port IN2+ as a positive terminal for the second power input, the upper right port being the second primary winding L_p2And the first port IN1+ is used as the positive end of the first power input, and the lower right port is the second primary coil L_p2And as a negative terminal for the second power input, and a second port IN 2-; the third coil and the fifth coil are connected in parallel to form a secondary coil L_sSecondary winding L_sAnd the two ports OUT + and OUT-are positioned on the right side of the transformer along the X axis, the port OUT + is positioned above the X axis and is used as a positive end of the synthesized power output, and the port OUT-is positioned below the X axis and is used as a negative end of the synthesized power output.

In one embodiment, the two-way power synthesis on-chip transformer with the adjustable impedance conversion ratio adopts a metal layer stacking structure of a 22nm CMOS process. With reference to fig. 3, the metal layer stacking structure of the 22nm CMOS process sequentially includes: substrate, first layer metal M1, second layer metal M2, third layer metal M3, fourth layer metal M4, fifth layer metal M5, sixth layer metal M6, seventh layer metal M7, eighth layer metal M8 and top layer metal AP.

In one embodiment, referring to fig. 1, the coils are octagonal, the first coil and the fourth coil use the top metal AP, the second coil uses the seventh metal M7, and the third coil and the fifth coil use the eighth metal M8. The seventh layer metal M7, the eighth layer metal M8 and the top layer metal AP are all thick metals, so that the loss of the transformer coil can be reduced, and the Q value is improved.

As a specific example, in one embodiment, the invention is further described. Referring to fig. 1, in one embodiment, the specific dimensions of the transformer are: the line widths of the first coil, the second coil, the third coil, the fourth coil and the fifth coil are all 12 micrometers, the length of the first coil is 360 micrometers, the width of the first coil is 260 micrometers, the distance between the first coil and the second coil is 30 micrometers, and the distance between the second coil and the third coil, the distance between the third coil and the fourth coil, and the distance between the fourth coil and the fifth coil are all 3 micrometers.

Referring to FIG. 2, capacitor C₃＝2C₂＝4C₁＝8C₀The NMOS transistors NM0, NM1, NM2 and NM3 have the same size as 0.8pF, where NM0 has a gate length of 30NM and a gate width of 32 μm.

Referring to FIG. 3, the first layer of metal M1 has a thickness h __M10.0825 μ M, the thickness of the second layer metal M2 is h __M20.0825 μ M, the thickness of the third layer metal M3 is h _ \_M30.0825 μ M, the thickness of the fourth layer metal M4 is h __M40.0825 μ M, thickness of fifth layer metal M5 is h _ \ u_M50.0825 μ M, the thickness of the sixth layer metal M6 is h __M60.0825 μ M, the thickness of the seventh layer metal M7 is h __M70.85 μ M, and the thickness of the eighth layer metal M8 is h \ u_M8Thickness h of top metal AP of 3.5 μm_AP2.8 μm. The distance between the first layer metal M1 and the second layer metal M2 is d₁0.1675 μ M, the distance between the second layer metal M2 and the third layer metal M3 is d₂0.1675 μ M, the distance between the third layer metal M3 and the fourth layer metal M4 is d₃0.1675 μ M, the distance between the fourth layer metal M4 and the fifth layer metal M5 is d₄0.1675 μ M, the distance between the fifth layer metal M5 and the sixth layer metal M6 is d₅0.1675 μ M, the distance between the sixth layer metal M6 and the seventh layer metal M7 is d₆0.6775 μ M, the distance between the seventh layer metal M7 and the eighth layer metal M8 is d₇1.59 um, the distance d between the eighth layer metal M8 and the top layer metal AP₈＝4.275μm。

FIG. 4 is a simulation result of the inductance and the impedance transformation ratio of the primary and secondary coils at the frequency point of 4.8GHz according to the embodiment of the present invention, showing that the tuning capacitance C is the tuning capacitance C_tWhen the inductance of the primary coil is increased from 0.45nH to 0.47nH and is basically kept unchanged, the inductance of the secondary coil is increased from 0.71nH to 1.12nH, and correspondingly, the impedance conversion ratio is increased from 1.59 to 2.39, so that the two-way power synthesis on-chip transformer with the adjustable impedance conversion ratio is realized.

The above embodiments are preferred embodiments of the present invention, but the present invention is not limited thereto, and any other changes, simplifications, substitutions and combinations that do not depart from the spirit and principles of the present invention are intended to be included within the scope of the present invention.