阅读说明：本技术 一种电路并行计算仿真分析方法和系统 (Circuit parallel computing simulation analysis method and system ) 是由 林畅 林俊杰 高路 纪锋 范征 庞辉 刘栋 毛航银 于 2020-06-01 设计创作，主要内容包括：本发明涉及一种电路并行计算仿真分析方法和系统,包括：根据电路拓扑结构中各节点间的连接形式确定电路拓扑结构中的节点集合；基于预设分配原则将各节点集合分配给仿真计算设备的各处理器；利用各处理器对其分配的节点集合对应的等效电路结构进行并行仿真计算。本发明提供的技术方案,将电路节点以集合的形式分配到不同的处理器中,并对多个处理器分配的节点进行并行计算仿真,解决了直流电网仿真速度和规模受限问题,减少了仿真计算时的计算误差,大幅度提高了仿真计算效率。(The invention relates to a simulation analysis method and a system for parallel computation of a circuit, which comprises the following steps: determining a node set in the circuit topological structure according to the connection form among all nodes in the circuit topological structure; distributing each node set to each processor of the simulation computing equipment based on a preset distribution principle; and carrying out parallel simulation calculation on equivalent circuit structures corresponding to the distributed node sets by utilizing each processor. According to the technical scheme provided by the invention, the circuit nodes are distributed to different processors in a set form, and the nodes distributed by a plurality of processors are subjected to parallel computing simulation, so that the problems of limited simulation speed and scale of a direct current network are solved, the computing error in simulation computation is reduced, and the simulation computation efficiency is greatly improved.)

1. A method for circuit parallel computing simulation analysis, the method comprising:

determining a node set in the circuit topological structure according to the connection form among all nodes in the circuit topological structure;

distributing each node set to each processor of the simulation computing equipment based on a preset distribution principle;

and carrying out parallel simulation calculation on equivalent circuit structures corresponding to the distributed node sets by utilizing each processor.

2. The method of claim 1, wherein determining the set of nodes in the circuit topology based on the connection types between the nodes in the circuit topology comprises:

if all branches between two nodes in the circuit topological structure are connected through transmission lines or inductors with inductance parameters larger than preset inductance threshold values, the connection form between the two nodes in the circuit topological structure is soft connection, otherwise, the connection form between the two nodes in the circuit topological structure is hard connection.

3. The method of claim 1, wherein determining the set of nodes in the partitioned circuit topology based on the connection types between the nodes in the circuit topology comprises:

if a connection relation exists between two nodes in the circuit topological structure and the connection form is hard connection, the two nodes are in the same node set;

if any node in the circuit topological structure has no connection relation with other nodes in the circuit topological structure or the connection form is soft connection, the node singly forms a node set.

4. The method of claim 1, wherein the preset allocation rules include a first priority preset allocation rule, a second priority preset allocation rule, and a third priority preset allocation rule;

the first priority preset allocation principle is that the total number of nodes allocated to each processor does not exceed the maximum number of nodes that the processor can process;

the second priority preset distribution principle is that the number of communication branches among the processors is minimum;

the third priority preset distribution principle is that the difference value of the node numbers distributed to the processors is minimum;

the connection branch is a branch between two nodes distributed to different processors, and the connection form between the two nodes is soft connection.

5. The method of claim 1, wherein determining the equivalent circuit structure corresponding to the ith processor-assigned set of nodes comprises:

decoupling equivalence is carried out on each connecting branch connected with the ith processor, and an equivalent structure of each connecting branch connected with the ith processor on the ith processor side is obtained;

connecting the equivalent structure of each contact branch at the ith processor side with a node which is in the node set distributed by the ith processor and has a connection relation with each contact branch to obtain an equivalent circuit structure corresponding to the node set distributed by the ith processor;

wherein i belongs to (1-N), and N is the number of processors of the simulation computing equipment.

6. The method of claim 5, wherein said decoupling equivalents of each of the communication branches connected to the ith processor to obtain an equivalent structure of each of the communication branches connected to the ith processor on the ith processor side comprises:

the method comprises the steps that a connection branch connected with an ith processor is equivalent to an equivalent structure formed by a grounding end and a parallel structure, wherein the parallel structure is formed by connecting equivalent impedance and an equivalent controlled current source in parallel;

if the connecting element of the j-th connection branch connected with the ith processor is an inductor with an inductance parameter larger than a preset inductance threshold value, the equivalent impedance of the j-th connection branch connected with the ith processor in the equivalent structure of the ith processor side

If the connecting element of the j-th connecting branch connected with the ith processor is a transmission line, the equivalent impedance of the j-th connecting branch connected with the ith processor in the equivalent structure of the ith processor side

If the current flows into the j-th connection branch connected with the ith processor from the node which is in the node set distributed by the ith processor and is in the connection relation with the j-th connection branch connected with the ith processor, the current of the equivalent controlled current source at the current time t in the equivalent structure of the i-th processor side of the j-th connection branch connected with the ith processor

If the current flows into the j-th connection branch connected with the ith processor from the node set distributed by the ith processor and the node which is in the connection relation with the j-th connection branch connected with the ith processor, the current of the equivalent controlled current source at the current time t in the equivalent structure of the i-th processor side of the j-th connection branch connected with the ith processor

In the above formula, L_ij,0Is the inductance value, L ', of the inductor element on the j-th interconnection branch connected to the i-th processor'_ij,0Distributed inductance of transmission line on j-th connecting branch connected with i-th processor, C_ij,0For the distributed capacitance of the transmission line on the j-th connecting branch connected with the I-th processor, dt is the parallel simulation calculation step length, I_ij,j'(t-2 τ) when a current flows into the jth connection branch connected to the ith processor from a node which is in the node set allocated to the ith processor and in connection with the jth connection branch connected to the ith processor, the current of the equivalent controlled current source at the time of t- τ in the equivalent structure of the ith processor side, I_ij,k(t-2 τ) when a current flows into a node, which is in the node set allocated to the ith processor and is connected to the jth connection branch of the ith processor, from the jth connection branch of the ith processor, the current, u τ, of the equivalent controlled current source at the time of t τ in the equivalent structure of the ith processor side in the jth connection branch of the ith processor_ij,j'(t- τ) when a current flows into the j-th connection branch connected to the ith processor from the node in the node set allocated to the ith processor and having a connection relationship with the jth connection branch connected to the ith processor, the voltage, u, of the node in the node set allocated to the ith processor and having a connection relationship with the jth connection branch connected to the ith processor at the current time t_ij,k(t- τ) when the current flows into the node, which is in the node set allocated to the ith processor and connected with the jth contact branch of the ith processor, of the jth contact branch connected with the ith processor, the voltage of the node, which is in the node set allocated to the ith processor and connected with the jth contact branch of the ith processor, at the current time t is obtained; tau is the delay time, if the connection element of the j-th communication branch connected with the i-th processor is a transmission line,thenl_ijFor the length of the transmission line of the j-th connection branch to which the i-th processor is connected,if the connection element of the j-th connection branch connected with the ith processor is an inductor with an inductance parameter larger than a preset inductance threshold value, t is dt, j is epsilon (1 to S), and S is the total number of the connection branches connected with the ith processor.

7. The method of claim 1, wherein the number of processors N emulating a computing device satisfies

Wherein A is the total number of nodes contained in the circuit topology structure, and B_maxCeil is a rounding symbol for the maximum number of nodes that each processor of the emulated computing device can handle.

8. The method of claim 1, wherein if there are more nodes in the set of nodes of the circuit topology than a maximum number of nodes that a single processor of the emulated computing device can handle, an error is reported and the operation is exited.

9. The method of claim 1, wherein before performing the parallel simulation calculation using the equivalent circuit structures corresponding to the node sets assigned to each processor, the method further comprises:

renumbering nodes in the node set distributed by the ith processor, generating a matching relation between the nodes in the node set distributed by the ith processor before renumbering and after renumbering, and constructing an information interaction network between an equivalent circuit structure corresponding to the node set distributed by the ith processor and equivalent circuit structures corresponding to the node sets distributed by other N-1 processors;

wherein i belongs to (1-N), and N is the number of processors of the simulation computing equipment.

10. A circuit parallel computing simulation analysis system, the system comprising:

the determining model is used for determining a node set in the circuit topological structure according to the connection form among all nodes in the circuit topological structure;

the distribution module is used for distributing each node set to each processor of the simulation computing equipment based on a preset distribution principle;

and the simulation module is used for performing parallel simulation calculation on the equivalent circuit structures corresponding to the node sets distributed by the processors.

Technical Field

The invention relates to the field of circuit simulation analysis, in particular to a circuit parallel computing simulation analysis method and system.

Background

At present, traditional direct current transmission projects with the highest transmission voltage and the maximum transmission capacity and flexible direct current transmission projects are put into use in China, and the worldwide renewable energy access problem increasingly depends on the use of a multi-terminal flexible direct current power grid and a flexible direct current power grid.

With the rapid development of the direct-current power grid, the transmission capacity and the voltage level are continuously increased, before the direct-current power grid is put into operation, simulation verification needs to be performed on system parameters and a control protection algorithm, the direct-current power grid contains a large number of power electronic devices and nonlinear devices, and a large number of computing resources need to be occupied in the simulation verification process.

According to the existing technical level, the requirement of electromagnetic transient simulation calculation of a large-scale direct-current power grid cannot be met only by virtue of the calculation capability of a single computer.

Disclosure of Invention

Aiming at the defects of the prior art, the invention aims to provide a circuit parallel computing simulation analysis method, which distributes circuit nodes to different processors in a set form and carries out parallel computing simulation on the nodes distributed by a plurality of processors, thereby solving the problems of limited simulation speed and scale of a direct current network, reducing the computing error in the process of simulation computation and greatly improving the simulation computation efficiency.

The purpose of the invention is realized by adopting the following technical scheme:

the invention provides a simulation analysis method for circuit parallel computing, which is improved in that the method comprises the following steps:

determining a node set in the circuit topological structure according to the connection form among all nodes in the circuit topological structure;

distributing each node set to each processor of the simulation computing equipment based on a preset distribution principle;

and carrying out parallel simulation calculation on equivalent circuit structures corresponding to the distributed node sets by utilizing each processor.

Preferably, the determining a set of nodes in the circuit topology according to the connection form between the nodes in the circuit topology comprises:

if all branches between two nodes in the circuit topological structure are connected through transmission lines or inductors with inductance parameters larger than preset inductance threshold values, the connection form between the two nodes in the circuit topological structure is soft connection, otherwise, the connection form between the two nodes in the circuit topological structure is hard connection.

Preferably, the determining a node set in the circuit topology according to a connection form between nodes in the circuit topology includes:

if a connection relation exists between two nodes in the circuit topological structure and the connection form is hard connection, the two nodes are in the same node set;

if any node in the circuit topological structure has no connection relation with other nodes in the circuit topological structure or the connection form is soft connection, the node singly forms a node set.

Preferably, the preset allocation principle includes a first priority preset allocation principle, a second priority preset allocation principle, and a third priority preset allocation principle;

the first priority preset allocation principle is that the total number of nodes allocated to each processor does not exceed the maximum number of nodes that the processor can process;

the second priority preset distribution principle is that the number of communication branches among the processors is minimum;

the third priority preset distribution principle is that the difference value of the node numbers distributed to the processors is minimum;

the connection branch is a branch between two nodes distributed to different processors, and the connection form between the two nodes is soft connection.

Preferably, the process of determining the equivalent circuit structure corresponding to the node set allocated by the ith processor includes:

decoupling equivalence is carried out on each connecting branch connected with the ith processor, and an equivalent structure of each connecting branch connected with the ith processor on the ith processor side is obtained;

connecting the equivalent structure of each contact branch at the ith processor side with a node which is in the node set distributed by the ith processor and has a connection relation with each contact branch to obtain an equivalent circuit structure corresponding to the node set distributed by the ith processor;

wherein i belongs to (1-N), and N is the number of processors of the simulation computing equipment.

Further, the decoupling equivalence is performed on each connection branch connected to the ith processor, and the equivalent structure of each connection branch connected to the ith processor on the ith processor side is obtained, including:

the method comprises the steps that a connection branch connected with an ith processor is equivalent to an equivalent structure formed by a grounding end and a parallel structure, wherein the parallel structure is formed by connecting equivalent impedance and an equivalent controlled current source in parallel;

if the connecting element of the j-th connection branch connected with the ith processor is an inductor with an inductance parameter larger than a preset inductance threshold value, the equivalent impedance of the j-th connection branch connected with the ith processor in the equivalent structure of the ith processor side

If the connecting element of the j-th connecting branch connected with the ith processor is a transmission line, the equivalent impedance of the j-th connecting branch connected with the ith processor in the equivalent structure of the ith processor side

If the current flows into the j-th connection branch connected with the ith processor from the node which is in the node set distributed by the ith processor and is in the connection relation with the j-th connection branch connected with the ith processor, the current of the equivalent controlled current source at the current time t in the equivalent structure of the i-th processor side of the j-th connection branch connected with the ith processor

If the current flows into the j-th connection branch connected with the ith processor from the node set distributed by the ith processor and the node which is in the connection relation with the j-th connection branch connected with the ith processor, the current of the equivalent controlled current source at the current time t in the equivalent structure of the i-th processor side of the j-th connection branch connected with the ith processor

In the above formula, L_ij,0Is the inductance value, L ', of the inductor element on the j-th interconnection branch connected to the i-th processor'_ij,0Distributed inductance of transmission line on j-th connecting branch connected with i-th processor, C_ij,0For the distributed capacitance of the transmission line on the j-th connecting branch connected with the I-th processor, dt is the parallel simulation calculation step length, I_ij,j'(t-2 τ) when a current flows into the jth connection branch connected to the ith processor from a node which is in the node set allocated to the ith processor and in connection with the jth connection branch connected to the ith processor, the current of the equivalent controlled current source at the time of t- τ in the equivalent structure of the ith processor side, I_ij,k(t-2 τ) when the current flows into the node which is in the node set distributed by the ith processor and is connected with the jth connection branch connected with the ith processor from the jth connection branch connected with the ith processor, the jth connection branch connected with the ith processor flows into the ith processor from the jth connection branchCurrent, u, at time t-tau of an equivalent controlled current source in an equivalent structure on the processor side_ij,j'(t- τ) when a current flows into the j-th connection branch connected to the ith processor from the node in the node set allocated to the ith processor and having a connection relationship with the jth connection branch connected to the ith processor, the voltage, u, of the node in the node set allocated to the ith processor and having a connection relationship with the jth connection branch connected to the ith processor at the current time t_ij,k(t- τ) when the current flows into the node, which is in the node set allocated to the ith processor and connected with the jth contact branch of the ith processor, of the jth contact branch connected with the ith processor, the voltage of the node, which is in the node set allocated to the ith processor and connected with the jth contact branch of the ith processor, at the current time t is obtained; tau is the delay time, if the connection element of the j-th communication branch connected to the i-th processor is a transmission line, thenl_ijFor the length of the transmission line of the j-th connection branch to which the i-th processor is connected,if the connection element of the j-th connection branch connected with the ith processor is an inductor with an inductance parameter larger than a preset inductance threshold value, t is dt, j is epsilon (1 to S), and S is the total number of the connection branches connected with the ith processor.

Preferably, the number of processors N of the emulated computing device satisfies

Wherein A is the total number of nodes contained in the circuit topology structure, and B_maxCeil is a rounding symbol for the maximum number of nodes that each processor of the emulated computing device can handle.

Preferably, if the number of nodes in the node set of the circuit topology exceeds the maximum number of nodes that can be processed by a single processor of the emulated computing device, an error is reported and the operation is exited.

Preferably, before performing parallel simulation calculation on the equivalent circuit structures corresponding to the node sets allocated to the processors, the method further includes:

renumbering nodes in the node set distributed by the ith processor, generating a matching relation between the nodes in the node set distributed by the ith processor before renumbering and after renumbering, and constructing an information interaction network between an equivalent circuit structure corresponding to the node set distributed by the ith processor and equivalent circuit structures corresponding to the node sets distributed by other N-1 processors;

wherein i belongs to (1-N), and N is the number of processors of the simulation computing equipment.

The invention provides a circuit parallel computing simulation analysis system, and the improvement is that the system comprises:

the determining model is used for determining a node set in the circuit topological structure according to the connection form among all nodes in the circuit topological structure;

the distribution module is used for distributing each node set to each processor of the simulation computing equipment based on a preset distribution principle;

and the simulation module is used for performing parallel simulation calculation on the equivalent circuit structures corresponding to the node sets distributed by the processors.

Compared with the closest prior art, the invention has the following beneficial effects:

according to the technical scheme provided by the invention, a node set in the circuit topological structure is determined according to the connection form among all nodes in the circuit topological structure; distributing each node set to each processor of the simulation computing equipment based on a preset distribution principle; performing parallel simulation calculation on equivalent circuit structures corresponding to the distributed node sets by using each processor; according to the scheme, the circuit nodes are distributed to different processors in a set mode, parallel computing simulation is carried out on the nodes distributed by the processors, the problems that the simulation speed and the scale of a direct current network are limited are solved, the computing error in simulation computing is reduced, and the simulation computing efficiency is greatly improved.

The technical scheme provided by the invention reduces the manual participation to the maximum extent, is simple to operate and can be flexibly used for simulation platforms under different conditions.

Drawings

FIG. 1 is a flow chart of a method for circuit parallel computation simulation analysis;

FIG. 2 is a diagram of a circuit topology in an embodiment of the present invention;

FIG. 3 is a schematic diagram illustrating a connection manner of nodes in a circuit topology according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a node set to which each node belongs in a circuit topology according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a node set allocation scheme in an embodiment of the present invention;

FIG. 6 is an equivalent structure of a circuit topology in an embodiment of the present invention;

FIG. 7 is a block diagram of a circuit parallel computing simulation analysis system.

Detailed Description

The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention provides a simulation analysis method for parallel computing of a circuit, which comprises the following steps of:

step 101, determining a node set in the circuit topological structure according to the connection form among nodes in the circuit topological structure;

102, distributing each node set to each processor of the simulation computing equipment based on a preset distribution principle;

and 103, carrying out parallel simulation calculation on equivalent circuit structures corresponding to the node sets distributed by the processors.

Specifically, the step 101 includes:

if all branches between two nodes in the circuit topological structure are connected through transmission lines or inductors with inductance parameters larger than preset inductance threshold values, the connection form between the two nodes in the circuit topological structure is soft connection, otherwise, the connection form between the two nodes in the circuit topological structure is hard connection.

Specifically, the step 102 includes:

if a connection relation exists between two nodes in the circuit topological structure and the connection form is hard connection, the two nodes are in the same node set;

if any node in the circuit topological structure has no connection relation with other nodes in the circuit topological structure or the connection form is soft connection, the node singly forms a node set.

Further, the preset allocation principle includes a first priority preset allocation principle, a second priority preset allocation principle, and a third priority preset allocation principle;

the first priority preset allocation principle is that the total number of nodes allocated to each processor does not exceed the maximum number of nodes that the processor can process;

the second priority preset distribution principle is that the number of communication branches among the processors is minimum;

the third priority preset distribution principle is that the difference value of the node numbers distributed to the processors is minimum;

the connection branch is a branch between two nodes distributed to different processors, and the connection form between the two nodes is soft connection.

In the preferred embodiment of the present invention, the difference value between the number of nodes assigned to each processor is the maximum value of the number of nodes assigned to the processor minus the minimum value of the number of nodes assigned to the processor.

Further, the process of determining the equivalent circuit structure corresponding to the node set allocated by the ith processor includes:

decoupling equivalence is carried out on each connecting branch connected with the ith processor, and an equivalent structure of each connecting branch connected with the ith processor on the ith processor side is obtained;

connecting the equivalent structure of each contact branch at the ith processor side with a node which is in the node set distributed by the ith processor and has a connection relation with each contact branch to obtain an equivalent circuit structure corresponding to the node set distributed by the ith processor;

wherein i belongs to (1-N), and N is the number of processors of the simulation computing equipment.

Further, the decoupling equivalence is performed on each connection branch connected to the ith processor, and the equivalent structure of each connection branch connected to the ith processor on the ith processor side is obtained, including:

the method comprises the steps that a connection branch connected with an ith processor is equivalent to an equivalent structure formed by a grounding end and a parallel structure, wherein the parallel structure is formed by connecting equivalent impedance and an equivalent controlled current source in parallel;

if the connecting element of the j-th connection branch connected with the ith processor is an inductor with an inductance parameter larger than a preset inductance threshold value, the equivalent impedance of the j-th connection branch connected with the ith processor in the equivalent structure of the ith processor side

If the connecting element of the j-th connecting branch connected with the ith processor is a transmission line, the equivalent impedance of the j-th connecting branch connected with the ith processor in the equivalent structure of the ith processor side

If the current flows into the j-th connection branch connected with the ith processor from the node which is in the node set distributed by the ith processor and is in the connection relation with the j-th connection branch connected with the ith processor, the j-th connection branch connected with the ith processor flows into the ith connection branchCurrent of equivalent controlled current source in equivalent structure of processor side at present time t

If the current flows into the j-th connection branch connected with the ith processor from the node set distributed by the ith processor and the node which is in the connection relation with the j-th connection branch connected with the ith processor, the current of the equivalent controlled current source at the current time t in the equivalent structure of the i-th processor side of the j-th connection branch connected with the ith processor

In the above formula, L_ij,0Is the inductance value, L ', of the inductor element on the j-th interconnection branch connected to the i-th processor'_ij,0Distributed inductance of transmission line on j-th connecting branch connected with i-th processor, C_ij,0For the distributed capacitance of the transmission line on the j-th connecting branch connected with the I-th processor, dt is the parallel simulation calculation step length, I_ij,j'(t-2 τ) when a current flows into the jth connection branch connected to the ith processor from a node which is in the node set allocated to the ith processor and in connection with the jth connection branch connected to the ith processor, the current of the equivalent controlled current source at the time of t- τ in the equivalent structure of the ith processor side, I_ij,k(t-2 τ) when a current flows into a node, which is in the node set allocated to the ith processor and is connected to the jth connection branch of the ith processor, from the jth connection branch of the ith processor, the current, u τ, of the equivalent controlled current source at the time of t τ in the equivalent structure of the ith processor side in the jth connection branch of the ith processor_ij,j'(t-tau) when the current flows into the j-th connection branch connected with the ith processor from the node which is in the node set distributed by the ith processor and is in the connection relation with the j-th connection branch connected with the ith processor, the current flows into the j-th connection branch connected with the ith processor and is in the node set distributed by the ith processorAnd the voltage u of the node which is connected with the jth connection branch of the ith processor and has the connection relation with the jth connection branch at the current moment t_ij,k(t- τ) when the current flows into the node, which is in the node set allocated to the ith processor and connected with the jth contact branch of the ith processor, of the jth contact branch connected with the ith processor, the voltage of the node, which is in the node set allocated to the ith processor and connected with the jth contact branch of the ith processor, at the current time t is obtained; tau is the delay time, if the connection element of the j-th communication branch connected to the i-th processor is a transmission line, thenl_ijFor the length of the transmission line of the j-th connection branch to which the i-th processor is connected,if the connection element of the j-th connection branch connected with the ith processor is an inductor with an inductance parameter larger than a preset inductance threshold value, t is dt, j is epsilon (1 to S), and S is the total number of the connection branches connected with the ith processor.

Specifically, the number N of processors of the emulated computing device satisfies

Wherein A is the total number of nodes contained in the circuit topology structure, and B_maxCeil is a rounding symbol for the maximum number of nodes that each processor of the emulated computing device can handle.

In a specific embodiment of the present invention, the number of processors N of the emulated computing device satisfies N-ceil (A/B)_max) The purpose of the method is to utilize hardware resources of the processor as much as possible and avoid resource waste.

Specifically, if the number of nodes in the node set of the circuit topology structure exceeds the maximum number of nodes that can be processed by a single processor of the simulation computing device, an error is reported and the operation is exited.

In the preferred embodiment of the present invention, if the number of nodes in the node set of the circuit topology exceeds the maximum number of nodes that can be processed by a single processor of the simulation computing device, an attempt may be made to replace the processor with a larger number of nodes to be processed, and parallel simulation computation may be performed according to the technical scheme provided by the present invention.

Specifically, before performing parallel simulation calculation on the equivalent circuit structures corresponding to the node sets allocated to the processors by using each processor, the method further includes:

renumbering nodes in the node set distributed by the ith processor, generating a matching relation between the nodes in the node set distributed by the ith processor before renumbering and after renumbering, and constructing an information interaction network between an equivalent circuit structure corresponding to the node set distributed by the ith processor and equivalent circuit structures corresponding to the node sets distributed by other N-1 processors;

wherein i belongs to (1-N), and N is the number of processors of the simulation computing equipment.

In the preferred embodiment of the present invention, the significance of renumbering the nodes in the node set allocated to the ith processor is to simplify the simulation calculation of the nodes in the node set allocated to the ith processor, reduce the calculation error of the ith processor, and improve the simulation efficiency of the ith processor.

In the embodiment of the present invention, the topological structure of the circuit in fig. 2 is taken as an example for explanation, and fig. 2 has 8 nodes, and the connection elements and parameters between the nodes are shown in table 1:

TABLE 1

According to the judgment principle of the connection form in the circuit: if all branches between two nodes in the circuit topological structure are connected through a transmission line or an inductor with an inductance parameter larger than a preset inductance threshold value, the connection form between the two nodes in the circuit topological structure is soft connection, otherwise, the connection form between the two nodes in the circuit topological structure is hard connection; the connection form between the node 1 and the nodes 5 and 6 in fig. 2 can be determined as hard connection, and the connection form between the node 5 and the node 6 is determined as hard connection; the connection form between the node No. 2 and the node No. 6 and the node No. 3 is soft connection; the connection form between the No. 3 node and the No. 4 node and the connection form between the No. 5 node and the No. 3 node are soft connection, the connection form between the No. 3 node and the No. 7 node are hard connection, and the connection form between the No. 4 node and the No. 7 node is hard connection;

table 2 shows the connection form of each node in the circuit topology (1 represents hard connection, 2 represents soft connection), the total number of connections between nodes, the total number of nodes, and the number of nodes that can be accommodated by a single processor;

TABLE 2

The connection form between two nodes of the simplified connection of the conducting wire is used for representing hard connection, and the connection form between two nodes of the inductive connection is used for representing soft connection; a simplified diagram of the topology of the circuit from that shown in figure 3;

determining a principle according to a node set of a circuit topological structure: if a connection relation exists between two nodes in the circuit topological structure and the connection form is hard connection, the two nodes are in the same node set; if any node in the circuit topological structure has no connection relation with other nodes in the circuit topological structure or the connection form is soft connection, the node singly forms a node set. The nodes in the topological structure of the circuit can be divided into 4 sets as shown in fig. 4, the node 1, the node 5 and the node 6 are distributed into one node set, the node 2 is separately distributed into one node set, the node 3 and the node 7 are respectively distributed into one node set, and the node 4 and the node 8 are distributed into one node set;

table 3 shows processors to which each node belongs in the point-to-point topology and the number of nodes in each node set;

TABLE 3

The number of nodes can be accommodated by a single processor is 5, the total number of nodes in the circuit topology is 8, and N is ceil (8/5) is 2, so that the number of processors for parallel computation simulation is at least 2, and nodes in a 4-node set need to be allocated to 2 processors; according to the preset distribution principle, 4 distribution schemes shown in the table 4 can be adopted;

TABLE 4

The four allocation schemes all satisfy the first priority preset allocation principle, two allocation schemes shown in table 5 can be selected according to the second priority preset allocation principle, and an allocation scheme shown in table 6 can be selected according to the third priority preset allocation principle:

TABLE 5

TABLE 6

After the scheme distribution is completed, the connection branch is a branch between the node 2 and the node 3 as shown in fig. 5, and the decoupling equivalence is performed on the connection branch to obtain the equivalent structure of the circuit topology structure as shown in fig. 6.

The invention provides a circuit parallel computing simulation analysis system, as shown in fig. 7, the system comprises:

the determining model is used for determining a node set in the circuit topological structure according to the connection form among all nodes in the circuit topological structure;

the distribution module is used for distributing each node set to each processor of the simulation computing equipment based on a preset distribution principle;

and the simulation module is used for performing parallel simulation calculation on the equivalent circuit structures corresponding to the node sets distributed by the processors.

Specifically, the system further comprises a determination model, specifically configured to:

if all branches between two nodes in the circuit topological structure are connected through transmission lines or inductors with inductance parameters larger than preset inductance threshold values, the connection form between the two nodes in the circuit topological structure is soft connection, otherwise, the connection form between the two nodes in the circuit topological structure is hard connection.

Specifically, the determination model is configured to:

if a connection relation exists between two nodes in the circuit topological structure and the connection form is hard connection, the two nodes are in the same node set;

if any node in the circuit topological structure has no connection relation with other nodes in the circuit topological structure or the connection form is soft connection, the node singly forms a node set.

Specifically, the preset allocation principle includes a first priority preset allocation principle, a second priority preset allocation principle, and a third priority preset allocation principle;

the first priority preset allocation principle is that the total number of nodes allocated to each processor does not exceed the maximum number of nodes that the processor can process;

the second priority preset distribution principle is that the number of communication branches among the processors is minimum;

the second priority preset allocation principle is that the difference value of the node numbers allocated to the processors is minimum;

the connection branch is a branch between two nodes distributed to different processors, and the connection form between the two nodes is soft connection.

Specifically, the process of determining the equivalent circuit structure corresponding to the node set allocated to the ith processor includes:

decoupling equivalence is carried out on each connecting branch connected with the ith processor, and an equivalent structure of each connecting branch connected with the ith processor on the ith processor side is obtained;

connecting the equivalent structure of each contact branch at the ith processor side with a node which is in the node set distributed by the ith processor and has a connection relation with each contact branch to obtain an equivalent circuit structure corresponding to the node set distributed by the ith processor;

wherein i belongs to (1-N), and N is the number of processors of the simulation computing equipment.

Further, the decoupling equivalence is performed on each connection branch connected to the ith processor, and the equivalent structure of each connection branch connected to the ith processor on the ith processor side is obtained, including:

the method comprises the steps that a connection branch connected with an ith processor is equivalent to an equivalent structure formed by a grounding end and a parallel structure, wherein the parallel structure is formed by connecting equivalent impedance and an equivalent controlled current source in parallel;

if the connecting element of the j-th connection branch connected with the ith processor is an inductor with an inductance parameter larger than a preset inductance threshold value, the equivalent impedance of the j-th connection branch connected with the ith processor in the equivalent structure of the ith processor side

If the connecting element of the j-th connecting branch connected with the ith processor is a transmission line, the equivalent impedance of the j-th connecting branch connected with the ith processor in the equivalent structure of the ith processor side

If the current flows into the j-th connection branch connected with the ith processor from the node which is in the node set distributed by the ith processor and is in the connection relation with the j-th connection branch connected with the ith processor, the current of the equivalent controlled current source at the current time t in the equivalent structure of the i-th processor side of the j-th connection branch connected with the ith processor

If the current flows into the j-th connection branch connected with the ith processor from the node set distributed by the ith processor and the node which is in the connection relation with the j-th connection branch connected with the ith processor, the current of the equivalent controlled current source at the current time t in the equivalent structure of the i-th processor side of the j-th connection branch connected with the ith processor

In the above formula, L_ij,0Is the inductance value, L ', of the inductor element on the j-th interconnection branch connected to the i-th processor'_ij,0Distributed inductance of transmission line on j-th connecting branch connected with i-th processor, C_ij,0For the distributed capacitance of the transmission line on the j-th connecting branch connected with the I-th processor, dt is the parallel simulation calculation step length, I_ij,j'(t-2 τ) when a current flows into the jth connection branch connected to the ith processor from a node which is in the node set allocated to the ith processor and in connection with the jth connection branch connected to the ith processor, the current of the equivalent controlled current source at the time of t- τ in the equivalent structure of the ith processor side, I_ij,k(t-2 τ) when a current flows into a node, which is in the node set allocated to the ith processor and is connected to the jth connection branch of the ith processor, from the jth connection branch of the ith processor, the current, u τ, of the equivalent controlled current source at the time of t τ in the equivalent structure of the ith processor side in the jth connection branch of the ith processor_ij,j'(t- τ) when a current flows into the j-th connection branch connected to the ith processor from the node in the node set allocated to the ith processor and having a connection relationship with the jth connection branch connected to the ith processor, the voltage, u, of the node in the node set allocated to the ith processor and having a connection relationship with the jth connection branch connected to the ith processor at the current time t_ij,k(t- τ) is the jth connection branch of the ith processor connectionWhen current flows into a node which is in the node set distributed by the ith processor and is in connection with the jth connection branch connected with the ith processor, the voltage of the node which is in the node set distributed by the ith processor and is in connection with the jth connection branch connected with the ith processor at the current time t is measured; tau is the delay time, if the connection element of the j-th communication branch connected to the i-th processor is a transmission line, thenl_ijFor the length of the transmission line of the j-th connection branch to which the i-th processor is connected,if the connection element of the j-th connection branch connected with the ith processor is an inductor with an inductance parameter larger than a preset inductance threshold value, t is dt, j is epsilon (1 to S), and S is the total number of the connection branches connected with the ith processor.

Specifically, the number N of processors of the emulated computing device satisfies

Wherein A is the total number of nodes contained in the circuit topology structure, and B_maxCeil is a rounding symbol for the maximum number of nodes that each processor of the emulated computing device can handle.

Specifically, if the number of nodes in the node set of the circuit topology structure exceeds the maximum number of nodes that can be processed by a single processor of the simulation computing device, an error is reported and the operation is exited.

Specifically, the system further includes a preprocessing module, specifically configured to:

renumbering nodes in the node set distributed by the ith processor, generating a matching relation between the nodes in the node set distributed by the ith processor before renumbering and after renumbering, and constructing an information interaction network between an equivalent circuit structure corresponding to the node set distributed by the ith processor and equivalent circuit structures corresponding to the node sets distributed by other N-1 processors;

wherein i belongs to (1-N), and N is the number of processors of the simulation computing equipment.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.