阅读说明：本技术 半导体器件的制造方法 (Method for manufacturing semiconductor device ) 是由 孟志贤 石艳伟 姚兰 于 2021-09-07 设计创作，主要内容包括：本申请公开了一种半导体器件的制造方法,包括：分别在衬底的高压器件区和低压器件区形成高压器件栅极和低压器件栅极,并在高压器件栅极和低压器件栅极的上方形成氮化物层；在高压器件栅极的两侧的衬底中形成高压器件区的源极和漏极；在高压器件栅极的两侧以及低压器件栅极的两侧形成第一侧墙,并在低压器件栅极的第一侧墙的两侧的衬底中形成低压器件区的源极和漏极；在高压器件栅极的第一侧墙的两侧以及低压器件栅极的第一侧墙的两侧形成第二侧墙,并在高压器件区的源极和漏极的处于高压器件栅极的第二侧墙的两侧的位置处形成掺杂浓度增高的掺杂区域；以及去除形成在高压器件栅极和低压器件栅极的上方的氮化物层。(The application discloses a manufacturing method of a semiconductor device, which comprises the following steps: forming a high-voltage device grid and a low-voltage device grid in a high-voltage device area and a low-voltage device area of the substrate respectively, and forming nitride layers above the high-voltage device grid and the low-voltage device grid; forming a source electrode and a drain electrode of a high-voltage device area in the substrate on two sides of the grid electrode of the high-voltage device; forming first side walls on two sides of a grid electrode of the high-voltage device and two sides of the grid electrode of the low-voltage device, and forming a source electrode and a drain electrode of a low-voltage device area in the substrate on two sides of the first side walls of the grid electrode of the low-voltage device; forming second side walls on two sides of the first side wall of the grid electrode of the high-voltage device and two sides of the first side wall of the grid electrode of the low-voltage device, and forming doping areas with increased doping concentration at positions of the source electrode and the drain electrode of the high-voltage device area, which are positioned on two sides of the second side wall of the grid electrode of the high-voltage device; and removing the nitride layer formed above the high-voltage device grid and the low-voltage device grid.)

1. A method of manufacturing a semiconductor device, comprising:

forming a high-voltage device grid and a low-voltage device grid in a high-voltage device area and a low-voltage device area of a substrate respectively, and forming nitride layers above the high-voltage device grid and the low-voltage device grid;

forming a source electrode and a drain electrode of the high-voltage device area in the substrate on two sides of the high-voltage device grid electrode;

forming first side walls on two sides of the high-voltage device grid and two sides of the low-voltage device grid, and forming a source electrode and a drain electrode of the low-voltage device area in the substrate on two sides of the first side walls of the low-voltage device grid;

forming second side walls on two sides of the first side wall of the grid electrode of the high-voltage device and two sides of the first side wall of the grid electrode of the low-voltage device, and forming doping areas with increased doping concentration at positions of the source electrode and the drain electrode of the high-voltage device area, which are positioned on two sides of the second side wall of the grid electrode of the high-voltage device; and

removing the nitride layer formed over the high-voltage device gate and the low-voltage device gate.

2. The manufacturing method of claim 1, wherein forming the high-voltage device gate and the low-voltage device gate in the high-voltage device region and the low-voltage device region of the substrate, respectively, comprises:

forming a gate oxide layer on the upper surface of the substrate;

forming a gate layer on the gate oxide layer;

patterning the gate layer to form the high-voltage device gate in the high-voltage device region and the low-voltage device gate in the low-voltage device region; and

and forming an oxide layer on the upper surface and the side surface of the high-voltage device grid and the upper surface and the side surface of the low-voltage device grid.

3. The manufacturing method according to claim 2, wherein the thickness of the gate oxide layer formed in the high-voltage device region is greater than the thickness of the gate oxide layer formed in the low-voltage device region.

4. The manufacturing method of claim 1, wherein a source and a drain of the high voltage device region are formed in the substrate on both sides of the high voltage device gate by a high voltage lightly doped source drain implant process.

5. The manufacturing method according to claim 1, wherein a source electrode and a drain electrode of the low-voltage device region are formed in the substrate on two sides of the first side wall of the low-voltage device gate electrode through a low-voltage lightly doped source-drain region implantation process.

6. The manufacturing method of claim 1, wherein forming second sidewalls on both sides of the first sidewall of the high-voltage device gate and both sides of the first sidewall of the low-voltage device gate comprises:

depositing an insulating oxide layer above the high-voltage device grid and the low-voltage device grid; and

and etching the insulating oxide layer by a dry method, and only keeping the insulating oxide layer positioned on two sides of the first side wall of the grid electrode of the high-voltage device and the insulating oxide layer positioned on two sides of the first side wall of the grid electrode of the low-voltage device so as to respectively form a second side wall of the grid electrode of the high-voltage device and a second side wall of the grid electrode of the low-voltage device.

7. The manufacturing method according to claim 1, wherein the nitride layer formed over the high-voltage device gate and the low-voltage device gate is removed simultaneously with a subsequent process for removing the metal silicide blocking layer.

8. The manufacturing method according to claim 1, wherein the manufacturing method further comprises: and forming a shallow groove isolation region between the high-voltage device region and the low-voltage device region.

9. The manufacturing method according to any one of claims 1 to 8, whichThe nitride layer, the first side wall of the high-voltage device grid and the first side wall of the low-voltage device grid are made of Si₃N₄And (4) forming.

10. A three-dimensional memory comprising a semiconductor device manufactured using the manufacturing method according to any one of claims 1 to 9.

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a method of manufacturing a semiconductor device for a peripheral circuit of a three-dimensional memory.

Background

With the continuous development of semiconductor process technology, in the three-dimensional memory process, a symmetric or asymmetric high-voltage double-diffusion drain terminal MOS device is often required to control a high-voltage signal in a peripheral circuit of a memory cell. Meanwhile, in order to increase the I/O speed of the memory, a faster low-voltage device is also required in the peripheral circuit. Therefore, a high voltage device and a low voltage device need to be combined in a chip.

High voltage devices are sensitive to hot carrier effects (HCI effects) to a different degree than low voltage devices. In the conventional process, the effective channel length of the high-voltage device is increased by increasing the width of the side wall, so that the effect of improving the HCI effect of the high-voltage device is achieved.

However, in the conventional process for forming the sidewall spacer, the gate conductor is easily damaged by etching due to the lack of the barrier layer structure above the gate conductor.

Disclosure of Invention

The present application provides a solution that may overcome, at least in part, at least one of the above-mentioned deficiencies in the related art.

In one aspect, the present application provides a method of manufacturing a semiconductor device, including: forming a high-voltage device grid and a low-voltage device grid in a high-voltage device area and a low-voltage device area of a substrate respectively, and forming nitride layers above the high-voltage device grid and the low-voltage device grid; forming a source electrode and a drain electrode of the high-voltage device area in the substrate on two sides of the high-voltage device grid electrode; forming first side walls on two sides of the high-voltage device grid and two sides of the low-voltage device grid, and forming a source electrode and a drain electrode of the low-voltage device area in the substrate on two sides of the first side walls of the low-voltage device grid; forming second side walls on two sides of the first side wall of the grid electrode of the high-voltage device and two sides of the first side wall of the grid electrode of the low-voltage device, and forming doping areas with increased doping concentration at positions of the source electrode and the drain electrode of the high-voltage device area, which are positioned on two sides of the second side wall of the grid electrode of the high-voltage device; and removing the nitride layer formed above the high-voltage device gate and the low-voltage device gate.

In some embodiments, forming the high-voltage device gate and the low-voltage device gate in the high-voltage device region and the low-voltage device region of the substrate, respectively, comprises: forming a gate oxide layer on the upper surface of the substrate; forming a gate layer on the gate oxide layer; patterning the gate layer to form the high-voltage device gate in the high-voltage device region and the low-voltage device gate in the low-voltage device region; and forming an oxide layer on the upper surface and the side surface of the high-voltage device grid and the upper surface and the side surface of the low-voltage device grid.

In some embodiments, the thickness of the gate oxide layer formed in the high-voltage device region is greater than the thickness of the gate oxide layer formed in the low-voltage device region.

In some embodiments, a source and a drain of the high voltage device region are formed in the substrate on both sides of the high voltage device gate by a high voltage lightly doped source drain implant process.

In some embodiments, a source and a drain of the low-voltage device region are formed in the substrate on both sides of the first sidewall of the low-voltage device gate by a low-voltage lightly doped source/drain implantation process.

In some embodiments, forming the second sidewalls at two sides of the first sidewall of the high-voltage device gate and two sides of the first sidewall of the low-voltage device gate includes: depositing an insulating oxide layer above the high-voltage device grid and the low-voltage device grid; and etching the insulating oxide layer by a dry method, and only keeping the insulating oxide layer positioned on two sides of the first side wall of the grid electrode of the high-voltage device and the insulating oxide layer positioned on two sides of the first side wall of the grid electrode of the low-voltage device so as to respectively form a second side wall of the grid electrode of the high-voltage device and a second side wall of the grid electrode of the low-voltage device.

In some embodiments, the nitride layer formed over the high-voltage device gate and the low-voltage device gate is removed at the same time as the metal silicide blocking layer is removed in a subsequent process.

In some embodiments, the method further comprises: and forming a shallow groove isolation region between the high-voltage device region and the low-voltage device region.

In some embodiments, the nitride layer, the first sidewall of the high voltage device gate, and the first sidewall of the low voltage device gate are formed of Si₃N₄And (4) forming.

In another aspect, the present application also provides a three-dimensional memory including a semiconductor device manufactured using the manufacturing method as above.

Unlike the prior art, in the method for manufacturing a semiconductor device according to the embodiment of the present application, after the high-voltage lightly doped source/drain implantation is performed, the nitride layer formed on the gate conductor is not removed, but sidewall structures are formed on both sides of the gate conductor, respectively, with the nitride layer remaining. The remaining nitride layer can be used as an etch stop layer for the gate conductor in a subsequent dry etching process, thereby effectively protecting the gate conductor from damage due to etching. In addition, the nitride layer may also prevent dopant ions from entering the gate conductor during the lightly/heavily doped source/drain implantation process. The remaining nitride layer is removed after the heavily doped high-voltage source drain region implant. Optionally, the remaining nitride layer may be removed during a subsequent process for removing the metal silicide blocking layer, thereby saving a wet removal process.

Drawings

The above and other advantages of embodiments of the present application will become apparent from the detailed description with reference to the following drawings, which are intended to illustrate and not to limit exemplary embodiments of the present application. In the drawings:

FIG. 1A shows a schematic circuit diagram of a memory cell string of a three-dimensional memory device;

fig. 1B shows a schematic structural diagram of a memory cell string of a three-dimensional memory device;

FIG. 2 illustrates a perspective view of a portion of a three-dimensional memory device including a memory cell;

FIG. 3 illustrates an internal structural diagram of a three-dimensional memory device;

fig. 4A to 4G schematically show stages of a method of manufacturing a semiconductor device according to an embodiment of the present application; and

fig. 5 shows a schematic flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. In addition, descriptions of features well known in the art may be omitted for the sake of clarity and conciseness.

Like reference numerals refer to like elements throughout the drawings and detailed description. The figures may not be drawn to scale and the relative sizes, proportions and depictions of the elements in the figures may be exaggerated for clarity, illustration and convenience.

It should be noted that the expressions first, second, etc. in this specification are used only to distinguish one feature from another feature, and do not indicate any limitation on the features. Thus, the first memory transistor discussed below may be referred to as a second memory transistor, and likewise, the second memory transistor may also be referred to as a first memory transistor, without departing from the teachings of the present application.

It will be understood that when an element or layer is referred to herein as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. When an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout the specification. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having," "contains" and/or "containing," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Moreover, when a statement such as "at least one of" appears after a list of listed features, the entirety of the listed features is modified rather than modifying individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Various aspects of the present application will be described in more detail below with reference to the figures.

Fig. 1A shows a schematic circuit diagram of a memory cell string 100 of a three-dimensional memory device, and fig. 1B shows a schematic block diagram of the memory cell string 100 of the three-dimensional memory device. In fig. 1A and 1B, a case where the memory cell string 100 includes 4 memory cells is shown. However, the present application is not limited thereto, and the present application includes a case where the number of memory cells in the memory cell string 100 may be any number, for example, the number of memory cells in the memory cell string 100 may be 8, 16, 32, or 64, and the like.

As shown in fig. 1A, the memory cell string 100 has a first terminal connected to a bit line BL and a second terminal connected to a source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal. For example, the memory cell string 100 may include a first selection transistor Q1, a first memory transistor M1, a second memory transistor M2, a third memory transistor M3, a fourth memory transistor M4, and a second selection transistor Q2. The gate of the first select transistor Q1 is connected to a string select line SSL, and the gate of the second select transistor Q2 is connected to a ground select line GSL. The gates of the first through fourth memory transistors M1 through M4 are connected to corresponding ones of word lines WL1 through WL4, respectively.

As shown in FIG. 1B, the first select transistor Q1 of the memory cell string 100 includes a gate conductor 122 and the second select transistor Q2 of the memory cell string 100 includes a gate conductor 123. Each of the first through fourth memory transistors M1 through M4 includes a gate conductor 121. The stacking direction of the gate conductors 121, 122, and 123 coincides with the stacking direction of the transistors in the memory cell string 100, and adjacent gate conductors are separated by an interlayer insulating layer, thereby forming a gate stack structure.

The memory cell string 100 may include a channel pillar 110. Channel pillar 110 extends through the gate stack structure. In the middle portion of the channel pillar 110, the gate conductor 121 and the channel layer 111 sandwich a tunnel dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114, thereby forming the first to fourth memory transistors M1 to M4. A blocking dielectric layer 114 is sandwiched between the gate conductors 122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

Fig. 2 shows a perspective view of a portion of a three-dimensional memory device including a memory cell 200. For clarity, fig. 2 does not show the various insulating layers in the three-dimensional memory device.

In the three-dimensional memory device shown in fig. 2, the memory cell 200 includes 16 memory cell strings 100 in total of 4 × 4, and each memory cell string 100 includes 4 memory cells, thereby forming a memory array having 64 memory cells in total of 4 × 4 × 4. It should be understood that the present application is not limited thereto, and the memory unit may include any number of memory unit strings, for example, 64 memory units in 8 × 8, 256 memory units in 16 × 16, 1024 memory units in 32 × 32, 4096 memory units in 64 × 64, and so on, and the number of memory units in each memory unit string may also be any number, for example, 8, 16, 32, or 64 memory units, and so on.

In the three-dimensional memory device, the memory cell strings respectively include respective channel pillars 110. A plurality of memory cell strings arranged in rows have common gate conductors 121, 122, and 123. The gate conductors 121, 122, and 123 are stacked in the same direction as the transistors in the memory cell string 100, and adjacent gate conductors are separated by an interlayer insulating layer, thereby forming a gate stack structure 120. For clarity, the interlayer insulating layers are not shown in fig. 2.

The channel pillars 110 penetrate the gate stack structure 120 and are arranged in an array. The first ends of the plurality of channel pillars 110 of the same column are commonly connected to the same bit line (i.e., one of the bit lines BL 1-BL 4), and the second ends are commonly connected to the substrate 101 and form a common source connection via the substrate 100.

The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by the gate line slit 171. The gate lines of the plurality of channel pillars 110 in the same row are commonly connected to the same string selection line (i.e., one of string selection lines SSL1 through SSL 4).

The first to fourth memory transistors M1 to M4 are respectively connected to corresponding word lines. If the gate conductors 121 of the first to fourth memory transistors M1 to M4 are divided into different gate lines by the gate line slit 171, the gate lines of the same layer reach the interconnect layer 132 via respective conductive paths 131 to be interconnected with each other, and then are connected to the same word line (i.e., one of the word lines WL1 to WL 4) via the conductive path 133.

The gate conductor of the second select transistor Q2 may be connected as one and to a ground select line by a conductive path. In some examples, the gate conductor 123 of the second selection transistor Q2 may be divided into different gate lines by the gate line slit 171, and at this time, the gate lines may reach the interconnect layer 132 via respective conductive paths 131 to be interconnected with each other, and then connected to the same ground selection line GSL via the conductive path 133.

Fig. 3 shows an internal structural diagram of a three-dimensional memory device.

As shown in fig. 3, the three-dimensional memory device may include a memory cell 200 and a peripheral circuit 300. The memory cell 200 may have a structure as shown in fig. 2, for example. The peripheral circuit 300 can be used for logic operation and data storage and reading by controlling and detecting the on-off state of each memory cell in the three-dimensional memory device through metal connecting wires. The peripheral circuits are usually composed of a large number of MOS transistors (metal-oxide-semiconductor field effect transistors). For example, in a three-dimensional memory device, a symmetric or asymmetric high-voltage Double-Diffused Drain MOS (Double Diffused MOS) device is generally used to control a high-voltage signal in a peripheral circuit of a memory cell. Meanwhile, in order to increase the I/O speed of the memory, a faster low-voltage device is also required in the peripheral circuit. This requires both low voltage logic devices (such as the intelligent control circuit of the microprocessor MCU) and high voltage devices (analog or high voltage circuits) on one chip.

As an example, only one peripheral high voltage device 310 is shown in fig. 3, which peripheral high voltage device 310 is connected to an interconnect layer 342 by a conductive via 341. It should be appreciated that the present application is not so limited and that the peripheral circuitry may include any number of high voltage devices and low voltage devices.

Fig. 4A to 4G schematically show stages of a method of manufacturing a semiconductor device according to an embodiment of the present application. In particular, fig. 4A to 4G schematically show various stages of a method of manufacturing a semiconductor device 400 having a high-voltage device region 410 and a low-voltage device region 420.

The semiconductor device 400 may include a substrate 101 and a high voltage device region 410 and a low voltage device region 420 formed in the substrate 101. High-voltage device region 410 and low-voltage device region 420 are separated by shallow trench isolation region 430. The high voltage device region 410 and the low voltage device region 420 are both active regions for subsequent processes to form a source, a drain, and a gate in each active region. Shallow trench isolation regions 430 may be used to define active regions or to provide isolation between devices to prevent short circuits between devices.

The processes for forming the shallow trench isolation region 430 may include isolation oxide deposition, mask layer deposition (e.g., nitride), mask layer and oxide layer etching and isolation shallow trench etching, filling the isolation shallow trench with an insulating material (e.g., oxide), planarization, and the like.

The material of the substrate 101 may include bulk silicon (bulk Si), bulk germanium (bulk Ge), silicon-on-insulator (SOI), germanium-on-insulator (GeOI), or other compound semiconductor substrate, such as SiGe, SiC, GaN, GaAs, InP, etc., and combinations thereof. In an exemplary embodiment, the substrate 101 is, for example, a doped monocrystalline silicon substrate. The substrate 101 may be a P-type substrate or an N-type substrate. Taking an N-type MOS transistor as an example, a P-type substrate or an N-type substrate with a P-well may be used. It is to be understood that the present application is not limited thereto, and the doping type and the doping concentration of the semiconductor substrate may be selected according to actual needs.

Fig. 4A is one of schematic structural diagrams of a semiconductor device in a manufacturing process according to an embodiment of the present application. Referring to fig. 4A, the substrate 101 may be a P-type single crystalline silicon substrate, and may have a high voltage device region 410 and a low voltage device region 420 in the substrate 101. A high-voltage deep well region 411 and a high-voltage well region 412 are formed in a region of the high-voltage device region 410 near the upper surface of the substrate 101. A low-voltage P-well region 421 is formed in a region of the low-voltage device region 420 near the upper surface of the substrate 101. The formation of the hvnw 411 may be that N-type doped ions are implanted in the region by an ion implantation process, and the formation of the hvnw 412 and the hvnw 421 may be that P-type doped ions are implanted in the corresponding regions by an ion implantation process.

In the high voltage device region 410, a voltage adjustment region 417 for adjusting a threshold voltage of a high voltage device may also be formed.

The following steps will be described with reference to a P-type single crystal silicon substrate shown in fig. 4A as an example. It is to be understood, however, that the drawings presented herein are for illustration purposes only and are not intended to limit the scope or application of the present application. Those skilled in the art can make corresponding adjustments on other types of substrates to achieve the same effect according to the inventive concept of the present application.

A gate oxide layer 440 is formed on the upper surface of the substrate 101. The gate oxide layer 440 may be a silicon oxide layer formed using a thermal oxidation method or an in-situ steam generation method. In the process of forming the gate oxide layer 440, the thickness of the gate oxide layer 440 located in the high-voltage device region 410 can be made larger than the thickness of the gate oxide layer 440 located in the low-voltage device region 420 by properly using a mask. The reduction of the thickness of the gate oxide layer 440 in the low-voltage device region 420 is beneficial to enable ions to penetrate through the gate oxide layer 440 under the condition of low energy such as ultra-shallow junction formation so as to form a source electrode and a drain electrode in a lightly doped source-drain region, and no channel effect is generated between the source electrode and the drain electrode.

Gate conductors 413 and 423 are formed on the gate oxide layer 440. Specifically, a polysilicon layer is deposited on the gate oxide layer 440, and the polysilicon layer is patterned using photolithography and etching to form the gate conductors 413 and 423. In an exemplary embodiment, the gate conductors 413 and 423 may have a single layer or a multi-layer structure. The material forming the gate conductors 413 and 423 may be, for example, a combination of polysilicon, amorphous silicon, or a metal electrode material, which may be a combination of one or more of TiN, TiAl, Al, TaN, TaC, W, or the like. The substrate regions on both sides of the gate conductors 413 and 423 are regions for forming source and drain regions.

Thin oxide layers may be formed on the upper and side surfaces of the gate conductors 413 and 423, respectively, for buffer isolation of the gate conductors and nitrides formed in subsequent steps. For example, a thin oxide layer 441 may be grown on the surface of gate conductor 413 located in high-voltage device region 410, and a thin oxide layer 442 may be grown on the surface of gate conductor 423 located in low-voltage device region 420.

In an exemplary embodiment, the material used to fill the shallow trench isolation regions 430, the gate oxide layer 440, and the thin oxide layers 441 and 442 may each be SiO₂。

Subsequently, nitride layers 415 and 425 are formed on oxide layers 441 and 442, respectively. For example, atomic layers may be usedNitride layers 415 and 425 are formed by deposition, physical vapor deposition, or chemical vapor deposition. The material of nitride layers 415 and 425 may be, for example, Si₃N₄. Nitride layer 415 may protect gate conductor 413 during a subsequent high-voltage lightly doped source drain implant (HV LDDIMP) process to prevent ion breakdown of thin oxide layer 441 into gate conductor 413.

As shown in fig. 4B, a high-voltage lightly doped source drain implant is performed in the high-voltage device region 410 to form lightly doped source drain regions 419 in the substrate 101 on both sides of the gate conductor 413. The doping ion type in the two lightly doped source drain regions 419 formed on both sides of the gate conductor 413 is opposite to the doping ion type in the hvw region 412. In an exemplary embodiment, the type of dopant ions in the hvw region 412 may be P-type ions, while the type of dopant ions implanted in the two lightly doped source-drain regions 419 by the hvw lightly doped source-drain implantation process may be N-type ions.

In the prior art, after the high-pressure lightly doped source/drain implantation process, phosphoric acid or hydrofluoric acid is used to remove the nitride layers 415 and 425 formed on the oxide layers 441 and 442, and sidewall structures are formed on both sides of the gate conductors 413 and 423. And then, carrying out a low-pressure lightly doped source and drain region implantation process.

Unlike the prior art, in the method of manufacturing the semiconductor device according to the embodiment of the present application, after the high-pressure lightly doped source/drain implantation is performed, the nitride layers 415 and 425 formed on the oxide layers 441 and 442 are not removed, but sidewall structures are formed on both sides of the gate conductors 413 and 423, respectively, with the nitride layers 415 and 425 remaining. Specifically, first side walls 415a and 415b may be formed on both sides of the gate conductor 413, and first side walls 425a and 425b may be formed on both sides of the gate conductor 423, as shown in fig. 4C. The first sidewalls 415a, 415b, 425a, and 425b may be formed of nitride. As an example, the first side walls 415a, 415b, 425a, and 425b may be made of Si₃N₄And (4) forming.

After the sidewall structures are formed, a low-voltage lightly doped source/drain implant (LV LDDIMP) is performed on the low-voltage device region 420 to form lightly doped source/drain regions 429 in the substrate 101 on both sides of the gate conductor 423, as shown in fig. 4D. The type of doping ions in the two lightly doped source/drain regions 429 formed on both sides of the gate conductor 413 is opposite to the type of doping ions in the lowvoltage well region 421. In an exemplary embodiment, the type of dopant ions in the hvw region 421 may be P-type ions, while the type of dopant ions implanted in the two lightly doped source drain regions 429 by the hvw implant process may be N-type ions.

Annealing can be carried out after the high-voltage lightly doped source-drain region injection and the low-voltage lightly doped source-drain region injection so as to repair the damage of silicon surface crystals caused by the injection.

After the low-pressure lightly doped source and drain implants are performed, as shown in fig. 4E, an insulating oxide layer 450 may be formed on the nitride layers 415 and 425 by atomic layer deposition, physical vapor deposition, or chemical vapor deposition. Thereafter, a Dry etch (Dry ET) is performed on insulating oxide layer 450, leaving only the insulating oxide layer on both sides of first sidewall spacers 415a and 415b of gate conductor 413 and first sidewall spacers 425a and 425b of gate conductor 423, as shown in fig. 4F. As such, second sidewalls 451 and 452 may be formed on both sides of the gate conductor 413, and second sidewalls 453 and 454 may be formed on both sides of the gate conductor 423, as shown in fig. 4G.

In the dry etching process, the nitride layers 415 and 425 remaining in the previous process may serve as an etch stop layer, thereby effectively protecting the gate conductors 413 and 423 from being damaged by etching.

As an example, the insulating oxide layer 450 may be made of SiO₂And (4) forming. The second sidewall 451, the first sidewall 415a, and the thin oxide layer 441 may form a deposited ONO structure (silicon oxide-silicon nitride-silicon oxide structure). Similarly, second sidewall 452, first sidewall 415b, and thin oxide 441 may form a deposited ONO structure, second sidewall 453, first sidewall 425a, and thin oxide 442 may form a deposited ONO structure, and second sidewall 454, first sidewall 425b, and thin oxide 442 may form a deposited ONO structure.

The deposited ONO structure formed on both sides of the gate conductors 413 and 423 may effectively block the implant near the gate region. In other words, by forming and depositing the ONO structure on both sides of the gate conductors 413 and 423, the channel length, especially the channel length of the high-voltage device region, can be effectively increased, thereby preventing the phenomenon that the channel is too short and even the source and drain are connected due to the fact that the source and drain injection is too close to the channel when the heavily doped source and drain injection is injected.

In addition, the channel length of the high-voltage device region is increased, so that an electric field between conductive channels is changed more slowly during ion implantation of the source electrode and the drain electrode, and the acceleration effect of the electric field on hot carriers is reduced, so that the hot carrier effect (HCI effect) is inhibited.

After forming the sidewalls with the deposited ONO structure on the two sides of the gate conductors 413 and 423, respectively, a heavily doped high voltage source/drain region implantation may be performed on the high voltage device region 410, so that the source and drain of the high voltage device region 410 form doped regions with increased doping concentration at the two sides of the second sidewall of the gate conductor 413. In the heavily doped high-voltage source/drain region implantation process, the doping concentration of ion implantation can be higher or far higher than that of ion implantation used during the high-voltage lightly doped source/drain region implantation. The heavily doped source and drain regions can help to thin the potential barrier when the metal is extracted, so that ohmic contact can be realized.

At this time, the nitride layer 415 remaining in the previous process may also protect the gate conductor 413 in the heavily doped high-voltage source drain implantation process to prevent ions from breaking through the thin oxide layer 441 into the gate conductor 413.

Since the high-voltage device and the low-voltage device have different sensitivity degrees to the hot carrier effect, the heavily doped high-voltage source drain region injection can be performed only for the high-voltage device region 410, and the heavily doped low-voltage source drain region injection is not required for the low-voltage device region 420. Therefore, the low-voltage device area has lower starting voltage and keeps the running speed of the low-voltage device under the condition of meeting the HCI requirement of the high-voltage device.

However, in some embodiments, the low-voltage device region 420 may also be heavily doped with a low-voltage source drain implant, so that the source and drain of the low-voltage device region 420 have a gradient concentration. Similarly, in the heavily doped low-voltage source/drain region implantation process, the doping concentration of the ion implantation can also be higher or far higher than that of the ion implantation used in the low-voltage lightly doped source/drain region implantation.

Nitride layers 415 and 425 remaining in the preceding process may be retained until the subsequent removal of the metal silicide block layer. Removing both nitride layers 415 and 425 may save a wet removal process when subsequently removing the metal silicide blocking layer, as compared to removing nitride layers 415 and 425 after the high-pressure lightly doped source drain implantation process.

Fig. 5 shows a schematic flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the present application.

Referring to fig. 5, at step S510, a high-voltage device gate and a low-voltage device gate are formed in the high-voltage device region 410 and the low-voltage device region 420 of the substrate 101, respectively, and nitride layers 415 and 425 are formed over the high-voltage device gate and the low-voltage device gate.

Forming the high-voltage device gate and the low-voltage device gate in the high-voltage device region 410 and the low-voltage device region 420 of the substrate 101 may include: forming a gate oxide layer 440 on the upper surface of the substrate 101; forming a gate layer on the gate oxide layer 440; patterning the gate layer to form a high-voltage device gate in the high-voltage device region 410 and a low-voltage device gate in the low-voltage device region 420; and oxide layers 441 and 442 are formed on the upper surface and side surfaces of the high voltage device gate and the upper surface and side surfaces of the low voltage device gate.

In an exemplary embodiment, the thickness of the gate oxide layer 440 formed at the high voltage device region 410 may be greater than the thickness of the gate oxide layer 440 formed at the low voltage device region 420.

At step S520, a source and a drain of the high voltage device region 410 are formed in the substrate 101 at both sides of the high voltage device gate. As an example, the source and drain of the high voltage device region 410 may be formed in the substrate 101 on both sides of the high voltage device gate by a high voltage lightly doped source drain implant process.

At step S530, first sidewalls are formed on two sides of the high-voltage device gate and two sides of the low-voltage device gate, and a source and a drain of the low-voltage device region 420 are formed in the substrate 101 on two sides of the first sidewall of the low-voltage device gate 413. As an example, the source and drain of the low-voltage device region 420 may be formed in the substrate 101 at both sides of the first sidewall of the low-voltage device gate 413 through a low-voltage lightly doped source/drain implantation process.

In step S540, second sidewalls are formed on two sides of the first sidewall of the high-voltage device gate and two sides of the first sidewall of the low-voltage device gate, and doped regions with increased doping concentration are formed at positions of the source and the drain of the high-voltage device region 410, which are located on two sides of the second sidewall of the high-voltage device gate.

In an exemplary embodiment, forming the second sidewalls at both sides of the first sidewall of the high-voltage device gate and both sides of the first sidewall of the low-voltage device gate may include: depositing an insulating oxide layer 450 above the high-voltage device gate and the low-voltage device gate; and dry etching the insulating oxide layer 450, and only the insulating oxide layer 450 positioned at two sides of the first sidewall of the high-voltage device gate and two sides of the first sidewall of the low-voltage device gate are remained, so as to respectively form a second sidewall 451 and 452 of the high-voltage device gate and a second sidewall 453 and 454 of the low-voltage device gate.

At step S550, the nitride layers 415 and 425 formed over the high-voltage device gate and the low-voltage device gate are removed. Alternatively, the nitride layers 415 and 425 formed over the high-voltage device gate and the low-voltage device gate may be removed at the same time as the metal silicide blocking layer is removed in a subsequent process.

The above description is only a preferred embodiment of the present application and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention herein disclosed is not limited to the particular combination of features described above, but also encompasses other arrangements formed by any combination of the above features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.