阅读说明：本技术 具有主动中介层的半导体元件及其制备方法 (Semiconductor device with active interposer and method of fabricating the same ) 是由 许平 于 2021-05-26 设计创作，主要内容包括：本公开提供一种具有主动中介层的半导体元件及其制备方法。半导体元件包括：一主动中介层,包括一可编程单元；一第一存储器晶粒,位于该主动中介层上方且包括一存储单元；以及一第一逻辑晶粒,位于该主动中介层下方。该主动中介层、该第一存储器晶粒、和该第一逻辑晶粒电性耦合。(The present disclosure provides a semiconductor device with an active interposer and a method for fabricating the same. The semiconductor element includes: an active interposer including a programmable element; a first memory die located above the active interposer and including a memory cell; and a first logic die located below the active interposer. The active interposer, the first memory die, and the first logic die are electrically coupled.)

1. A semiconductor component, comprising:

an active interposer including a programmable element;

a first memory die located above the active interposer and including a memory cell; and

a first logic die located below the active interposer;

wherein the active interposer, the first memory die, and the first logic die are electrically coupled.

2. The semiconductor device of claim 1, further comprising a plurality of through substrate vias in the active interposer, wherein the active interposer and the first logic die are electrically coupled through the plurality of through substrate vias.

3. The semiconductor device of claim 2, further comprising a plurality of micro-bumps between the active interposer and the first logic die, wherein the plurality of micro-bumps are electrically coupled to the plurality of through substrate vias and the plurality of micro-bumps are electrically coupled to the first logic die.

4. The semiconductor device of claim 1, further comprising a plurality of through substrate vias in the first memory die, wherein the active interposer and the first memory die are electrically coupled through the plurality of through substrate vias.

5. The semiconductor device of claim 4, further comprising a plurality of micro-bumps between the active interposer and the first logic die, wherein the plurality of micro-bumps are electrically coupled to the plurality of through substrate vias and the plurality of micro-bumps are electrically coupled to the active interposer.

6. The semiconductor device of claim 5, wherein a width of a top surface of each of the plurality of through substrate vias is between about 1 μm and about 22 μm.

7. The semiconductor device of claim 5, wherein each of the plurality of substrate through holes has a depth of about 20 μm to about 160 μm.

8. The semiconductor device of claim 5, wherein each of the plurality of through substrate vias has an aspect ratio of about 1: 2 to about 1: 35.

9. the semiconductor device of claim 5, wherein each of the plurality of through substrate vias comprises a filler layer in the first memory die and an insulating layer surrounding the filler layer, the filler layer being formed of polysilicon, tungsten, copper, carbon, nanotubes, or solder alloy, and the insulating layer being formed of silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane, parylene, epoxy, or parylene.

10. The semiconductor device of claim 9, further comprising a barrier layer between the insulating layer and the filler layer, wherein the barrier layer is formed of tantalum, tantalum nitride, titanium nitride, rhenium, nickel boride, or tantalum nitride/tantalum bi-layer.

11. The semiconductor device of claim 9, further comprising an adhesion layer between said insulating layer and said filler layer, wherein said adhesion layer is formed of titanium, tantalum, titanium tungsten, or manganese nitride.

12. The semiconductor device of claim 9, further comprising a seed layer between the insulating layer and the filler layer, wherein the seed layer has a thickness of about 10nm to about 40 nm.

13. The semiconductor device of claim 1, further comprising a redistribution layer between the active interposer and the first memory die, wherein the active interposer and the first memory die are electrically coupled through the redistribution layer.

14. The semiconductor device of claim 1, further comprising a plurality of micro-pillars between the active interposer and the first memory die, wherein the active interposer and the first memory die are electrically coupled through the plurality of micro-pillars.

15. The semiconductor device as claimed in claim 5, further comprising a plurality of micro-pillars located between the active interposer and the plurality of micro-bumps, wherein the active interposer and the plurality of micro-pillars are electrically coupled and the plurality of micro-pillars are connected to the plurality of micro-bumps.

16. The semiconductor device of claim 1, further comprising a second memory die located above said first memory die, wherein said first memory die and said second memory die are electrically coupled.

17. The semiconductor device of claim 1, further comprising a third memory die located above the active interposer and adjacent to the first memory die, wherein the third memory die and the active interposer are electrically coupled.

18. A method for manufacturing a semiconductor device includes:

providing an active interposer including a programmable cell;

providing a first logic die and bonding a first side of the active interposer to the first logic die;

providing a first memory die comprising a memory cell; and

bonding the first memory die to a second side of the active interposer, wherein the second side of the active interposer is parallel to the first side of the active interposer.

19. The method of claim 18, further comprising a step of forming a plurality of micro-pillars on the second side of the active interposer, wherein the first memory die and the active interposer are bonded by the plurality of micro-pillars.

20. The method of claim 19, further comprising a step of forming a plurality of micro-bumps on the first side of the active interposer, wherein the active interposer and the first logic die are bonded by the plurality of micro-bumps.

Technical Field

The present disclosure claims priority and benefit from U.S. official application No. 16/889,218, filed on 1/6/2020, the contents of which are incorporated herein by reference in their entirety.

Background

Semiconductor devices have been used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are being scaled to meet the ever increasing demand for computing power. However, various problems occur during the process of miniaturization, and these problems are continuously increasing. Thus, challenges remain in improving quality, yield, performance, and reliability, as well as reducing complexity.

The above description of "prior art" is merely provided as background, and it is not an admission that the above description of "prior art" discloses the subject matter of the present disclosure, does not form prior art to the present disclosure, and that any description of "prior art" above should not be taken as an admission that it is any part of the present disclosure.

Disclosure of Invention

An embodiment of the present disclosure provides a semiconductor device, including: an active interposer including a programmable unit (programmable unit); a first memory die located above the active interposer and including a memory cell; and a first logic die located below the active interposer. The active interposer, the first memory die, and the first logic die are electrically coupled.

In some embodiments, the semiconductor device further includes a plurality of through substrate vias (through substrate vias) in the active interposer. The active interposer and the first logic die are electrically coupled through the plurality of through substrate vias.

In some embodiments, the semiconductor device further includes a plurality of micro-bumps (micro-bumps) between the active interposer and the first logic die. The plurality of micro-bumps are electrically coupled to the plurality of through substrate vias and the plurality of micro-bumps are electrically coupled to the first logic die.

In some embodiments, the semiconductor device further includes a plurality of through substrate vias in the first memory die. The active interposer and the first memory die are electrically coupled through the plurality of through substrate vias.

In some embodiments, the semiconductor device further includes a plurality of microbumps between the active interposer and the first logic die. The micro bumps are electrically coupled to the through substrate vias and the micro bumps are electrically coupled to the active interposer.

In some embodiments, a width of a top surface of each of the plurality of substrate through holes is between about 1 μm and about 22 μm.

In some embodiments, each of the plurality of substrate through holes of the semiconductor device has a depth of about 20 μm to about 160 μm.

In some embodiments, an aspect ratio of each of the plurality of substrate vias is between about 1: 2 to about 1: 35.

in some embodiments, each of the plurality of through substrate vias includes a filler layer in the first memory die and an insulating layer surrounding the filler layer. The filler layer is formed of polysilicon, tungsten, copper, carbon, nanotubes, or solder alloys. The insulating layer is formed of silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (tetra-ethyl ortho-silicate), parylene, epoxy resin, or parylene.

In some embodiments, the semiconductor device further comprises a barrier layer disposed between the insulating layer and the filler layer. The barrier layer is formed of tantalum, tantalum nitride, titanium nitride, rhenium, nickel boride, or a tantalum nitride/tantalum bilayer.

In some embodiments, the semiconductor device further includes an adhesion layer (adhesion layer) between the insulating layer and the filler layer. The adhesion layer is formed of titanium, tantalum, titanium tungsten, or manganese nitride.

In some embodiments, the semiconductor device further includes a seed layer between the insulating layer and the filler layer. The seed layer has a thickness between about 10nm and about 40 nm.

In some embodiments, the semiconductor device further includes a redistribution layer between the active interposer and the first memory die. The active interposer and the first memory die are electrically coupled through the redistribution layer.

In some embodiments, the semiconductor device further includes a plurality of micro-bumps between the active interposer and the first memory die, wherein the active interposer and the first memory die are electrically coupled through the plurality of micro-bumps.

In some embodiments, the semiconductor device further includes a plurality of micro-pillars (micro-pillars) between the active interposer and the first memory die. The active interposer and the first memory die are electrically coupled through the plurality of micropillars.

In some embodiments, the semiconductor device further includes a plurality of micro-pillars located between the active interposer and the plurality of micro-bumps. The active interposer is electrically coupled to the plurality of micro-pillars and the plurality of micro-pillars are connected to the plurality of micro-bumps.

In some embodiments, the semiconductor device further includes a second memory die located above the first memory die. The first memory die and the second memory die are electrically coupled.

In some embodiments, the semiconductor device further includes a third memory die located above the active interposer and adjacent to the first memory die. The third memory die and the active interposer are electrically coupled.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, including: providing an active interposer including a programmable cell; providing a first logic die and bonding a first side of the active interposer to the first logic die; providing a first memory die comprising a memory cell; and bonding the first memory die to a second side of the active interposer. The second side of the active interposer is parallel to the first side of the active interposer.

In some embodiments, the method further comprises a step of forming a plurality of micro-pillars on the second side of the active interposer. The first memory die and the active interposer are bonded by the plurality of micropillars.

In some embodiments, the method further includes a step of forming a plurality of micro-bumps on the first side of the active interposer. The active interposer and the first logic die are bonded by the plurality of micro-bumps.

Due to the design of the semiconductor element of the present disclosure, the first memory die may include only a plurality of memory cells. Thus, fabrication of the first memory die may be simplified. As a result, the manufacturing cost of the semiconductor device can be reduced. In addition, the through substrate via may reduce the interconnect length between the active interposer, the first memory die, and the first logic die to improve the performance of the semiconductor device.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

Aspects of the disclosure can be read with reference to the following drawings and detailed description. It is emphasized that, in accordance with industry standard practice, the various features (features) are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily expanded or reduced for clarity of discussion.

Fig. 1 is a schematic top view illustrating a semiconductor device according to an embodiment of the present disclosure.

Fig. 2 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

Fig. 3 is a schematic cross-sectional view illustrating a substrate via of a semiconductor device according to an embodiment of the present disclosure.

FIG. 4 is a cross-sectional view of a programmable cell showing a semiconductor device according to an embodiment of the present disclosure.

FIG. 5 is a cross-sectional view of a memory cell of a semiconductor device according to one embodiment of the present disclosure.

Fig. 6 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

Fig. 7 is a schematic top view illustrating a semiconductor device according to an embodiment of the present disclosure.

Fig. 8 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

Fig. 9 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

Fig. 10 is a flow chart illustrating a method of fabricating a semiconductor device according to an embodiment of the present disclosure.

Fig. 11-26 are cross-sectional views schematically illustrating a process flow for fabricating a semiconductor device according to an embodiment of the present disclosure.

Description of reference numerals:

1A: semiconductor device with a plurality of semiconductor chips

1B: semiconductor device with a plurality of semiconductor chips

1C: semiconductor device with a plurality of semiconductor chips

1D: semiconductor device with a plurality of semiconductor chips

10: active interposer

10 FS: first side

10 SS: second side

20: first memory die

20 FS: first side

20 SS: second side

30: a first logic die

40: second memory die

50: third memory die

60: method of producing a composite material

100: programmable cell

101: substrate

103: a first isolation layer

105: a second insulating layer

107: a first active region

109: spike portion

109-1: a first facet

109-3: second facet

111: gate dielectric layer

111-1: covering part

111-3: flat part

113: gate bottom conductive layer

115: first gate spacer

117: second gate spacer

119: gate top conductive layer

121: a first lightly doped region

123: first doped region

125: first conductive layer

127: first contact

129: second contact

131: insulating layer

133: insulating layer

200: memory cell

201: substrate

203: insulating layer

205: character line structure

205-1: word line dielectric layer

205-3: character line electrode

205-5: word line capping layer

207: impurity region

209: bit line contact

211: bit line

213: capacitive contact

215: capacitor structure

215-1: capacitor bottom electrode

215-3: capacitor dielectric layer

215-5: capacitor top electrode

217: insulating layer

219: insulating layer

221: insulating layer

223: insulating layer

300: functional circuit

501: substrate perforation

501-1: insulating layer

501-3: barrier layer

501-5: adhesive layer

501-7: seed layer

501-9: packing layer

501 SS: side surface

501 TS: top surface

503: micro-bump

505-1: redistribution layer

505-3: redistribution layer

505-5: redistribution layer

505-7: redistribution layer

507: microcolumn

509: passivation layer

511: a first carrier layer

513: a second carrier layer

D1: depth of field

MS 1: memory stack

S11: step (ii) of

S13: step (ii) of

S15: step (ii) of

W1: width of

W2: width of

W3: width of

W4: width of

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of embodiments of the disclosure. Examples of specific elements and arrangements thereof are described below to simplify the embodiments of the present disclosure. These are, of course, merely examples and are not intended to limit the scope of the embodiments of the disclosure in any way. For example, when reference is made in the description to a first element being formed "on" or "over" a second element, it can include embodiments in which the first element is in direct contact with the second element, and can also include embodiments in which other elements are formed therebetween without direct contact. Furthermore, the present disclosure may repeat reference numerals and/or symbols in various embodiments. These iterations are for simplicity and clarity and are not intended to limit the relationship between the various embodiments and/or structures discussed.

Furthermore, spatially relative terms are used herein, such as: "below," "lower," "over," "upper," and similar terms in … … are used for convenience in describing the relationship of one element or component to another element or component as illustrated in the figures. These spatial relationships are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be turned to a different orientation (rotated 90 degrees or otherwise), and the spatially relative adjectives used herein may be similarly interpreted.

It will be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element unless otherwise indicated. Thus, for example, a first element, component, or section discussed below could be termed a second element, component, or section without departing from the teachings of the present disclosure.

Unless the context indicates otherwise, terms like "same", "equal", "plane", or "coplanar" used herein when referring to an orientation, a layout, a position, a shape, a size, a quantity, or other measure do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other measure, but are intended to encompass nearly the same orientation, layout, position, shape, size, quantity, or other measure within an acceptable range of variation, e.g., due to a manufacturing process. The word "substantially" may be used herein to reflect this meaning. For example, items described as "substantially identical," "substantially equal," or "substantially planar" may be exactly identical, equal, or planar, or may be identical, equal, or planar within acceptable variations due to, for example, manufacturing processes.

It should be noted that the word "about" used in modifying the amounts of ingredients, components, or reactants used in the present disclosure refers to quantitative variations that may occur, for example, through typical measurements and liquid handling procedures used to prepare concentrates or solutions. In addition, variations may occur due to inadvertent errors in the measurement procedure, differences in the manufacture, source or purity of the ingredients used to make the composition or implement the method. In one aspect, the word "about" means within 10% of the reported numerical value. On the other hand, the word "about" means within 5% of the reported numerical value. In yet another aspect, the word "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.

In the present disclosure, a semiconductor element generally refers to an element that can function by utilizing semiconductor characteristics, and an electro-optical element, a light-emitting display element, a semiconductor circuit, and an electronic element are included in the category of semiconductor elements.

It should be noted that, in the description of the present disclosure, the upper (above) or up (up) corresponds to an arrow direction of the direction Z, and the lower (below) or down (down) corresponds to an arrow direction opposite to the direction Z.

Fig. 1 is a schematic top view illustrating a semiconductor device 1A according to an embodiment of the present disclosure. Fig. 2 is a schematic cross-sectional view illustrating a semiconductor device 1A according to an embodiment of the present disclosure. Fig. 3 is a schematic cross-sectional view illustrating a substrate via 501 of a semiconductor device 1A according to an embodiment of the present disclosure. Fig. 4 is a cross-sectional view of the programmable cell 100 showing the semiconductor device 1A according to an embodiment of the present disclosure. Fig. 5 is a cross-sectional view of a memory cell 200 of the semiconductor device 1A according to an embodiment of the present disclosure.

Referring to fig. 1 and 2, the semiconductor device 1A may include an active interposer 10, a first memory die 20, a first logic die 30, a through substrate via 501, and a micro bump 503.

Referring to fig. 1 and 2, the active interposer 10, the first memory die 20, and the first logic die 30 may be vertically arranged and electrically coupled to each other. In particular, the first memory die 20 may be disposed above the active interposer 10. The active interposer 10 may be disposed over the first logic die 30. The width W1 (or dimension) of the active interposer 10 may be greater than the width W2 (or dimension) of the first memory die 20. The width W3 (or size) of the first logic die 30 may be equal to or greater than the width W1 of the active interposer 10.

Referring to fig. 1 and 2, the first memory die 20 may include a plurality of memory cells 200 (only one memory cell 200 is shown in fig. 2 for clarity) arranged in an array pattern in a top perspective view (not shown in fig. 1 for clarity). In some embodiments, the memory cell 200 may also include sense amplifier circuitry, selection circuitry, equalization circuitry, or sub-word line driver circuitry.

It should be noted that in some embodiments, the first memory die 20 may not include programmable circuitry, memory control circuitry, decoding circuitry, repair circuitry, address buffer circuitry, clock generator circuitry (clock generator circuitry), direct current generator circuitry (DC) or input and output (I/O) buffer circuitry. The aforementioned circuitry may be located in the active interposer 10 or the first logic die 30 and electrically coupled to the first memory die 20. Since the first memory die 20 may include only the plurality of memory cells 200, the fabrication of the first memory die 20 may be simplified. Thus, the manufacturing cost of the first memory die 20 can be reduced.

Referring to fig. 1 and 2, the active interposer 10 may include programmable cells 100 (only two programmable cells 100 are shown in fig. 2 for clarity). The programmable unit 100 may be an electronic Fuse (e-Fuse), an anti-Fuse (anti-Fuse), or a redundancy circuit (redundancy circuit), but is not limited thereto. In some embodiments, the active interposer 10 may also include programmable circuitry, memory control circuitry, decode circuitry, repair circuitry, address buffer circuitry, clock generation circuitry, DC generation circuitry, I/O buffer circuitry, system I/O circuitry, power management circuitry, test circuitry, or monitor circuitry.

Referring to fig. 1 and 2, the first logic die 30 may include functional circuits 300 (only two functional circuits 300 are shown in fig. 2 for clarity) to process digital data for operating the control semiconductor element 1A. In some embodiments, first logic die 30 may also include programmable circuitry, memory control circuitry, decode circuitry, repair circuitry, address buffer circuitry, clock generation circuitry, DC generation circuitry, I/O buffer circuitry, system I/O circuitry, power management circuitry, test circuitry, or monitor circuitry.

Referring to fig. 1 and 2, through substrate vias 501 may be disposed in the active interposer 10 and the first memory die 20, respectively, correspondingly. The bottom surface of the substrate through-hole 501 disposed in the first memory die 20 may be substantially (substitially) coplanar with the surface of the first memory die 20 facing the active interposer 10. The bottom surface of the substrate through-hole 501 disposed in the active interposer 10 may be substantially coplanar with the surface of the active interposer 10 facing the first logic die 30.

Referring to fig. 2 and 3, the micro-bumps 503 may be disposed between the active interposer 10 and the first memory die 20 and between the active interposer 10 and the first logic die 30, respectively. In some embodiments, the micro bumps 503 may be connected to the bottom surface of the substrate through hole 501. The active interposer 10, the first memory die 20, and the first logic die 30 may be vertically stacked through the through substrate via 501 and the micro bump 503. The micro-bumps 503 may be formed of, for example, copper, nickel, tin, silver, alloys of the foregoing, or combinations of the foregoing. In some embodiments, each microbump 503 may be a stacked layer including, from bottom to top, a first layer, a second layer, and a third layer. The first layer may be formed of copper and may have a thickness between about 1 μm to about 3 μm. The second layer may be formed of nickel and may have a thickness of between about 1 μm to about 3 μm. The third layer may be formed of a tin-silver alloy and may have a thickness of between about 3 μm to about 7 μm.

For convenience of description, only one substrate through-hole 501 is described. Referring to fig. 2 and 3, the top surface 501TS of the substrate through-hole 501 may have a width W4 of between about 1 μm to about 22 μm. The substrate via 501 may have a depth D1 of between about 20 μm to about 160 μm. In some embodiments, the substrate through-hole 501 may have a thickness of between about 1: 2 to about 1: 35, aspect ratio. In some embodiments, the angle α between the top surface 501TS of the substrate through-hole 501 and the side surface 501SS of the substrate through-hole 501 may be between about 83 degrees to about 90 degrees.

Referring to fig. 2 and 3, a through-substrate via 501 may include an insulating layer 501-1, a barrier layer 501-3, an adhesive layer 501-5, a seed layer 501-7, and a filler layer 501-9. Filler layers 501-9 may be disposed in the first memory die 20 (or in the active interposer 10). For example, filler layers 501-9 may be disposed in substrate 201 of first memory die 20. The top surface of filler layers 501-9 may be substantially coplanar with the top surface of substrate 201. The bottom surface of filler layers 501-9 may be substantially coplanar with the bottom surface of substrate 201. The filler layers 501-9 may be formed of, for example, polysilicon, tungsten, copper, carbon nanotubes, or solder alloys.

Referring to fig. 2 and 3, seed layers 501-7 may surround the side surfaces of filler layers 501-9. Seed layer 501-7 may be formed of, for example, copper. Seed layer 501-7 may have a thickness between about 10nm and about 40 nm. The seed layer 501-7 may reduce the resistivity of the through substrate via 501 during the formation of the through substrate via.

Referring to fig. 2 and 3, an adhesive layer 501-5 may surround the side surface of the seed layer 501-7. Adhesion layer 501-5 may be formed of, for example, titanium, tantalum, titanium tungsten, or manganese nitride. The adhesion layer 501-5 may improve adhesion between the seed layer 501-7 and the barrier layer 501-3.

Referring to fig. 2 and 3, the barrier layer 501-3 may surround a side surface of the adhesion layer 501-5. Barrier layer 501-3 may be formed of, for example, tantalum nitride, titanium nitride, rhenium, nickel boride, or a tantalum nitride/tantalum bilayer. The barrier layer 501-3 may inhibit the conductive material of the filler layer 501-9 from diffusing into the insulating layer 501-1 or the substrate 201.

Referring to fig. 2 and 3, an insulating layer 501-1 may surround a side surface of the barrier layer 501-3. In some embodiments, insulating layer 501-1 can be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or tetraethoxysilane. The insulating layer 501-1 may have a thickness between about 50nm to about 200 nm. In some embodiments, insulating layer 501-1 may be formed of parylene, epoxy, or parylene, for example. The insulating layer 501-1 may have a thickness of between about 1 μm to about 5 μm. The insulating layer 501-1 may ensure that the substrate via 501 is electrically isolated in the substrate 201.

The through substrate via 501 may reduce the length of the interconnect between the active interposer 10, the first memory die 20, and the first logic die 30. As a result, reflection noise, crosstalk noise (cross talk noise), synchronous switching noise (synchronous switching noise), electromagnetic interference, and delay (latency) of the semiconductor element 1A can be reduced. In addition, since the parasitic capacitance is proportional to the interconnect length, the total power consumption in the semiconductor device 1A can be reduced due to the reduced parasitic capacitance.

Referring to fig. 2 and 4, in some embodiments, the programmable cell 100 may be an antifuse, and may include a substrate 101, a first isolation layer 103, a second isolation layer 105, a first active region 107, a peak portion 109, a gate dielectric layer 111, a gate bottom conductive layer 113, a first gate spacer 115, a second gate spacer 117, a gate top conductive layer 119, a first lightly doped region 121, a first doped region 123, a first conductive layer 125, a first contact 127, a second contact 129, and insulating layers 131, 133.

Referring to fig. 2 and 4, the substrate 101 may be formed of, for example, silicon, germanium, silicon carbide, silicon germanium carbide, gallium arsenide, indium phosphide, or other group IV-IV, III-V, or II-VI semiconductor materials. The substrate 101 may have a first lattice constant and a crystal orientation <100 >. In some embodiments, the substrate 101 may include an organic semiconductor or a layered semiconductor such as silicon/silicon germanium, silicon-on-insulator (soi), or silicon germanium-on-insulator (soi). When the substrate 101 is formed of silicon on insulator, the substrate 101 may include a top semiconductor layer and a bottom semiconductor layer formed of silicon and a buried insulating layer that may separate the top semiconductor layer from the bottom semiconductor layer. The buried insulating layer may comprise, for example, crystalline or amorphous oxide, nitride, or a combination of any of the foregoing.

Referring to fig. 2 and 4, a first isolation layer 103 and a second isolation layer 105 may be disposed in the substrate 101. The first isolation layer 103 and the second isolation layer 105 may define a first active region 107 in the substrate 101. The first isolation layer 103 and the second isolation layer 105 may be formed of an insulating material such as, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or a fluoride-doped silicate.

It should be noted that in the present disclosure, silicon oxynitride refers to a substance that contains silicon, nitrogen, and oxygen and in which the proportion of oxygen is greater than that of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen and in which the proportion of nitrogen is greater than that of oxygen.

Referring to fig. 2 and 4, an insulating layer 131 may be disposed on the substrate 101. The insulating layer 133 may be disposed on the insulating layer 131. The insulating layers 131 and 133 may be made of, for example, silicon nitride, silicon oxide, silicon oxynitride, flowable oxide (flowable oxide), Donen's silazane (ton-silazen), undoped silicate glass (undoped silicate glass), (borosilicate glass), phosphosilicate glass (phosphosilicate glass), borophosphate silicate glass (borophosphate glass), plasma-enhanced tetraethoxysilane (plasma-enhanced tetra-ethyl orthosilicate), silicon fluoride glass (fluoride silicate), carbon-doped silicon oxide (carbon-doped silicate oxide), amorphous carbon fluoride (amorphous fluorinated carbonate), organosilicate glass (organic silicate glass), or a combination thereof, but not limited thereto. The insulating layers 131 and 133 may be formed of different materials, but are not limited thereto.

Referring to fig. 2 and 4, the peak portion 109 may be disposed on the first active region 107 and in the insulating layer 131. The peak portion 109 may have a triangular cross-sectional profile and may include a first facet 109-1 and a second facet 109-3 that intersect each other. The angle between the top surface of the substrate 101 and the first facet 109-1 may be between about 50 degrees and about 60 degrees. The first facet 109-1 and the second facet 109-3 may have a crystal orientation <111 >. In some embodiments, the peak portion 109 may have a cross-sectional profile of a diamond, a pentagon, or a shape having more than five sides. The peak portion 109 may be formed of, for example, silicon, germanium, silicon carbide, silicon germanium carbide, gallium arsenide, indium phosphide, or other group IV-IV, III-V, or II-VI semiconductor materials.

Referring to fig. 2 and 4, a gate dielectric layer 111 may be disposed on the first facet 109-1 and the substrate 101. The gate dielectric layer 111 may be disposed in the insulating layer 131. The gate dielectric layer 111 may include a capping portion 111-1 and two flat portions 111-3. The cover portion 111-1 may be disposed on the first facet 109-1 and the second facet 109-3. Two flat portions 111-3 may be respectively connected to both ends of the cover portion 111-1. Two flat portions 111-3 may be disposed on the substrate 101. A portion of one of the two flat portions 111-3 may be disposed on the first isolation layer 103. The thickness of the two flat portions 111-3 may be greater than or equal to the thickness of the cover portion 111-1. In some embodiments, the thickness of the two flat portions 111-3 may be greater than the thickness of the cover portion 111-1.

In some embodiments, the gate dielectric layer 111 may be formed of, for example, silicon oxide. In some embodiments, the gate dielectric layer 111 may be formed of, for example, a high dielectric constant (k) dielectric material, such as a metal oxide, a metal nitride, a metal silicate, a transition metal oxide, a transition metal nitride, a transition metal silicate, a metal oxynitride, a metal aluminate, zirconium silicate, zirconium aluminate, or a combination of the foregoing. Specifically, the gate dielectric layer 111 may be made of hafnium oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium zirconium oxide, lanthanum silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or a combination of the foregoing. In some embodiments, the gate dielectric layer 111 may be a multi-layer structure including, for example, one layer of silicon oxide and another layer of high dielectric constant (k) dielectric material.

Referring to fig. 2 and 4, a gate bottom conductive layer 113 may be disposed on the gate dielectric layer 111 and in the insulating layer 131. The gate bottom conductive layer 113 may be formed of a conductive material such as, for example, polysilicon, polycrystalline silicon germanium, or a combination of the foregoing. In some embodiments, the gate bottom conductive layer 113 may be doped with a dopant such as phosphorus, arsenic, antimony, or boron.

Referring to fig. 2 and 4, a first gate spacer 115 and a second gate spacer 117 may be disposed on sidewalls of the gate bottom conductive layer 113 and sidewalls of the gate dielectric layer 111. The first gate spacer 115 and the second gate spacer 117 may be disposed in the insulating layer 131. A first gate spacer 115 may be disposed on the first active region 107. A second gate spacer 117 may be disposed on the first isolation layer 103. The first gate spacer 115 and the second gate spacer 117 may be formed of, for example, silicon oxide, silicon nitride, or the like.

Referring to fig. 2 and 4, a gate top conductive layer 119 may be disposed on the gate bottom conductive layer 113 and in the insulating layer 131. The gate top conductive layer 119 may have a thickness between about 2nm to about 20 nm. The gate top conductive layer 119 may be formed of, for example, titanium silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide.

Referring to fig. 2 and 4, a first lightly doped region 121 may be disposed under the first gate spacer 115 and in the first active region 107. The first lightly doped region 121 may be opposite to the first isolation layer 103. In some embodiments, the first lightly doped region 121 may be doped with a dopant such as phosphorus, arsenic, or antimony, and may have the first electrical type. In some embodiments, the first lightly doped region 121 may be doped with a dopant, such as boron, and may have the second electrical type.

Referring to fig. 2 and 4, the first doping region 123 may be disposed in the first active region 107 and adjoin the first lightly doped region 121. The first doped region 123 may be disposed between the first lightly doped region 121 and the second isolation layer 105. In other words, the first doping region 123 may be opposite to the first isolation layer 103. The first doping region 123 may have the same electrical type as the first lightly doped region 121 and may be doped with a dopant such as phosphorus, arsenic, antimony, or boron. The dopant concentration of the first doped region 123 may be greater than the dopant concentration of the first lightly doped region 121.

Referring to fig. 2 and 4, a first conductive layer 125 may be disposed on the first doping region 123 and in the insulating layer 131. The first conductive layer 125 may have the same thickness as the gate top conductive layer 119, but is not limited thereto. The first conductive layer 125 may be formed of the same material as the gate top conductive layer 119, but is not limited thereto.

Referring to fig. 2 and 4, a first contact 127 may be disposed on the gate top conductive layer 119 and in the insulating layer 133. A second contact 129 may be disposed on the first conductive layer 125 and disposed through the insulating layers 131, 133. In some embodiments, the sidewalls of the first contact 127 and the sidewalls of the second contact 129 may have a sloped cross-sectional profile. In some embodiments, the width of the first contact 127 or the width of the second contact 129 may gradually widen from bottom to top along the direction Z. In some embodiments, the entirety of the first contact 127 or the entirety of the second contact 129 may have a uniform slope. The first contact 127 and the second contact 129 may be used to apply a programming voltage or current to the programmable cell 100.

During programming of the programmable cell 100, a programming voltage may be provided and applied to the programmable cell 100, and a channel region may be formed under the gate dielectric layer 111 and between the first lightly doped region 121 and the first isolation layer 103. A programming current may flow through the channel region and heat the region around the channel region. During programming of the programmable cell 100, the apex of the peak portion 109 may be the most vulnerable portion because the electric field is concentrated at sharp contours. Since the peak of the peak portion 109 can obtain the highest electric field, the gate dielectric layer 111 can be broken down to form a breaking point of the gate dielectric layer 111 adjacent to the peak of the peak portion 109, and the resistivity can be lowered accordingly. Thus, the programmable cell 100 is blown and programmed. During programming, the location of the break point of the gate dielectric layer 111 can be easily limited to be adjacent to the location of the peak portion 109 having the highest electric field. As a result, the programming reliability of the programmable cell 100 can be increased.

Referring to fig. 2 and 5, the memory cell 200 may include a substrate 201, an isolation layer 203, two word line structures 205, an impurity region 207, a bit line contact 209, a bit line 211, two capacitor contacts 213, a capacitor structure 215, and insulating layers 217, 219, 221, 223.

Referring to fig. 2 and 5, the substrate 201 may be formed of the same material as the substrate 101, but is not limited thereto.

Referring to fig. 2 and 5, an isolation layer 203 may be disposed in the substrate 201. The isolation layer 103 may be formed of the same material as the first isolation layer 103, but is not limited thereto.

Referring to fig. 2 and 5, two word line structures 205 may be disposed in an upper portion of the substrate 201. Each of the two wordline structures 205 may include a wordline dielectric layer 205-1, a wordline electrode 205-3, and a wordline cap layer 205-5.

Referring to fig. 2 and 5, a wordline dielectric layer 205-1 may be disposed inward in an upper portion of the substrate 201. The word line dielectric layer 205-1 may be formed of the same material as the gate dielectric layer 111, but is not limited thereto. The wordline dielectric 205-1 may have a thickness of about 0.5nm to about 10 nm.

Referring to fig. 2 and 5, word line electrodes 205-3 may be disposed on the word line dielectric layer 205-1. The word line electrode 205-3 may be formed of a conductive material such as, for example, polysilicon, silicon germanium, a metal alloy, a metal silicide, a metal nitride, a metal carbide, or a combination of layers including the foregoing. When multiple layers are present, a diffusion barrier layer (not shown), such as titanium nitride or tantalum nitride, may be disposed between each of the multiple layers. The metal may be aluminum, copper, tungsten, or cobalt. The metal silicide may be nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like. The word line electrode 205-3 may have a thickness between about 50nm and about 500 nm.

Referring to fig. 2 and 5, a wordline cap 205-5 may be disposed on the wordline electrode 205-3. The top surface of the wordline cap 205-5 may be flush with the top surface of the substrate 201. The wordline cap 205-5 may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluoride-doped silicate, or the like.

Referring to fig. 2 and 5, an impurity region 207 may be disposed in an upper portion of the substrate 201. The impurity region 207 may be disposed between two word line structures 205 and the isolation layer 203. The impurity region 207 may be doped with a dopant such as phosphorus, arsenic, or antimony.

Referring to fig. 2 and 5, insulating layers 217, 219, 221, 223 may be stacked on the substrate 201. The insulating layers 217, 219, 221, 223 may be formed of the same material as the insulating layer 131, but are not limited thereto.

Referring to fig. 2 and 5, the bit line contact 209 may be disposed in the insulating layer 217. A bit line contact 209 may be disposed on the impurity region 207 and electrically connected to the impurity region 207 disposed between the two wordline structures 205. The bit line contacts 209 may be formed of, for example, doped polysilicon, metal, or metal silicide.

Referring to fig. 2 and 5, the bit line 211 may be disposed in the insulating layer 219. A bit line 211 may be disposed on the bit line contact 209 and electrically connected to the bit line contact 209. The bit lines 211 may be formed of, for example, doped polysilicon, copper, nickel, cobalt, aluminum, tungsten, or combinations thereof.

Referring to fig. 2 and 5, the capacitor contact 213 may be disposed through the insulating layers 217, 219, 221. The capacitor contacts 213 may be respectively disposed on the impurity regions 207 and electrically connected to the impurity regions 207 disposed between the two word line structures 205 and the isolation layer 203. The capacitive contact 213 may be formed of, for example, doped polysilicon, titanium nitride, tantalum nitride, tungsten, copper, aluminum, or an aluminum alloy.

Referring to fig. 2 and 5, the capacitor structures 215 may be disposed in the insulating layer 223 and respectively disposed on the capacitor contacts 213. The capacitor structure 215 may be electrically connected to the capacitor contact 213. The capacitive structure 215 may include a capacitive bottom electrode 215-1, a capacitive dielectric layer 215-3, and a capacitive top electrode 215-5.

Referring to fig. 2 and 5, the capacitor bottom electrode 215-1 may be disposed inwardly in the insulating layer 223. The bottom surfaces of the capacitor bottom electrodes 215-1 may respectively correspondingly contact the top surfaces of the capacitor contacts 213. The capacitor bottom electrode 215-1 may be formed of, for example, doped polysilicon, metal, or metal silicide. A capacitor dielectric layer 215-3 may be disposed on the capacitor bottom electrode 215-1 and cover the top surface of the insulating layer 223. The capacitive dielectric layer 215-3 may be formed of a single layer including an insulating material having a dielectric constant of about 4.0 or more. The capacitive dielectric layer 215-3 may have a thickness between about 1 angstrom and about 100 angstroms. Alternatively, in another embodiment, the capacitance dielectric layer 215-3 may be formed of stacked layers formed of silicon oxide, silicon nitride, and silicon oxide. A capacitive top electrode 215-5 may be disposed on the capacitive dielectric layer 215-3. The capacitive top electrode 215-5 may be formed of, for example, doped polysilicon or metal.

Fig. 6 is a schematic cross-sectional view illustrating a semiconductor device 1B according to an embodiment of the present disclosure. Fig. 7 is a schematic top view illustrating a semiconductor device 1C according to an embodiment of the present disclosure. Fig. 8 is a schematic cross-sectional view illustrating a semiconductor device 1C according to an embodiment of the present disclosure. Fig. 9 is a schematic cross-sectional view illustrating a semiconductor device 1D according to an embodiment of the present disclosure.

Referring to fig. 6, in the semiconductor element 1B, the second memory die 40 may be disposed on the first memory die 20. The second memory die 40 and the first memory die 20 may be electrically coupled through the substrate through-hole 501 and the micro-bump 503. The second memory die 40 may have a similar structure as the first memory die 20. The first memory die 20 and the second memory die 40 together form a memory stack MS 1. Memory stack MS1 may increase the bandwidth of semiconductor element 1B and may improve the power efficiency of semiconductor element 1B. It should be noted that more memory dies may be stacked to form a memory stack disposed on the active interposer 10.

Referring to fig. 7 and 8, in the semiconductor element 1C, a third memory die 50 may be disposed on the active interposer 10 and adjacent to the first memory die 20. The third memory die 50 may have a similar structure as the first memory die 20. The third memory die 50 and the active interposer 10 may be electrically coupled through the through substrate via 501 and the micro bump 503. The third memory die 50 and the first memory die 20 may be electrically coupled through the active interposer 10.

Referring to fig. 9, in the semiconductor device 1D, redistribution layers 505-1, 505-3, 505-5, 505-7 may be disposed between the active interposer 10 and the first memory die 20 and between the active interposer 10 and the first logic die 30, respectively.

In particular, redistribution layers 505-1, 505-3, 505-5, 505-7 may be disposed on a bottom surface of the first memory die 20, on a top surface of the active interposer 10, on a bottom surface of the active interposer 10, and on a top surface of the first logic die 30, respectively. The redistribution layer 505-1 may be disposed between the through substrate vias 501 in the first memory die 20 and the micro-bumps 503 between the active interposer 10 and the first memory die 20. The redistribution layer 505-3 may be disposed between the active interposer 10 and the micro-bumps 503 disposed between the active interposer 10 and the first memory die 20. The redistribution layer 505-5 may be disposed between the active interposer 10 and the micro-bumps 503 disposed between the active interposer 10 and the first logic die 30. The redistribution layer 505-7 may be disposed between the first logic die 30 and the micro-bumps 503 disposed between the active interposer 10 and the first logic die 30. The redistribution layers 505-1, 505-3, 505-5, 505-7 may be electrically coupled to the active interposer 10, the first memory die 20, the first logic die 30, the through substrate via 501, and the micro bumps 503.

Referring to fig. 9, micro pillars 507 may be disposed between the redistribution layer 505-3 and the micro bumps 503 disposed between the active interposer 10 and the first memory die 20. The micro-pillars 507 may be electrically coupled to the micro-bumps 503 and the redistribution layer 505-3. Each of the microcolumns 507 may be a stacked layer including a first layer, a second layer, and a third layer from the bottom to the top. The first layer may be formed of copper and may have a thickness between about 1 μm to about 5 μm. The second layer may be formed of nickel and may have a thickness of between about 1 μm to about 3 μm. The third layer may be formed of gold and may have a thickness of between about 0.05 μm to about 0.2 μm.

Referring to fig. 9, a passivation layer 509 may be disposed between the active interposer 10 and the redistribution layer 505-5. The substrate through-hole 501 disposed in the active interposer 10 may penetrate the passivation layer 509 and connect to the redistribution layer 505-5. The passivation layer 509 may be formed of, for example, silicon nitride.

The redistribution layers 505-1, 505-3, 505-5, 505-7 may reroute electrical connections from the substrate via 501 to larger bond-pads (bond-pads) to minimize challenges associated with perfect alignment between the substrate via 501 and the micro-bumps 503 or micro-pillars 507, and fan out (fan out) and/or enlarge inter-die connections. In addition to relaxing constraints related to connection spacing and size, the redistribution layers 505-1, 505-3, 505-5, 505-7 may also reduce insertion loss of the substrate through-hole 501 while also improving signal transmission and reliability.

It should be noted that the terms "forming", "formed", and "form" may be used to denote and include any method of creating, building (building), patterning, implanting, or depositing elements, dopants, or materials. Examples of the formation method may include, but are not limited to, atomic layer deposition (atomic layer deposition), chemical vapor deposition (chemical vapor deposition), physical vapor deposition (physical vapor deposition), sputtering (sputtering), co-sputtering (co-sputtering), spin coating (spin coating), diffusion, deposition, growth, implantation (implantation), photolithography (photolithography), dry etching, and wet etching.

Fig. 10 is a flow chart illustrating a method 60 of fabricating a semiconductor device 1D according to an embodiment of the present disclosure. Fig. 11 to 26 are schematic cross-sectional views showing a manufacturing flow of the semiconductor device 1D according to an embodiment of the present disclosure.

Referring to fig. 10 and 11, in step S11, an active interposer 10 may be provided.

Referring to fig. 11, the active interposer 10 may include a plurality of programmable cells 100, a first side 10FS, and a second side 10 SS. The first side 10FS and the second side 10SS may be parallel to each other. The plurality of programmable cells 100 may be formed adjacent to the second side 10 SS. The substrate through-hole 501 may be formed in the active interposer 10 and formed adjacent to the first side 10 FS. In some embodiments, the substrate through-hole 501 may be formed prior to forming the plurality of programmable cells 100. In some embodiments, the substrate through-hole 501 may be formed during the formation of the plurality of programmable cells 100. In some embodiments, the substrate through-hole 501 may be formed after the plurality of programmable cells 100 are formed.

Referring to fig. 10 and 12-19, in step S13, a first logic die 30 may be provided and the active interposer 10 may be bonded to the first logic die 30.

Referring to fig. 12, a redistribution layer 505-3 may be formed on the second side 10SS of the active interposer 10. The redistribution layer 505-3 may be electrically coupled to the active interposer 10. A plurality of micro pillars 507 may be formed on the redistribution layer 505-3. In other words, the plurality of micro pillars 507 may be opposite to the active interposer 10 with the redistribution layer 505-3 interposed therebetween.

Referring to fig. 13, a first carrier layer 511 may be bonded onto the redistribution layer 505-3 and cover the micro-pillars 507. Subsequently, the intermediate semiconductor element may be flipped upside down so that the first side 10FS of the active interposer 10 faces upwards. The intermediate semiconductor element may be removed from the top to reduce the thickness of the active interposer 10 and expose the ends of the substrate through-holes 501. An end of the substrate through-hole 501 may protrude from the first side 10FS of the active interposer 10. The removal process may include a planarization process such as chemical mechanical polishing and an etching process such as wet etching.

Referring to fig. 14, a passivation layer 509 may be formed to cover the first side 10FS of the active interposer 10 and the end of the substrate through-hole 501. The passivation layer 509 may prevent the end portion of the substrate through-hole 501 from being oxidized.

Referring to fig. 15, a planarization process, such as chemical mechanical polishing, may be performed to provide a substantially planar surface for subsequent process steps. After the planarization process, the substrate via 501 and the passivation layer 509 may be substantially coplanar. After the planarization process, a portion of the substrate via 501 may be exposed.

Referring to fig. 16, a redistribution layer 505-5 may be formed on the passivation layer 509 and the substrate via 501. The redistribution layer 505-5 may be electrically coupled to the substrate via 501. Subsequently, micro bumps 503 may be formed on the redistribution layer 505-5. The micro bumps 503 may be electrically coupled to the redistribution layer 505-5.

Referring to fig. 17, a separation process may be performed to separate the first carrier layer 511 and the active interposer 10. The separation process may be performed by applying ultraviolet light or a heat source to the intermediate semiconductor element. After the separation process, the micro-pillars 507 may be exposed.

Referring to fig. 18, a first logic die 30 may be provided. Redistribution layer 505-7 may be formed on first logic die 30. Redistribution layer 505-7 may be electrically coupled to first logic die 30. The active interposer 10 in fig. 17 may be flipped back so that the first side 10FS of the active interposer 10 faces downward. Since the active interposer 10 and the first logic die 30 are fabricated separately, the first logic die 30 can be fabricated before/during/after fabrication of the active interposer 10 shown in fig. 17.

Referring to fig. 19, a bonding process may be performed to bond the micro bumps 503 to the redistribution layer 505-7. The active interposer 10 and the first logic die 30 may be electrically coupled through the through substrate via 501, the micro bump 503, and the redistribution layers 505-5, 505-7. The bonding process may be performed by applying a heat source to the intermediate semiconductor element.

Referring to fig. 10 and 20-26, in step S15, a first memory die 20 may be provided and the first memory die 20 may be bonded to the active interposer 10.

Referring to fig. 20, a first memory die 20 may be provided. The first memory die 20 may include a plurality of memory cells 200, a first side 20FS, and a second side 20 SS. The first side 20FS and the second side 20SS may be parallel to each other. The plurality of memory cells 200 may be formed adjacent to the first side 20FS of the first memory die 20. The through substrate via 501 may be formed in the first memory die 20 and adjacent to the second side 20SS of the first memory die 20. In some embodiments, the substrate via 501 may be formed prior to forming the memory cell 200. In some embodiments, the substrate through-hole 501 may be formed during the formation of the plurality of memory cells 200. In some embodiments, the substrate through-hole 501 may be formed after the plurality of memory cells 200 are formed.

Referring to fig. 21, a second carrier layer 513 may be bonded to the first side 20FS of the first memory die 20. The intermediate semiconductor element may then be turned upside down so that the second side 20SS of the first memory die 20 faces upward.

Referring to fig. 22, a planarization process, such as chemical mechanical polishing, may be performed to provide a substantially planar surface for subsequent process steps. After the planarization process, a portion of the substrate via 501 may be exposed. In some embodiments, similar steps as shown in fig. 13-15 can be performed on the second side 20SS of the first memory die 20, and a passivation layer (not shown) can be formed on the second side 20SS of the first memory die 20.

Referring to fig. 23, a redistribution layer 505-1 may be formed on the second side 20SS of the first memory die 20 and the through substrate via 501. The redistribution layer 505-1 may be electrically coupled with the substrate via 501. Subsequently, micro bumps 503 may be formed on the redistribution layer 505-1. The micro bumps 503 may be electrically coupled to the redistribution layer 505-1.

Referring to fig. 24, a separation process may be performed to separate the second carrier layer 513 and the first memory die 20. The separation process may be performed by a similar procedure as shown in fig. 17.

Referring to fig. 25 and 26, the first memory die 20 shown in fig. 24 may be flipped back so that the second side 20SS of the first memory die 20 faces downward. Subsequently, a bonding process may be performed to bond the micro bumps 503 formed on the redistribution layer 505-1 to the micro pillars 507. The active interposer 10 and the first memory die 20 may be electrically coupled through the through substrate via 501, the micro bump 503, the micro pillar 507, and the redistribution layers 505-1, 505-3. The bonding process may be performed by a similar step as shown in fig. 19.

Another embodiment of the present disclosure provides a semiconductor device including: an active interposer including a programmable element; a first memory die located above the active interposer and including a memory cell; and a first logic die located below the active interposer. The active interposer, the first memory die, and the first logic die are electrically coupled.

Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including: providing an active interposer including a programmable cell; providing a first logic die and bonding a first side of the active interposer to the first logic die; providing a first memory die comprising a memory cell; and bonding the first memory die to a second side of the active interposer. The second side of the active interposer is parallel to the first side of the active interposer.

Due to the design of the semiconductor element of the present disclosure, the first memory die 20 may include only a plurality of memory cells 200. Thus, fabrication of the first memory die 20 may be simplified. As a result, the manufacturing cost of the semiconductor element 1A can be reduced. In addition, the through substrate via 501 reduces the length of the interconnect between the active interposer 10, the first memory die 20, and the first logic die 30 to improve the performance of the semiconductor device 1A.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above can be performed in different ways and replaced with other processes or combinations of the foregoing.

Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims of this disclosure.