SiC MOSFET device and preparation method thereof
阅读说明：本技术 一种SiC MOSFET器件及其制备方法 (SiC MOSFET device and preparation method thereof ) 是由 任炜强 春山正光 谢文华 杨正友 于 2021-09-29 设计创作，主要内容包括：本申请涉及碳化硅功率器领域,公开了一种SiC MOSFET器件及其制备方法,SiC MOSFET器件包括衬底、外延底层、基层、源极层、栅极、栅介质层、沟道段、沟道长度减缩段、浮空段、隔离层、源极和漏极；SiC MOSFET器件基于如下方法制备,包括：在衬底的第一表面上形成外延底层和基层,在基层上形成源极层和基极结,在沟槽内形成栅极、栅介质层、沟道段、沟道长度减缩段和浮空段,在栅极层上形成隔离层,在隔离层和源极层上形成源极,在衬底第二表面上形成漏极。本申请的栅介质层缺陷密度低,击穿电压高,可靠性高。(The application relates to the field of silicon carbide power devices and discloses a SiC MOSFET device and a preparation method thereof, wherein the SiC MOSFET device comprises a substrate, an epitaxial bottom layer, a base layer, a source electrode layer, a grid electrode, a grid dielectric layer, a channel section, a channel length reduction section, a floating section, an isolation layer, a source electrode and a drain electrode; the SiC MOSFET device is prepared based on the following method, including: an epitaxial bottom layer and a base layer are formed on the first surface of the substrate, a source electrode layer and a base electrode junction are formed on the base layer, a grid electrode, a grid medium layer, a channel section, a channel length reduction section and a floating section are formed in the groove, an isolation layer is formed on the grid electrode layer, a source electrode is formed on the isolation layer and the source electrode layer, and a drain electrode is formed on the second surface of the substrate. The gate dielectric layer is low in defect density, high in breakdown voltage and high in reliability.)
1. A SiC MOSFET device, comprising:
a substrate (10) having a first surface (11) and an opposing second surface (12);
the epitaxial layer is arranged on the first surface (11) of the substrate (10), the epitaxial layer comprises an epitaxial bottom layer (20), a base layer (30) located on the epitaxial bottom layer (20), and a source layer (40) located on the base layer (30), the epitaxial layer is provided with a groove (61), the groove (61) penetrates through the source layer (40) and the base layer (30) and extends to the epitaxial bottom layer (20), the groove (61) has a groove bottom located in the epitaxial bottom layer (20), the width of an upper opening of the groove (61) is larger than that of a lower groove bottom of the groove, and an included angle between two oblique side walls of the groove (61) and the groove side of the first surface (11) is 50-70 degrees;
the epitaxial layer is formed with a redefined channel layer following the in-groove shape of the groove (61), wherein the redefined channel layer comprises a channel section (62) positioned at the upper part of two inclined side walls, a channel length reducing section (63) positioned at the lower part of one side or two inclined side walls, and a floating section (64) positioned at the bottom of the groove;
the gate dielectric layer (65) covers the redefined channel layer and comprises a first dielectric layer (651) and a second dielectric layer (652), wherein the first dielectric layer (651) is arranged at the bottom of the groove (61), the second dielectric layer (652) covers the inclined side walls on two sides of the groove (61) and is integrally connected to the first dielectric layer (651), and the thickness of the dielectric on the bottom of the groove (61) is larger than that of the inclined side walls on the two sides;
a gate (60) disposed within the trench (61), a bottom of the gate (60) being controlled within a height of the channel length reduction (63).
2. The SiC MOSFET device of claim 1, further comprising:
an isolation layer (70) disposed on the gate electrode (60);
a source (80) disposed on the isolation layer (70) and the epitaxial layer;
a drain electrode (90) disposed on the second surface (12) of the substrate (10);
the crystal face of the inclined side wall of the groove (61) is (0327), (0328), (0329), (0337), (0338) or (0339);
the defect density of the first dielectric layer (651) of the gate dielectric layer (65) is 1E 10-1E 11 cm-3。
3. The SiC MOSFET device of claim 1, wherein an upper end of the channel length reduction section (63) extends into a height range of the base layer (30).
4. The SiC MOSFET device of claim 1, wherein the epitaxial layer further comprises a base junction (50), the base junction (50) being located in the source layer (40) on the base layer (30) such that the source layer (40) is patterned on the epitaxial layer exposed surface, the base junction (50) not extending to the trench opening of the trench (61).
5. The SiC MOSFET device of claim 1, wherein the first dielectric layer (651) is of a material selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and high-K materials; the material of the second dielectric layer (652) is selected from one or more of silicon oxide, aluminum oxide and a high-K material;
the thickness of the first dielectric layer (651) is 600-2000 angstroms, and the thickness of the second dielectric layer (652) is 400-1200 angstroms.
6. A preparation method of a SiC MOSFET device is characterized by comprising the following steps:
forming an epitaxial layer on a first surface (11) of a substrate (10), the epitaxial layer comprising an epitaxial bottom layer (20), a base layer (30) on the epitaxial bottom layer (20), and a source layer (40) on the base layer (30);
the epitaxial layer is provided with a groove (61), the groove (61) penetrates through the source layer (40) and the base layer (30) and extends to the epitaxial bottom layer (20), the groove (61) is provided with a groove bottom positioned in the epitaxial bottom layer (20), the width of an upper opening of the groove (61) is larger than that of a lower groove bottom of the groove, and an included angle between two side inclined side walls of the groove (61) and the groove side of the first surface (11) is 50-70 degrees;
forming a redefined channel layer, a gate dielectric layer (65) and a gate electrode (60) in the groove (61), wherein the redefined channel layer comprises a channel section (62) positioned at the upper part of two inclined side walls, a channel length reducing section (63) positioned at the lower part of one side or two inclined side walls, and a floating section (64) positioned at the bottom of the groove, and the gate dielectric layer (65) covers the gate dielectric layer of the redefined channel layer and wraps the gate electrode (60);
forming an isolation layer (70) on the gate (60) layer;
forming a source electrode (80) on the spacer layer (70) and source electrode layer (40);
a drain (90) is formed on the second surface (12) of the substrate (10).
7. The method of manufacturing the SiC MOSFET device according to claim 6, wherein the opening method of the trench (61) comprises the steps of:
etching the source layer (40), the base layer (30) and the epitaxial bottom layer (20) by adopting plasma to form a vertical groove (61), wherein the groove bottom of the groove (61) is positioned in the epitaxial bottom layer (20), and the used first etching gas is SF6Or is SF6And O2The mixed gas of (3);
etching the side walls of the vertical groove (61) by adopting plasma to form the groove (61) with an upper opening width larger than the width of the bottom of the lower groove and an inverted trapezoid shape, wherein the included angle between the inclined side walls at two sides of the groove (61) and the groove side of the first surface (11) is 50-70 degrees, and the used second etching gas is selected from Cl2And O2Mixed gas of (3), BCl3And O2Mixed gas of (1), SF6And O2Mixed gas of (2) and CF4And O2The etching temperature of one of the mixed gases is 800-1000 ℃.
8. The method of fabricating the SiC MOSFET device of claim 6, wherein the method of forming the redefined channel layer comprises the steps of:
implanting ions into the bottom and the inclined side walls of the trench (61) by ion implantation to form a redefined channel initiation layer (66), wherein the implantation energy is 30-400 kev, and the implantation dose is 1E 12-9E 13cm-2The implantation depth is 0.1-0.5 μm, and the ion implantation temperature is 400-500 ℃ when high-temperature implantation is adopted, or 15-35 ℃ when low-temperature implantation is adopted;
performing high-temperature annealing on the redefined channel initial layer (66) to activate ions in the redefined channel initial layer (66), wherein the annealing temperature is 1500-1900 ℃, the annealing time is 10-60 min, and the annealing atmosphere is argon or nitrogen;
defining the forming area of the channel length reduction section (63) by photoetching, and implanting ions into a preset area of the redefined channel initial layer by adopting an ion implantation method to form the channel length reduction section (63), wherein the implantation energy is 30-190 kev, and the total implantation dosage is 1E 12-9E 14 cm-2；
Wherein the redefined channel initiation layer (66) located on the upper portion of the two side inclined sidewalls is a channel section (62), the redefined channel initiation layer (66) located on the bottom of the groove is a floating section (64), and the channel section (62), the reduced channel length section (63) and the floating section (64) constitute the redefined channel layer.
9. The method of manufacturing the SiC MOSFET device of claim 6, wherein the method of forming the gate dielectric layer (65) comprises the steps of:
forming a first dielectric layer (651), wherein the forming method of the first dielectric layer (651) comprises the following steps:
depositing one or more materials of a high-K material, silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide at the bottom of the groove (61) by a deposition method to form a first dielectric layer (651) with the thickness of 600-2000 angstroms; alternatively, the first and second electrodes may be,
depositing monocrystalline silicon at the bottom of the groove (61) by adopting a deposition method, and then forming silicon oxide on the monocrystalline silicon by adopting a thermal oxidation method to form a first dielectric layer (651) with the thickness of 600-2000 angstroms;
forming a second dielectric layer (652), wherein the forming method of the second dielectric layer (652) comprises the following steps:
depositing one or more materials of a high-K material, silicon oxide and aluminum oxide on the groove bottom and the inclined side wall of the groove (61) by adopting a deposition method to form a second dielectric layer (652) with the thickness of 400-1200 angstroms; alternatively, the first and second electrodes may be,
depositing monocrystalline silicon on the bottom and the inclined side walls of the groove (61) by adopting a deposition method, and then forming the monocrystalline silicon into silicon oxide by adopting a thermal oxidation method, wherein the oxidation temperature is 600-900 ℃ so as to form a first dielectric layer (651) with the thickness of 400-1200 angstroms; alternatively, the first and second electrodes may be,
forming oxide layers with the thickness of 400-1200 angstroms on the bottom and the inclined side walls of the groove (61) by adopting a thermal growth method, wherein the growth temperature is 1100-1400 ℃, then annealing is carried out in the atmosphere of nitrogen or phosphorus, the annealing temperature is 1100-1300 ℃, and finally secondary annealing is carried out in the atmosphere of argon, and the annealing temperature is 1100-1300 ℃ so as to form the second dielectric layer (652);
wherein, the growth sequence of the first dielectric layer (651) and the second dielectric layer (652) can be exchanged.
10. The method of manufacturing the SiC MOSFET device of claim 6, wherein the forming method of the base layer (30) includes the steps of:
implanting ions into the surface of the epitaxial bottom layer (20) by adopting an ion implantation method to form the base layer (30) in the epitaxial bottom layer (20), wherein the implantation energy is 30-400 kev, and the implantation dosage is 1E 13-9E 14 cm-2The implantation depth is 0.3-1 μm, and the ion implantation temperature is 400-500 ℃ when high-temperature implantation is adopted, or 15-35 ℃ when low-temperature implantation is adopted.
Technical Field
The application relates to the field of silicon carbide power devices, in particular to a SiC MOSFET device and a preparation method thereof.
Background
Due to the large forbidden band width, high thermal conductivity, high breakdown field strength, high electronic saturation rate and strong radiation resistance of the silicon carbide, the silicon carbide power semiconductor device can be applied to the working environments of high temperature, high pressure, high frequency and strong radiation.
The vertical MOSFET mainly includes a planar dual injection type MOSFET and a trench type MOSFET. Among them, the trench MOSFET device has no JFET area resistance and has a higher cell density, and thus is considered to have a wider application prospect.
However, in the trench MOSFET, the gate oxide is directly exposed in the drift region, and the electric field is concentrated at the gate oxide corners. The dielectric constant of SiC is SiO2The dielectric constant is 2.5 times, under the blocking state, the gate oxide is broken down in advance when the gate oxide corner at the bottom of the groove does not reach the SiC critical breakdown electric field, and the reliability of the device is reduced.
Disclosure of Invention
In order to solve the problem that gate oxide of a groove type SiC MOSFET device is broken down in advance and improve the reliability of the groove type SiC MOSFET device, the application provides a SiC MOSFET device and a preparation method thereof.
In a first aspect, the present application provides a SiC MOSFET device, which adopts the following technical solution:
a SiC MOSFET device, comprising:
a substrate having a first surface and an opposing second surface;
the epitaxial layer is arranged on the first surface of the substrate and comprises an epitaxial bottom layer, a base layer located on the epitaxial bottom layer and a source layer located on the base layer, a groove is formed in the epitaxial layer, the groove penetrates through the source layer and the base layer and extends to the epitaxial bottom layer, the groove is provided with a groove bottom located in the epitaxial bottom layer, the width of an upper opening of the groove is larger than the width of the groove bottom at the lower part of the groove, and an included angle between the inclined side walls at two sides of the groove and the groove side of the first surface ranges from 50 degrees to 70 degrees;
the epitaxial layer is formed with a redefined channel layer along the shape of the groove, and the redefined channel layer comprises a channel section positioned on the upper part of the two inclined side walls, a channel length reducing section positioned on the lower part of one or two inclined side walls and a floating section positioned on the bottom of the groove;
the gate dielectric layer covering the redefined channel layer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is arranged at the bottom of the groove, the second dielectric layer covers the inclined side walls on the two sides of the groove and is integrally connected on the first dielectric layer, and the thickness of the dielectric on the bottom of the groove is larger than that of the inclined side walls on the two sides;
a gate disposed within the trench, a bottom of the gate being controlled within a height of the channel length reduction.
Through the technical scheme, the width of the upper opening of the groove is larger than that of the bottom of the lower groove, and the included angle between the inclined side walls on the two sides of the groove and the groove side of the first surface is 50-70 degrees, so that the defect density of the gate dielectric layer in the groove can be reduced, the carrier mobility of the groove can be improved, and the on-resistance is reduced. In addition, the redefined channel layer can redefine the channel length to reduce the defect density of gate oxide, can resist an electric field of reverse breakdown voltage of a DS electrode, effectively reduces the electric field intensity borne by the gate dielectric layer, plays a role in protecting the gate dielectric layer, further prevents the gate dielectric layer from being broken down in advance, and improves the breakdown voltage of a device. And secondly, because the two sides of the groove are mainly provided with the base layers, the base layers with the same conductivity type as the grid electrode can further resist the electric field of the reverse breakdown voltage of the DS electrode, protect the grid medium layer and improve the reliability of the device.
Preferably, the SiC MOSFET device further includes:
an isolation layer disposed on the gate electrode;
the source electrode is arranged on the isolation layer and the epitaxial layer;
a drain electrode disposed on the second surface of the substrate;
the inclination of the grooveThe crystal face of the side wall is (0327), (0328), (0329), (0337), (0338) or (0339); the defect density of the first dielectric layer of the gate dielectric layer is 1E 10-1E 11 cm-3。
Research and development shows that the etching rate of the SiC material of the crystal face is slower than that of other crystal faces, so that the crystal face of the inclined side wall of the groove is the crystal face, and the defect density of a gate dielectric layer formed in the groove of the crystal face can be as low as 1E 10-1E 11 cm-3(ii) a In addition, the electron mobility of the crystal surface groove is high, and finally the on-resistance of the device per unit area is reduced.
The gate dielectric layer is low in defect density, high in breakdown voltage, not prone to breakdown in advance and high in reliability.
Preferably, the upper end of the channel length reduction section extends into the height range of the base layer.
Because the implantation thickness of the base layer can tolerate larger process error, the lower part of the inclined side walls at two sides of the groove is provided with a channel length reduction section, the channel length can be adjusted, and the implantation concentration of the channel section can be stabilized.
Preferably, the epitaxial layer further comprises a base junction in the source layer on the base layer such that the source layer is patterned on the exposed surface of the epitaxial layer, the base junction not extending to the trench opening of the trench.
Through the technical scheme, the base electrode junction is matched with the source electrode layer, so that the carrier mobility of the groove can be further improved, and the on-resistance is reduced.
Preferably, the material of the first dielectric layer is selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and high-K material; the material of the second dielectric layer is selected from one or more of silicon oxide, aluminum oxide and high-K materials.
Because the gate oxide corner at the groove bottom of the groove in the related technology is subjected to advanced breakdown when the gate oxide corner does not reach the SiC critical breakdown electric field, the thickness of the gate dielectric layer at the groove bottom can be increased through the matching of the first dielectric layer and the second dielectric layer, the gate dielectric layer corner is prevented from being subjected to advanced breakdown, and the reliability of the gate dielectric layer is further improved. In addition, the first dielectric layer is arranged at the bottom of the grid electrode, so that the grid dielectric layer can bear a higher electric field, and the grid dielectric layer at the bottom of the groove is prevented from being broken down or damaged by the electric field.
Preferably, the thickness of the first dielectric layer is 600-2000 angstroms, and the thickness of the second dielectric layer is 400-1200 angstroms.
Through the technical scheme, the second dielectric layer in the thickness range can effectively inhibit the short trench effect and keep a good subthreshold slope. The first dielectric layer with the thickness in the range can bear higher electric field and prevent the groove bottom gate dielectric layer from being broken down or damaged by the electric field. In addition, in order to ensure the depth of the groove and enable the grid electrode in the groove to be located on the base layer and the epitaxial layer at the same time, the top surface of the first medium layer is lower than the bottom surface of the base layer.
In a second aspect, the present application provides a method for manufacturing a SiC MOSFET device, which adopts the following technical scheme:
a preparation method of a SiC MOSFET device is used for preparing the SiC MOSFET device and comprises the following steps:
forming an epitaxial layer on a first surface of a substrate, wherein the epitaxial layer comprises an epitaxial bottom, a base layer located on the epitaxial bottom and a source layer located on the base layer, a groove is formed in the epitaxial layer, the groove penetrates through the source layer and the base layer and extends to the epitaxial bottom, the groove is provided with a groove bottom located in the epitaxial bottom, the width of an upper opening of the groove is larger than the width of the groove bottom at the lower part of the groove, and an included angle between two side inclined side walls of the groove and the groove side of the first surface is 50-70 degrees;
forming a redefined channel layer, a gate dielectric layer and a gate in the groove, wherein the redefined channel layer comprises a channel section positioned at the upper part of the inclined side walls on two sides, a channel length reducing section positioned at the lower part of one or two inclined side walls and a floating section positioned at the bottom of the groove, and the gate dielectric layer covers the gate dielectric layer of the redefined channel layer and wraps the gate;
forming an isolation layer on the gate layer;
forming a source electrode on the isolation layer and the source electrode layer;
and forming a drain electrode on the second surface of the substrate.
Through the technical scheme, the preparation method is simple, and the reliability of the device can be improved without increasing excessive processes. First, a trench with the upper width larger than the lower width is formed in the source electrode layer to reduce the defect density of the gate dielectric layer in the trench, and also to improve the carrier mobility of the trench and reduce the on-resistance. And secondly, the channel section is formed in the groove, so that the electric field of reverse breakdown voltage of the DS pole can be resisted, the electric field intensity borne by the gate dielectric layer is effectively reduced, the effect of protecting the gate dielectric layer is achieved, the gate dielectric layer is further prevented from being broken down in advance, and the breakdown voltage of the device is improved.
Preferably, the opening method of the trench includes the following steps:
adopting plasma to etch the source electrode layer, the base layer and the epitaxial bottom layer to form a vertical groove, wherein the groove bottom of the groove is positioned in the epitaxial bottom layer, and the used first etching gas is SF6Or is SF6And O2The mixed gas of (3);
etching the side walls of the vertical grooves by adopting plasma to form grooves with an upper opening width larger than the width of the bottom of the lower groove and an inverted trapezoid shape, wherein the included angle between the inclined side walls at two sides of the grooves and the groove side of the first surface is 50-70 degrees, and the used second etching gas is selected from Cl2And O2Mixed gas of (3), BCl3And O2Mixed gas of (1), SF6And O2Mixed gas of (2) and CF4And O2The etching temperature of one of the mixed gases is 800-1000 ℃.
According to the method, the vertical groove is formed through a two-step etching method, then the oblique side wall of the vertical groove is etched through the plasma, and therefore the inverted trapezoidal groove with the upper width larger than the lower width of the oblique side wall and the included angle of 50-80 degrees between the oblique side wall and the substrate is finally formed. In the second step of etching process, the oblique side wall of the trench is etched by using the second etching gas, and the oblique side wall of the trench with the crystal face of (0327), (0328), (0329), (0337), (0338) or (0339) is finally formed by using the characteristics of the second etching gas and the SiC material, so that the electron mobility of the trench is improved, and the on-resistance of the device is reduced.
Preferably, the method of forming the redefined channel layer includes the steps of:
implanting ions into the bottom and the inclined side walls of the trench by ion implantation to form a redefined channel initial layer, wherein the implantation energy is 30-400 kev, and the implantation dose is 1E 12-9E 13cm-2The injection depth is 0.1-0.5 μm; the ion implantation temperature is 400-500 ℃ when high-temperature implantation is adopted, or 15-35 ℃ when low-temperature implantation is adopted;
performing high-temperature annealing on the redefined channel initial layer to activate ions in the redefined channel initial layer, wherein the annealing temperature is 1500-1900 ℃, the annealing time is 10-60 min, and the annealing atmosphere is argon or nitrogen;
defining a forming area of the channel length reduction section by photoetching, and implanting ions into a preset area of a redefined channel initial layer by adopting an ion implantation method to form the channel length reduction section, wherein the implantation energy is 30-190 kev, and the total implantation dosage is 1E 12-9E 14 cm-2；
The redefined channel initial layer positioned on the upper parts of the inclined side walls on the two sides is a channel section, the redefined channel initial layer positioned on the bottom of the groove is a floating section, and the channel section, the channel length reducing section and the floating section form the redefined channel layer.
Through the technical scheme, the channel section is formed by implanting ions into the groove bottom of the groove or the groove bottom and the inclined side wall of the groove, the method is simple, and the doping concentration of the ions is higher than that of the base layer due to the fact that the implantation dosage of the ions is higher; in addition, the high-temperature annealing is carried out on the channel section, so that damage can be reduced, and the electron mobility of the channel section is improved; the channel section formed by the method effectively reduces the electric field intensity borne by the gate dielectric layer, plays a role in protecting the gate dielectric layer, further prevents the gate dielectric layer from being broken down in advance, and improves the breakdown voltage of the device.
In the related SiC MOSFET device, the channel length is generally defined by the substrate before the trench is opened, and the channel length is redefined after the trench is opened, so that the defect density of the gate oxide can be reduced.
Preferably, the forming method of the gate dielectric layer includes the following steps:
forming a first dielectric layer, wherein the forming method of the first dielectric layer comprises the following steps:
depositing one or more materials of a high-K material, silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide at the bottom of the groove by a deposition method to form a first dielectric layer with the thickness of 600-2000 angstroms; alternatively, the first and second electrodes may be,
depositing monocrystalline silicon at the bottom of the groove by adopting a deposition method, and then forming silicon oxide on the monocrystalline silicon by adopting a thermal oxidation method to form a first dielectric layer with the thickness of 600-2000 angstroms;
forming a second dielectric layer, wherein the preparation method of the second dielectric layer comprises the following steps:
depositing one or more materials of a high-K material, silicon oxide and aluminum oxide on the groove bottom and the inclined side wall of the groove by adopting a deposition method to form a second dielectric layer with the thickness of 400-1200 angstroms; alternatively, the first and second electrodes may be,
depositing monocrystalline silicon on the bottom and the inclined side wall of the groove by a deposition method, and then forming the monocrystalline silicon into silicon oxide by a thermal oxidation method, wherein the oxidation temperature is 600-900 ℃, so as to form a first dielectric layer with the thickness of 400-1200 angstroms; alternatively, the first and second electrodes may be,
forming oxide layers with the thickness of 400-1200 angstroms on the bottom and the oblique side walls of the groove by adopting a thermal growth method, wherein the growth temperature is 1100-1400 ℃, then annealing is carried out in the atmosphere of nitrogen or phosphorus, the annealing temperature is 1100-1300 ℃, and finally secondary annealing is carried out in the atmosphere of argon, and the annealing temperature is 1100-1300 ℃ so as to form the second dielectric layer;
the growth sequence of the first dielectric layer and the second dielectric layer can be exchanged.
The preparation method of the gate dielectric layer is various, the defect density of the gate dielectric layer is effectively reduced, and the reliability of the gate dielectric layer is improved. Specifically, the thickness of the gate dielectric layer at the bottom of the groove can be increased through the matching of the first dielectric layer and the second dielectric layer, the gate dielectric layer corner is prevented from being broken down in advance, and the reliability of the gate dielectric layer is further improved. In addition, the first dielectric layer is arranged at the bottom of the grid electrode, so that the grid dielectric layer can bear a higher electric field, and the grid dielectric layer at the bottom of the groove is prevented from being broken down or damaged by the electric field.
In addition, the second dielectric layer formed by adopting a thermal growth method is beneficial to ensuring the uniformity of the second dielectric layer and improving the performance of a device; the interface of the first or second dielectric layer, the epitaxial layer and the base layer is passivated through high-temperature annealing, and in the annealing process, nitrogen or phosphorus can be diffused to the interface of the first or second dielectric layer, the epitaxial layer and the base layer to fill up interface dangling bonds or compensate charges, so that the interface state density is reduced, and the carrier mobility is improved; meanwhile, annealing is favorable for eliminating self lattice defects of the first dielectric layer or the second dielectric layer so as to further improve the compactness of the first dielectric layer or the second dielectric layer, and is favorable for forming good protection on the grid, so that the resistance increase of the grid caused by the diffusion of impurity atoms in the subsequent process to the grid is avoided.
Preferably, the method for forming the base layer includes the steps of:
implanting ions into the surface of the epitaxial layer by adopting an ion implantation method to form the base layer in the epitaxial layer, wherein the implantation energy is 30-400 kev, and the implantation dosage is 1E 13-9E 14 cm-2The implantation depth is 0.3-1 μm, and the ion implantation temperature is 400-500 ℃ when high-temperature implantation is adopted, or 15-35 ℃ when low-temperature implantation is adopted.
In summary, the present application includes at least one of the following beneficial technical effects:
1. the structure of the SiC MOSFET device is optimized, the design of the trench gate structure is beneficial to reducing the on-resistance and on-power consumption of the device, the device can have smaller input capacitance, the switching rate of the device is improved, and the switching power consumption is reduced; the conducting groove is changed from the transverse direction to the longitudinal direction, so that the area of the device can be effectively saved, and the power density is higher.
2. The width of the upper opening of the groove of the SiC MOSFET is larger than the width of the bottom of the lower groove of the SiC MOSFET, so that the groove has 50-70-degree inclined slope surfaces, the defect density of a gate dielectric layer in the groove can be reduced, the carrier mobility of the groove can be improved, and the on-resistance is reduced.
3. The redefined channel layer of the present embodiment may redefine the channel length after trenching to reduce the defect density of the gate oxide.
4. The defect density of the gate dielectric layer of the SiC MOSFET is 1E 10-1E 11 cm-3Significantly lower than the gate oxide of the related art (typically 1E12 cm)-3) Therefore, the gate dielectric layer is high in breakdown voltage, not prone to breakdown in advance and high in reliability.
5. The gate dielectric layer of the SiC MOSFET can resist an electric field with reverse breakdown voltage of the DS electrode, the electric field intensity born by the gate dielectric layer is reduced, the gate dielectric layer is protected from being broken down in advance, and therefore the reliability of the gate dielectric layer is improved.
6. The preparation method of the SiC MOSFET is simple, and the reliability of the device can be improved without adding excessive processes.
Drawings
Fig. 1 is a cross-sectional view of a SiC MOSFET device according to a preferred embodiment of the present application.
Fig. 2 is a perspective cross-sectional view of a SiC MOSFET device according to a preferred embodiment of the present application.
Fig. 3 is a schematic diagram of an epitaxial layer formed on a substrate during the fabrication of a SiC MOSFET device according to a preferred embodiment of the present application.
Fig. 4 is a schematic illustration of the formation of a base layer within an epitaxial layer during the fabrication of a SiC MOSFET device according to a preferred embodiment of the present application.
Fig. 5 is a schematic illustration of the formation of a source layer and a base junction in a base layer during the fabrication of a SiC MOSFET device according to a preferred embodiment of the present application.
Fig. 6 is a schematic diagram of forming vertical trenches in the process of fabricating a SiC MOSFET device according to a preferred embodiment of the present application.
Fig. 7 is a schematic view of trenches with an inverted trapezoid shape formed in the process of manufacturing a SiC MOSFET device according to a preferred embodiment of the present application.
Fig. 8 is a schematic view of the formation of channel segments on the bottom and sloped sidewalls of a trench during the fabrication of a SiC MOSFET device in accordance with a preferred embodiment of the present application.
Fig. 9 is a schematic diagram of the formation of a first dielectric layer in the process of fabricating a SiC MOSFET device according to a preferred embodiment of the present application.
Fig. 10 is a schematic diagram of the formation of a SiN dielectric layer in the process of manufacturing a SiC MOSFET device according to the preferred embodiment of the present application.
FIG. 11 is a schematic diagram of an etched region for forming a SiN dielectric layer in the process of manufacturing a SiC MOSFET device according to the preferred embodiment of the present application.
Fig. 12 is a schematic view showing the removal of the first dielectric layer used as a photoresist in the process of manufacturing the SiC MOSFET device according to the preferred embodiment of the present application.
Fig. 13 is a schematic view of a channel length reduction section formed in a predetermined region of a channel section in a process of manufacturing a SiC MOSFET device according to a preferred embodiment of the present application.
Fig. 14 is a schematic diagram of the first dielectric layer used as photoresist for removing the SiN dielectric layer and the trench sloped sidewalls in the process of manufacturing the SiC MOSFET device according to the preferred embodiment of the present application.
Fig. 15 is a schematic view of the formation of a second dielectric layer during the fabrication of a SiC MOSFET device according to a preferred embodiment of the present application.
Fig. 16 is a schematic diagram of forming a gate in a trench during the fabrication of a SiC MOSFET device according to a preferred embodiment of the present application.
Fig. 17 is a schematic illustration of the source layer and base junction being exposed during fabrication of a SiC MOSFET device according to a preferred embodiment of the present application.
Fig. 18 is a schematic view of a spacer formed on a gate electrode in the process of manufacturing a SiC MOSFET device according to the preferred embodiment of the present application.
Fig. 19 is a schematic diagram of source and drain formation during fabrication of a SiC MOSFET device according to a preferred embodiment of the present application.
Fig. 20 is a cross-sectional view of a SiC MOSFET device of another embodiment of the present application.
Description of reference numerals:
10. a substrate; 11. a first surface; 12. a second surface; 20. an epitaxial bottom layer; 30. a base layer; 40. a source layer; 50. a base junction; 60. a gate electrode; 61. a trench; 62. a channel section; 63. a channel length reduction section; 64. a floating section; 65. a gate dielectric layer; 651. a first dielectric layer; 652. a second dielectric layer; 66. redefining a channel initial layer; 67. a SiN dielectric layer; 68. a photomask; 70. an isolation layer; 80. a source electrode; 90. and a drain electrode.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments for understanding the inventive concept of the present application, and do not represent all the embodiments, nor do they explain the only embodiments. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application under the understanding of the inventive concept of the present application are within the protection scope of the present application.
It should be noted that if directional indications (such as up, down, left, right, front, and back … …) are referred to in the embodiment of the present application, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture, and if the specific posture is changed, the directional indications are changed accordingly. For the sake of easier understanding of the technical solutions of the present application, the field effect transistor structure and the manufacturing method thereof of the present application will be described and explained in further detail below, but are not intended to limit the scope of the present application.
The failure of the SiC MOSFET device is mostly started from the failure of the gate oxide layer, so that the reliability of the gate oxide layer plays an important role in the SiC MOSFET device. The failure of the gate oxide layer is mostly expressed as that the leakage current of the device is gradually increased until breakdown occurs.
The SiC material contains Si atoms and SiO can be formed by a thermal oxidation method2The gate oxide film, however, contains C atoms which cannot be completely converted into gas to leave the oxide layer during the actual thermal oxidation process, and C residues may cause structural defects. And because of the distance between SiC and SiO2The barrier height of the conduction band is also low,these all result in SiO2SiO (silicon oxide) with interface defect trap charge ratio in SiC (silicon carbide) system2the/Si system is two orders of magnitude more.
In the embodiment, the reliability of the gate dielectric layer is improved through the gate dielectric layer with low lattice defects, and in addition, the electric field intensity of the trench gate dielectric layer is prevented from being reduced through the channel section, so that the premature breakdown of the trench gate dielectric layer is avoided.
Referring to fig. 1 and 2, the present embodiment provides a SiC MOSFET device comprising a substrate 10, an epitaxial layer including an epitaxial bottom layer 20, a base layer 30, a source layer 40 and a base junction 50, a gate 60, a gate dielectric layer 65, an isolation layer 70, a source 80, a drain 90 and a redefined channel layer including a channel segment 62, a channel length reduction segment 63 and a float-over segment 64; the conductivity types of the substrate 10, the epitaxial underlayer 20, the source layer 40 and the channel length reduction section 63 are the first conductivity type, and the conductivity types of the base layer 30, the base junction 50, the gate 60, the channel section 62 and the floating section 64 are the second conductivity type. Specifically, the first conductivity type is N-type, and the second conductivity type is P-type; or the first conduction type is P type, and the second conduction type is N type. Preferably, the first conductivity type is N-type and the second conductivity type is P-type.
The substrate 10 has a first surface 11 and an opposite second surface 12, wherein the epitaxial underlayer 20 includes an epitaxial underlayer 20 located on the first surface 11 of the substrate 10, a base layer 30 located on the epitaxial underlayer 20, and a source layer 40 located on the base layer 30.
Both the substrate 10 and the epitaxial bottom layer 20 are of SiC. The crystal plane of the substrate 10 is (0001). The inventors have found that the SiC material in this crystal plane is advantageous for the growth of the epitaxial underlayer 20, and can improve the interface characteristics between the substrate 10 and the epitaxial underlayer 20. In addition, the epitaxial bottom layer 20 is grown on the SiC substrate 10 having the (0001) crystal plane with an off-axis angle of 4 ° to 8 °, and the interface characteristics of the substrate 10 and the epitaxial bottom layer 20 can be further improved. The thickness and doping concentration of the epitaxial bottom layer 20 are designed according to the requirements of the device, and the embodiment is not particularly limited.
The base layer 30 is formed by implanting Al ions into the surface of the epitaxial bottom layer 20 by an ion implantation method. Wherein the conductivity type of the base layer 30 is opposite to the conductivity type of the epitaxial bottom layer 20. In addition, the present embodiment may also implant other ions into the surface of the epitaxial bottom layer 20 to form the base layer 30 with a conductivity type opposite to that of the epitaxial bottom layer 20. Wherein the implantation energy, implantation dose and implantation depth of the ions determine the doping concentration and thickness of the base layer 30.
Preferably, the implantation energy of the ions of the base layer 30 is 30 to 400kev, and exemplary is 30 kev, 50 kev, 100 kev, 150 kev, 200 kev, 250 kev, 300kev, 350 kev, 400 kev. Preferably, the implantation energy of the ions of the base layer 30 is 100 to 300 kev.
Preferably, the implantation dose of the ions of the base layer 30 is 1E 13-9E 14 cm-2Exemplary is 1E13cm-2、3E13cm-2、5E13cm-2、8E13cm-2、1E14cm-2、3E14cm-2、5E14cm-2、7E14cm-2、9E14cm-2. Preferably, the implantation dose of the ions of the base layer 30 is 5E 13-5E 14 cm-2。
Preferably, the base layer 30 has ions implanted to a depth of 0.3 to 1 μm, illustratively 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm. Preferably, the implantation dose of the ions of the base layer 30 is 0.5 to 0.8 μm.
The ions of the base layer 30 may be implanted at a high temperature or at a normal temperature, and preferably, the implantation temperature of the ions of the base layer 30 is 400 to 500 ℃ or 15 to 35 ℃.
The source layer 40 is patterned by photolithography, and then ion implantation is performed at a position corresponding to the source layer 40 on the surface of the base layer 30, thereby forming the source layer 40 having the same conductivity type as the epitaxial underlayer 20. Preferably, the implantation energy of the ions in the source layer 40 is 30 to 190kev, and the implantation dose is 1E13 to 1E15 cm-2。
The base junction 50 is located in the source layer 40 on the base layer 30 such that the source layer 40 is patterned on the exposed surface of the epitaxial layer, wherein the base junction 50 does not extend to the trench opening of the trench 61.
The base junction 50 is patterned by photolithography, and then ion implantation is performed at a position corresponding to the base junction 50 on the surface of the base layer 30 to form a conductive type andthe opposite base junction 50 of the epitaxial bottom layer 20. Preferably, the implantation energy of the ions in the base junction 50 is 30 to 190kev, and the implantation dose is 1E14 to 1E15 cm-2。
In another embodiment of the present application, the epitaxial layer may be devoid of a base junction.
Specifically, the epitaxial bottom layer 20 is provided with a groove 61, the groove 61 penetrates through the source layer 40 and the base layer 30 and extends to the epitaxial bottom layer 20, the groove 61 has a groove bottom located in the epitaxial bottom layer 20, the width of an upper opening of the groove 61 is greater than the width of a lower groove bottom, and an included angle between two side inclined side walls of the groove 61 and the groove side of the first surface 11 is 50-70 °. The width of the upper opening of the groove 61 is greater than the width of the bottom of the lower groove, so that the included angle between the inclined side walls of the groove 61 and the groove side of the first surface 11 is 50 ° -70 °, which further enables the SiC on the inclined side walls of the groove 61 to form the following crystal planes: (0327) (0328), (0329), (0337), (0338) or (0339). Research and development shows that the etching rate of the SiC material of the crystal face is slower than that of other crystal faces, so that the crystal face of the inclined side wall of the groove 61 is the crystal face, and the defect density of the gate dielectric layer 65 formed in the crystal face groove 61 can be as low as 1E 10-1E 11 cm-3Thus, the electron mobility of the trench 61 is increased, thereby reducing the on-resistance of the device, and finally, the on-resistance per unit area of the device is reduced.
After the trench 61 is formed, the epitaxial lower layer 20 is formed with a redefined channel layer along the shape of the trench 61, the redefined channel layer including a channel section 62 located on the upper portion of the two sloped sidewalls, a channel length reducing section 63 located on the lower portion of one or both of the sloped sidewalls, and a floating section 64 located on the bottom of the trench.
The SiC MOSFET device of interest generally has the substrate 30 defining the channel length before trenching, and in this embodiment redefining the channel length after trenching, which reduces the gate oxide defect density.
Specifically, carriers can directly enter the base layer 30 through the channel length reduction section 63, thereby reducing the channel length.
Preferably, the upper end of the channel length reducing section 63 extends into the height of the base layer 30.
Since the thickness of the base layer 30 depends on the product design requirement, that is, the thickness of the base layer 30 is predetermined to be a public plate structure, based on the requirement of the adjustment of the trench length, when the adjustment is small, a trench length reducing section 63 may be provided at the lower portion of the inclined sidewall at one side of the trench, as shown in fig. 20; when the adjustment amplitude is larger, a channel length reducing section 63 can be arranged at the lower part of the inclined side wall at two sides of the groove, as shown in fig. 1; this allows SiC MOSFET devices of different channel lengths to be fabricated under a common plate of base layer 30 implant.
In addition, since the implantation thickness of the base layer 30 can tolerate larger process errors, the channel length reduction section 63 is disposed at the lower portion of the inclined sidewall at both sides of the trench, so as to not only adjust the channel length, but also stabilize the implantation concentration of the channel section 62.
The redefined channel layer of the present embodiment may be formed by implanting ions into the SiC surfaces of the bottom and the sloped sidewalls of the trench 61 by an ion implantation method; or may be formed by a method of depositing SiC. The redefined channel layer of the present embodiment is used for resisting the electric field of the reverse breakdown voltage of the DS electrode, so as to reduce the electric field strength borne by the gate dielectric layer 65, protect the gate dielectric layer 65, prevent the gate dielectric layer 65 from being broken down in advance, and improve the breakdown voltage of the device.
In addition, the base layer 30 with the same conductivity type as the gate 60 and arranged on the two sides of the trench 61 can also resist the electric field of reverse breakdown voltage of the DS electrode, effectively protect and avoid the gate dielectric layer 65, and improve the reliability of the device.
The channel length reducing section 63 of the present embodiment may be formed by performing ion implantation on a predetermined region of the channel section 62 by an ion implantation method, and may be formed on one side of the channel section 62 by single-sided ion implantation, or may be formed on both sides of the channel section 62 by double-sided ion implantation.
Preferably, the channel length reduction segment 63 of the present embodiment has the same potential as the base layer 30 and is connected between the epitaxial bottom layer 20 and the base layer 30. The channel length reduction section 63 of this embodiment can prevent the gate 60 from floating, and is beneficial to improving the dynamic characteristics of the device under the condition that no point is floating.
The gate dielectric layer 65 of this embodiment covers the redefined channel layer, and includes a first dielectric layer 651 and a second dielectric layer 652, where the first dielectric layer 651 is disposed at the bottom of the trench 61, and the second dielectric layer 652 covers the two side oblique sidewalls of the trench 61 and is integrally connected to the first dielectric layer 651, so that the dielectric thickness at the bottom of the trench 61 is greater than the dielectric thickness at the two side oblique sidewalls, thereby eliminating gate oxidation at the bottom of the trench.
The gate 60 of this embodiment is disposed in the trench 61, and the bottom of the gate 60 is controlled within the height of the channel length reducing section 63.
Specifically, the gate 60 is polysilicon, which has a conductivity type opposite to that of the epitaxial bottom layer 20 and has a doping concentration of 1018~1020 ions/cm3. Preferably, the doping concentration of the gate 60 may be the same as that of the substrate 10 to improve the turn-on performance of the gate 60.
In order to prevent the corner of the gate dielectric layer 65 at the bottom of the trench 61 from being broken down in advance when the SiC critical breakdown field is not reached, the second dielectric layer 652 of the present embodiment covers the two side inclined sidewalls of the trench 61 and is integrally connected to the first dielectric layer 651, so that the dielectric thickness on the bottom of the trench 61 is greater than the dielectric thickness on the two side inclined sidewalls.
Preferably, the material of the first dielectric layer 651 is selected from one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and high-K material; the material of the second dielectric layer 652 is selected from one or more of silicon oxide, aluminum oxide and a high-K material.
Through the mutual matching of the materials of the trench 61, the redefined channel layer, the first dielectric layer 651 and the second dielectric layer 652, the defect density of the gate dielectric layer 65 of the embodiment is 1E 10-1E 11 cm-3Significantly lower than the gate oxide of the related art (typically 1E12 cm)-3) Therefore, the gate dielectric layer 65 of the present embodiment has a high breakdown voltage, is not easily broken down in advance, and has high reliability.
In addition, in the present embodiment, by matching the first dielectric layer 651 and the second dielectric layer 652, the thickness of the gate dielectric layer 65 at the bottom of the trench 61 may be increased, which prevents the gate dielectric layer 65 from being broken down at the corners in advance, and further improves the reliability of the gate dielectric layer 65. In addition, in this embodiment, the first dielectric layer 651 is disposed at the bottom of the gate electrode 60, so that the gate dielectric layer 65 can withstand a higher electric field, and the bottom gate dielectric layer 65 is prevented from being broken down or damaged by the electric field.
Preferably, the material of the first dielectric layer 651 is selected from a high-K material, the material of the second dielectric layer 652 is selected from a high-K material, and the high-K material has a thicker material thickness under the same equivalent oxide layer thickness, so that the direct tunneling current between the gate and the trench 61 can be reduced. In particular, the high-K material is selected from hafnium oxide or zinc peroxide.
Preferably, the first dielectric layer 651 is made of zinc peroxide, and the second dielectric layer 652 is made of hafnium oxide.
The isolation layer 70 is formed on the gate electrode 60 and made of an insulating material to isolate the gate electrode 60 from the source electrode 80. The isolation layer 70 is made of one or more materials selected from silicon oxide, silicon nitride, silicon oxynitride, spin-on dielectric materials (s pi n-o n i e c t r i m a t e ia l), and low-k dielectric materials (l o w-k dielectric materials). Preferably, the material of the isolation layer 70 is USG (uranium silicate glass) and/or BPSG (boron phosphorus silicate glass). In this embodiment, the source electrode 80 is formed on the isolation layer 70, the source electrode layer 40 and the base junction 50 and is made of metal.
The drain electrode 90 is provided on the second surface of the substrate 10 and is also made of metal. Preferably, the metal material of the source electrode 80 and the drain electrode 90 is selected from one of Al, AlCu, AlSiCu.
The embodiment also provides a preparation method of the SiC MOSFET device, which is used for preparing the SiC MOSFET device and comprises the following steps:
s1, forming an epitaxial layer on the first surface of the substrate;
specifically, the method comprises the following steps:
s11, forming an epitaxial bottom layer on the first surface of the substrate;
referring to fig. 3, a substrate 10 has a first surface 11 and an opposite second surface 12, specifically, an epitaxial underlayer 20 of SiC is formed off-axis by 4 ° to 8 ° on a SiC substrate 10 having a crystal plane of (0001). Preferably, the conductivity type of the substrate 10 and the epitaxial lower layer 20 is N-type.
The inventors have found that the SiC material in this crystal plane is advantageous for the growth of the epitaxial underlayer 20, and can improve the interface characteristics between the substrate 10 and the epitaxial underlayer 20. The thickness and doping concentration of the epitaxial bottom layer 20 are designed according to the requirements of the device, and the embodiment is not particularly limited.
S12, forming a base layer in the epitaxial bottom layer;
referring to fig. 4, defining a substrate region by photolithography, forming a photoresist, implanting ions into the surface of the substrate region of the epitaxial bottom layer 20 by an ion implantation method after development to form a substrate 30 in the epitaxial bottom layer 20, wherein the implantation energy is 30 to 400kev, and the total implantation dose is 1E13 to 9E14 cm-2The implantation depth is 0.3-1 μm, and the ion implantation temperature is 400-500 ℃ when high-temperature implantation is adopted, or 15-35 ℃ when low-temperature implantation is adopted. The implantation mode may be a single implantation or a multiple implantation.
Preferably, the implanted ions are Al ions, corresponding to the formation of the P-type base layer 30 within the epitaxial bottom layer 20.
S13, forming a source layer in the base layer;
referring to fig. 5, a source region is defined by photolithography, a photoresist (not shown) is formed, and ions are implanted into the surface of the source region of the base layer 30 by ion implantation after development to form a source layer 40 in the base layer 30, with an implantation energy of 30 to 190kev and a total implantation dose of 1E13 to 9E15 cm-2. The implantation mode may be a single implantation or a multiple implantation.
Preferably, the implanted ions are P-ions, corresponding to the formation of an N-type source layer 40 within the base layer 30.
Referring to fig. 5, defining the base region while defining the source region by photolithography, removing the photoresist after forming the source layer, and implanting ions into the surface of the base layer 30 outside the source region by ion implantation to form a base junction 50 in the base layer 30, wherein the implantation energy is 30 to 190kev and the total implantation dose is 1E14 to 1E15 cm-2. The implantation mode may be a single implantation or a multiple implantation.
Preferably, the implanted ions are Al ions, which correspond to the formation of the P-type base junction 50 in the base layer 30.
S14, forming a groove;
specifically, the method comprises the following steps:
s141, forming a vertical groove;
referring to FIG. 6, 5000-30000 angstroms of SiO is formed2Masking (not shown), defining trench region by photolithography, etching the source layer 40 and the epitaxial bottom layer 20 by plasma to form a vertical trench 61 with a depth of 0.5-2 μm, wherein the bottom of the trench 61 is located in the epitaxial bottom layer 20, and the first etching gas is SF6Or is SF6And O2The mixed gas of (1).
The trench 61 extends through the source layer 40 and the base layer 30 to the epitaxial bottom layer 20, and the trench 61 has a trench bottom in the epitaxial bottom layer 20.
S142, forming an inverted trapezoidal groove;
referring to fig. 7, the inclined side walls of the trench 61 are etched by using plasma to form an inverted trapezoid trench 61 with an upper opening width larger than the width of the bottom of the lower groove, the included angle between the inclined side walls at two sides of the trench 61 and the groove side of the first surface 11 is 50-70 °, and the second etching gas is selected from Cl2And O2Mixed gas of (3), BCl3And O2Mixed gas of (1), SF6And O2Mixed gas of (5) or CF4And O2The etching temperature of one of the mixed gases is 800-1000 ℃.
In the present embodiment, a vertical trench 61 is formed by etching first by a two-step etching method, and then the oblique sidewall of the trench 61 is etched by using plasma, so as to obtain an inverted trapezoidal trench 61 with high accuracy and less loss.
In addition, in the second step of etching process, the second etching gas is used to etch the inclined sidewall of the trench 61, and the etching rate of the SiC material with the crystal face (0327), (0328), (0329), (0337), (0338) or (0339) slower than that of other crystal faces is obtained by using the characteristics of the second etching gas and the SiC material, so that the inclined sidewall of the trench 61 of the crystal face is formed, and since the SiC material of the crystal face has a relatively low interface state, the defect density of the gate dielectric layer 65 can be reduced when the gate dielectric layer 65 is formed in the subsequent process, and meanwhile, the electron mobility of the trench 61 is improved, and the on-resistance of the device is reduced.
Preferably, the second etching gas is Cl2And O2Mixed gas of (2), Cl2And O2The gas flow rate ratio of (1-2): 1.
S2, forming a redefined channel initial layer;
referring to FIG. 8, the protection region is defined by photolithography, and ions are implanted into the inclined sidewall and the bottom of the trench 61 by ion implantation to form a redefined channel initiation layer 66, with an implantation energy of 30-400 kev and a total implantation dose of 1E 12-9E 13cm-2The implantation depth is 0.1-0.5 μm, and the ion implantation temperature is 400-500 ℃ when high-temperature implantation is adopted, or 15-35 ℃ when low-temperature implantation is adopted. The implantation mode may be a single implantation or a multiple implantation.
Preferably, the implanted ions are Al ions, corresponding to the formation of the P-type redefined channel initiation layer 66 within the SiC on the sloped sidewalls and bottom of the trench 61.
Preferably, the implantation angle of the ions at the inclined sidewall of the trench 61 is 0 to 40 °, so that the thickness uniformity of the redefined channel initiation layer 66 can be secured.
Preferably, after forming the redefined channel initiation layer 66, the method further includes the following steps: and annealing the redefined channel initiation layer 66 at 1500-1900 ℃ for 10-60 min in an atmosphere of argon or nitrogen to activate Al ions in the redefined channel initiation layer 66.
Since the trench 61 is lost during the etching process and has a rough surface, the quality of the redefined channel initiation layer 66 may be affected if Al ions are directly implanted into the trench 61.
Preferably, before forming the redefined channel initiation layer 66, a thermal oxidation method is used to form a sacrificial oxide layer (not shown) on the bottom and the inclined sidewalls of the trench 61, wherein the thickness of the sacrificial oxide layer is 200-1000 angstroms, and the growth temperature is 800-1200 ℃; and removing the sacrificial oxide layer by adopting a wet etching method. The sacrificial oxide layer is formed before the redefined channel initiation layer 66 is formed and then removed, so that defects formed by etching the groove 61 can be reduced, the surface roughness of the groove 61 is reduced, and the forming quality of the redefined channel initiation layer 66 is improved.
In the present embodiment, Al ions are implanted into the sloped sidewalls and the bottom of the trench 61 to form the redefined channel initiation layer 66, which is simple and has a doping concentration higher than that of the base layer 30 due to the higher implantation dose of Al ions; in addition, the embodiment can reduce the damage and improve the electron mobility of the redefined channel initiation layer 66 by performing a high temperature annealing on the redefined channel initiation layer 66; the redefined channel initial layer 66 formed by the method effectively reduces the electric field intensity borne by the gate dielectric layer 65, plays a role in protecting the gate dielectric layer 65, further prevents the gate dielectric layer 65 from being broken down in advance, and improves the breakdown voltage of the device.
S3, forming a redefined channel layer and a gate dielectric layer;
specifically, the method comprises the following steps:
s31, forming a first dielectric layer;
referring to fig. 9, a first dielectric layer 651 covers the redefined channel initiation layer 66 and the surfaces (the source layer 40 and the base junction 50) outside the trench 61, and the first dielectric layer 651 is fabricated by a method including the following three steps:
firstly, depositing one or more materials of a high-K material, silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide at the bottom of a groove 61 in the groove 61 by a deposition method to form a first dielectric layer 651 with the thickness of 600-2000 angstroms;
secondly, depositing the monocrystalline silicon at the bottom of the groove 61 by a deposition method, and then forming silicon oxide from the monocrystalline silicon by a thermal oxidation method to form a first dielectric layer 651 with the thickness of 600-2000 angstroms.
To form the channel length reduction segment 63 in the redefined channel initiation layer 66 using the first dielectric layer 651 as a photoresist, the method further includes the steps of:
and etching the first dielectric layer 651 on the oblique side wall of the groove 61, and reducing the thickness of the first dielectric layer 651 on the oblique side wall of the groove 61 to 300-900 angstroms.
S32, forming a redefined channel layer;
specifically, the method comprises the following steps:
referring to fig. 10, a SiN dielectric layer 67 with a thickness of 2000-10000 angstroms is deposited on the first dielectric layer 651;
referring to fig. 11, the etching region of the SiN dielectric layer 67 is defined by photolithography through the mask 68, and then the etching region of the SiN dielectric layer 67 is etched by development;
wherein, the etching area of the SiN dielectric layer 67 is located at one side or two sides of the SiN dielectric layer 67, and the etching area can not completely leak out of the base layer 30;
referring to fig. 12, the first dielectric layer 651 serving as a photoresist, which is exposed from the etched region of the SiN dielectric layer 67, is removed, and a predetermined region of the redefined channel initiation layer 66 is exposed; in other embodiments of the present application, the first dielectric layer 651 used as a photoresist exposed in the etched region of the SiN dielectric layer 67 may be removed after the channel length reduction 63 is formed.
Referring to FIG. 13, the channel length reduction section 63 is formed by implanting ions into a predetermined region of the redefined channel initiation layer by ion implantation with an implantation energy of 30 to 190kev and a total implantation dose of 1E12 to 9E14 cm-2. The implantation mode may be a single implantation or a multiple implantation.
It should be noted that the redefined channel initialization layer 66 located on the upper portion of the two side inclined sidewalls is the channel section 62, and the redefined channel initialization layer 66 located on the bottom of the groove is the floating section 64, wherein the channel section 62, the reduced channel length section 63, and the floating section 64 constitute a redefined channel layer, and the redefined channel layer of the present application is formed to follow the in-groove shape of the groove 61.
Preferably, the implanted ions are P ions corresponding to the formation of the N-type channel length reduction section 63 in the redefined channel initiation layer 66.
Preferably, the angle of implantation of the ions at the inclined side walls of the redefined channel initiation layer 66 is 20 to 40, which ensures that the ions are implanted into the predetermined region of the redefined channel initiation layer 66.
And carrying out high-temperature annealing on the channel length reduction section 63 to activate the P ions in the channel length reduction section 63, wherein the annealing temperature is 1500-1900 ℃, the annealing time is 10-60 min, and the annealing atmosphere is argon or nitrogen.
Referring to fig. 14, the SiN dielectric layer 67 and the first dielectric layer 651 used as photoresist on the inclined sidewalls of the trench 61 are removed, and the first dielectric layer 651 on the bottom of the trench 61, the source layer 40 and the base junction 50 is remained;
s43, forming a second dielectric layer;
referring to fig. 15, a second dielectric layer 652 covers the redefined channel layer and the surfaces (the source layer 40 and the base junction 50) outside the trench 61, and the first dielectric layer 651 is fabricated by a method including the following three steps:
firstly, depositing one or more materials of a high-K material, silicon oxide and aluminum oxide on the groove bottom and the inclined side wall of the groove 61 by a deposition method to form a second dielectric layer 652 with the thickness of 400-1200 angstroms;
secondly, depositing monocrystalline silicon on the bottom and the inclined side walls of the groove 61 by a deposition method, and then forming silicon oxide from the monocrystalline silicon by a thermal oxidation method at the oxidation temperature of 600-900 ℃ to form a second dielectric layer 652 with the thickness of 400-1200 angstroms;
thirdly, forming oxide layers with the thickness of 400-1200 angstroms on the bottom and the inclined side walls of the groove 61 by adopting a thermal growth method, wherein the growth temperature is 1100-1400 ℃, then annealing in the atmosphere of nitrogen or phosphorus, the annealing temperature is 1100-1300 ℃, and finally secondary annealing in the atmosphere of argon is carried out, wherein the annealing temperature is 1100-1300 ℃ so as to form a second dielectric layer 652.
In this embodiment, the defect density of the gate dielectric layer 65 can be effectively reduced by using the three methods for preparing the second dielectric layer 652.
It should be noted that the smaller the defect density of the gate dielectric layer 65, the lower the scattering degree of the carriers, the higher the mobility of the device, and the lower the resistivity, and when the same current is passed, the lower the power consumption, and the higher the current carrying capacity. The key to determining the lifetime of the gate dielectric layer 65 is the structural defects of the oxide layer caused by the heavy ions in the gate dielectric layer 65.
Specifically, 1, a second dielectric layer 652 is formed by depositing a high-K material by a deposition method, so that the vacancy density and defects in the film can be reduced; 2. monocrystalline silicon is formed firstly by adopting a deposition method, then silicon oxide is formed by oxidation to form a second dielectric layer 652, and low-temperature oxidation is carried out at 600-900 ℃, so that vacancy density and defects in the film can be reduced; 3. the second dielectric layer 652 formed by adopting a thermal growth method is beneficial to ensuring the uniformity of the second dielectric layer 652 and improving the performance of the device; the interfaces between the first or second dielectric layer 652 and the epitaxial bottom layer 20 and the base layer 30 are passivated by high-temperature annealing, and in the annealing process, nitrogen or phosphorus can diffuse to the interfaces between the first or second dielectric layer 652 and the interfaces between the epitaxial bottom layer 20 and the base layer 30 to fill up interface dangling bonds or compensate charges, so that the interface state density is reduced, and the carrier mobility is improved; meanwhile, annealing helps to eliminate lattice defects of the first or second dielectric layer 652 itself to further improve the compactness thereof, and helps to form good protection for the gate 60, thereby preventing impurity atoms in the subsequent process from diffusing into the gate 60 to increase the resistance of the gate 60.
It should be noted that, in other embodiments, after the redefined channel initiation layer 66 is formed, the protection region may be defined by photolithography, the photoresist may be formed, and the channel length reduction section 63 may be formed in the predetermined region of the redefined channel initiation layer 66, and then the first dielectric layer 651 and the second dielectric layer 652 are formed, that is, after step 3 is completed, step S42 is performed first, and then steps S61 and S43 are performed, where the steps of forming the first dielectric layer 651 and the second dielectric layer 652 may need to be fine-adjusted. In addition, in other embodiments, the steps of forming the first dielectric layer 651 and the second dielectric layer 652 may be interchanged.
S4, forming a grid electrode in the groove;
specifically, the method comprises the following steps:
s41, referring to fig. 16, polysilicon is deposited in the trench 61 by LPCVD, and then doped or implanted by in-situ method to form a gate 60 with a conductivity type opposite to that of the epitaxial bottom layer 20, the gate 60 being doped with a concentration of 1018~1020 ions/cm3The thickness is 1000 to 1500 angstroms.
S42, see fig. 17, the gate 60 and the gate dielectric layer 65 are removed by etching or planarization (CMP) to expose the source layer 40 and the base junction 50.
Preferably, the upper surface of the gate 60 in the trench 61 is lower than the upper surfaces of the source layer 40 and the base junction 50 to facilitate the subsequent formation of the isolation layer 70. Preferably, the top surface of the gate 60 in the trench 61 is 10-1000 angstroms lower than the top surfaces of the source layer 40 and the base junction 50.
S5, forming an isolation layer;
referring to fig. 18, a spacer 70 is formed on the gate 60 by high density plasma deposition, and then the spacer 70 is etched away from the gate 60 by photolithography definition, exposing the source layer 40 and the base junction 50.
S6, forming a source electrode and a drain electrode;
referring to fig. 19, a source 80 is formed by depositing metal on the surfaces of the spacer layer 70, the source layer 40 and the base junction 50; the substrate 10 is thinned and metal is deposited on the second surface of the substrate 10 to form the drain 90. Preferably, the metal material of the source electrode 80 and the drain electrode 90 is selected from one of Al, AlCu, AlSiCu.
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