阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 廖忠志 于 2021-02-24 设计创作，主要内容包括：根据本公开的实施例的半导体器件包括第一晶体管和第二晶体管。第一晶体管包括位于第一和第二源极/漏极部件之间的第一沟道构件、包围在第一沟道构件周围的第一栅极结构、设置在第一源极/漏极部件上方的第一源极/漏极接触件以及设置在第一栅极结构与第一源极/漏极接触件之间的第一顶部栅极间隔件。第二晶体管包括位于第三和第四源极/漏极部件之间的第二沟道构件、包围在第二沟道构件周围的第二栅极结构、设置在第三源极/漏极部件上方的第二源极/漏极接触件以及设置在第二栅极结构与第二源极/漏极接触件之间的第二顶部栅极间隔件。第二栅极间隔件和第二源极/漏极接触件之间的距离大于第一栅极间隔件和第一源极/漏极接触件之间的距离。(A semiconductor device according to an embodiment of the present disclosure includes a first transistor and a second transistor. The first transistor includes a first channel member between the first and second source/drain features, a first gate structure surrounding the first channel member, a first source/drain contact disposed over the first source/drain feature, and a first top gate spacer disposed between the first gate structure and the first source/drain contact. The second transistor includes a second channel member between the third and fourth source/drain features, a second gate structure surrounding the second channel member, a second source/drain contact disposed over the third source/drain feature, and a second top gate spacer disposed between the second gate structure and the second source/drain contact. The distance between the second gate spacer and the second source/drain contact is greater than the distance between the first gate spacer and the first source/drain contact.)

1. A semiconductor device, comprising:

a first transistor located in a first device region of a substrate, the first transistor comprising:

a first source/drain feature and a second source/drain feature,

a first plurality of channel members sandwiched between the first source/drain feature and the second source/drain feature,

a first gate structure surrounding each of the first plurality of channel members,

a first source/drain contact disposed over the first source/drain feature, and

a first top gate spacer disposed between the first gate structure and the first source/drain contact; and

a second transistor located in a second device region of the substrate, the second transistor comprising:

a third source/drain feature and a fourth source/drain feature,

a second plurality of channel members sandwiched between the third source/drain feature and the fourth source/drain feature,

a second gate structure surrounding each of the second plurality of channel members,

a second source/drain contact disposed over the third source/drain feature, and

a second top gate spacer disposed between the second gate structure and the second source/drain contact,

wherein a distance between the second top gate spacer and the second source/drain contact is greater than a distance between the first top gate spacer and the first source/drain contact.

2. The semiconductor device as set forth in claim 1,

wherein each of the first plurality of channel members extends in a first direction,

wherein each of the second plurality of channel members extends in a second direction,

wherein the first top gate spacer has a first thickness along the first direction,

wherein the second top gate spacer has a second thickness along the second direction, and

wherein the second thickness is greater than the first thickness.

3. The semiconductor device as set forth in claim 1,

wherein the first transistor further comprises a first etch stop layer disposed between the first source/drain contact and the first top gate spacer,

wherein the second transistor further comprises a second etch stop layer and a low-k dielectric layer disposed between the second source/drain contact and the second top gate spacer.

4. The semiconductor device of claim 3, wherein the first etch stop layer is in direct contact with the first source/drain contact and the first top gate spacer.

5. The semiconductor device of claim 3, wherein the second etch stop layer is in direct contact with the second top gate spacer and the low-k dielectric layer.

6. The semiconductor device of claim 3, wherein a thickness of the first etch stop layer is less than a thickness of the second etch stop layer.

7. The semiconductor device as set forth in claim 3,

wherein the first etch stop layer and the second etch stop layer comprise silicon nitride,

wherein the low-k dielectric layer comprises silicon oxide.

8. The semiconductor device as set forth in claim 1,

wherein the first device region is a high density device region,

wherein the second device region is a high voltage device region.

9. A semiconductor device, comprising:

a first transistor comprising:

a first source/drain feature and a second source/drain feature,

a first plurality of channel members sandwiched between the first source/drain feature and the second source/drain feature along a first direction,

a first gate structure surrounding each of the first plurality of channel members, and

a first plurality of interior spacer features disposed between the first gate structure and the first source/drain features; and

a second transistor comprising:

a third source/drain feature and a fourth source/drain feature,

a second plurality of channel members sandwiched between the third source/drain feature and the fourth source/drain feature along a second direction,

a second gate structure surrounding each of the second plurality of channel members, and

a second plurality of inner spacer features disposed between the second gate structure and the third source/drain features,

wherein each of the first plurality of interior spacer components has a first thickness along the first direction,

wherein each of the second plurality of interior spacer components has a second thickness along the second direction,

wherein the second thickness is greater than the first thickness.

10. A semiconductor device, comprising:

a high density transistor comprising:

a first gate structure and a second gate structure defining a first pitch, an

A first source/drain contact disposed between the first gate structure and the second gate structure along a first direction; and

a high voltage transistor, comprising:

third and fourth gate structures defining a second pitch greater than the first pitch, an

A second source/drain contact disposed between the third gate structure and the fourth gate structure along a second direction,

wherein the first source/drain contact is spaced apart from the first gate structure by a first distance,

wherein the second source/drain contact is spaced apart from the third gate structure by a second distance, the second distance being greater than the first distance.

Technical Field

Embodiments of the present application relate to a semiconductor device.

Background

The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have resulted in generations of ICs, where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, the functional density (i.e., the number of interconnected devices per unit of chip area) is generally increasing as the geometry (i.e., the smallest component (or line) that can be created using a fabrication process) decreases. Such a scale-down process typically provides many benefits by increasing yield efficiency and reducing associated costs. This scaling down process also increases the complexity of processing and manufacturing the IC.

For example, as Integrated Circuit (IC) technology moves toward smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing Short Channel Effects (SCE). Multi-gate devices generally refer to devices having a gate structure or a portion thereof disposed over more than one side of a channel region. Fin field effect transistors (finfets) and multi-bridge channel (MBC) transistors are examples of multi-gate devices that have become popular and promising candidates for high-performance and low-leakage applications. The raised channel of a FinFET is surrounded by a gate on more than one side (e.g., the gate surrounds the top and sidewalls of a "fin" of semiconductor material extending from the substrate). The gate structure of the MBC transistor may extend partially or fully around the channel region to provide access to two or more sides of the channel region. Since the gate structure of the MBC transistor surrounds the channel region, the MBC transistor may also be referred to as a wrap gate transistor (SGT) or a full Gate All Around (GAA) transistor. The channel region of the MBC transistor may be formed by a nanowire, nanosheet, or other nanostructure, and for this reason, the MBC transistor may also be referred to as a nanowire transistor or a nanosheet transistor.

The size reduction achieved by the implementation of multi-gate devices also reduces the spacing between the gate structures and the source/drain contacts, which may increase parasitic capacitance and reduce switching speed. While conventional multi-gate device structures are generally adequate for their intended purposes, they are not satisfactory in all respects.

Disclosure of Invention

In some embodiments, a semiconductor device includes: a first transistor located in a first device region of a substrate, the first transistor comprising: a first source/drain feature and a second source/drain feature, a first plurality of channel members sandwiched between the first source/drain feature and the second source/drain feature, a first gate structure surrounding each of the first plurality of channel members, a first source/drain contact disposed above the first source/drain feature, and a first top gate spacer disposed between the first gate structure and the first source/drain contact; and a second transistor located in a second device region of the substrate, the second transistor comprising: a third source/drain feature and a fourth source/drain feature, a second plurality of channel members sandwiched between the third source/drain feature and the fourth source/drain feature, a second gate structure wrapped around each of the second plurality of channel members, a second source/drain contact disposed over the third source/drain feature, and a second top gate spacer disposed between the second gate structure and the second source/drain contact, wherein a distance between the second top gate spacer and the second source/drain contact is greater than a distance between the first top gate spacer and the first source/drain contact.

In some embodiments, a semiconductor device includes: a first transistor comprising: a first source/drain feature and a second source/drain feature, a first plurality of channel members sandwiched between the first source/drain feature and the second source/drain feature along a first direction, a first gate structure wrapped around each of the first plurality of channel members, and a first plurality of internal spacer features disposed between the first gate structure and the first source/drain feature; and a second transistor including: a third source/drain feature and a fourth source/drain feature, a second plurality of channel members sandwiched between the third source/drain feature and the fourth source/drain feature along a second direction, a second gate structure surrounding each of the second plurality of channel members, and a second plurality of internal spacer features disposed between the second gate structure and the third source/drain feature, wherein each of the first plurality of internal spacer features has a first thickness along the first direction, wherein each of the second plurality of internal spacer features has a second thickness along the second direction, wherein the second thickness is greater than the first thickness.

In some embodiments, a semiconductor device includes: a high density transistor comprising: first and second gate structures defining a first pitch, and a first source/drain contact disposed between the first and second gate structures along a first direction; and a high voltage transistor comprising: a third gate structure and a fourth gate structure defining a second pitch that is greater than the first pitch, and a second source/drain contact disposed between the third gate structure and the fourth gate structure along a second direction, wherein the first source/drain contact is spaced apart from the first gate structure by a first distance, wherein the second source/drain contact is spaced apart from the third gate structure by a second distance that is greater than the first distance.

Embodiments of the present application provide multi-gate device structures.

Drawings

The invention is best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 illustrates a layout diagram of a first device region of a semiconductor device in accordance with various aspects of the present disclosure.

Fig. 2 illustrates a layout diagram of a second device region of a semiconductor device in accordance with various aspects of the present disclosure.

Fig. 3 illustrates a partial cross-sectional view of a first device region taken along section a-a' in fig. 1, in accordance with various aspects of the present disclosure.

Fig. 4 illustrates a partial cross-sectional view of the second device region taken along section B-B' in fig. 2, in accordance with various aspects of the present disclosure.

Fig. 5 and 7 illustrate partial cross-sectional views of the first device region taken along section C-C in fig. 1, in accordance with various aspects of the present disclosure.

Fig. 6 and 8 illustrate partial cross-sectional views of the second device region taken along section D-D' in fig. 2, in accordance with various aspects of the present disclosure.

Fig. 9 illustrates a partial cross-sectional view of a third device region of a semiconductor device along an active region according to one or more aspects of the present disclosure.

Fig. 10 illustrates a layout diagram of a fourth device region of a semiconductor device in accordance with one or more aspects of the present disclosure.

Fig. 11 illustrates a layout view of a fifth device region of a semiconductor device in accordance with one or more aspects of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

For ease of description, spatial relational terms such as "below," "lower," "above," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such.

Further, when values or ranges of values are described with "about", "approximately", etc., the word is intended to cover the numbers within a reasonable range, given the variations inherently produced during manufacture as understood by one of ordinary skill in the art. For example, a value or range of values encompasses a reasonable range that includes the value, such as within +/-10% of the value, based on known manufacturing tolerances associated with manufacturing components having features associated with the value. For example, a material layer having a thickness of "about 5 nm" may cover a dimensional range of 4.25nm to 5.75nm, with manufacturing tolerances associated with depositing the material layer known to those of ordinary skill in the art to be +/-15%. Additionally, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The present disclosure relates generally to multi-gate transistors, and more particularly to source/drain contacts of multi-gate transistors.

MBC transistors allow aggressive gate length scaling to improve performance and density. To meet various design requirements in mobile devices, communication networks, High Performance Computing (HPC), Artificial Intelligence (AI), Virtual Reality (VR), big data applications, IC chips may include different types of devices working in concert. These different types of devices may include high density devices, high voltage devices, low leakage devices, high performance devices, and high bandwidth devices. Implementing different types of MBC transistors in one chip requires an overall solution rather than block-wise optimization.

The present disclosure provides embodiments of various types and combinations of MBC transistors for different functions and applications. For example, the present disclosure provides a structure of a first MBC transistor with a smaller gate length and pitch and source/drain contacts formed using self-aligned contact (SAC) technology. The present disclosure also provides a structure for a second MBC transistor with a larger gate length and pitch and non-SAC source/drain contacts. The first MBC transistor may be used for high density circuit applications. The second MBC transistor may be used for high voltage applications, such as drivers and controllers for electronic fuse devices.

Various aspects of the disclosure will now be described in more detail with reference to the figures. Fig. 1 illustrates a layout of a first device region 100-1 of a semiconductor device 100. Fig. 2 illustrates a layout diagram of the second device region 100-2 of the semiconductor device 100. Fig. 3 illustrates a partial cross-sectional view of the first device region 100-1 along section a-a 'in fig. 1, where section a-a' cuts through the first gate structure 120-1. Fig. 4 illustrates a partial cross-sectional view of the second device region 100-2 along section B-B 'in fig. 2, where section B-B' cuts through the second gate structure 120-2. Fig. 5 and 7 show partial cross-sectional views of the first device region 100-1 along section C-C 'in fig. 1, where section C-C' cuts through the first active region 110-1. Fig. 6 and 8 show partial cross-sectional views of the second device region 100-2 along section D-D 'in fig. 2, where section D-D' cuts through the third active region 110-3. Fig. 9 illustrates a partial cross-sectional view of the third device region 100-3 of the semiconductor device 100 along the active area. Fig. 10 illustrates a layout of the fourth device region 100-4 of the semiconductor device 100. Fig. 11 illustrates a layout of a fifth device region 100-5 of the semiconductor device 100. In fig. 1-11, the X, Y and Z directions are perpendicular to each other and are used consistently. Additionally, like reference numerals are used to refer to like parts throughout the present disclosure.

Referring first to fig. 1, a semiconductor device 100 is shown. Semiconductor device 100 includes and is fabricated on a substrate 102. In one embodiment, the substrate 102 may be a silicon (Si) substrate. In some other embodiments, the substrate 102 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or a III-V semiconductor material. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 102 may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure.

The semiconductor device 100 may include a plurality of well regions on a substrate 102. In the embodiments shown in fig. 1-4 and 10-11, semiconductor device 100 includes an N-type well region 102N (or N-well 102N) and a P-type well region 102P (or P-well 102P) for fabricating transistors of different conductivity types. Each of the N-well 102N and the P-well 102P is formed from the substrate 102 and includes a doping profile. The N-well 102N includes a doping profile of an N-type dopant, such As phosphorus (P) or arsenic (As). P-well 102P includes a doping profile of a P-type dopant, such as boron (B). Ion implantation or thermal diffusion may be used to form the doping of the N-well 102N and the P-well 102P, and a portion of the substrate 102 may be considered. Fig. 4 also shows an N-well 102N and a P-well 102P. As shown in fig. 1, the first device region 100-1 includes a first N-type MBC transistor 1000-1N located over a P-well 102P and a first P-type MBC transistor 1000-1P located over the N-well 102N. In fig. 2, the second device region 100-2 includes a second N-type MBC transistor 1000-2N located over the P-well 102P and a second P-type MBC transistor 1000-2P located over the N-well 102N. The third device region 100-3 shown in fig. 9 includes a third N-type MBC transistor 1000-3N located over the P-well 102P and a third P-type MBC transistor (not shown) located over the N-well 102N. As shown in fig. 10, the fourth device region 100-4 includes a fourth N-type MBC transistor 1000-4N located over the P-well 102P and a fourth P-type MBC transistor 1000-4P located over the N-well 102N. As shown in fig. 11, the fifth device region 100-5 includes a fifth N-type MBC transistor 1000-5N located over the P-well 102P and a fifth P-type MBC transistor 1000-5P located over the N-well 102N. Fig. 5 and 7 show a first N-type MBC transistor 1000-1N located over the P-well 102P. Fig. 6 and 8 show a second N-type MBC transistor 1000-2N located over the P-well 102P.

The semiconductor device 100 may include more than one device region, such as the first device region 100-1 shown in fig. 1, the second device region 100-2 shown in fig. 2, the third device region 100-3 shown in fig. 9, the fourth device region 100-4 shown in fig. 10, and the fifth device region 100-5 shown in fig. 11. As used herein, different device regions of semiconductor device 100 are suitable for different applications. In some embodiments, the MBC transistors in the first device region 100-1 are configured to have a high packing density and are suitable for high density circuit applications; the MBC transistors in the second device region 100-2 are configured to withstand high voltages and are suitable for high voltage applications; the MBC transistors in the third device region 100-3 are configured to have low parasitic capacitance and are suitable for high frequency circuit applications; the MBC transistors in the fourth device region 100-4 are suitable for low power applications; and the MBC transistors in the fifth device region 100-5 are configured to have low resistance and are suitable for high speed circuit applications. It should be noted that semiconductor device 100 may include different combinations of device regions to meet the design requirements of different specific circuits. For example, the semiconductor device 100 may include a first device region 100-1 and a third device region 100-3 to function as a serializer/deserializer circuit operating at a high frequency. For another example, the semiconductor device 100 may include a first device region 100-1 and a fourth device region 100-4 (or a fifth device region 100-5) to function as analog or low power circuits.

Referring again to fig. 1, the first device region 100-1 may include one or more active regions, such as a first active region 110-1 and a second active region 110-2. Each of the first active region 110-1 and the second active region 110-2 may be formed of a fin structure patterned from a stack of semiconductor layers. Such a stack may include a plurality of channel layers interleaved by a plurality of sacrificial layers. The channel layer and the sacrificial layer may have different semiconductor compositions. In some embodiments, the channel layer is formed of silicon (Si) and the sacrificial layer is formed of silicon germanium (SiGe). In these embodiments, the additional germanium content in the sacrificial layer allows for selective removal or notching of the sacrificial layer without substantial damage to the channel layer. In some embodiments, the sacrificial layer and the channel layer may be deposited using an epitaxial process, such as Vapor Phase Epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or Molecular Beam Epitaxy (MBE). Any number of sacrificial layers and channel layers may be formed in the stack to meet design requirements. As shown in fig. 3 to 9, the first, second, third, and fourth channel members 1081, 1082, 1083, and 1084 may be formed of a channel layer. In some embodiments, the channel member may include silicon (Si).

Referring to fig. 3 and 4, the active regions may be isolated from each other by an isolation member 106. The isolation features 106 may also be referred to as Shallow Trench Isolation (STI) features 106. In some embodiments, the isolation feature 106 may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorine doped silicate glass (FSG), low-k dielectrics, combinations thereof, and/or other suitable materials. The first gate structure 120-1 of fig. 1, 3, 5, and 7, the second gate structure 120-2 of fig. 2, 4, 6, and 8, the third gate structure 120-3 of fig. 9, the fourth gate structure 120-4 of fig. 10, and the fifth gate structure 120-5 of fig. 5 may be formed using a gate replacement or a gate last process. In the gate last process, a dummy gate stack is first formed over the channel region of the active region to serve as a placeholder for functional gate structures, such as the first gate structure 120-1, the second gate structure 120-2, the third gate structure 120-3, the fourth gate structure 120-4, and the fifth gate structure 120-5. The dummy gate stack includes a dummy dielectric layer and a dummy gate electrode. In some embodiments, the dummy dielectric layer comprises silicon oxide and the dummy gate electrode comprises polysilicon. After forming the dummy gate stack, gate spacers are formed along sidewalls of the dummy gate stack. The gate spacer layer may also be referred to as a top spacer or top gate spacer because the gate spacer is not disposed between the channel members but is disposed over the active region. The first device region 100-1 includes a first top spacer 122-1 shown in fig. 1, 3, 5, and 7 and a second top spacer 122-2 shown in fig. 2, 4, 6, and 8. The third device region 100-3 also includes a first top spacer 122-1. The fourth device region 100-4 and the fifth device region 100-5 include a second top spacer 122-2. The first top spacer 122-1, the second top spacer 122-2, and the third top spacer 122-3 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, porous oxide, and/or combinations thereof. The top spacer may include an air gap.

The gate structures, such as the first gate structure 120-1, the second gate structure 120-2, the third gate structure 120-3, the fourth gate structure 120-4, and the fifth gate structure 120-5, include a gate dielectric layer and a gate electrode. The gate dielectric layer includes an interfacial layer and a high-K dielectric layer. As used and described herein, a high-K gate dielectric includes a dielectric material having a high dielectric constant (e.g., a dielectric constant greater than thermal silicon oxide (approximately 3.9)). The interfacial layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. In one embodiment, the high-K dielectric layer may include hafnium oxide. Alternatively, the high-k dielectric layer may include other high-k dielectrics, such as titanium oxide (TiO)₂) Hafnium zirconium oxide (HfZrO), tantalum oxide (Ta)₂O₅) Hafnium silicon oxide (HfSiO)₄) Zirconium oxide (ZrO)₂) Zirconium oxide silicon (ZrSiO)₂) Lanthanum oxide (La)₂O₃) Alumina (Al)₂O₃) Zirconium oxide (ZrO), yttrium oxide (Y)₂O₃)、SrTiO₃(STO)、BaTiO₃(BTO), BaZrO, lanthanum hafnium oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), tantalum hafnium oxide (HfTaO), titanium hafnium oxide (HfTiO), (Ba, Sr) TiO₃(BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The gate electrode of the gate structure may comprise a single layer or alternatively a multi-layer structure such as various combinations of metal layers having selected work functions (work function metal layers), liners, wetting layers, adhesion layers, metal alloys or metal silicides that enhance device performance. For example, the gate electrode may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials or combinations thereof.

In some embodiments, the gate structure may include different work function layers for N-type MBC transistors (such as the first N-type MBC transistor 1000-1N, the second N-type MBC transistor 1000-2N, the third N-type MBC transistor 1000-3N, the fourth N-type MBC transistor 1000-4N, or the fifth N-type MBC transistor 1000-5N) and P-type MBC transistors (such as the first P-type MBC transistor 1000-1P, the second P-type MBC transistor 1000-2P, the third P-type MBC transistor, the fourth P-type MBC transistor 1000-4P, or the fifth P-type MBC transistor 1000-5P). Refer to fig. 3 and 4. N-type MBC transistors may be formed over the P-well 102P, and P-type MBC transistors may be formed over the N-well 102N. As shown in fig. 3 and 4, each of the first gate structure 120-1 and the second gate structure 120-2 is shared by an n-type MBC transistor and a p-type MBC transistor. In order to provide a desired threshold voltage for both devices, each of the first gate structure 120-1 and the second gate structure 120-2 may include two gate electrode portions. Referring first to fig. 3, the first gate structure 120-1 includes a gate dielectric layer 1202, a first gate electrode portion 1204 over the P-well 102P, and a second gate electrode portion 1206 over the N-well 102N. The first gate electrode portion 1204 includes an n-type work function layer, and the second gate electrode portion 1206 includes a p-type work function layer. The first gate electrode portion 1204 and the second gate electrode portion 1206 have different compositions and are formed separately. Similarly, the second gate structure 120-2 includes a gate dielectric layer 1202, a first gate electrode portion 1204 over the P-well 102P, and a second gate electrode portion 1206 over the N-well 102N. Along its length direction (Y-direction), the gate structure may terminate in a gate terminal dielectric member 140 as shown in fig. 1-4 and 10-11. In some embodiments, the gate terminal dielectric component 140 may be formed of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, porous oxide, and/or combinations thereof. The gate dielectric layer 1202 may have a thickness between about 3nm and 20 nm. In some embodiments, the gate dielectric layer 1202 has a uniform thickness in the first and second device regions 100-1 and 100-2. In some alternative embodiments, not explicitly shown in the figures, the gate dielectric layer in the second device region 100-2 is about 0.5nm and about 3nm thicker than the gate dielectric layer in the first device region 100-1.

An MBC transistor according to the present disclosure includes two source/drain features, a plurality of channel members extending between the two source/drain features, and a gate structure surrounding each channel member. A plurality of channel members are vertically stacked or arranged in the Z-direction. For example, the first gate structure 120-1 shown in FIG. 5 is wrapped around a first channel member 1081 that extends between two first N-type source/drain features 136N-1 (or two first N-type features 136N-1) along the X-direction. In some embodiments, first N-type component 136N-1 comprises silicon doped with an N-type dopant, such As phosphorus (P) or arsenic (As). The first N-type component 136N-1 is in contact with the first channel member 1081, but is spaced apart from the first gate structure 120-1 by the first interior spacer component 124-1. The first interior spacer component 124-1 interleaves the first channel members 1081. The first interior spacer component 124-1 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, porous oxide, and/or combinations thereof. Similarly, the second gate structure 120-2 shown in FIG. 6 is wrapped around a third channel member 1083 that extends between the two second N-type source/drain features 136N-2 (or the two second N-type features 136N-2) along the X-direction. In some embodiments, the second N-type component 136N-2 comprises silicon (Si) doped with an N-type dopant such As phosphorus (P) or arsenic (As). The second N-type component 136N-2 is in contact with the third channel member 1083, but is spaced apart from the second gate structure 120-2 by the second interior spacer component 124-2. The second interior spacer component 124-2 interleaves the third channel member 1083. The second interior spacer component 124-2 may be similar in composition to the first interior spacer component 124-1. As will be described below, the first interior spacer component 124-1 and the second interior spacer component 124-2 have different dimensions. Although not explicitly shown in the figures, the first device region 100-1 includes a second channel member 1082 (shown in fig. 3) extending between the two first p-type source/drain features, and the second device region 100-2 includes a fourth channel member 1084 (shown in fig. 4) extending between the two p-type source/drain features. The p-type source/drain features may include silicon germanium (SiGe) doped with a p-type dopant such as boron (B).

The first, second, third, fourth and fifth device regions 100-1, 100-2, 100-3, 100-4, 100-5 include source/drain contacts electrically coupled to source/drain features. During fabrication of the MBC transistor, the coupling to the channel member occurs after formation of the source/drain features. An interlayer dielectric (ILD) layer may be deposited over the source/drain features. In some embodiments, to control the etching of the source/drain contact openings, a Contact Etch Stop Layer (CESL) is deposited over the source/drain features prior to depositing the ILD layer. The source/drain contacts may be formed using a self-aligned contact (SAC) process or a non-SAC process. In a SAC process, source/drain contact openings are defined in a region surrounded by dielectric layers having different etch selectivity. In non-SAC processes, the source/drain contact openings are defined only by a photolithography process. Therefore, SAC processes are less dependent on the coverage of the photomask, whereas non-SAC processes are dependent on a satisfactory coverage of the photomask. An exemplary SAC process includes using a SAC dielectric layer, such as the gate SAC dielectric layer 150 shown in fig. 3-9. As described below, a SAC dielectric layer may be present when some source/drain contacts are formed using a non-SAC process when forming SAC source/drain contacts and non-SAC source/drain contacts on the same substrate. SAC processes reduce the spacing (i.e., distance) between the gate structure and the source/drain contacts and are suitable for forming contact structures for high density circuit applications where the gate pitch is tight. non-SAC processes increase the spacing (i.e., distance) between the gate structure and the source/drain contacts and are suitable for applications where gate-to-contact capacitance and contact-to-gate breakdown voltage are undesirable.

Source/drain contacts formed using a SAC process are shown in fig. 1, 5, 7, 10, and 11, while source/drain contacts formed using a non-SAC process are shown in fig. 2, 6, 8, and 9. Referring to fig. 1, 5 and 7, the first source/drain contact 130 is formed using a SAC process. In the embodiment shown in fig. 1 and 5, where CESL is not formed, the first source/drain contact 130 is sandwiched between two first top spacers 122-1 and between two gate SAC dielectric layers 150. That is, the first source/drain contact 130 is in direct contact with the gate SAC dielectric layer 150 and the first top spacer 122-1. In the embodiment shown in fig. 7, where the first CESL 156 is formed over the first N-type source/drain feature 136N-1, the first CESL 156 is disposed between the first source/drain contact 130 and the gate SAC dielectric feature 150 and between the first source/drain contact 130 and the first top spacer 122-1. In some embodiments, the first CESL 156 may include silicon nitride. Similarly, as shown in fig. 10 and 11, the fourth and fifth source/drain contacts 134 and 135 may be in contact with the first top spacer 122-1, either directly or indirectly, through a CESL (not shown). As shown in fig. 3-9, the source/drain contacts are coupled to the source/drain features through the silicide layer 138. In some embodiments, the silicide layer may comprise titanium silicide, cobalt silicide, or nickel silicide.

In the embodiment shown in fig. 2, 6 and 8, the second source/drain contact 132 extends through the first ILD layer 151 disposed between the two second top spacers 122-2 and between the two gate SAC dielectric layers 150. That is, the second source/drain contact 132 is spaced apart from the second top spacer 122-2 by the first ILD layer 151. In the embodiment shown in fig. 8, where the second CESL 158 is formed over the second N-type source/drain features 136N-2, the second CESL 158 is disposed between the first ILD layer 151 and the gate SAC dielectric features 150 and between the first ILD layer 151 and the second top spacers 122-2. Like the first CESL 156, the second CESL 158 may include silicon nitride. The first ILD layer 151 may comprise a low-k dielectric material such as Tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), Fused Silica Glass (FSG), phosphosilicate glass (PSG), boron doped silica glass (BSG), and the like. Similarly, as shown in fig. 9, the third source/drain contact 133 is spaced apart from the gate SAC dielectric layer 150 and the second top spacer 122-2 by the first ILD layer 151 and the second CESL 158. In some embodiments not explicitly shown, the third source/drain contact 133 may be spaced apart from the gate SAC dielectric layer 150 and the second top spacer 122-2 only by the first ILD layer 151 when the second CESL 158 is not formed.

Although the first CESL 156 and the second CESL 158 may have the same thickness when first deposited, the first CESL 156 and the second CESL 158 have different thicknesses in the final structure due to different source/drain contact formation processes. The first CESL 156 is subjected to an etching process during the SAC, while the second CESL 158 is not subjected to any etching process in the non-SAC process. As a result, the thickness of the second CESL 158 is greater than the thickness of the first CESL 156. In some embodiments, the thickness of the first CESL 156 in the X-direction may be between about 0.2nm and about 3 nm. In some embodiments, the thickness of the second CESL 158 in the X-direction may be between about 1.2nm and about 5 nm.

A gate contact via electrically couples the gate structure to the metal layer. In fig. 3, a first gate contact via 160 extends from the first gate structure 120-1 through the gate SAC dielectric layer 150, the second ILD layer 152 to couple to a metal line in the first metal layer 200, which includes an inter-metal dielectric (IMD) layer 154 surrounding the metal line. Similarly, a second gate contact via 162 extends from the second gate structure 120-2 through the gate SAC dielectric layer 150, the second ILD layer 152 to couple to a metal line in the first metal layer 200. The second ILD layer 152 and IMD layer 154 may have similar compositions as the first ILD layer 151. The first source/drain contact 130, the second source/drain contact 132, the first gate contact via 160, the second gate contact via 162, and the first metal layer 200 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), platinum (Pt), copper (Cu), aluminum (Al), ruthenium (Ru), tungsten (W), nickel (Ni), cobalt (Co), or a combination thereof. In some embodiments, the first source/drain contact 130, the second source/drain contact 132, the first gate contact via 160, the second gate contact via 162, and the first metal layer 200 may include a liner or barrier layer formed of a metal nitride (such as titanium nitride).

The MBC device structures in the first device region 100-1, the second device region 100-2, the third device region 100-3, the fourth device region 100-4, and the fifth device region 100-5 are further described in conjunction with fig. 1-11. Reference is again made to fig. 1. The first device region 100-1 includes a first source/drain contact 130 formed using a SAC process. With the first source/drain contact 130 in contact with the first top spacer 122-1, the first spacing S1 between the first source/drain contact 130 and the first top spacer 122-1 is substantially zero. Each first gate structure 120-1 extends in a length direction along the Y-direction and has a first gate length G1. Additionally, the first gate structures 120-1 in the first device region 100-1 have a first pitch P1. Second device region 100-2 in fig. 2 includes second source/drain contacts 132 formed using a non-SAC process. With the first ILD layer 151 present between the second top spacer 122-2 and the second source/drain contact 132, the second spacing S2 between the second source/drain contact 132 and the second top spacer 122-2 is greater than 5nm, such as between about 5nm and about 50 nm. Because the first spacing S1 is substantially zero, the difference between the second spacing S2 and the first spacing S1 may be between about 5nm and about 50 nm. In addition, because the MBC transistors in the second device region 100-2 are used for high voltage circuit applications, the second gate length G2 of the second gate structure 120-2 is greater than the first gate length G1 of the first gate structure. In some cases, the second gate length G2 is about 1.2 to about 5 times the first gate length G1. The presence of the first ILD layer 151 between the second top spacer 122-2 and the second source/drain contact 132 also causes the second pitch P2 to be about 1.4 times to about 4 times the first pitch P1. The presence of the larger second spacing S2 and the low-k first ILD layer 151 helps reduce gate-to-contact leakage or parasitic capacitance between the second gate structure 120-2 and the second source/drain contact 132. Fig. 7 and 8 illustrate embodiments of forming a first CESL 156 and a second CESL 158. As described above, since the second CESL 158 disposed along the sidewalls of the second top spacer 122-2 is not etched, the thickness of the second CESL 158 is greater than that of the first CESL 156.

Further, the non-SAC source/drain contacts may be larger than the SAC source/drain contacts to reduce resistance-capacitance (RC) delay. For example, the second contact dimension C2 of the second source/drain contact 132 shown in fig. 2, 6, and 8 is greater than the first contact dimension C1 of the first source/drain contact 130 shown in fig. 1, 5, and 7. In some embodiments, the ratio of the second contact dimension C2 to the first contact dimension C1 (C2/C1) is between about 1.2 and about 3. The larger second contact dimension C2 allows for larger source/drain contact vias, which may result in reduced resistance. For example, the source/drain contact via 170 above the second source/drain contact 132 may gain dimension in the X-direction because the second source/drain contact 132 has a larger second contact dimension C2. In some embodiments, the larger second contact dimension C2 allows the width or diameter (if circular) of the source/drain contact via 170 to be expanded by a factor of about 1.2 to about 4 as compared to the smaller first contact dimension C1. To improve the gate-contact breakdown voltage for high voltage applications, the second top spacer 122-2 in the second device region 100-2 is thicker than the first top spacer 122-1 in the first device region 100-1, and the second inner spacer component 124-2 in the second device region 100-2 is thicker than the first inner spacer component 124-1 in the first device region 100-1, along the X-direction. In some cases, the difference between the thickness of the second top spacer 122-2 and the thickness of the first top spacer 122-1 is between about 0.5nm and 5 nm. The first top spacer component 122-1 may have a thickness between about 3nm and about 12 nm. In some cases, the difference between the thickness of the second interior spacer component 124-2 and the thickness of the first interior spacer component 124-1 is between about 0.5nm and 5 nm. The first interior spacer component 124-1 may have a thickness between about 3nm and about 12 nm. The larger the second spacing S2 and the second contact dimension C2 naturally results in a wider source/drain feature along the X-direction. For example, the width of the second N-type source/drain feature 136N-2 is greater than the width of the first N-type source/drain feature 136N-1.

In some embodiments, the height of the source/drain features along the Z-direction may be different depending on the formation process of the source/drain contacts. When a SAC process is used to form the first source/drain contact 130, as shown in fig. 5 and 7, the first N-type source/drain feature 136N-1 has a first height H1. When a non-SAC process is used to form second source/drain contact 132, first N-type source/drain feature 136N-1 has a second height H2, as shown in fig. 6 and 8. To accommodate the SAC process, the first N-type source/drain feature 136N-1 is deposited until it is higher than the topmost first channel member 1081 to reduce the aspect ratio when forming the contact opening for the first source/drain contact 130. Conversely, the second N-type source/drain feature 136N-2 may be coplanar with the topmost third channel member 1083 or lower to increase the source/drain-gate breakdown voltage. In these embodiments, the first height H1 is greater than the second height H2.

Refer to fig. 3 and 4. To accommodate the lower hole mobility in the channel members and provide improved Complementary Metal Oxide Semiconductor (CMOS) transistor performance, the first channel member 1081, the second channel member 1082, the third channel member 1083 and the fourth channel member 1084 may have different channel widths along the Y-direction. As shown in fig. 3, in the first device region 100-1, each first channel member 1081 may have a first channel width W1, and each second channel member 1082 may have a second channel width W2. In some embodiments, the second channel width W2 of the P-type MBC transistor over the N-well 102N is greater than the first channel width W1 of the N-type MBC transistor over the P-well 102P. In some cases, the ratio of the second channel width W2 to the first channel width W1 (W2/W1) is between about 1.05 and about 2. The lower end of this range accounts for about 5% of process variation. This means that a W2/W1 ratio of between 1 and 1.05 may not indicate that the second channel width W2 is intended to be greater than the first channel width W1. The W2/W1 ratio cannot exceed about 2 because such a difference in width may require a significant amount of over-etching to release the channel member having the second channel width W2, and such over-etching may undesirably reduce the thickness of the channel member having the first channel width W1. As shown in fig. 4, in the first device region 100-1, each third channel member 1083 may have a third channel width W3, and each fourth channel member 1084 may have a fourth channel width W4.

In some embodiments, the fourth channel width W4 of the P-type MBC transistor over the N-well 102N is greater than the third channel width W3 of the N-type MBC transistor over the P-well 102P. In some cases, a ratio of the fourth channel width W4 to the third channel width W3 (W2/W1) is between about 1.05 and about 2. The lower end of this range accounts for about 5% of process variation. This means that a W4/W3 ratio of between 1 and 1.05 may not indicate that the fourth channel width W4 is intended to be greater than the third channel width W3. The W4/W3 ratio cannot exceed about 2 because such a difference in width may require a significant amount of over-etching to release the channel member having the fourth channel width W4, and such over-etching may undesirably reduce the thickness of the channel member having the third channel width W3. In addition, the channel width of the second device region 100-2 may be equal to or greater than the first device region 100-1 to accommodate the greater drive current associated with high voltage applications. In some cases, the ratio of the third channel width W3 to the first channel width W1 may be between about 1 and about 3. In some cases, the ratio of the fourth channel width W4 to the second channel width W2 may be between about 1 and about 3. The channel thickness and the channel spacing in the Z direction of the first, second, third, and fourth channel members 1081, 1082, 1083, and 1084 may be substantially the same.

The MBC transistor in the first device region 100-1 or the second device region 100-2 may be used with a different structure of MBC transistors in the third device region 100-3 shown in fig. 9, the fourth device region 100-4 shown in fig. 10, or the fifth device region 100-5 shown in fig. 11. For ease of reference, the MBC transistor in the first device region 100-1 may be referred to as a first MBC transistor, the MBC transistor in the second device region 100-2 may be referred to as a second MBC transistor, the MBC transistor in the third device region 100-3 may be referred to as a third MBC transistor, the MBC transistor in the fourth device region 100-4 may be referred to as a fourth MBC transistor, and the MBC transistor in the fifth device region 100-5 may be referred to as a fifth MBC transistor. As described above, the first, second, third, fourth, and fifth MBC transistors may be n-type or p-type.

Referring now to fig. 9, a layout diagram of the third device region 100-3 is shown. The third MBC transistor in the third device region 100-3 is for high frequency circuit applications, which is sensitive to parasitic capacitance between the gate structure and the source/drain contacts. As shown in fig. 9, the third MBC transistor includes a third channel portion 1083 extending between two second N-type source/drain portions 136N-2. A third gate structure 120-3 surrounds each third channel member 1083. A third source/drain contact 133 is disposed over the second N-type source/drain feature 136N-2. The third source/drain contact 133 is formed using a non-SAC process and is spaced apart from the third gate structure 120-3 by a third spacing S3. The third source/drain contact 133 has a third contact dimension C3 along the X-direction. The third gate structure 120-3 has a third gate length G3 and a third pitch P3. Since the third MBC transistor is not used for high voltage applications, the third gate length G3 is less than the second gate length G2 and may be similar to the first gate length G1. In some cases, the ratio of the second gate length G2 to the third gate length G3 may be between 1.2 and about 2. To increase the gate-contact spacing, the third pitch P3 may be similar to the second pitch P2. The third interval S3 may be similar to the second interval S2. In some cases, the third spacing S3 is greater than 5nm, such as between about 5nm and about 50 nm. The third contact dimension C3 is greater than the first contact dimension S1. In some embodiments, the ratio of the third contact dimension C3 to the first contact dimension C1 may be greater than 1.4, such as between about 1.4 and about 2.

As shown in fig. 10, the fourth MBC transistor includes a fourth gate structure 120-4 disposed between two fourth source/drain contacts 134. The fourth source/drain contact 134 is formed using a SAC process and is in contact with the fourth top spacer 122-4. That is, the fourth source/drain contact 134 is spaced apart from the fourth top spacer 122-4 by a first spacing S1 that is substantially zero. The fourth source/drain contact 134 has a fourth contact dimension C4 along the X-direction. The fourth gate structure 120-4 has a fourth gate length G4 and a fourth pitch P4. The fourth MBC transistor is used for low power circuit applications. The fourth gate length G4 is greater than the first gate length G1. In some embodiments, the ratio of the fourth gate length G4 to the first gate length G1 may be between about 1.1 and about 1.5. Similarly, the ratio of the fourth pitch P4 to the first pitch P1 may be between about 1.1 and 1.5. When the ratio of the fourth pitch P4 to the first pitch P1 is less than 1.1 (i.e., differs by 10%), the gain of the source off current (Isoff) may be small, and it cannot be justified to implement a different gate pitch. When the ratio of the fourth pitch P4 to the first pitch P1 is greater than 1.5, the on current (Ion) may deteriorate too much to meet the design requirements of advanced device nodes. The fourth top spacer 122-4 may be similar to the first top spacer 122-1.

As shown in fig. 11, the fifth MBC transistor includes a fifth gate structure 120-5 disposed between two fifth source/drain contacts 135. A fifth source/drain contact 135 is formed using a SAC process and is in contact with the fifth top spacer 122-5. That is, the fifth source/drain contact 135 is spaced apart from the fifth top spacer 122-5 by a first spacing S1 that is substantially zero. The fifth source/drain contact 135 has a fifth contact dimension C5 along the X-direction. The fifth gate structure 120-5 has a fifth gate length G5 and a fifth pitch P5. The fifth MBC transistor is used for high speed circuit applications. The fifth gate length G5 may be similar to the first gate length G1. Similarly, the ratio of the fifth pitch P5 to the first pitch P1 may be between about 1.1 and 1.5. When the ratio of the fifth pitch P5 to the first pitch P1 is less than 1.1 (i.e., differs by 10%), the gain of the source off current (Isoff) may be small, and it cannot be justified to implement a different gate pitch. When the ratio of the fifth pitch P5 to the first pitch P1 is greater than 1.5, the on current (Ion) may deteriorate too much to meet the design requirements of advanced device nodes.

In some embodiments, the semiconductor device 100 may include a first MBC transistor in the first device region 100-1 and a third MBC transistor in the third device region 100-3 to function as a serializer/deserializer circuit operating at high frequencies. In some other embodiments, the semiconductor device 100 may include a first MBC transistor in the first device region 100-1 and a fourth MBC transistor in the fourth device region 100-4 (or a fifth MBC transistor in the fifth device region 100-5) to function as an analog or low power circuit.

Although not intended to be limiting, one or more embodiments of the present invention provide many benefits to semiconductor devices and the formation thereof. For example, the present disclosure provides a structure of a first MBC transistor having a smaller gate length and pitch and source/drain contacts formed using a self-aligned contact (SAC) process and a second MBC transistor having a larger gate length and pitch and non-SAC source/drain contacts. The first MBC transistor allows for dense packaging, suitable for high density circuit applications. The second MBC transistor has a larger gate-contact spacing to improve breakdown voltage and parasitic capacitance, suitable for high voltage applications, such as drivers and controllers for electronic fuse devices. The present disclosure also provides a third MBC transistor suitable for high frequency applications, a fourth MBC transistor suitable for low power applications, and a fifth MBC transistor suitable for high speed applications.

In one exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device includes a first transistor in a first device region of a substrate and a second transistor in a second device region of the substrate. The first transistor includes a first source/drain feature and a second source/drain feature, a first plurality of channel members sandwiched between the first source/drain feature and the second source/drain feature, a first gate structure surrounding each of the first plurality of channel members, a first source/drain contact disposed over the first source/drain feature, and a first top gate spacer disposed between the first gate structure and the first source/drain contact. The second transistor includes a third source/drain feature and a fourth source/drain feature, a second plurality of channel members sandwiched between the third source/drain feature and the fourth source/drain feature, a second gate structure surrounding each of the second plurality of channel members, a second source/drain contact disposed over the third source/drain feature, and a second top gate spacer disposed between the second gate structure and the second source/drain contact. The distance between the second top gate spacer and the second source/drain contact is greater than the distance between the first top gate spacer and the first source/drain contact.

In some embodiments, each of the first plurality of channel members extends in a first direction, each of the second plurality of channel members extends in a second direction, the first top gate spacer has a first thickness in the first direction, the second top gate spacer has a second thickness in the second direction, and the second thickness is greater than the first thickness. In some embodiments, the first transistor further comprises a first etch stop layer disposed between the first source/drain contact and the first top gate spacer, and the second transistor further comprises a second etch stop layer and a low-k dielectric layer disposed between the second source/drain contact and the second top gate spacer. In some cases, the first etch stop layer is in direct contact with the first source/drain contact and the first top gate spacer. In some embodiments, the second etch stop layer is in direct contact with the second top gate spacer and the low-k dielectric layer. In some embodiments, the first etch stop layer has a thickness less than a thickness of the second etch stop layer. In some cases, the first and second etch stop layers comprise silicon nitride and the low-k dielectric layer comprises silicon oxide. In some embodiments, the first device region is a high density device region and the second device region is a high voltage device region. In some embodiments, the first gate structure includes a first gate length and the second gate structure includes a second gate length greater than the first gate length.

In another exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device includes a first transistor and a second transistor. The first transistor includes a first source/drain feature and a second source/drain feature, a first plurality of channel members sandwiched between the first source/drain feature and the second source/drain feature along a first direction, a first gate structure surrounding each of the first plurality of channel members, and a first plurality of internal spacer features disposed between the first gate structure and the first source/drain feature. The second transistor includes third and fourth source/drain features, a second plurality of channel members sandwiched between the third and fourth source/drain features along the second direction, a second gate structure surrounding each of the second plurality of channel members, and a second plurality of internal spacer features disposed between the second gate structure and the third source/drain feature. Each of the first plurality of interior spacer components has a first thickness in a first direction, each of the second plurality of interior spacer components has a second thickness in a second direction, and the second thickness is greater than the first thickness.

In some embodiments, the first plurality of channel members are interleaved with the first plurality of interior spacer features. In some cases, a width of the first source/drain feature along the first direction is less than a width of the third source/drain feature along the second direction. In some embodiments, the first transistor may further include a first source/drain contact over the first source/drain feature and a first top spacer disposed along sidewalls of the first gate structure over the first plurality of channel members. The second transistor may further include a second source/drain contact over the third source/drain feature and a second top spacer disposed along sidewalls of the second gate structure over the second plurality of channel members. The distance between the first source/drain contact and the first top spacer is less than the distance between the second source/drain contact and the second top spacer. In some embodiments, the first source/drain contact includes a third width (W3) along the first direction, the second source/drain contact includes a fourth width (W4) along the second direction, and the fourth width (W4) is greater than the third width (W3). In some cases, a ratio of the fourth width to the third width (W4/W3) is between about 1.2 and 3.0.

In yet another exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device includes a high-density transistor and a high-voltage transistor. The high density transistor includes first and second gate structures defining a first pitch and a first source/drain contact disposed between the first and second gate structures along a first direction. The high voltage transistor includes third and fourth gate structures defining a second pitch that is greater than the first pitch and a second source/drain contact disposed between the third and fourth gate structures along the second direction. The first source/drain contact is spaced apart from the first gate structure by a first distance. The second source/drain contact is spaced apart from the third gate structure by a second distance, the second distance being greater than the first distance.

In some embodiments, the high-density transistor further comprises a first contact via over the first source/drain contact, the high-voltage transistor further comprises a second contact via over the second source/drain contact, and a width of the first contact via in the first direction is less than a width of the second contact via in the second direction. In some embodiments, the semiconductor device may further include a substrate, and the high-density transistor further includes a first plurality of channel members stacked in a third direction away from the substrate and a first source/drain feature in contact with the first plurality of channel members. In some cases, the high voltage transistor further includes a second plurality of channel members stacked in the third direction and a second source/drain feature in contact with the second plurality of channel members. The first source/drain feature is taller in the third direction than a topmost channel member of the first plurality of channel members. The second source/drain feature is substantially flush with a topmost channel member of the second plurality of channel members along the third direction. In some cases, the high-density transistor further includes a first etch stop layer disposed between the first source/drain contact and the first gate structure, the high-voltage transistor further includes a second etch stop layer disposed between the second source/drain contact and the third gate structure, and a thickness of the second etch stop layer in the second direction is greater than a thickness of the first etch stop layer in the first direction. In some cases, the first etch stop layer is in contact with the first source/drain contact and the second etch stop layer is spaced apart from the second source/drain contact by an interlayer dielectric layer.

In some embodiments, a semiconductor device includes: a first transistor located in a first device region of a substrate, the first transistor comprising: a first source/drain feature and a second source/drain feature, a first plurality of channel members sandwiched between the first source/drain feature and the second source/drain feature, a first gate structure surrounding each of the first plurality of channel members, a first source/drain contact disposed above the first source/drain feature, and a first top gate spacer disposed between the first gate structure and the first source/drain contact; and a second transistor located in a second device region of the substrate, the second transistor comprising: a third source/drain feature and a fourth source/drain feature, a second plurality of channel members sandwiched between the third source/drain feature and the fourth source/drain feature, a second gate structure wrapped around each of the second plurality of channel members, a second source/drain contact disposed over the third source/drain feature, and a second top gate spacer disposed between the second gate structure and the second source/drain contact, wherein a distance between the second top gate spacer and the second source/drain contact is greater than a distance between the first top gate spacer and the first source/drain contact. In some embodiments, each of the first plurality of channel members extends in a first direction, wherein each of the second plurality of channel members extends in a second direction, wherein the first top gate spacer has a first thickness in the first direction, wherein the second top gate spacer has a second thickness in the second direction, and wherein the second thickness is greater than the first thickness. In some embodiments, the first transistor further comprises a first etch stop layer disposed between the first source/drain contact and the first top gate spacer, wherein the second transistor further comprises a second etch stop layer and a low-k dielectric layer disposed between the second source/drain contact and the second top gate spacer. In some embodiments, a first etch stop layer is in direct contact with the first source/drain contact and the first top gate spacer. In some embodiments, a second etch stop layer is in direct contact with the second top gate spacer and the low-k dielectric layer. In some embodiments, the first etch stop layer has a thickness less than a thickness of the second etch stop layer. In some embodiments, the first etch stop layer and the second etch stop layer comprise silicon nitride, wherein the low-k dielectric layer comprises silicon oxide. In some embodiments, the first device region is a high density device region, wherein the second device region is a high voltage device region. In some embodiments, the first gate structure comprises a first gate length, wherein the second gate structure comprises a second gate length greater than the first gate length.

In some embodiments, a semiconductor device includes: a first transistor comprising: a first source/drain feature and a second source/drain feature, a first plurality of channel members sandwiched between the first source/drain feature and the second source/drain feature along a first direction, a first gate structure wrapped around each of the first plurality of channel members, and a first plurality of internal spacer features disposed between the first gate structure and the first source/drain feature; and a second transistor including: a third source/drain feature and a fourth source/drain feature, a second plurality of channel members sandwiched between the third source/drain feature and the fourth source/drain feature along a second direction, a second gate structure surrounding each of the second plurality of channel members, and a second plurality of internal spacer features disposed between the second gate structure and the third source/drain feature, wherein each of the first plurality of internal spacer features has a first thickness along the first direction, wherein each of the second plurality of internal spacer features has a second thickness along the second direction, wherein the second thickness is greater than the first thickness. In some embodiments, a first plurality of channel members is interleaved with the first plurality of interior spacer features. In some embodiments, a width of the first source/drain feature along the first direction is less than a width of the third source/drain feature along the second direction. In some embodiments, the first transistor further comprises: a first source/drain contact located above the first source/drain feature, and a first top spacer disposed along a sidewall of the first gate structure on the first plurality of channel members, wherein the second transistor further comprises: a second source/drain contact located over the third source/drain feature, and a second top spacer disposed along a sidewall of the second gate structure on the second plurality of channel members, wherein a distance between the first source/drain contact and the first top spacer is less than a distance between the second source/drain contact and the second top spacer. In some embodiments, the first source/drain contact includes a third width (W3) along the first direction, wherein the second source/drain contact includes a fourth width (W4) along the second direction, and wherein the fourth width (W4) is greater than the third width (W3). In some embodiments, a ratio of the fourth width to the third width (W4/W3) is between about 1.2 and 3.0.

In some embodiments, a semiconductor device includes: a high density transistor comprising: first and second gate structures defining a first pitch, and a first source/drain contact disposed between the first and second gate structures along a first direction; and a high voltage transistor comprising: a third gate structure and a fourth gate structure defining a second pitch that is greater than the first pitch, and a second source/drain contact disposed between the third gate structure and the fourth gate structure along a second direction, wherein the first source/drain contact is spaced apart from the first gate structure by a first distance, wherein the second source/drain contact is spaced apart from the third gate structure by a second distance that is greater than the first distance. In some embodiments, the high-density transistor further comprises a first contact via over the first source/drain contact, wherein the high-voltage transistor further comprises a second contact via over the second source/drain contact, wherein a width of the first contact via along the first direction is less than a width of the second contact via along the second direction. In some embodiments, further comprising a substrate, wherein the high density transistor further comprises: a first plurality of channel members stacked in a third direction away from the substrate, and a first source/drain feature in contact with the first plurality of channel members, wherein the high voltage transistor further comprises: a second plurality of channel members stacked along the third direction, and a second source/drain feature in contact with the second plurality of channel members, and wherein the first source/drain feature is taller in the third direction than a topmost channel member of the first plurality of channel members, wherein the second source/drain feature is substantially flush with the topmost channel member of the second plurality of channel members along the third direction. In some embodiments, the high-density transistor further comprises a first etch stop layer disposed between the first source/drain contact and the first gate structure, wherein the high-voltage transistor further comprises a second etch stop layer disposed between the second source/drain contact and the third gate structure, wherein a thickness of the second etch stop layer in the second direction is greater than a thickness of the first etch stop layer in the first direction. In some embodiments, a first etch stop layer is in contact with the first source/drain contact, wherein the second etch stop layer is spaced apart from the second source/drain contact by an interlayer dielectric layer.

The components of several embodiments are discussed above so that those skilled in the art may better understand the various embodiments of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.