阅读说明：本技术 半导体器件及其形成方法 (Semiconductor device and method of forming the same ) 是由 陈奕寰 郑光茗 周建志 亚历山大卡尔尼斯基 刘思贤 袁焕之 于 2021-03-09 设计创作，主要内容包括：一种半导体器件及其形成方法。半导体器件包含位于衬底内的阱区。源极区和漏极区布置于阱区的相对侧上的衬底内。栅极电极布置于阱区上方,栅极电极具有布置于衬底的最顶部表面下方且在源极区与漏极区之间延伸的底部表面。沟槽隔离结构包围源极区、漏极区以及栅极电极。栅极介电结构将栅极电极与阱区、源极区、漏极区以及沟槽隔离结构分离。栅极电极结构具有中心部分和拐角部分。中心部分具有第一厚度,且拐角部分具有大于第一厚度的第二厚度。(A semiconductor device and a method of forming the same. The semiconductor device includes a well region located within a substrate. Source and drain regions are disposed within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, the gate electrode having a bottom surface arranged below a topmost surface of the substrate and extending between the source and drain regions. The trench isolation structure surrounds the source region, the drain region and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source region, the drain region, and the trench isolation structure. The gate electrode structure has a center portion and corner portions. The central portion has a first thickness and the corner portions have a second thickness greater than the first thickness.)

1. A semiconductor device, comprising:

the well region is positioned in the substrate;

a source region and a drain region disposed within the substrate on opposite sides of the well region;

a gate electrode disposed over the well region, the gate electrode comprising a bottom surface disposed below a topmost surface of the substrate and extending between the source and drain regions;

a trench isolation structure surrounding the source region, the drain region, and the gate electrode; and

a gate dielectric structure separating the gate electrode from the well region, the source region, the drain region, and the trench isolation structure,

wherein the gate dielectric structure includes a center portion having a first thickness and corner portions having a second thickness, and wherein the second thickness is greater than the first thickness.

2. The semiconductor device of claim 1, wherein the gate electrode extends in a first direction from the source region to the drain region, wherein the gate electrode extends in a second direction perpendicular to the first direction from a first side of the trench isolation structure to a second side of the trench isolation structure, and wherein the corner portions of the gate dielectric structure are disposed directly above and contact the first and second sides of the trench isolation structure.

3. The semiconductor device of claim 1, wherein the second thickness is at least three times the first thickness.

4. The semiconductor device of claim 1, wherein the corner portion of the gate dielectric structure has a third thickness measured in the same direction as the first and second thicknesses, and wherein the third thickness is greater than the first and second thicknesses.

5. The semiconductor device of claim 1, wherein a lower portion of the gate electrode disposed over the central portion of the gate dielectric structure is narrower than an upper portion of the gate electrode disposed over the corner portions of the gate dielectric structure.

6. A semiconductor device, comprising:

the well region is positioned in the substrate;

a source region and a drain region disposed within the substrate on opposite sides of the well region;

a gate electrode arranged within the substrate and directly between the source and drain regions;

a trench isolation structure continuously surrounding the source region, the drain region, and the gate electrode; and

a gate dielectric structure disposed on outer sidewalls and a bottom surface of the gate electrode,

wherein the gate dielectric structure comprises: a central portion having a first thickness; an inner corner portion having a second thickness, the second thickness being greater than the first thickness; and an external corner portion having a third thickness, the third thickness being greater than the second thickness, and

wherein the first thickness, the second thickness, and the third thickness are measured in a same direction from a bottommost surface of the gate dielectric structure.

7. The semiconductor device of claim 6, wherein the inner corner portions couple the central portion to the outer corner portions, wherein the outer corner portions overlie the trench isolation structures and the central portion extends between opposite sides of the trench isolation structures.

8. The semiconductor device of claim 6, wherein the gate dielectric structure comprises three dielectric layers.

9. A method, comprising:

forming a trench isolation structure to surround a well region of a substrate;

removing a portion of the substrate to form a recess in the substrate, wherein an outer sidewall of the recess is defined by the trench isolation structure;

forming a first gate dielectric layer over a surface of the recess in the substrate;

forming a second gate dielectric layer over the first gate dielectric layer;

performing a removal process to remove a central portion of the first gate dielectric layer and the second gate dielectric layer, wherein a portion of the first gate dielectric layer and a portion of the second gate dielectric layer remain on the trench isolation structure after the removal process;

forming a third gate dielectric layer over the surface of the recess in the substrate and over the second gate dielectric layer; and

a gate electrode is formed over the third gate dielectric layer.

10. The method of claim 9, wherein after the removing process, the first gate dielectric layer contacts a portion of the well region.

Technical Field

Embodiments of the invention relate to a semiconductor device and a method of forming the same.

Background

Many electronic devices contain numerous metal oxide semiconductor field-effect transistors (MOSFETs). The MOSFET includes a gate arranged between a source and a drain. MOSFETs may be classified as a High Voltage (HV) device, a Medium Voltage (MV) device, or a Low Voltage (LV) device depending on the magnitude of a voltage applied to a gate to turn on the MOSFET. The structural design parameters of each MOSFET in an electronic device vary depending on the desired electrical properties.

Disclosure of Invention

An embodiment of the present invention provides a semiconductor device, including: the well region is positioned in the substrate; a source region and a drain region disposed within the substrate on opposite sides of the well region; a gate electrode disposed over the well region, the gate electrode comprising a bottom surface disposed below a topmost surface of the substrate and extending between the source and drain regions; a trench isolation structure surrounding the source region, the drain region and the gate electrode; and a gate dielectric structure separating the gate electrode from the well region, the source region, the drain region, and the trench isolation structure, wherein the gate dielectric structure includes a central portion having a first thickness and corner portions having a second thickness, and wherein the second thickness is greater than the first thickness.

An embodiment of the present invention provides a semiconductor device, including: the well region is positioned in the substrate; a source region and a drain region disposed within the substrate on opposite sides of the well region; a gate electrode arranged within the substrate and directly between the source region and the drain region; a trench isolation structure continuously surrounding the source region, the drain region and the gate electrode; and a gate dielectric structure disposed on the outer sidewall and the bottom surface of the gate electrode, wherein the gate dielectric structure includes a central portion having a first thickness, inner corner portions having a second thickness greater than the first thickness, and outer corner portions having a third thickness greater than the second thickness, and wherein the first thickness, the second thickness, and the third thickness are measured in the same direction from a bottommost surface of the gate dielectric structure.

The embodiment of the invention provides a method, which comprises the following steps: forming a trench isolation structure to surround a well region of a substrate; removing a portion of the substrate to form a recess in the substrate, wherein an outer sidewall of the recess is defined by the trench isolation structure; forming a first gate dielectric layer over a surface of a recess in a substrate; forming a second gate dielectric layer over the first gate dielectric layer; performing a removal process to remove a central portion of the first gate dielectric layer and the second gate dielectric layer, wherein after the removal process, a portion of the first gate dielectric layer and a portion of the second gate dielectric layer remain on the trench isolation structure; forming a third gate dielectric layer over the surface of the recess in the substrate and over the second gate dielectric layer; and forming a gate electrode over the third gate dielectric layer.

Drawings

Aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A and 1B illustrate cross-sectional views of some embodiments of a recessed Metal Oxide Semiconductor Field Effect Transistor (MOSFET) including a gate dielectric structure having thicker corner portions than a central portion.

Fig. 2A and 2B show cross-sectional views of some alternative embodiments of the recessed MOSFET of fig. 1A and 1B, respectively.

Fig. 3 illustrates a cross-sectional view of some embodiments of a recessed MOSFET having a gate electrode surrounded by a gate dielectric structure and extending between source/drain regions.

Fig. 4 shows a top view of a recessed MOSFET including a gate dielectric structure having corner portions thicker than a central portion.

Fig. 5A and 5B illustrate cross-sectional views of some embodiments from another perspective of a recessed MOSFET including a gate dielectric structure having corner portions that are thicker than a central portion.

Fig. 6 illustrates a cross-sectional view of some embodiments of two recessed MOSFETs disposed on and within a substrate and including a gate dielectric structure having corner portions that are thicker than a central portion.

Fig. 7 shows a graph of current versus gate voltage when applied to a recessed MOSFET including a gate dielectric structure having corner portions that are thicker than a central portion.

Fig. 8A-8C, 9A-9C, and 10A-10C illustrate various views of some alternative embodiments of recessed MOSFETs including gate dielectric structures having thicker corner portions than a central portion.

Fig. 11A and 11B through 27A and 27B illustrate various views of some embodiments of methods of forming a recessed MOSFET including a gate dielectric structure having corner portions thicker than a central portion.

Fig. 28 illustrates a flow diagram of some embodiments of methods corresponding to the methods illustrated in fig. 11A and 11B through 27A and 27B.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) includes a gate electrode arranged between source and drain regions on a substrate. Further, a gate dielectric layer may be disposed between the gate electrode and the substrate. In Medium Voltage (MV) devices, the gate dielectric layer is thicker to withstand higher voltages without breaking down than in Low Voltage (LV) devices. However, a thicker gate dielectric layer may increase the overall height of the MV device compared to the LV device. Thus, some MV devices may utilize a recessed MOSFET, where the gate dielectric layer and gate electrode are recessed in a lateral direction below the topmost surface of the substrate and directly between the source and drain regions.

Although the recessed MOSFET reduces the height of the MV device, the reliability of the recessed MOSFET may be affected. For example, as the gate voltage applied to the gate electrode increases, the increase in current through the recessed MOSFET may not have a substantially constant slope as the voltage increases. In some cases, the inconsistent behavior of current versus voltage (vers) is due to the gate dielectric layer being thinner near the lower corners of the gate electrode beneath the recessed substrate, resulting in threshold voltages that differ at different regions of the gate electrode.

Various embodiments of the present disclosure are directed to forming a gate dielectric structure in a recessed MOSFET having an outer portion surrounding thicker corners of the gate electrode to improve predictability, controllability, and reliability of the overall recessed MOSFET. In such embodiments, thicker corners of the gate dielectric structure may be arranged at regions of the gate dielectric structure that directly contact the trench isolation structure and that are arranged at the corners of the source and drain regions. The trench isolation structure may continuously surround the recessed MOSFET, and the gate electrode may extend from a first side of the trench isolation structure to a second side of the trench isolation structure. In some embodiments, to increase the thickness of the corners of the gate dielectric structure, a second gate dielectric layer is formed over the first gate dielectric layer within the recess of the substrate. Then, the central portions of the first gate dielectric layer and the second gate dielectric layer are removed by photolithography and a removal process such that the remaining portions of the first gate dielectric layer and the second gate dielectric layer directly overlie the trench isolation structure. In some embodiments, a third dielectric layer is then formed over the second dielectric layer and the substrate. Thus, a majority of the gate dielectric structure has a first thickness of the third dielectric layer, while corner portions of the gate dielectric structure have a second thickness that is equivalent to the sum of the thicknesses of the first, second and third gate dielectric layers. The corner portions of the gate dielectric structure may prevent undesired current flow in the substrate below the corner portions. The reliability of the recessed MOSFET is improved as the thickness of the corner portions of the overlying trench isolation structure of the gate dielectric structure is increased.

Fig. 1A illustrates a cross-sectional view 100A of some embodiments of an integrated chip including a recessed Metal Oxide Semiconductor Field Effect Transistor (MOSFET) having a gate dielectric structure with thicker corner portions.

The cross-sectional view 100A of fig. 1A may be taken from the yz plane of the recessed MOSFET, while the source and drain regions of the recessed MOSFET may be seen in the xz plane (see fig. 3) perpendicular to the yz plane. The cross-sectional view 100A of fig. 1A includes a substrate 101. In some embodiments, the substrate 101 may be or include a semiconductor material (e.g., silicon, germanium, etc.), may be a silicon-on-insulator (SOI) substrate, or some other suitable substrate. In some embodiments, substrate 101 includes well region 102. Well region 102 may have a higher doping concentration and/or a different doping type than substrate 101. For example, in some embodiments, the substrate 101 may be undoped, while the well region 102 may have a first doping type (e.g., p-type) or a second doping type (e.g., n-type).

In some embodiments, trench isolation structure 104 is disposed within substrate 101 and surrounds well region 102 and/or a region of substrate 101. In some embodiments, the trench isolation structure 104 is a Shallow Trench Isolation (STI) structure such that the trench isolation structure 104 extends into the substrate 101 to a depth between the front side and the back side of the substrate 101. In other embodiments, the trench isolation structure 104 may be a full or deep trench isolation structure such that the trench isolation structure 104 extends completely or nearly completely through the thickness of the substrate 101. In some embodiments, the trench isolation structure 104 comprises a dielectric material such as silicon dioxide and prevents signals (e.g., current, voltage) of the recessed MOSFET from interfering with other devices on the substrate 101 outside the area of the well region 102 surrounded by the trench isolation structure 104.

In some embodiments, the gate electrode 108 is arranged within the substrate 101. In some embodiments, the gate electrode 108 extends in the y-direction from a first side of the trench isolation structure 104 to a second side of the trench isolation structure 104. In some embodiments, the spacer structures 110 may be arranged over the substrate 101. In some embodiments, the spacer structure 110 is primarily used during formation of the gate electrode 108 and/or other features of the recessed MOSFET. In some embodiments, the interconnect structure 112 is disposed over the substrate 101. In some embodiments, the interconnect structure 112 includes a contact via 116 and an interconnect line 118 within the interconnect dielectric structure 114. The interconnect structure 112 may provide a conductive path between the gate electrode 108 of the integrated chip and other devices.

In some embodiments, the gate electrode 108 has a topmost surface 108t that is approximately planar with the topmost surface 101t of the substrate 101. Thus, the bottommost surface 108b of the gate electrode 108 is arranged below the topmost surface 101t of the substrate 101. Since the gate electrode 108 is recessed below the substrate 101, the overall height of the recessed MOSFET can be reduced.

In some embodiments, the gate dielectric structure 106 is arranged on an outer surface and a lower surface of the gate electrode 108. The gate dielectric structure 106 may include: a central portion 106a covering a bottommost surface 108b of the gate electrode 108; and corner portions 106b surrounding the central portion 106a and arranged on the lower surface and the outer sidewalls of the gate electrode 108. In some embodiments, corner portions 106b of the gate dielectric structure 106 directly contact the trench isolation structure 104 and a portion of the well region 102 of the substrate 101. In some embodiments, the corner portions 106b of the gate dielectric structure 106 further include inner corner portions 106c and outer corner portions 106 d. In such embodiments, the inner corner portions 106c may couple the central portion 106a of the gate dielectric structure 106 to the outer corner portions 106 d.

In some embodiments, the central portion 106a of the gate dielectric structure 106 has a first thickness t₁(ii) a The internal corner portions 106c of the gate dielectric structure 106 have a thickness greater than the first thickness t₁Second thickness t₂(ii) a And the outer corner portions 106d of the gate dielectric structure 106 have a thickness approximately equal to or greater than the second thickness t₂Third thickness t₃. In such embodiments, the first thickness t₁A second thickness t₂And a third thickness t₃Are measured in the z-direction and from the bottommost surface of the gate dielectric structure 106. In some embodiments, the corner portions 106b of the gate dielectric structure 106 may comprise three gate dielectric layers, and the central portion 106a of the gate dielectric structure 106 may comprise one gate dielectric layer. In some embodiments, the gate dielectric layers comprising the gate dielectric structure 106 comprise the same or similar materials (e.g., oxides), and thus in the cross-sectional view 100A, it may be difficult to distinguish the individual gate dielectric layers of the gate dielectric structure 106. In some embodiments, the corner portions 106b have a greater thickness than the central portion 106a of the gate dielectric structure 106 to ensure a recessed MOSFET gateThe pole dielectric structure 106 has corner portions 106b that are sufficiently thick to reduce undesirable current flow in the substrate 101, thereby improving the predictability and reliability of the recessed MOSFET.

FIG. 1B illustrates a cross-sectional view 100B of an alternative embodiment of the cross-sectional view 100A of FIG. 1A, in which the layers of the gate electrode structure are depicted.

The gate dielectric structure 106 of fig. 1B includes a first gate dielectric layer 120, a second gate dielectric layer 122 disposed over the first gate dielectric layer 120, and a third gate dielectric layer 124. In some embodiments, the first gate dielectric layer 120, the second gate dielectric layer 122, and the third gate dielectric layer 124 comprise the same or similar materials, and thus, in fig. 1B, the interfaces between the first gate dielectric layer 120, the second gate dielectric layer 122, and the third gate dielectric layer 124 are shown by dashed lines. In some embodiments, the second gate dielectric layer 122 comprises a high temperature oxide material. In some embodiments, the corner portions 106b of the gate dielectric structure 106 include the first gate dielectric layer 120, the second gate dielectric layer 122, and the third gate dielectric layer 124, while the central portion 106a of the gate dielectric structure 106 includes the third gate dielectric layer 124, but not the first gate dielectric layer 122 and the second gate dielectric layer 124. Thus, in some embodiments, the first thickness t₁Equal to the thickness of the third gate dielectric layer 124. In some embodiments, the addition of the first and second gate dielectric layers 122, 124 increases the thickness of the gate dielectric structure 106 at the corner portions 106b of the gate dielectric structure 106.

In some embodiments, the sum of the thicknesses of first gate dielectric layer 120 and second gate dielectric layer 122 is equal to first thickness t₁And a second thickness t₂The difference between them. In some embodiments, the first thickness t₁And a second thickness t₂The difference between and the first thickness t₁Is in a range between, for example, approximately 1.5 and approximately 3. In some embodiments, the first thickness t₁And a second thickness t₂The difference between and the third thickness t₃Is in a range of, for example, between approximately 0.25 and approximately 0.33. In some embodiments, the first thicknessDegree t₁And a third thickness t₃For example, in a range between approximately 0.125 and approximately 0.18. In some embodiments, the second thickness t₂And a third thickness t₃For example, in a range between approximately 0.5 and approximately 1.

In some embodiments, the first gate dielectric layer 120 and the second gate dielectric layer 122 of the corner portion 106b of the gate dielectric structure 106 extend from the trench isolation structure 104 to a first distance d directly above the well region 102₁. In some embodiments, the first distance d₁May be in a range between approximately 0.1 microns and approximately 0.3 microns, for example. In some embodiments, the first gate dielectric layer 120 and the second gate dielectric layer 122 of the corner portion 106b of the gate dielectric structure 106 extend over the trench isolation structure 104 for a second distance d₂. In some embodiments, the first distance d₁A second distance d from₂For example, in a range between approximately 0.5 and approximately 2. In some embodiments, the third distance d₃Is measured between the outermost sidewalls of the gate dielectric structure 106, and a fourth distance d₄The opposing first gate dielectric layers 120 are separated. In some embodiments, the first distance d₁At a fourth distance d₄For example, in a range between approximately 0.01 and approximately 0.2. In some embodiments, the fourth distance d₄A third distance d from₃For example, in a range between approximately 0.9 and approximately 0.99.

Fig. 2A illustrates a cross-sectional view 200A of some other embodiments of a recessed MOSFET including a gate dielectric structure having thicker corner portions than a central portion.

In some embodiments, the gate electrode 108 has a bottommost surface 108b arranged below the topmost surface 101t of the substrate 101, and has a topmost surface 108t arranged above the topmost surface 101t of the substrate 101. In some such embodiments, the recessed MOSFET still has an overall reduced height because the gate electrode 108 has a bottommost surface 108b arranged below the topmost surface 101t of the substrate 101. In some embodiments, the spacer structure 110 is arranged on the topmost surface 101t of the substrate 101 and/or the gate dielectric structure 106, and directly contacts the outermost sidewalls of the gate electrode 108. Furthermore, in some embodiments, a silicide layer 202 may be arranged over the gate electrode 108 to improve the performance of the contact between the contact via 116 and the gate electrode 108.

In some embodiments, due to the corner portions 106b of the gate dielectric structure 106, the gate electrode 108 includes a lower portion 108L, the lower portion 108L being arranged directly on the central portion 106a of the gate dielectric structure 106 and having an outer sidewall surrounded by the inner corner portions 106c of the gate dielectric structure 106. Furthermore, in some embodiments, the gate electrode 108 includes an upper portion 108U disposed above the lower portion 108L, directly on the inner corner portions 106c of the gate dielectric structure 106 and having outer sidewalls surrounded by the outer corner portions 106d of the gate dielectric structure 106. In some embodiments, the upper portion 108U of the gate electrode 108 is wider than the lower portion 108L of the gate electrode 108. In some embodiments, the lower portion 108L of the gate electrode 108 may have a width measured in the y-direction and in a range between approximately 0.1 microns and approximately 100 microns, for example. Furthermore, in some embodiments, the upper portion 108U of the gate electrode 108 is thicker than the lower portion 108L of the gate electrode 108. In some other embodiments, the upper portion 108U of the gate electrode 108 may be thinner or about equal to the thickness of the lower portion 108L of the gate electrode 108.

In some embodiments, the gate electrode 108 may comprise, for example, polysilicon, aluminum, cobalt, ruthenium, or some other suitable conductive material. Furthermore, in some embodiments, the gate dielectric structure 106 may comprise, for example, silicon oxynitride, silicon dioxide, hafnium oxide, or some other suitable dielectric material. In some embodiments, the first thickness t of the gate dielectric structure 106₁May be in a range between approximately 100 angstroms and approximately 300 angstroms, for example. In some embodiments, the second thickness t of the gate dielectric structure 106₂May be in a range between approximately 300 angstroms and approximately 500 angstroms, for example. In some embodiments, the third thickness t of the gate dielectric structure 106₃May be in a range between approximately 0.08 microns and approximately 2 microns, for example. It will be appreciated that the first thickness t₁A second thickness t₂And a third thickness t₃Are also within the scope of the present disclosure.

Fig. 2B illustrates a cross-sectional view 200B of an alternative embodiment of the cross-sectional view 200A of fig. 2A, in which the layers of the gate electrode structure are depicted.

As shown in the cross-sectional view 200B of fig. 2B, in some embodiments, the first gate dielectric layer 120, the second gate dielectric layer 122, and the third gate dielectric layer 124 of the gate dielectric structure 106 may be distinguishable from one another. In some embodiments, the gate electrode 108 directly contacts only the third gate dielectric layer 124 of the gate dielectric structure 106.

Fig. 3 illustrates a cross-sectional view 300 of some embodiments of a recessed MOSFET out of the xz-plane.

In some embodiments, the xz plane is, for example, substantially perpendicular to the yz plane of fig. 1A and 2A. In some embodiments, the recessed MOSFET includes source/drain regions 302 arranged within the area of the substrate 101 defined by the trench isolation structure 104. In some embodiments, the source/drain regions 302 may have a doping type opposite the well region 102. In some embodiments, the source/drain region 302 is surrounded by a lightly doped region 304, wherein the lightly doped region 304 is doped with the same type but with a lower doping concentration than the source/drain region 302.

In some embodiments, in cross-sectional view 300, gate electrode 108 extends in the x-direction between source/drain regions 302 and is also recessed within substrate 101. In some embodiments, the interconnect structure 112 has contact vias 116 coupled to the source/drain regions 302 and the gate electrode 108. In some embodiments, the source/drain regions 302 are arranged directly between the gate electrode 108 and the trench isolation structure 104 in the x-direction. In some embodiments, the spacer structure 110 is arranged on the substrate 101 and directly contacts the outer sidewall of the gate electrode 108. In other embodiments, the gate electrode 108 has a topmost surface 108t that is substantially coplanar with the topmost surface 101t of the substrate 101, and thus the spacer structure 110 does not directly contact the gate electrode 108.

In some embodiments, the corner portions (106b) of the gate dielectric structure 106 are not visible from the cross-sectional view 300 on the xz-plane. In some embodiments, the gate dielectric structure 106 surrounds the bottom surface and the outer sidewalls of the gate electrode 108 as viewed in the xz-plane to prevent the gate electrode 108 from contacting the well region 102, the lightly doped region 304, and/or the source/drain region 302. In some embodiments, the gate dielectric structure 106 has a first thickness t as viewed in the xz-plane₁And thus the gate dielectric structure 106 disposed directly between the source/drain regions 302 may comprise a first thickness t₁A gate dielectric layer. In some such embodiments, the gate dielectric structure 106 includes the third gate dielectric layer 124, and the first and second gate dielectric layers (120, 122 of fig. 2A) are not visible from the xz plane. The gate dielectric structure 106 has a substantially uniform first thickness t surrounding the gate electrode 108 between the source/drain regions 302₁Such that the same "ON" gate voltage may be used to simultaneously "turn ON" the entire channel region under the gate electrode 108 to allow mobile charge carriers to move between the source/drain regions 302.

Fig. 4 illustrates a top view 400 of some embodiments of a recessed MOSFET transistor including a gate dielectric structure with thicker corner portions.

In some embodiments, cross-section line AA 'of fig. 2A may correspond to cross-section line AA' of fig. 4, and cross-section line BB 'of fig. 3 may correspond to cross-section line BB' of fig. 4.

The top view 400 of FIG. 4 shows: in some embodiments, the outer corner portion 106d of the gate dielectric structure 106 directly overlies the trench isolation structure 104. Furthermore, the inner corner portion 106c of the gate dielectric structure 106 is arranged below the gate electrode 108 and is not visible from the top view 400. Therefore, the inner corner portion 106c is shown by a dotted line in fig. 4 for easy understanding. In some embodiments, the inner corner portions 106c are disposed directly between outer portions of the source/drain regions 302. In some embodiments, any line extending through the source/drain regions 302 along the x-direction does not also extend through the outer corner portions 106d of the gate dielectric structure 106. In some other embodiments, the internal corner portions 106c are not arranged directly between the outer portions of the source/drain regions 302, and thus any line extending through the source/drain regions 302 along the x-direction does not also extend through the internal corner portions 106c of the gate dielectric structure 106.

Fig. 5A illustrates a cross-sectional view 500A of some embodiments of a recessed MOSFET transistor including a gate dielectric structure with thicker corner portions extending between isolation structures on the xz plane. In some embodiments, cross-sectional view 500A includes cross-sectional line CC 'corresponding to cross-sectional line CC' of fig. 4.

Cross-sectional line CC of fig. 4 extends through corner portion 106b of gate dielectric structure 106. Thus, in some embodiments, cross-sectional view 500A of figure 5A illustrates corner portions 106b extending between opposite sides of trench isolation structure 104. In other words, from some perspectives, the gate dielectric structure 106 continuously has the second thickness t as the gate dielectric structure 106 extends in the x-direction between the trench isolation structures 104₂。

Fig. 5B illustrates a cross-sectional view 500B of an alternative embodiment of the cross-sectional view 500A of fig. 5A, in which the layers of the gate electrode structure are depicted.

As shown in the cross-sectional view 500B of fig. 5B, in some embodiments, the first gate dielectric layer 120, the second gate dielectric layer 122, and the third gate dielectric layer 124 of the gate dielectric structure 106 may be distinguishable from one another and extend between opposite sides of the trench isolation structure 104 in the x-direction.

Fig. 6 illustrates a cross-sectional view 600 of some embodiments of a first recessed MOSFET flanking a second recessed MOSFET arranged on the yz plane.

In some embodiments, the integrated chip includes a first recessed MOSFET 602 disposed alongside a second recessed MOSFET 604. In some embodiments, the first recessed MOSFET 602 can be an n-type MOSFET, where the mobile charge carriers are electrons when the first recessed MOSFET 602 is "on". In such embodiments, the first recessed MOSFET 602 can have the first well region 102a that is p-type. In some embodiments, the second recessed MOSFET 604 can be a p-type MOSFET, where the mobile charge carriers are holes when the second recessed MOSFET 604 is "on". In such embodiments, the second recessed MOSFET 604 can have the second well region 102b that is n-type.

In some embodiments, the first and second recessed MOSFETs 602 and 604 include a gate dielectric structure 106 having corner portions 106b, the corner portions 106b having a greater thickness than the central portion 106 a. In some embodiments, the interconnect structure 112 further includes interconnect vias 620 and bonding pads 622. Other integrated chips and/or semiconductor devices may be coupled to the first recessed MOSFET 602 and/or the second recessed MOSFET 604 through the bond pads 622.

Fig. 7 illustrates a graph 700 of some embodiments of current versus gate voltage when applied to a recessed MOSFET having a gate dielectric structure with thicker corner portions than a central portion, as illustrated, for example, in fig. 1A-6.

Graph 700 shows exemplary data points 702 of the absolute value of the current in the recessed MOSFET as a function of increasing absolute value of the voltage applied to the gate electrode (108 of fig. 3). In some embodiments, when the gate voltage is equal to the transition voltage 704 and the first transition current 708 travels through the recessed MOSFET, current begins to flow through the recessed MOSFET. In some embodiments, as the gate voltage increases from the transition voltage 704, the current may increase at a substantially constant rate until the current reaches a saturation current 712 at a threshold voltage 706, with the channel region fully open under the gate electrode (108 of fig. 3) and between the source/drain regions (302 of fig. 3). In some embodiments, the threshold voltage 706 of the entire recessed MOSFET (e.g., at the cross-sectional view 200A of fig. 2A and at the cross-sectional view 300 of fig. 3) is substantially the same due to the corner portions (106b of fig. 2A) of the gate dielectric structure (106 of fig. 2A) in the recessed MOSFET, and thus the slope 710 of the example data point 702 is substantially constant between the first transition current 708 and the saturation current 712. A recessed MOSFET with a substantially constant slope 710 is more reliable than if the slope 710 varied between the first transition current 708 and the saturation current 712.

Fig. 8A-8C illustrate various views 800A-800C of some alternative embodiments of recessed MOSFETs having gate dielectric structures with corner portions that are thicker than the central portion.

As shown in the top view 800A of fig. 8A, in some embodiments, the corner portions 106b of the gate dielectric structure 106 do not extend continuously in the x-direction between the outermost portions of the gate dielectric structure 106.

Cross-sectional view 800B of fig. 8B illustrates some embodiments of the recessed MOSFET of fig. 8A from the yz plane. In some embodiments, cross-section line AA 'of fig. 8A corresponds to cross-section line AA' of fig. 8B. In other words, in some embodiments, the cross-sectional view 800B of fig. 8B corresponds to the cross-sectional line AA' of the top view 800A of fig. 8A. Further, the top view 800A of fig. 8A corresponds to the cross-sectional line AA' of fig. 8B.

As shown in the cross-sectional view 800B of fig. 8B, the cross-sectional line AA' of fig. 8A extends through the corner portion 106B of the gate dielectric structure 106. Thus, in some embodiments, the cross-sectional view 800B of fig. 8B includes the gate dielectric structure 106 having corner portions 106B, the corner portions 106B surrounding the central portion 106a and being thicker than the central portion 106 a.

Cross-sectional view 800C of fig. 8C illustrates some embodiments of the recessed MOSFET of fig. 8A from the xz plane. In some embodiments, cross-section line CC 'of fig. 8A corresponds to cross-section line CC' of fig. 8C. In other words, in some embodiments, the cross-sectional view 800C of fig. 8C corresponds to the cross-sectional line CC' of fig. 8A. Further, the top view 800A of fig. 8A corresponds to the cross-section line CC' of fig. 8C.

In some embodiments, has a second thickness t₂Extends completely between opposite sides of the trench isolation structure 104. However, in some embodiments, the corner portion 106b may not directly overlie the trench isolation structure 104 or only partially directly overlie the trench isolation structure 104. In some other embodiments, the trench isolation structure 104 is continuously buried throughout the gate dielectric structure 106 from the cross-sectional view 800C, xz-plane of fig. 8C.

In some embodiments, the first gate dielectric layer 120 and the second gate dielectric layer 122 are disposed directly between the third gate dielectric layer 124 and the well region 102. Furthermore, in some embodiments, third gate dielectric layer 124 surrounds the outermost sidewalls of first gate dielectric layer 120 and second gate dielectric layer 122 perpendicular to the x-direction as viewed from the xz-plane. In some such embodiments, a third gate dielectric layer 124 separates the first gate dielectric layer 120 and the second gate dielectric layer 122 from the trench isolation structure 104.

Fig. 9A-9C show various views 900A-900C of some other alternative embodiments of recessed MOSFETs having gate dielectric structures with corner portions that are thicker than the central portion.

As shown in the top view 900A of fig. 9A, in some embodiments, a plurality of corner portions 106b are arranged over the trench isolation structures 104. In some such embodiments, a line extending in the x-direction may intersect the plurality of corner portions 106 b.

In some embodiments, cross-section line AA 'of fig. 9A corresponds to cross-section line AA' of fig. 9B. In other words, in some embodiments, the cross-sectional view 900B of fig. 9B corresponds to the cross-sectional line AA' of the top view 900A of fig. 9A. Further, the top view 900A of fig. 9A corresponds to the cross-section line AA' of fig. 9B.

As shown in the cross-sectional view 900B of fig. 9B, the cross-sectional line AA' of fig. 9A extends in the y-direction through the corner portion 106B of the gate dielectric structure 106. Thus, in some embodiments, the cross-sectional view 900B of fig. 9B includes the gate dielectric structure 106 having corner portions 106B, the corner portions 106B surrounding the central portion 106a and being thicker than the central portion 106 a.

Cross-sectional diagram 900C of fig. 9C illustrates some embodiments of the recessed MOSFET of fig. 9A coming out of the xz plane. In some embodiments, cross-section line CC 'of fig. 9A corresponds to cross-section line CC' of fig. 9C. In other words, in some embodiments, cross-sectional view 900C of fig. 9C corresponds to cross-sectional line CC' of top view 900A of fig. 9A. Further, the top view 900A of fig. 9A corresponds to the cross-section line CC' of fig. 9C.

As shown in cross-sectional view 900C of fig. 9C, in some embodiments, a plurality of corner portions 106b of the gate dielectric structure 106 are arranged between opposite sides of the trench isolation structure 104 in the x-direction. In some embodiments, third gate dielectric layer 124 extends continuously between corner portions 106 b.

Fig. 10A-10C show various views 1000A-1000C of some other alternative embodiments of recessed MOSFETs having gate dielectric structures with corner portions that are thicker than the central portion.

As shown in top view 1000A of fig. 10A, in some embodiments, corner portions 106b of gate dielectric structure 106 include an additional inner corner portion 106e, wherein inner corner portion 106c is between outer corner portion 106d and additional inner corner portion 106 e. In some embodiments, the additional internal corner portions 106e are disposed directly between the source/drain regions 302, while in other embodiments, the additional internal corner portions 106e are not disposed directly between the source/drain regions 302. Furthermore, in some embodiments, additional internal corner portions 106e are arranged behind the gate electrode 108 and are thus shown by dashed lines, as seen from the top view 1000A of fig. 10A.

In some embodiments, cross-section line AA 'of fig. 10A corresponds to cross-section line AA' of fig. 10B. In other words, in some embodiments, the cross-sectional view 1000B of fig. 10B corresponds to the cross-sectional line AA' of the top view 1000A of fig. 10A. Further, the top view 1000A of fig. 10A corresponds to the cross-sectional line AA' of fig. 10B.

As shown in the cross-sectional view 1000B of fig. 10B, the cross-sectional line AA' of fig. 10A extends in the y-direction through the corner portion 106B of the gate dielectric structure 106. Thus, in some embodiments, the cross-sectional view 1000B of fig. 10B includes the gate dielectric structure 106 having corner portions 106B that surround the central portion 106a and are thicker than the central portion 106 a. Furthermore, in some embodiments, the gate dielectric structure 106 includes additional internal corner portions 106e, the additional internal corner portions 106e being thicker than the central portion 106a and the internal corner portions 106c of the gate dielectric structure 106. In some such embodiments, the additional inner corner portion 106e may comprise a thicker portion 122a of the second gate dielectric layer 122. In some such embodiments, additional inner corner portions 106e of the gate dielectric structure 106 may be arranged directly above the well region 102, rather than directly above the trench isolation structure 104. In some other embodiments, the additional inner corner portion 106e may directly overlie the trench isolation structure 104. In some embodiments, additional internal corner portions 106e are thicker than internal corner portions 106c, which further reduces undesired current flow in well region 102 of substrate 101.

The cross-sectional view 1000C of fig. 10C illustrates some embodiments of the recessed MOSFET of fig. 10A from the xz plane. In some embodiments, cross-section line CC 'of fig. 10A corresponds to cross-section line CC' of fig. 10C. In other words, in some embodiments, the cross-sectional view 1000C of fig. 10C corresponds to cross-sectional line CC' of the top view 1000A of fig. 10A. Further, the top view 1000A of fig. 10A corresponds to the cross-sectional line CC' of fig. 10C.

As shown in cross-sectional view 1000C of fig. 10C, in some embodiments, corner portion 106b includes, from the xz plane, a first gate dielectric layer 120, a second gate dielectric layer 122, and a third gate dielectric layer 124 that extend continuously between opposite sides of trench isolation structure 104. In some such embodiments, cross-section line CC of fig. 10A does not intersect additional interior corner portion 106e, and thus additional interior corner portions (106 e of fig. 10A) are not present in cross-section view 1000C of fig. 10C.

Fig. 11A and 11B through 27A and 27B illustrate various views 1100A and 1100B through 2700A and 2700B of some embodiments of a method of forming a recessed MOSFET having a gate dielectric structure with thicker corner portions than a central portion. Although fig. 11A and 11B-27A and 27B are described with respect to a method, it should be understood that the structure disclosed in fig. 11A and 11B-27A and 27B is not limited to this method, but may instead stand alone as a structure independent of the method.

As shown in cross-sectional view 1100A of fig. 11A, a substrate 101 is provided. In various embodiments, the substrate 101 may include any type of semiconductor body (e.g., silicon/CMOS bulk, SiGe, SOI, etc.), such as a semiconductor wafer or one or more dies on a wafer, as well as any other type of semiconductor material. In some embodiments, the trench isolation structure 104 may be formed within the substrate 101. The trench isolation structure 104 may be formed by selectively etching the substrate 101 to form a trench defined by sidewalls of the substrate 101. Subsequently, the trench is filled with one or more dielectric materials, such as silicon dioxide, thereby forming a trench isolation structure 104. In some embodiments, the trench isolation structure 104 continuously surrounds a region of the substrate 101. In some embodiments, cross-sectional view 1100A represents trench isolation structure 104 from an xz-plane and from a yz-plane perspective.

Fig. 11B illustrates a top view 1100B of some embodiments that may correspond to fig. 11A. In some embodiments, cross-section line AA' of fig. 11B corresponds to cross-section view 1100A of fig. 11A. The top view 1100B is in the xy plane. In some embodiments, the trench isolation structure 104 is a continuously connected ring-like structure within the substrate 101.

In the following fig. 12A to 27B, the "a" diagram represents a certain step in the method of forming a recessed MOSFET from a cross-sectional view on the yz plane, and the "B" diagram represents a certain step in the method of forming a recessed MOSFET from a cross-sectional view on the xz plane; and the "C" diagram represents a certain step in the method of forming a recessed MOSFET from a top view pattern on the xy plane. For example, the cross-sectional view 1200A of fig. 12A is on the yz plane, the cross-sectional view 1200B of fig. 12B is on the xz plane, and the top view 1200C of fig. 12C is on the xy plane. Further, fig. 12A, 12B and 12C show the same step of the method from different planes/perspectives.

As shown in cross-sectional view 1200A of fig. 12A, recesses 1202 are formed by photolithography and subsequent etching of the substrate 101 between the trench isolation structures 104. In some embodiments, an inner portion of trench isolation structure 104 is removed, and thus recess 1202 has outer sidewalls defined by trench isolation structure 104. In some embodiments, the depth of the recess 1202 is in a range between approximately 0.08 microns to approximately 2 microns, for example. Furthermore, in some embodiments, an ion implantation process is performed on substrate 101 to form well region 102 between trench isolation structures 104. In some embodiments, well region 102 also extends to under trench isolation structure 104 and/or beyond the outer sidewalls of trench isolation structure 104. In some embodiments, the well region 102 has a first doping type (e.g., n-type) or a second doping type (e.g., p-type).

As shown in cross-sectional view 1200B of fig. 12B, in some embodiments, the recess 1202 does not extend into the trench isolation structure 104. Thus, from the perspective of the xz plane, the recess 1202 has an outer sidewall defined by the substrate 101. Furthermore, in some embodiments, the recess 1202 is narrower in the x-direction than in the y-direction of fig. 12A.

As shown in top view 1200C of fig. 12C, in some embodiments, a recess 1202 extends between trench isolation structures 104 in the y-direction. From top view 1200C, dashed lines are used to define the outer sidewalls of recess 1202. In some embodiments, cross-sectional view 1200A of fig. 12A corresponds to cross-sectional line AA 'of fig. 12C, and cross-sectional view 1200B of fig. 12B corresponds to cross-sectional line BB' of fig. 12C.

As shown in cross-sectional view 1300A of fig. 13A, a first gate dielectric layer 120 is deposited on the surface of the recess 1202. In some embodiments, the first gate dielectric layer 120 may comprise, for example, silicon dioxide, silicon oxynitride, hafnium oxide, or some other suitable dielectric material. In some embodiments, the first gate dielectric layer 120 is formed by means of a thermal oxidation process. In other embodiments, the first gate dielectric layer 120 may be formed by a deposition process (e.g., Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), etc.). In some embodiments, the first gate dielectric layer 120 is formed on an upper surface of the trench isolation structure 104, while in other embodiments, the first gate dielectric layer 120 is not formed on an upper surface of the trench isolation structure 104. In some embodiments, the first gate dielectric layer 120 has a fourth thickness t that is substantially uniform over the surface of the recess 1202₄. In some embodiments, the fourth thickness t₄In example (b)Such as between approximately 100 angstroms and approximately 200 angstroms.

As shown in cross-sectional view 1300B of fig. 13B, in some embodiments, first gate dielectric layer 120 is also visible from the xz plane. In some embodiments, first gate dielectric layer 120 is also formed over a portion of topmost surface 101t of substrate 101.

As shown in the cross-sectional view 1400A of fig. 14A and the cross-sectional view 1400B of fig. 14B, in some embodiments, the lightly doped region 304 is formed directly along the x-direction between the trench isolation structure 104 and the recess 1202. Thus, in some embodiments, the cross-sectional view 1400A of fig. 14A does not change between fig. 13A and 14A. In some embodiments, lightly doped region 304 is formed using photolithography and ion implantation processes such that lightly doped region 304 is arranged directly between trench isolation structure 104 and recess 1202 and also has a different doping type than well region 102.

In some other embodiments, the lightly doped region 304 and/or the well region 102 are formed before the first gate dielectric layer 120 is formed within the recess 1202. Thus, it should be appreciated that the order of the steps of the method illustrated in fig. 11A-14B may be changed.

As shown in cross-sectional view 1500A of fig. 15A and cross-sectional view 1500B of fig. 15B, the second gate dielectric layer 122 is formed directly on the first gate dielectric layer 120. In some embodiments, the second gate dielectric layer 122 comprises the same material as the first gate dielectric layer 120. In some other embodiments, the second gate dielectric layer 122 may comprise a different material than the first gate dielectric layer 120. In some embodiments, the second gate dielectric layer 122 may be formed by means of Chemical Vapor Deposition (CVD) or by means of some other suitable deposition process (e.g., PVD, ALD, etc.). Furthermore, in some embodiments, the second gate dielectric layer 122 may comprise a high temperature oxide. For example, in some embodiments, the second gate dielectric layer 122 may comprise silicon dioxide formed at high temperatures. In some such embodiments, the reactants to form the high temperature silicon dioxide may include dichlorosilane and nitrous oxide, and may be reacted in a chamber set to a temperature in a range between, for example, approximately 800 degrees celsius and approximately 1000 degrees celsius. In some other embodiments, the high temperature oxide may include silicon oxynitride.

In some embodiments, the second gate dielectric layer 122 has a fifth thickness t that is substantially uniform over the first gate dielectric layer 120₅. In some embodiments, the fifth thickness t₅In a range between approximately 100 angstroms and approximately 200 angstroms, for example.

As shown in cross-sectional view 1600A of fig. 16A and cross-sectional view 1600B of fig. 16B, in some embodiments, a first mask structure 1602 is formed directly over a portion of first gate dielectric layer 120 and a portion of second gate dielectric layer 122 that directly contact and/or directly overlie trench isolation structure 104. Thus, in some embodiments, first mask structure 1602 is visible in the cross-sectional view 1600A of fig. 16A on the yz plane, but not in the cross-sectional view 1600B of fig. 16B on the xz plane. In some other embodiments, first mask structure 1602 may cover trench isolation structure 104 from the xz plane, and thus be visible from the xz plane. In some embodiments, the first mask structure 1602 also directly overlies a portion of the well region 102 that is in direct contact with the first gate dielectric layer 120. In some embodiments, first mask structure 1602 has a first distance d measured in the y-direction₁Directly overlying a portion of well region 102. In some embodiments, the first distance d₁For example, between approximately 0.1 microns and approximately 0.3 microns.

In some embodiments, the first mask structure 1602 can be formed using a photolithography and removal (e.g., etching) process. In some embodiments, the first mask structure 1602 includes a photoresist material or a hardmask material. In some embodiments, the first mask structure 1602 also directly covers the trench isolation structure 104 in the cross-sectional view 1600A of fig. 16A. In some other embodiments, the first mask structure 1602 may also be formed over the entire trench isolation structure 104, and thus in some embodiments, the first mask structure 1602 may be present directly over the trench isolation structure 104 in the cross-sectional view 1600B of fig. 16B.

As shown in top view 1600C of fig. 16C, in some embodiments, first mask structure 1602 resembles two rectangles. In some embodiments, cross-sectional view 1600A of fig. 16A corresponds to cross-sectional line AA 'of fig. 16C, and cross-sectional view 1600B of fig. 16B corresponds to cross-sectional line BB' of fig. 16C. In some other embodiments, from the top view 1600C of fig. 16C, the first mask structure 1602 may also completely cover the trench isolation structure 104 to protect the trench isolation structure 104 from the subsequent removal process.

In some other embodiments, from top view 1600C, first mask structure 1602 has a different design to achieve a different gate electrode structure design, such as the designs shown in fig. 8A-8C, 9A-9C, and/or 10A-10C. For example, in some other embodiments, the alternative first mask structure 1602a of fig. 16C may be used in place of the first mask structure 1602. In such other embodiments, the alternative first mask structure 1602a, shown by a dashed line, is narrower in the x-direction than the recess 1202. In some such other embodiments, an alternative first mask structure 1602a may be used to form the embodiments shown in fig. 8A-8C.

As shown in cross-sectional view 1700A of fig. 17A and cross-sectional view 1700B of fig. 17B, in some embodiments, a removal process is performed to remove portions of first gate dielectric layer 120 and portions of second gate dielectric layer 122 that are not directly under first masking structure 1602. Accordingly, in some embodiments, the removal process of fig. 17A and 17B removes central portions of first gate dielectric layer 120 and second gate dielectric layer 122 such that remaining portions of first gate dielectric layer 120 and second gate dielectric layer 122 directly contact trench isolation structure 104 along the yz plane. In some embodiments, the removal process of fig. 17A and 17B may include a dry etch process performed in a substantially z-direction. After the removal process of fig. 17A and 17B, recess 1202 includes some lower surfaces and outer sidewalls defined by substrate 101 and/or regions of substrate 101 (e.g., well region 102 and lightly doped region 304).

In some embodiments, the trench isolation structure 104 is substantially resistant to removal by the removal process of fig. 17A and 17B. In some other embodiments, first mask structure 1602 covers the entire trench isolation structure 104, and thus first mask structure 1602 prevents trench isolation structure from being removed using the removal process of fig. 17A and 17B.

As shown in top view 1700C of fig. 17C, in some embodiments, the first and second gate dielectric layers (120, 122 of fig. 17A) are not present because the first and second gate dielectric layers (120, 122 of fig. 17A) are behind the first mask structure 1602. In some embodiments, the cross-sectional view 1700A of fig. 17A corresponds to cross-sectional line AA 'of fig. 17C, and the cross-sectional view 1700B of fig. 17B corresponds to cross-sectional line BB' of fig. 17C.

As shown in cross-sectional view 1800A of fig. 18A and cross-sectional view 1800B of fig. 18B, in some embodiments, the first mask structure (1602 of fig. 16A) is removed and a third gate dielectric layer 124 is formed over the surface of the recess 1202 and over the second gate dielectric layer 122. In some embodiments, third gate dielectric layer 124 may comprise the same material as first gate dielectric layer 120 and/or second gate dielectric layer 122, while in some other embodiments, third gate dielectric layer 124 may comprise a different material than first gate dielectric layer 120 and/or second gate dielectric layer 122. In some embodiments, the third gate dielectric layer 124 may be formed by Chemical Vapor Deposition (CVD) or by some other suitable deposition process (e.g., PVD, ALD, etc.). In some embodiments, the third gate dielectric layer 124 has a substantially uniform first thickness t over the first gate dielectric layer 120₁. In some embodiments, the first thickness t₁In a range between approximately 100 angstroms and approximately 300 angstroms, for example.

As shown in the top view 1800C of fig. 18C, in some embodiments, the second gate dielectric layer 122 is shown by dashed lines to depict the second gate dielectric layer 122 only disposed under certain portions of the third gate dielectric layer 124. In some embodiments, cross-sectional view 1800A of fig. 18A corresponds to cross-sectional line AA 'of fig. 18C, and cross-sectional view 1800B of fig. 18B corresponds to cross-sectional line BB' of fig. 18C.

As shown in the cross-sectional views 1900A and 1900B of fig. 19A and 19B, in some embodiments, a gate electrode material 1902 is then formed over the third gate dielectric layer 124 and fills the recess (1202 of fig. 18A and 18B) within the substrate 101. In some embodiments, the gate electrode material 1902 may be formed by means of a deposition process (e.g., CVD, PVD, ALD, sputtering, electroplating, etc.). In some embodiments, the gate electrode material 1902 may comprise polysilicon, aluminum, cobalt, ruthenium, or some other suitable conductive material.

As shown in cross-sectional view 2000A of fig. 20A and cross-sectional view 2000B of fig. 20B, in some embodiments, the gate electrode material (1902 of fig. 19A) is planarized by a planarization process, such as Chemical Mechanical Planarization (CMP), to form a gate electrode 108 having a substantially planar topmost surface 108 t. Since the topmost surface 108t of the gate electrode 108 is substantially planar, the subsequently deposited layer above the gate electrode 108 may also have a substantially planar upper surface. In some embodiments, the gate electrode material (1902 of fig. 19A) is planarized such that the topmost surface 108t of the gate electrode 108 is substantially planar with the topmost surface 101t of the substrate 101. In some other embodiments, the topmost surface 108t of the gate electrode 108 may be subjected to a planarization process (e.g., CMP) and a removal process (e.g., etching) such that the topmost surface 108t of the gate electrode 108 is disposed above the topmost surface 101t of the substrate 101. In some other embodiments (not shown), a work function layer may be formed within the recess (1202 of fig. 18A) and above or below the gate electrode 108 to further adjust the threshold voltage of the recessed MOSFET.

Furthermore, in some embodiments, the planarization process (e.g., CMP) and/or some other removal process (e.g., etching) of fig. 20A and 20B may remove any portion of the first gate dielectric layer 120, the second gate dielectric layer 122, and/or the third gate dielectric layer 124 disposed over the topmost surface 101t of the substrate 101. After the planarization process and/or removal process of fig. 20A and 20B, first gate dielectric layer 120, second gate dielectric layer 122, and third gate dielectric layer 124 constitute gate dielectric structure 106 surrounding gate electrode 108. From the cross-sectional view 2000A of FIG. 20A, the gate dielectric structure 106 includes a central portion 106a, the central portion 106a comprising only the third gate dielectric layer 124 and having the first thickness t₁. In some embodiments, the first thickness t is measured from the bottommost surface 106L of the gate dielectric structure 106 to the first middle surface 106f of the gate dielectric structure 106₁Wherein the first middle surface 106f is between the bottom-most surface 106L and the top-most surface 106t of the gate dielectric structure 106. In some embodiments, from the cross-sectional view 2000B of fig. 20B, the gate dielectric structure 106 includes only the third gate dielectric layer 124, and thus has the first thickness t₁。

Furthermore, the gate dielectric structure 106 comprises corner portions 106b surrounding the central portion 106a and directly overlying the trench isolation structure 104. The corner portions 106b of the gate dielectric structure 106 have a second thickness t₂Said second thickness t₂Equal to the thickness (t) of the first gate dielectric layer 120, the second gate dielectric layer 122, and the third gate dielectric layer 124₄、t₅、t₁) The sum of (a) and (b). In some embodiments, the second thickness t is measured between the bottommost surface 106L of the gate dielectric structure 106 and the second middle surface 106s of the gate dielectric structure 106₂Wherein the second middle surface 106s of the gate dielectric structure 106 is between the first middle surface 106f and the topmost surface 106t of the gate dielectric structure 106. In some embodiments, the corner portion 106b also has a third thickness t₃Said third thickness t₃May be defined as the height of the gate dielectric structure 106 and is measured in the z-direction from the bottommost surface 106L to the topmost surface 106t of the gate dielectric structure 106. A first thickness t₁A second thickness t₂And a third thickness t₃Are all measured in the same z-direction. Second thickness t₂Is greater than the first thickness t₁To ensure that the ratio of current to gate voltage is substantially constant to improve the reliability of the recessed MOSFET. In some embodiments, the second thickness t₂Is a first thickness t₁At least three times as thick because, in some embodiments, first gate dielectric layer 120, second gate dielectric layer 122, and third gate dielectric layer 124 may each be at least 100 angstroms thick.

As shown in the top view 2000C of fig. 20C, in some embodiments, the first gate dielectric layer 120, the second gate dielectric layer 122, and the third gate dielectric layer 124 are visible. In some embodiments, the first gate dielectric layer 120 and the second gate dielectric layer 122 directly overlie the trench isolation structure 104. In some embodiments, the first gate dielectric layer 120 and/or the second gate dielectric layer 122 also directly overlie and contact portions of the well region (102 of fig. 20A). In some embodiments, the cross-sectional view 2000A of fig. 20A corresponds to cross-sectional line AA 'of fig. 20C, and the cross-sectional view 2000B of fig. 20B corresponds to cross-sectional line BB' of fig. 20C.

As shown in the cross-sectional view 2100A of fig. 21A, the cross-sectional view 2100B of fig. 21B, and the top view 2100C of fig. 21C, a hardmask layer 2102 may be formed over the gate electrode 108. In some embodiments, the hard mask layer 2102 may also directly overlie some or all of the gate dielectric structure 106. In some embodiments, the hard mask layer 2102 comprises a hard mask material, such as silicon nitride, silicon carbide, or some other suitable hard mask material. In some embodiments, the hard mask layer 2102 is first deposited over the substrate 101 by means of a deposition process (e.g., CVD, PVD, ALD, etc.), and then patterned by means of a photolithography process and a removal (e.g., etching) process.

Furthermore, in some embodiments, spacer structures 110 may be formed on the outer sidewalls of the hard mask layer 2102. In some embodiments, the spacer structure 110 is formed by: depositing a spacer layer over the hard mask layer 2102 and the substrate 101; a dry etch process may then be performed to remove substantially horizontal portions of the spacer layer, thereby forming spacer structures 110. In some embodiments, the spacer structure 110 may comprise, for example, silicon dioxide, silicon nitride, some other suitable dielectric material, or a combination of the foregoing. In some embodiments, the spacer structure 110 has substantially curved outer sidewalls. Furthermore, in some embodiments, the spacer structure 110 and the hard mask layer 2102 together may completely and directly overlie the gate electrode 108 and the gate dielectric structure 106.

In some other embodiments, the hard mask layer 2102 may be formed prior to performing the removal process of the gate electrode 108. For example, in some embodiments, the gate electrode material (1902 of fig. 19A) may first undergo a planarization process (e.g., CMP), and then a hard mask layer 2102 may be formed over the planarized gate electrode material. Next, in some embodiments, an etch process in accordance with the hard mask layer 2102 may be performed to remove the outer portions of the planarized gate electrode, thereby forming the gate electrode 108. In such other embodiments, the gate electrode 108 may have a topmost surface 108t arranged above the topmost surface 101t of the substrate 101.

As shown in the cross-sectional views 2200A and 2200B of fig. 22A and 22B of fig. 22A, in some embodiments, the source/drain regions 302 may be formed laterally between the spacer structures 110 and the trench isolation structures 104. In some embodiments, source/drain regions 302 are formed by doping portions of lightly doped regions 304 by ion implantation. The source/drain regions 302 may have the same doping type but a higher doping concentration than the lightly doped regions 304. The source/drain regions 302 may be formed by a self-aligned process, wherein the hard mask layer 2102 and the spacer structure 110 act as a mask during the ion implantation process. The source/drain regions 302 are not visible from the cross-sectional view 2200A of fig. 22A because there is no space between the spacer structure and the trench isolation structure 104 for forming the source/drain regions 302.

As shown in the cross-sectional view 2300A of fig. 23A and the cross-sectional view 2300B of fig. 23B, in some embodiments, a first interconnect dielectric layer 114a is formed over the substrate 101 and the hard mask layer 2102. In some embodiments, the first interconnect dielectric layer 114a is formed by a deposition process (e.g., PVD, CVD, ALD, etc.) and may include, for example, nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k oxides (e.g., carbon-doped oxide, SiCOH), or the like.

As shown in cross-sectional view 2400A of fig. 24A and cross-sectional view 2400B of fig. 24B, in some embodiments, a planarization process (e.g., CMP) may be performed to remove a portion of the first interconnect dielectric layer 114A disposed over the hard mask layer 2102. In some embodiments, the planarization process (e.g., CMP) may also remove the spacer structures 110 and the upper portions of the hard mask layer 2102, such that the spacer structures 110 may have a substantially planar upper surface. In some other embodiments, the planarization process (e.g., CMP) of fig. 24A and 24B does not remove portions of the spacer structure 110 and/or portions of the hard mask layer 2102.

As shown in the cross-sectional view 2500A of fig. 25A, the cross-sectional view 2500B of fig. 25B, and the top view 2500C of fig. 25C, in some embodiments, the hard mask layer is selectively removed from the gate electrode 108 (2102 of fig. 24A). In some embodiments, the spacer structure 110 is not removed. In some embodiments, the hard mask layer is removed by means of a wet etch or a dry etch (2102 of fig. 24A), and the gate electrode 108, the gate dielectric structure 106, and the trench isolation structure 104 may be substantially resistant to removal by the wet etch or the dry etch.

In some embodiments (not shown), a gate replacement process may optionally be performed after removing the hard mask layer (2102 of fig. 24A). In such embodiments, the gate electrode 108 may be selectively removed from the gate dielectric structure 106 and a different gate electrode material may be formed within the gate dielectric structure 106. In some such embodiments, the gate electrode 108 formed in fig. 19A-19B and 20A-20C may be referred to as a "dummy gate electrode," and then the dummy gate electrode is removed and replaced with the gate electrode 108 in fig. 25A-25C. For example, in some embodiments, a gate replacement process may be used to reduce damage to the gate electrode 108 during various processing steps.

As shown in the cross-sectional view 2600A of fig. 26A, the cross-sectional view 2600B of fig. 26B, and the top view 2600C of fig. 26C, in some embodiments, a silicide layer 202 is formed on the gate electrode 108. In some embodiments, the silicide layer 202 is formed when the gate electrode 108 comprises polysilicon. In some such embodiments, the silicide layer 202 may comprise, for example, cobalt silicide, titanium silicide, nickel silicide, or some other suitable metal silicide material. In some embodiments, the silicide layer 202 is formed by: a transition metal layer is deposited overlying the gate electrode 108 and subsequently heated to react with the polysilicon of the gate electrode 108. In some embodiments, the silicide layer 202 facilitates conductive features that will be formed over the gate electrode 108 to couple to the gate electrode 108.

As shown in cross-sectional views 2700A of fig. 27A and 2700B of fig. 27B, in some embodiments, interconnect structure 112 is formed over gate electrode 108 and source/drain regions 302 so that the recessed MOSFET can be coupled to more devices (e.g., a memory device, another transistor, an image sensor, etc.) arranged over substrate 101. In some embodiments, the interconnect structure 112 includes a contact via 116, an interconnect wire 118, and an interconnect via 620 disposed in the first interconnect dielectric layer 114a, the second interconnect dielectric layer 114b, the third interconnect dielectric layer 114c, and/or the fourth interconnect dielectric layer 114 d. In some embodiments, the first, second, third and/or fourth interconnect dielectric layers 114a, 114b, 114c, 114d may include, for example, nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k oxides (e.g., carbon-doped oxide, SiCOH), or the like. Furthermore, in some embodiments, the contact via 116, the interconnect wire 118, and the interconnect via 620 may each comprise, for example, copper, tungsten, aluminum, titanium, tantalum, or some other suitable conductive material. In some embodiments, the interconnect structure 112 may be formed by various steps including deposition processes (e.g., PVD, CVD, ALD, sputtering, etc.), removal processes (e.g., wet etch, dry etch, CMP, etc.), and/or patterning processes (e.g., photolithography/etch).

Fig. 28 illustrates a flow diagram of some embodiments of a method 2800 of forming a gate dielectric structure in a recessed MOSFET having corner portions that are thicker than the central portion.

While the method 2800 is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments described herein. Further, one or more of the acts depicted herein may be performed in one or more separate acts and/or phases.

At act 2802, a trench isolation structure is formed to surround a well region of a substrate. Fig. 11A illustrates a cross-sectional view 1100A of some embodiments corresponding to act 2802.

At act 2804, a portion of the substrate is removed to form a recess in the substrate, wherein an outer sidewall of the recess is defined by the trench isolation structure. Fig. 12A illustrates a cross-sectional view 1200A of some embodiments corresponding to act 2804.

At act 2806, a first gate dielectric layer is formed over a surface of a recess in a substrate. Fig. 14A illustrates a cross-sectional view 1400A of some embodiments corresponding to act 2806.

At act 2808, a second gate dielectric layer is formed over the first gate dielectric layer. Figure 15A illustrates a cross-sectional view 1500A of some embodiments corresponding to act 2808.

At act 2810, a removal process is performed to remove a central portion of the first gate dielectric layer and the second gate dielectric layer. Fig. 17A illustrates a cross-sectional view 1700A of some embodiments corresponding to act 2810.

At act 2812, a third gate dielectric layer is formed over a surface of the recess in the substrate and over the second gate dielectric layer. Fig. 18A shows a cross-sectional view 1800A of some embodiments corresponding to act 2812.

At act 2814, a gate electrode is formed over the third gate dielectric layer. Fig. 20A illustrates a cross-sectional view 2000A of some embodiments corresponding to act 2814.

Accordingly, the present disclosure relates to a method of increasing the thickness of a gate dielectric structure at corner portions of the gate dielectric structure in a recessed MOSFET to improve the reliability of the recessed MOSFET.

Accordingly, in some embodiments, the present disclosure relates to a semiconductor device comprising: the well region is positioned in the substrate; a source region and a drain region disposed within the substrate on opposite sides of the well region; a gate electrode disposed over the well region, the gate electrode comprising a bottom surface disposed below a topmost surface of the substrate and extending between the source region and the drain region; a trench isolation structure surrounding the source region, the drain region and the gate electrode; and a gate dielectric structure separating the gate electrode from the well region, the source region, the drain region, and the trench isolation structure, wherein the gate dielectric structure includes a center portion having a first thickness and corner portions having a second thickness, and wherein the second thickness is greater than the first thickness.

In some embodiments, the gate electrode extends in a first direction from the source region to the drain region, wherein the gate electrode extends in a second direction perpendicular to the first direction from a first side of the trench isolation structure to a second side of the trench isolation structure, and wherein the corner portion of the gate dielectric structure is disposed directly above and contacts the first and second sides of the trench isolation structure. In some embodiments, the second thickness is at least three times the first thickness. In some embodiments, the first thickness of the central portion of the gate dielectric structure is measured between a bottommost surface and a first middle surface of the gate dielectric structure, wherein the second thickness of the corner portions of the gate dielectric structure is measured between the bottommost surface and a second middle surface of the gate dielectric structure, wherein the first middle surface is between the second middle surface and the bottommost surface of the gate dielectric structure, and wherein the second middle surface is below a topmost surface of the gate dielectric structure. In some embodiments, the corner portions of the gate dielectric structure have a third thickness measured in the same direction as the first and second thicknesses, and wherein the third thickness is greater than the first and second thicknesses. In some embodiments, the gate electrode extends in a first direction from the source region to the drain region, and wherein any line extending in the first direction through the source and drain regions does not extend through the corner portions of the gate dielectric structure. In some embodiments, a lower portion of the gate electrode disposed over the central portion of the gate dielectric structure is narrower than an upper portion of the gate electrode disposed over the corner portions of the gate dielectric structure. In some embodiments, the corner portions of the gate dielectric structure include a first region directly overlying the trench isolation structure and a second region directly overlying and contacting the well region, wherein the first region is thinner than the second region.

In other embodiments, the present disclosure relates to a semiconductor device including: the well region is positioned in the substrate; a source region and a drain region disposed within the substrate on opposite sides of the well region; a gate electrode disposed within the substrate and directly between the source region and the drain region; a trench isolation structure continuously surrounding the source region, the drain region and the gate electrode; and a gate dielectric structure disposed on the outer sidewall and the bottom surface of the gate electrode, wherein the gate dielectric structure includes a central portion having a first thickness, inner corner portions having a second thickness greater than the first thickness, and outer corner portions having a third thickness greater than the second thickness, and wherein the first thickness, the second thickness, and the third thickness are measured in the same direction from a bottommost surface of the gate dielectric structure.

In some embodiments, the inner corner portions couple the central portion to the outer corner portions, wherein the outer corner portions overlie the trench isolation structures and the central portion extends between opposite sides of the trench isolation structures. In some embodiments, the inner corner portions of the gate dielectric structure overlie and directly contact the trench isolation structure and the well region. In some embodiments, the gate electrode comprises an upper portion having a first width and a lower portion having a second width, the second width being less than the first width, wherein an outer sidewall of the upper portion contacts the outer corner portion of the gate dielectric structure, and wherein an outer sidewall of the lower portion contacts the inner corner portion of the gate dielectric structure. In some embodiments, the gate dielectric structure comprises three dielectric layers. In some embodiments, the inner corner portions and the outer corner portions of the gate dielectric structure comprise the three dielectric layers, and wherein the central portion of the gate dielectric structure comprises one of the three dielectric layers. In some embodiments, the one of the three dielectric layers is a topmost layer of the internal corner portions of the gate dielectric structure.

In yet other embodiments, the present disclosure relates to a method comprising: forming a trench isolation structure to surround a well region of a substrate; removing a portion of the substrate to form a recess in the substrate, wherein an outer sidewall of the recess is defined by the trench isolation structure; forming a first gate dielectric layer over a surface of a recess in a substrate; forming a second gate dielectric layer over the first gate dielectric layer; performing a removal process to remove a central portion of the first gate dielectric layer and the second gate dielectric layer, wherein after the removal process, a portion of the first gate dielectric layer and a portion of the second gate dielectric layer remain on the trench isolation structure; forming a third gate dielectric layer over a surface of the recess in the substrate and over the second gate dielectric layer; and forming a gate electrode over the third gate dielectric layer.

In some embodiments, the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer comprise the same material. In some embodiments, the first gate dielectric layer contacts a portion of the well region after the removal process. In some embodiments, the method further comprises: performing a planarization process on the gate electrode and on the first, second and/or third gate dielectric layers, wherein after the planarization process, the gate electrode, the first, second, third gate dielectric layers and the substrate have upper surfaces that are substantially coplanar. In some embodiments, the method further comprises: forming a masking structure over outer portions of the first and second gate dielectric layers prior to the removal process, wherein the masking structure does not directly overlie the central portions of the first and second gate dielectric layers.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.