阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 陈勇 于 2020-06-03 设计创作，主要内容包括：本申请提供半导体结构及其形成方法,所述半导体结构包括：半导体衬底,所述半导体衬底包括第一区域和第二区域；第一隧穿氧化层,位于所述第一区域的半导体衬底上；第二隧穿氧化层,位于所述第二区域的半导体衬底上,所述第二隧穿氧化层的厚度大于所述第一隧穿氧化层的厚度；浮置栅极,位于所述第一隧穿氧化层和第二隧穿氧化层上。本申请所述的半导体结构及其形成方法,将常规半导体结构中的隧穿氧化层分为厚度不同的两部分,可以同时兼顾闪存器件擦除速度以及应力诱导泄漏电流,即保证擦除速度的同时尽量降低应力诱导泄漏电流。(The present application provides a semiconductor structure and a method of forming the same, the semiconductor structure comprising: a semiconductor substrate including a first region and a second region; the first tunneling oxide layer is positioned on the semiconductor substrate of the first area; the second tunneling oxide layer is positioned on the semiconductor substrate of the second area, and the thickness of the second tunneling oxide layer is larger than that of the first tunneling oxide layer; and the floating grid is positioned on the first tunneling oxide layer and the second tunneling oxide layer. According to the semiconductor structure and the forming method thereof, the tunneling oxide layer in the conventional semiconductor structure is divided into two parts with different thicknesses, so that the erasing speed and the stress induced leakage current of the flash memory device can be considered at the same time, namely the erasing speed is ensured, and the stress induced leakage current is reduced as much as possible.)

1. A method of forming a semiconductor structure, comprising:

providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region;

forming a first tunneling oxide layer on the semiconductor substrate of the first region;

forming a second tunneling oxide layer on the semiconductor substrate in the second region, wherein the thickness of the second tunneling oxide layer is greater than that of the first tunneling oxide layer;

and forming a floating grid on the first tunneling oxide layer and the second tunneling oxide layer.

2. The method of forming the semiconductor structure of claim 1, wherein forming a first tunnel oxide layer on the semiconductor substrate in the first region and forming a second tunnel oxide layer on the semiconductor substrate in the second region, the second tunnel oxide layer having a thickness greater than a thickness of the first tunnel oxide layer comprises:

forming a first tunneling oxide material layer on the semiconductor substrate of the first region and the second region;

removing the first tunneling oxide material layer on the semiconductor substrate of the first region;

and forming a second tunneling oxide material layer on the semiconductor substrate of the first region and the first tunneling oxide material layer of the second region, wherein the second tunneling oxide material layer on the first region forms the first tunneling oxide layer, and the first tunneling oxide material layer and the second tunneling oxide material layer on the second region form the second tunneling oxide layer.

3. The method of forming the semiconductor structure of claim 1, wherein forming a first tunnel oxide layer on the semiconductor substrate in the first region and forming a second tunnel oxide layer on the semiconductor substrate in the second region, the second tunnel oxide layer having a thickness greater than a thickness of the first tunnel oxide layer comprises:

forming a tunneling oxide material layer on the semiconductor substrate of the first region and the second region;

and etching back part of the tunneling oxide material layer on the semiconductor substrate in the first region, wherein the tunneling oxide material layer on the first region forms the first tunneling oxide layer, and the tunneling oxide material layer on the second region forms the second tunneling oxide layer.

4. The method of claim 1, wherein a difference in thickness between the second tunnel oxide layer and the first tunnel oxide layer is between 5 angstroms and 50 angstroms.

5. The method of claim 1, wherein the first tunnel oxide layer has a length of 5 nm to 150 nm, and the second tunnel oxide layer has a length of 10 nm to 150 nm.

6. The method of claim 1, wherein the second tunnel oxide layer has a thickness of 70 a to 110 a, and the first tunnel oxide layer has a thickness of 20 a to 105 a.

7. The method of claim 1, wherein a material of the second tunnel oxide layer is the same as a material of the first tunnel oxide layer.

8. The method of forming a semiconductor structure of claim 1, further comprising: and forming a drain electrode in the semiconductor substrate on one side of the second tunneling oxide layer, and forming a source electrode in the semiconductor substrate on one side of the first tunneling oxide layer.

9. The method of forming a semiconductor structure of claim 1, further comprising: and forming a control gate dielectric layer on the floating gate, and forming a control gate on the control gate dielectric layer.

10. The method of forming a semiconductor structure of claim 9, wherein the control gate dielectric layer is a tri-layer oxide-nitride-oxide structure.

11. A semiconductor structure, comprising:

a semiconductor substrate including a first region and a second region;

the first tunneling oxide layer is positioned on the semiconductor substrate of the first area;

the second tunneling oxide layer is positioned on the semiconductor substrate of the second area, and the thickness of the second tunneling oxide layer is larger than that of the first tunneling oxide layer;

and the floating grid is positioned on the first tunneling oxide layer and the second tunneling oxide layer.

12. The semiconductor structure of claim 11, wherein a difference in thickness between the second tunnel oxide layer and the first tunnel oxide layer is between 5 angstroms and 50 angstroms.

13. The semiconductor structure of claim 11, wherein the first tunnel oxide layer has a length of 5 nm to 150 nm, and the second tunnel oxide layer has a length of 10 nm to 150 nm.

14. The semiconductor structure of claim 11, wherein the second tunnel oxide layer has a thickness of 70 a to 110 a, and the first tunnel oxide layer has a thickness of 20 a to 105 a.

15. The semiconductor structure of claim 11, wherein a material of the second tunnel oxide layer is the same as a material of the first tunnel oxide layer.

16. The semiconductor structure of claim 11, further comprising: the drain electrode is positioned in the semiconductor substrate on one side of the second tunneling oxide layer, and the source electrode is positioned in the semiconductor substrate on one side of the first tunneling oxide layer.

17. The semiconductor structure of claim 11, further comprising: the control grid dielectric layer is positioned on the floating grid, and the control grid is positioned on the control grid dielectric layer.

18. The semiconductor structure of claim 17, wherein the control gate dielectric layer is a tri-layer oxide-nitride-oxide structure.

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.

Background

In the current semiconductor industry, integrated circuit products can be divided into three major categories: logic, memory, and analog circuits, where memory devices represent a significant proportion of the products of integrated circuits. Among the memory devices, flash memory (flash memory) has become the mainstream of non-volatile memory.

Flash memories can be classified into floating gate Flash (flg) and charge-trapping Flash (CTF). For a floating gate structure flash memory, due to the existence of a floating gate, the flash memory can complete reading (reading), writing (programming) and erasing (erase) of information, even under the condition of no power supply, the existence of the floating gate can keep the integrity of stored data, and the floating gate has the advantages of high integration level, higher access speed, easiness in erasing and rewriting and the like, thereby being widely applied to various fields such as microcomputer, automatic control and the like.

However, the current flash memory device still has the problem that it is difficult to achieve both the erase speed and the stress-induced leakage current, so it is necessary to provide a new flash memory device and a method for manufacturing the same to achieve both the erase speed and the stress-induced leakage current.

Disclosure of Invention

The application provides a semiconductor structure and a forming method thereof, which can simultaneously take account of the erasing speed of a flash memory device and the generation of stress induced leakage current.

One aspect of the present application provides a method of forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region; forming a first tunneling oxide layer on the semiconductor substrate of the first region; forming a second tunneling oxide layer on the semiconductor substrate in the second region, wherein the thickness of the second tunneling oxide layer is greater than that of the first tunneling oxide layer; and forming a floating grid on the first tunneling oxide layer and the second tunneling oxide layer.

In some embodiments of the present application, a method of forming a first tunnel oxide layer on the semiconductor substrate of the first region and forming a second tunnel oxide layer on the semiconductor substrate of the second region, the second tunnel oxide layer having a thickness greater than that of the first tunnel oxide layer, includes: forming a first tunneling oxide material layer on the semiconductor substrate of the first region and the second region; removing the first tunneling oxide material layer on the semiconductor substrate of the first region; and forming a second tunneling oxide material layer on the semiconductor substrate of the first region and the first tunneling oxide material layer of the second region, wherein the second tunneling oxide material layer on the first region forms the first tunneling oxide layer, and the first tunneling oxide material layer and the second tunneling oxide material layer on the second region form the second tunneling oxide layer.

In some embodiments of the present application, a method of forming a first tunnel oxide layer on the semiconductor substrate of the first region and forming a second tunnel oxide layer on the semiconductor substrate of the second region, the second tunnel oxide layer having a thickness greater than that of the first tunnel oxide layer, includes: forming a tunneling oxide material layer on the semiconductor substrate of the first region and the second region; and etching back part of the tunneling oxide material layer on the semiconductor substrate in the first region, wherein the tunneling oxide material layer on the first region forms the first tunneling oxide layer, and the tunneling oxide material layer on the second region forms the second tunneling oxide layer.

In some embodiments of the present application, a difference in thickness between the second tunnel oxide layer and the first tunnel oxide layer is 5 to 50 angstroms.

In some embodiments of the present application, the length of the first tunnel oxide layer is 5 nm to 150 nm, and the length of the second tunnel oxide layer is 10 nm to 150 nm.

In some embodiments of the present application, the second tunnel oxide layer has a thickness of 70 to 110 angstroms, and the first tunnel oxide layer has a thickness of 20 to 105 angstroms.

In some embodiments of the present application, a material of the second tunnel oxide layer is the same as a material of the first tunnel oxide layer.

In some embodiments of the present application, the method of forming a semiconductor structure further comprises: and forming a drain electrode in the semiconductor substrate on one side of the second tunneling oxide layer, and forming a source electrode in the semiconductor substrate on one side of the first tunneling oxide layer.

In some embodiments of the present application, the method of forming a semiconductor structure further comprises: and forming a control gate dielectric layer on the floating gate, and forming a control gate on the control gate dielectric layer.

In some embodiments of the present application, the control gate dielectric layer is an oxide-nitride-oxide tri-layer structure.

Another aspect of the present application also provides a semiconductor structure comprising: a semiconductor substrate including a first region and a second region; the first tunneling oxide layer is positioned on the semiconductor substrate of the first area; the second tunneling oxide layer is positioned on the semiconductor substrate of the second area, and the thickness of the second tunneling oxide layer is larger than that of the first tunneling oxide layer; and the floating grid is positioned on the first tunneling oxide layer and the second tunneling oxide layer.

In some embodiments of the present application, a difference in thickness between the second tunnel oxide layer and the first tunnel oxide layer is 5 to 50 angstroms.

In some embodiments of the present application, the length of the first tunnel oxide layer is 5 nm to 150 nm, and the length of the second tunnel oxide layer is 10 nm to 150 nm.

In some embodiments of the present application, the second tunnel oxide layer has a thickness of 70 to 110 angstroms, and the first tunnel oxide layer has a thickness of 20 to 105 angstroms.

In some embodiments of the present application, a material of the second tunnel oxide layer is the same as a material of the first tunnel oxide layer.

In some embodiments of the present application, the semiconductor structure further comprises: the drain electrode is positioned in the semiconductor substrate on one side of the second tunneling oxide layer, and the source electrode is positioned in the semiconductor substrate on one side of the first tunneling oxide layer.

In some embodiments of the present application, the semiconductor structure further comprises: the control grid dielectric layer is positioned on the floating grid, and the control grid is positioned on the control grid dielectric layer.

In some embodiments of the present application, the control gate dielectric layer is an oxide-nitride-oxide tri-layer structure.

According to the semiconductor structure and the forming method thereof, the tunneling oxide layer in the conventional semiconductor structure is divided into two parts with different thicknesses, so that the erasing speed of the flash memory device and the stress induced leakage current can be considered at the same time.

Drawings

The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:

FIG. 1 is a schematic diagram of a semiconductor structure;

fig. 2 to 14 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure.

Detailed Description

The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.

FIG. 1 is a schematic diagram of a semiconductor structure. Referring to fig. 1, the semiconductor structure includes a semiconductor substrate 200, a tunnel oxide layer 210, a floating gate 220, a control gate dielectric layer 230 and a control gate 240 are sequentially formed on the surface of the semiconductor substrate 200, and a source 250 and a drain 260 are respectively formed in the semiconductor substrate 200 on both sides of the tunnel oxide layer 210. The high-quality tunneling oxide layer can reduce stress-induced oxide Damage (stress-induced oxide Damage), thereby affecting electron/hole traps.

When the semiconductor structure performs a "write" function, electrons move along trace 20 from drain 260 through tunnel oxide 210 into floating gate 220; when the semiconductor structure performs the "erase" function, electrons move from the floating gate 220 through the tunnel oxide layer 210 into the source 250 along the trace 21. The "writing" and "erasing" have strict requirements on the thickness of the tunnel oxide layer 210, and when the semiconductor structure performs the "writing" function, if the tunnel oxide layer 210 is too thin, stress-induced leakage current "SILC" may be generated at one side of the drain 260; when the semiconductor structure performs the "erase" function, the erase speed is reduced if the tunnel oxide layer 210 is too thick.

However, as shown in fig. 1, the thickness of the tunnel oxide layer 210 is uniform, and if the tunnel oxide layer 210 is too thin, stress-induced leakage current may be generated on the drain 260 side; if the tunnel oxide layer 210 is too thick, the erase speed is reduced. The tunnel oxide layer 210 cannot simultaneously take into account the erase speed and the generation of stress induced leakage current.

In order to solve the above problems, the present application provides a semiconductor structure and a method for forming the same, which divides a tunnel oxide layer into two parts with different thicknesses for different electron migration paths during "writing" and "erasing" to simultaneously achieve the problems of erasing speed and stress induced leakage current.

Fig. 2 to 14 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure.

An embodiment of the present application provides a method for forming a semiconductor structure, including: referring to fig. 2 to 3, a semiconductor substrate 100 is provided, the semiconductor substrate 100 comprising a first region 101 and a second region 102; referring to fig. 5 to 8, a first tunnel oxide layer 121 is formed on the semiconductor substrate 100 of the first region 101, and a second tunnel oxide layer 122 is formed on the semiconductor substrate 100 of the second region 102, where the thickness of the second tunnel oxide layer 122 is greater than that of the first tunnel oxide layer 121; referring to fig. 9, a floating gate 130 is formed on the first and second tunnel oxide layers 121 and 122.

Referring to fig. 2, fig. 2 is a top view of the semiconductor substrate 100. The semiconductor substrate 100 comprises a first region 101 and a second region 102, and the semiconductor substrate 100 further comprises a number of isolation structures 110 and a number of active regions separated by the number of isolation structures 110. On the one hand, fig. 2 can briefly illustrate the distribution of the regions in the semiconductor substrate 100; on the other hand, since the subsequent process steps will provide the sectional views in different directions to illustrate the technical solution of the present application, different sectional positions a-a and B-B can be marked in fig. 2.

Referring to fig. 3, a semiconductor substrate 100 is provided, the semiconductor substrate 100 comprising a first region 101 and a second region 102. It should be noted that the first region 101 and the second region 102 are used to define the positions of the first tunnel oxide layer and the second tunnel oxide layer formed subsequently, and are not actual structures in the semiconductor substrate.

The semiconductor substrate 100 is made of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In some embodiments of the present application, the semiconductor substrate 100 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

Referring to fig. 4, a plurality of active regions and an isolation structure 110 for isolating the plurality of active regions are formed in the semiconductor substrate 100, and a top surface of the isolation structure 110 is higher than an upper surface of the semiconductor substrate 100.

In some embodiments of the present application, the material forming the isolation structure 110 may be silicon oxide, silicon nitride, or other low dielectric constant material.

Referring to fig. 5 to 8, a first tunnel oxide layer 121 is formed on the semiconductor substrate 100 of the first region 101, and a second tunnel oxide layer 122 is formed on the semiconductor substrate 100 of the second region 102, where the thickness of the second tunnel oxide layer 122 is greater than that of the first tunnel oxide layer 121.

Referring to fig. 5, a first tunnel oxide material layer 121a is formed on the semiconductor substrate 100.

In some embodiments of the present application, a method of forming the first tunneling oxide material layer 121a includes a chemical vapor deposition process or a physical vapor deposition process or a thermal oxidation method.

Referring to fig. 6, the first tunnel oxide material layer 121a on the first region 101 and on the semiconductor substrate 100 near the first region 101 is removed.

In some embodiments of the present application, the method for removing the first tunneling oxide material layer 121a on the first region 101 and on the semiconductor substrate 100 close to the first region 101 includes wet etching or dry etching.

In some embodiments of the present application, the method of removing the first tunneling oxide material layer 121a on the first region 101 and on the semiconductor substrate 100 near the first region 101 includes: forming a patterned mask layer on the first tunnel oxide material layer 121a, where the patterned mask layer defines a position of the first tunnel oxide material layer 121a to be removed; and etching the first tunneling oxide material layer 121 a.

Referring to fig. 7, a second tunnel oxide material layer 122a is formed on the semiconductor substrate 100 and the first tunnel oxide material layer 121a, wherein the second tunnel oxide material layer 122a on the first region 101 forms the first tunnel oxide layer 121, and the first tunnel oxide material layer 121a and the second tunnel oxide material layer 122a on the second region 102 form the second tunnel oxide layer 122.

It should be noted that the dimensional ratios in the drawings are not actual dimensional ratios, and are merely for convenience of describing different structures. The thickness of the first tunnel oxide material layer 121a is relatively thin, the difference between the thicknesses of the first tunnel oxide layer on the first region 101 and the second tunnel oxide layer on the second region 102 is not very obvious, the step shape at the boundary between the first region 101 and the second region 102 is not obvious, and an arc-shaped transition structure is formed at the boundary in an actual deposition process. And the length of the transition structure is small relative to the thickness of the entire tunnel oxide layer, and the division of the first tunnel oxide layer 121 and the second tunnel oxide layer 122 on the first region 101 and the second region 102 is not affected.

In some embodiments of the present application, a method of forming the second tunneling oxide material layer 122a includes a chemical vapor deposition process or a physical vapor deposition process or a thermal oxidation method.

Referring to fig. 8, the first tunnel oxide material layer 121a and the second tunnel oxide material layer 122a are sequentially formed on the active regions.

Referring to fig. 9, a floating gate 130 is formed on the first and second tunnel oxide layers 121 and 122. The thickness difference between the first tunnel oxide layer 121 and the second tunnel oxide layer 122 is small enough not to affect the function of the floating gate 130.

In some embodiments of the present application, the material forming the floating gate 130 may be a semiconductor material, such as silicon, polysilicon, germanium, or the like. The method of forming the floating gate 130 may be a chemical vapor deposition process.

Referring to fig. 10, the upper surface of the floating gate 130 is flush with the top surface of the isolation structure 110.

In some embodiments of the present application, a method of forming the floating gate 130 includes: forming a floating gate material layer on the second tunneling oxide material layer 122a and on the isolation structure 110; a chemical mechanical polishing process is used to remove the floating gate material layer above the top surface of the isolation structure 110.

Referring to fig. 11, the isolation structure 110 is etched back until the top surface of the isolation structure 110 is flush with the surface of the second tunneling oxide material layer 122 a.

In some embodiments of the present application, the etch-back comprises a wet etch.

Referring to fig. 12, a control gate dielectric layer 140 is formed on the floating gate 130, and a control gate 150 is formed on the control gate dielectric layer 140.

In some embodiments of the present application, the method for forming the control gate dielectric layer 170 may be a chemical vapor deposition process.

In some embodiments of the present application, the control gate dielectric layer 140 is a triple oxide-nitride-oxide structure. For example, the control gate dielectric layer 140 may be a silicon oxide-silicon nitride-silicon oxide triple layer structure.

In some embodiments of the present application, the control gate dielectric layer 140 may also be a nitride layer, an oxide layer, or a double-layer structure of a nitride and an oxide layer.

In some embodiments of the present application, the material forming the control gate 180 may be a metal oxide, a metal silicide, a metal alloy, a composite thereof, and the like.

In some embodiments of the present application, the method of forming the control gate 180 may be a chemical vapor deposition process or a physical vapor deposition process.

Referring to fig. 13, a control gate dielectric layer 140 is formed on the floating gate 130 and the isolation structure 110, and a control gate 150 is formed on the control gate dielectric layer 140

Referring to fig. 14, removing the first tunnel oxide material layer 121a, the second tunnel oxide material layer 122a, the floating gate 130, the control gate dielectric layer 140 and the control gate 150 on the semiconductor substrate 100 outside the first region 101 and the second region 102, wherein the second tunnel oxide material layer 122a on the first region 101 constitutes the first tunnel oxide layer 121, and the first tunnel oxide material layer 121a and the second tunnel oxide material layer 122a on the second region 102 constitute the second tunnel oxide layer 122; a drain electrode 170 is formed in the semiconductor substrate 100 on the side of the second tunnel oxide layer 122, and a source electrode 160 is formed in the semiconductor substrate 100 on the side of the first tunnel oxide layer 121.

When the semiconductor structure performs a "write" function, electrons move from the drain 170 through the second tunnel oxide 122 into the floating gate 130 along the trace 10; when the semiconductor structure performs the "erase" function, electrons move along trace 11 from floating gate 130 through first tunnel oxide layer 121 and into source 160.

In some embodiments of the present application, the method for removing the first tunnel oxide material layer 121a, the second tunnel oxide material layer 122a, the floating gate 130, the control gate dielectric layer 140, and the control gate 150 on the semiconductor substrate 100 outside the first region 101 and the second region 102 includes wet etching or dry etching.

In some embodiments of the present application, the difference between the thicknesses of the second tunnel oxide layer 122 and the first tunnel oxide layer 121 is 5 to 50 angstroms, such as 10 angstroms, 20 angstroms, 30 angstroms or 40 angstroms. The thickness difference cannot be too large or may affect the performance of the floating gate.

In some embodiments of the present application, the length of the first tunnel oxide layer 121 is 5 nm to 150 nm, such as 50 nm, 100 nm, or 150 nm; the length of the second tunnel oxide layer 122 is 10 nm to 150 nm, for example, 50 nm, 100 nm, or 150 nm. Specifically, the length may be set according to the overall size of the device and the electron migration paths 10 and 11, such that the path 10 does not pass through the first tunnel oxide layer 121, and the path 11 does not pass through the second tunnel oxide layer 122. Wherein the length refers to the dimension in the a-a direction.

In some embodiments of the present application, the thickness of the second tunnel oxide layer 122 is 70 to 110 angstroms, such as 80, 90 or 100 angstroms, and the like, and in particular, the thickness of the second tunnel oxide layer 122 may be referred to as a thickness required for not generating stress-induced leakage current; the thickness of the first tunnel oxide layer 121 is 20 to 105 angstroms, for example, 50 angstroms, 80 angstroms or 100 angstroms, and in particular, the thickness of the first tunnel oxide layer 121 may be set according to the requirement of the semiconductor device for erase speed.

In some embodiments of the present application, the material of the second tunnel oxide layer 122 is the same as the material of the first tunnel oxide layer 121. For example, the material of the second tunnel oxide layer 122 and the first tunnel oxide layer 121 may be silicon oxide.

In other embodiments of the present application, a method for forming a first tunnel oxide layer 121 on the semiconductor substrate 100 in the first region 101, and forming a second tunnel oxide layer 122 on the semiconductor substrate 100 in the second region 102, where a thickness of the second tunnel oxide layer 122 is greater than a thickness of the first tunnel oxide layer 121, includes: forming a tunneling oxide material layer on the semiconductor substrate 100 of the first region 101 and the second region 102; and etching back part of the tunnel oxide material layer on the semiconductor substrate 100 of the first region 101, where the tunnel oxide material layer on the first region 101 constitutes the first tunnel oxide layer 121, and the tunnel oxide material layer on the second region 102 constitutes the second tunnel oxide layer 122. The method only needs to deposit the tunneling oxide material layer once, so that the process steps can be saved, but the requirement on the precision of the back etching process is higher because the thickness difference between the first tunneling oxide layer and the second tunneling oxide layer is smaller.

Embodiments of the present application also provide a semiconductor structure, referring to fig. 14, comprising: a semiconductor substrate 100, the semiconductor substrate 100 comprising a first region 101 and a second region 102; a first tunnel oxide layer 121 located on the semiconductor substrate 100 of the first region 101; a second tunnel oxide layer 122 located on the semiconductor substrate 100 in the second region 102, wherein the thickness of the second tunnel oxide layer 122 is greater than that of the first tunnel oxide layer 121; and a floating gate 130 on the first tunnel oxide layer 121 and the second tunnel oxide layer 122.

Referring to fig. 14, the material of the semiconductor substrate 100 is silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In some embodiments of the present application, the semiconductor substrate 100 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. It should be noted that the first region 101 and the second region 102 are used to define the positions of the first tunnel oxide layer and the second tunnel oxide layer formed subsequently, and are not actual structures in the semiconductor substrate.

With reference to fig. 14, a first tunnel oxide layer 121 is formed on the semiconductor substrate 100 in the first region 101, and a second tunnel oxide layer 122 is formed on the semiconductor substrate 100 in the second region 102, where the thickness of the second tunnel oxide layer 122 is greater than that of the first tunnel oxide layer 121.

It should be noted that the dimensional ratios in the drawings are not actual dimensional ratios, and are merely for convenience of describing different structures. The difference in thickness between the first tunnel oxide layer 121 and the second tunnel oxide layer 122 is not very obvious, and the step shape at the junction between the first tunnel oxide layer 121 and the second tunnel oxide layer 122 is not very obvious, and in an actual structure, an arc-shaped transition structure is formed at the junction. And the length of the transition structure is small relative to the thickness of the entire tunnel oxide layer, and the division of the first tunnel oxide layer 121 and the second tunnel oxide layer 122 on the first region 101 and the second region 102 is not affected.

In some embodiments of the present application, the difference between the thicknesses of the second tunnel oxide layer 122 and the first tunnel oxide layer 121 is 5 to 50 angstroms, such as 10 angstroms, 20 angstroms, 30 angstroms or 40 angstroms. The thickness difference cannot be too large or may affect the performance of the floating gate.

In some embodiments of the present application, the length of the first tunnel oxide layer 121 is 5 nm to 150 nm, such as 50 nm, 100 nm, or 150 nm; the length of the second tunnel oxide layer 122 is 10 nm to 150 nm, for example, 50 nm, 100 nm, or 150 nm. Specifically, the length may be set according to the overall size of the device and the electron migration paths 10 and 11, such that the path 10 does not pass through the first tunnel oxide layer 121, and the path 11 does not pass through the second tunnel oxide layer 122. Wherein the length refers to the dimension in the a-a direction.

In some embodiments of the present application, the thickness of the second tunnel oxide layer 122 is 70 to 110 angstroms, such as 80, 90 or 100 angstroms, and the like, and in particular, the thickness of the second tunnel oxide layer 122 may be referred to as a thickness required for not generating stress-induced leakage current; the thickness of the first tunnel oxide layer 121 is 20 to 105 angstroms, for example, 50 angstroms, 80 angstroms or 100 angstroms, and in particular, the thickness of the first tunnel oxide layer 121 may be set according to the requirement of the semiconductor device for erase speed.

In some embodiments of the present application, the material of the second tunnel oxide layer 122 is the same as the material of the first tunnel oxide layer 121. For example, the material of the second tunnel oxide layer 122 and the first tunnel oxide layer 121 may be silicon oxide.

With continued reference to fig. 14, a floating gate 130 is formed on the first tunnel oxide layer 121 and the second tunnel oxide layer 122. The thickness difference between the first tunnel oxide layer 121 and the second tunnel oxide layer 122 is small enough not to affect the function of the floating gate 130.

In some embodiments of the present application, the material forming the floating gate 130 may be a semiconductor material, such as silicon, polysilicon, germanium, or the like.

With continued reference to fig. 14, a control gate dielectric layer 140 is formed on the floating gate 130, and a control gate 150 is formed on the control gate dielectric layer 140.

In some embodiments of the present application, the control gate dielectric layer 140 is a triple oxide-nitride-oxide structure. For example, the control gate dielectric layer 140 may be a silicon oxide-silicon nitride-silicon oxide triple layer structure.

In some embodiments of the present application, the control gate dielectric layer 140 may also be a nitride layer, an oxide layer, or a double-layer structure of a nitride and an oxide layer.

In some embodiments of the present application, the material forming the control gate 180 may be a metal oxide, a metal silicide, a metal alloy, a composite thereof, and the like.

With continued reference to fig. 14, a drain 170 is formed in the semiconductor substrate 100 on the side of the second tunnel oxide layer 122, and a source 160 is formed in the semiconductor substrate 100 on the side of the first tunnel oxide layer 121.

When the semiconductor structure performs a "write" function, electrons move from the drain 170 through the second tunnel oxide 122 into the floating gate 130 along the trace 10; when the semiconductor structure performs the "erase" function, electrons move along trace 11 from floating gate 130 through first tunnel oxide layer 121 and into source 160.

In the semiconductor structure of the present application, the tunnel oxide layer may be divided into two portions with different thicknesses, namely, the first tunnel oxide layer 121 and the second tunnel oxide layer 122, according to the different electron migration paths 10 and 11 during "writing" and "erasing", and the first tunnel oxide layer 121 and the second tunnel oxide layer 122 with different thicknesses are arranged to simultaneously satisfy the thickness requirements of "writing" and "erasing" on the tunnel oxide layer, so as to simultaneously solve the problems of the erasing speed and the stress-induced leakage current, that is, to ensure the erasing speed and simultaneously reduce the stress-induced leakage current as much as possible.

Comparing fig. 14 and fig. 1, the thickness of the tunnel oxide layer 210 in the conventional semiconductor structure is uniform, and the erase speed and the stress-induced leakage current cannot be considered at the same time. In the method for forming a semiconductor structure and a semiconductor structure provided by the present application, a tunnel oxide layer may be divided into two portions with different thicknesses, a first tunnel oxide layer 121 and a second tunnel oxide layer 122, for different electron migration paths 10 and 11 during "writing" and "erasing", and for different requirements for the thicknesses of the tunnel oxide layers during "writing" and "erasing", the first tunnel oxide layer 121 and the second tunnel oxide layer 122 with different thicknesses are provided to simultaneously satisfy the thickness requirements for the tunnel oxide layers during "writing" and "erasing", thereby simultaneously considering both the erasing speed and the stress-induced leakage current, that is, ensuring the erasing speed and simultaneously reducing the stress-induced leakage current as much as possible.

In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.

It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.

Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.