阅读说明：本技术 电源控制装置、驱动模块及开关电源装置 (Power supply control device, drive module and switching power supply device ) 是由 赤穂直史 于 2021-04-15 设计创作，主要内容包括：本发明在抑制端子数增加的同时,实现控制端子的连接相关的确认功能。本发明涉及一种电源控制装置、驱动模块及开关电源装置。本发明的电源控制装置具有：控制端子,用来与驱动模块间输入输出控制信号；使能输出端子,用来将使能信号输出到所述驱动模块；控制电路；及输入输出电路,在使输出晶体管为导通状态,使同步整流晶体管为断开状态时,使所述控制信号成为第1逻辑电平,在使所述输出晶体管为断开状态,使所述同步整流晶体管为导通状态时,使所述控制信号成为第2逻辑电平,能够根据来自所述控制电路的指令成为输入待机状态；所述控制电路在所述输入输出电路为所述输入待机状态时,将用来启动所述驱动模块的电平的使能信号传送到所述驱动模块,确认所述控制信号是否为既非所述第1逻辑电平又非所述第2逻辑电平的第3逻辑电平。(The invention realizes a confirmation function related to connection of control terminals while suppressing increase of the number of terminals. The invention relates to a power supply control device, a driving module and a switching power supply device. The power supply control device of the present invention includes: the control terminal is used for inputting and outputting control signals with the driving module; an enable output terminal for outputting an enable signal to the driving module; a control circuit; and an input/output circuit which sets the control signal to a 1 st logic level when the output transistor is turned on and the synchronous rectification transistor is turned off, and sets the control signal to a 2 nd logic level when the output transistor is turned off and the synchronous rectification transistor is turned on, and which can be set to an input standby state in accordance with an instruction from the control circuit; when the input/output circuit is in the input standby state, the control circuit transmits an enable signal for starting the level of the driving module to the driving module, and confirms whether the control signal is a 3 rd logic level which is not the 1 st logic level or the 2 nd logic level.)

1. A power control device for use with a driver module that drives on/off of an output transistor and a synchronous rectification transistor, and

comprising:

the control terminal is used for inputting and outputting control signals with the driving module;

an enable output terminal for outputting an enable signal to the driving module;

a control circuit; and

an input/output circuit that sets the control signal to a 1 st logic level when the output transistor is turned on and the synchronous rectification transistor is turned off, and sets the control signal to a 2 nd logic level when the output transistor is turned off and the synchronous rectification transistor is turned on, and that can be set to an input standby state in response to an instruction from the control circuit; and is

When the input/output circuit is in the input standby state, the control circuit transmits an enable signal for starting the level of the driving module to the driving module, and confirms whether the control signal is a 3 rd logic level which is not the 1 st logic level or the 2 nd logic level.

2. The power supply control device according to claim 1, wherein the enable signal can be any one of an L (low) level, an H (high) level, and an M level between the L level and the H level,

the level used to activate the drive module is the M level.

3. The power supply control device according to claim 1 or 2, wherein when the input/output circuit is in the input standby state and the enable signal is at a level indicating prohibition, the control circuit confirms that the control signal is at the 1 st logic level or the 2 nd logic level,

the control circuit transmits an enable signal for starting the level of the driving module to the driving module.

4. The power supply control device according to claim 3, wherein the control terminal is plural,

when the input/output circuit is in the input standby state and the enable signal is at a level indicating prohibition, the control circuit checks whether or not a combination of levels of the control signals matches a permitted combination.

5. The power supply control device according to claim 4, wherein an application terminal of the voltage of the 3 rd logic level can be connected to the control terminal not used for connection with the drive module.

6. The power supply control device according to any one of claims 1 to 5, wherein the enable output terminal is plural,

the control terminal is a plurality of.

7. A driving module for driving the on/off of an output transistor and a synchronous rectification transistor, and

the method for integrating the packaging structure into a single package comprises the following steps:

a driving logic circuit which makes the output transistor in a conducting state and makes the synchronous rectification transistor in a disconnecting state when a control signal is at a 1 st logic level, and makes the output transistor in a disconnecting state and makes the synchronous rectification transistor in a conducting state when the control signal is at a 2 nd logic level;

an internal voltage generating part for generating an internal voltage and starting the internal voltage by using an enable signal;

a power-on reset unit configured to cancel resetting of the drive logic circuit based on the internal voltage; and

and a logic level switching circuit configured to switch the control signal to a 3 rd logic level that is not the 1 st logic level or the 2 nd logic level in accordance with an instruction from the drive logic circuit when the reset is released.

8. The drive module of claim 7, wherein

The logic level switching circuit has:

a 1P channel MOS transistor having a gate driven by the enable signal and a source connected to an application terminal of a power supply voltage;

a resistor having a 1 st terminal connected to the drain of the 1 st P-channel MOS transistor;

a 2P channel MOS transistor having a source connected to the 2 nd terminal of the resistor, a drain connected to a terminal to which a ground voltage is applied, and a gate driven by the internal voltage;

an N-channel MOS transistor having a gate connected to a node connecting the 2 nd terminal of the resistor and the source of the 2P-channel MOS transistor, and a source connected to an application terminal of the control signal; and

and a 3P channel MOS transistor having a source connected to the application terminal of the power supply voltage, a drain connected to the drain of the N channel MOS transistor, and a gate to which a gate signal output from the drive logic circuit is applied.

9. The drive module according to claim 7 or 8, further having a logic level fixing circuit that fixes the control signal to a logic level of each model when the enable signal indicates disable.

10. The drive module according to any one of claims 7 to 9, further having a zero-crossing detection circuit that detects zero-crossings of an inductor current flowing when the synchronous rectification transistor is in a conductive state,

the logic level switching circuit switches the control signal to the 3 rd logic level in accordance with an instruction from the drive logic circuit when the zero crossing is detected.

11. The drive module according to any one of claims 7 to 10, which also has the output transistor and the synchronous rectification transistor integrated into the package.

12. A switching power supply device has a driving module and a power supply control device, the driving module drives the output transistor and the synchronous rectification transistor to be turned on/off, and

the power supply control device includes:

the control terminal is used for inputting and outputting control signals with the driving module;

an enable output terminal for outputting an enable signal to the driving module;

a control circuit; and

an input/output circuit that sets the control signal to a 1 st logic level or a 2 nd logic level in order to turn on and off the output transistor and the synchronous rectification transistor, and that is set in an input standby state according to an instruction from the control circuit;

when the input/output circuit is in the input standby state, the control circuit transmits an enable signal for starting the level of the driving module to the driving module, and confirms whether the control signal is a 3 rd logic level which is not the 1 st logic level or the 2 nd logic level;

the drive module has, integrated into a single package:

a drive logic circuit which makes the output transistor in a conducting state and makes the synchronous rectification transistor in a disconnecting state when the control signal is at the 1 st logic level, and makes the output transistor in a disconnecting state and makes the synchronous rectification transistor in a conducting state when the control signal is at the 2 nd logic level;

an internal voltage generating part which generates an internal voltage and is started by the enable signal;

a power-on reset unit configured to cancel resetting of the drive logic circuit based on the internal voltage; and

and a logic level switching circuit for switching the control signal to the 3 rd logic level in response to an instruction from the drive logic circuit when the reset is released.

Technical Field

The invention relates to a drive module for a switching power supply device and a power supply control device.

Background

In recent years, as a component of a switching power supply device, a Driver module (so-called DrMOS (Driver Metal-Oxide-Semiconductor Field Effect Transistor)) is put into practical use, in which a pair of MOSFETs forming a switching output stage and a Driver logic circuit for driving the pair of MOSFETs are integrated into 1 package.

As an example of the conventional art related to the above, patent document 1 is cited.

[ Prior art documents ]

[ patent document ]

[ patent document 1] Japanese patent laid-open publication No. 2017-195768

Disclosure of Invention

[ problems to be solved by the invention ]

Conventionally, the drive module is controlled by a power control device. The power control device has a control terminal. The drive logic circuit drives the MOSFET to be turned on and off according to a logic level of a control signal output from the control terminal.

Here, it is desirable that the power supply control device can confirm the type of the drive module connected to the control terminal or the presence or absence of a connection failure of the control terminal when the switching power supply device is started. In this case, it is required to suppress an increase in the number of terminals of the power supply control device.

In view of the above circumstances, an object of the present invention is to provide a power supply control device, a drive module, and a switching power supply device that can realize a confirmation function regarding connection of a control terminal of the power supply control device while suppressing an increase in the number of terminals.

[ means for solving problems ]

The power control device of the present invention is used together with a driving module that drives on/off of an output transistor and a synchronous rectification transistor, and

the structure (1 st structure) is provided with:

the control terminal is used for inputting and outputting control signals with the driving module;

an enable output terminal for outputting an enable signal to the driving module;

a control circuit; and

an input/output circuit that sets the control signal to a 1 st logic level when the output transistor is turned on and the synchronous rectification transistor is turned off, and sets the control signal to a 2 nd logic level when the output transistor is turned off and the synchronous rectification transistor is turned on, and that can be set to an input standby state in accordance with an instruction from the control circuit; and is

When the input/output circuit is in the input standby state, the control circuit transmits an enable signal for starting the level of the driving module to the driving module, and confirms whether the control signal is a 3 rd logic level which is not the 1 st logic level or the 2 nd logic level.

In addition, in the configuration 1, the enable signal may be at any one of an L (low) level, an H (high) level, and an M level between the L level and the H level (configuration 2),

the level used to activate the drive module is the M level.

In the configuration 1 or 2, when the input/output circuit is in the input standby state and the enable signal is at a level indicating prohibition, the control circuit may transmit an enable signal at a level for activating the driver module to the driver module after confirming that the control signal is at the 1 st logic level or the 2 nd logic level (configuration 3).

In addition, in the configuration 3, the control circuit may check whether or not a combination of levels of the control signals matches an allowable combination when the input/output circuit is in the input standby state and the enable signal is at a level indicating prohibition (the configuration 4).

In addition, in the above configuration 4, the voltage application terminal of the 3 rd logic level may be connected to the control terminal that is not used for connection to the driving module (configuration 5).

In addition, in any of the configurations 1 to 5, the enable output terminal may be provided in plurality, and the control terminal may be provided in plurality (configuration 6).

In addition, the driving module of the invention drives the output transistor and the synchronous rectification transistor to be switched on/off, and

the structure (7 th structure) is provided with, as a single package:

a driving logic circuit which makes the output transistor in a conducting state and makes the synchronous rectification transistor in a disconnecting state when a control signal is at a 1 st logic level, and makes the output transistor in a disconnecting state and makes the synchronous rectification transistor in a conducting state when the control signal is at a 2 nd logic level;

an internal voltage generating part for generating an internal voltage and starting the internal voltage by using an enable signal;

a power-on reset unit configured to cancel resetting of the drive logic circuit based on the internal voltage; and

and a logic level switching circuit configured to switch the control signal to a 3 rd logic level that is not the 1 st logic level or the 2 nd logic level in accordance with an instruction from the drive logic circuit when the reset is released.

In addition, in the above-mentioned 7 th configuration (8 th configuration),

the logic level switching circuit has:

a 1P channel MOS transistor having a gate driven by the enable signal and a source connected to an application terminal of a power supply voltage;

a resistor having a 1 st terminal connected to the drain of the 1 st P-channel MOS transistor;

a 2P channel MOS transistor having a source connected to the 2 nd terminal of the resistor, a drain connected to a terminal to which a ground voltage is applied, and a gate driven by the internal voltage;

an N-channel MOS transistor having a gate connected to a node connecting the 2 nd terminal of the resistor and the source of the 2P-channel MOS transistor, and a source connected to an application terminal of the control signal; and

and a 3P channel MOS transistor having a source connected to the application terminal of the power supply voltage, a drain connected to the drain of the N channel MOS transistor, and a gate to which a gate signal output from the drive logic circuit is applied.

In addition, the 7 th or 8 th configuration may further include a logic level fixing circuit configured to fix the control signal to a logic level of each model when the enable signal indicates prohibition (a 9 th configuration).

In addition, any of the configurations 7 to 9 may further include a zero-crossing detection circuit that detects a zero crossing of an inductor current flowing when the synchronous rectification transistor is in an on state, and the logic level switching circuit may switch the control signal to the 3 rd logic level in accordance with an instruction from the drive logic circuit when the zero crossing is detected (configuration 10).

In addition, in any of the configurations 7 to 10, the output transistor and the synchronous rectification transistor may be provided so as to be integrated into the package (11 th configuration).

The switching power supply device of the present invention includes a driving module for driving on/off of an output transistor and a synchronous rectification transistor, and a power supply control device,

the power supply control device includes:

the control terminal is used for inputting and outputting control signals with the driving module;

an enable output terminal for outputting an enable signal to the driving module;

a control circuit; and

an input/output circuit that sets the control signal to a 1 st logic level or a 2 nd logic level in order to turn on and off the output transistor and the synchronous rectification transistor, and that is set in an input standby state according to an instruction from the control circuit;

when the input/output circuit is in the input standby state, the control circuit transmits an enable signal for starting the level of the driving module to the driving module, and confirms whether the control signal is a 3 rd logic level which is not the 1 st logic level or the 2 nd logic level;

the drive module has, integrated into a single package:

a drive logic circuit which makes the output transistor in a conducting state and makes the synchronous rectification transistor in a disconnecting state when the control signal is at the 1 st logic level, and makes the output transistor in a disconnecting state and makes the synchronous rectification transistor in a conducting state when the control signal is at the 2 nd logic level;

an internal voltage generating part which generates an internal voltage and is started by the enable signal;

a power-on reset unit configured to cancel resetting of the drive logic circuit based on the internal voltage; and

and a logic level switching circuit for switching the control signal to the 3 rd logic level in response to an instruction from the drive logic circuit when the reset is released.

[ Effect of the invention ]

According to the present invention, it is possible to realize a confirmation function regarding connection of the control terminal of the power supply control device while suppressing an increase in the number of terminals.

Drawings

Fig. 1 is a diagram showing an overall configuration of a switching power supply device according to an exemplary embodiment.

Fig. 2 is a diagram showing an internal configuration example of a drive module of the switching power supply device.

Fig. 3 is a diagram showing an example of the configuration of the pull-down type logic level fixing circuit.

Fig. 4 is a diagram showing an example of the configuration of the pull-up type logic level fixing circuit.

Fig. 5 is a diagram showing an example of the configuration of the logic level switching circuit.

Fig. 6 is a diagram showing an example of the configuration of the input/output circuit.

Fig. 7 is a flowchart relating to the startup procedure of the switching power supply device.

Fig. 8 is a timing chart showing example 1 of the startup procedure of the switching power supply device (example of normal startup).

Fig. 9 is a timing chart showing example 2 of the startup procedure of the switching power supply device (an example of an error occurrence).

Fig. 10 is a timing chart showing example 3 of the startup procedure of the switching power supply device (an example of an error occurrence).

Fig. 11 is a diagram showing an overall configuration of a switching power supply device according to a modification.

Fig. 12 is a timing chart showing an example of the startup procedure of the configuration shown in fig. 11.

Detailed Description

< integral construction of switching Power supply device >

Fig. 1 is a diagram showing an overall configuration of a switching power supply device. The switching power supply device 1 of the present configuration example is a multi-phase (4-phase in the present figure) step-down DC/DC (Direct Current to Direct Current) converter, generates an output voltage Vout from an input voltage Pvin, supplies the output voltage Vout to a load Z (central processing unit, etc.), which is not shown, and has 4 drive modules 10(1) to 10(4), a power supply control device 20, inductors L1(1) to L1(4), and a capacitor Co, which are connected in parallel.

The power supply control device 20 has control terminals Tp1 to Tp8, and 1 to 8 drive modules 10 can be connected to the power supply control device 20 according to the connection mode of the drive modules 10, as described below. That is, a 1-phase to 8-phase step-down DC/DC converter can be configured. In fig. 1, as an example, the control terminals Tp1 to Tp4 are used for connection of the drive module 10, and the other control terminals Tp5 to Tp8 are not used.

The driving modules 10(1) to 10(4) are semiconductor devices (so-called DrMOS) in which a pair of MOSFETs forming a switching output stage and a driving logic circuit (not shown) for driving the pair of MOSFETs are integrated into 1 package, respectively.

The pair of MOSFETs are connected between the application terminal of the input voltage PVin and the application terminal of the ground voltage PGND, and are basically on/off controlled by the control signals PWM1 to PWM 4. As a result, the switching voltages SW (1) to SW (4) pulse-driven between the input voltage Pvin and the ground voltage PGND are output from the driving modules 10(1) to 10(4), and the switching voltages are accumulated, rectified and smoothed by the inductors L1(1) to L1(4) and the capacitor Co, thereby generating the output voltage Vout input to the load Z.

By using the driving modules 10(1) to 10(4), the circuit scale of the switching power supply device 1 can be reduced significantly compared to the case where the pair of MOSFETs or the driving logic circuit is provided individually.

The power supply control device 20 is a semiconductor device (so-called PMIC (power management IC, Integrated Circuit)) that is a control subject of the switching power supply device 1. The power control device 20 includes a control circuit 21, an input/output circuit 22, an internal voltage generating unit 23, and a MOS switch 24, which are integrated into 1 package.

The power supply control device 20 includes control terminals Tp1 to Tp8, an enable output terminal Tden, a drive input terminal Ten, a standby terminal Tst, an internal voltage output terminal Treg, an internal voltage input terminal Tregin, an interrupt terminal Tint, a feedback input terminal Ts +, Ts-, a power supply terminal Tcc, and a ground terminal Tgd, and serves as an external terminal for establishing electrical connection with the outside.

The control circuit 21 mainly performs output feedback control (duty control) of the control signal PWM in order to obtain a desired output voltage Vout from the input voltage Pvin. The control circuit 21 instructs the input/output circuit 22 based on the voltage between both ends of the load Z detected by remote sensing (i.e., the difference between the remote sensing signals S + and S-), and causes the input/output circuit 22 to generate the control signals PWM (1) to PWM (4) of the drive modules 10(1) to 10(4), respectively, to perform the output feedback control. The remote sensing signal S +, S-is input to the feedback input terminals Ts +, Ts-. The generated control signals PWM (1) to PWM (4) are output from the control terminals Tp1 to Tp4 to the drive modules 10(1) to 10 (4).

The control circuit 21 also has a function (details will be described later) of setting the input/output circuit 22 to an input standby state, monitoring the logic level of the control signal PWM, and performing switching of the operation mode of the switching power supply device 1, or determination of the type or connection of the drive module 10 based on the monitoring result.

The input/output circuit 22 is a circuit block that inputs/outputs a control signal PWM, and switches its operating state (output state or input standby state) in response to a command from the control circuit 21. When the input/output circuit 22 is in the output state, the input/output circuit 22 outputs the control signal PWM at the H (High) level or the L (low) level, thereby performing on/off control of a pair of MOSFETs (described later) included in the drive module 10. On the other hand, when the input/output circuit 22 is in the input standby state, the input/output circuit 22 detects the logic level (H/L/M (Middle) level) of the control signal PWM and outputs the detection result to the control circuit 21 (details will be described later).

The control circuit 21 also has a function of outputting an enable signal DREN having 3 values (H/M/L) common to the drive modules 10(1) to 10 (4). The enable signal DREN is output from the enable output terminal Tden to the driving modules 10(1) to 10 (4).

When DREN is equal to L (e.g., GND), the drive modules 10(1) to 10(4) are disabled.

When DREN is H (e.g., Vcc), the drive modules 10(1) to 10(4) are activated in the 1 st operation mode (an operation mode in which pulse driving of the switching voltages SW (1) to SW (4) is always performed in accordance with the control signals PWM1 to PWM 4).

When DREN is equal to M (e.g., Vcc/2), the drive modules 10(1) to 10(4) start the operation in the 2 nd operation mode (the operation mode in which the control signals PWM1 to PWM4 are switched to the M level and the switching voltages SW (1) to SW (4) are set to the output high impedance state (HiZ)) by themselves when zero-crossing detection of the inductor currents IL (1) to IL (4) is performed.

The control circuit 21 also has the following functions (details will be described below): when DREN is L or M, the input/output circuit 22 is appropriately set to the input standby state of the control signals PWM1 to PWM4, and each logic level is detected, thereby performing a transition process from the heavy load mode (PWM [ pulse width modulation ] mode) to the light load mode (PFM [ pulse frequency modulation ] mode), or performing model identification or connection determination of the drive modules 10(1) to 10 (4).

The internal voltage generator 23 is a circuit that generates and outputs an internal voltage Vreg15 based on the power supply voltage Vcc applied to the power supply terminal Tcc, and includes, for example, an LDO (Low Dropout). For example, Vcc is 3V, while Vreg is 1.5V. The internal voltage Vreg15 is output from the internal voltage output terminal Treg to the outside. The internal voltage Vreg15 output to the outside is input to the internal voltage input terminal Tregin and supplied to the control circuit 21.

The MOS switch 24 includes an NMOS transistor. The source of the MOS switch 24 is connected to the application terminal of the ground voltage GND, and the drain is connected to the interrupt terminal Tint. The interrupt terminal Tint is pulled up. The MOS switch 24 is controlled to be turned on or off by the control circuit 21. When the MOS switch 24 is in the off state, the interrupt signal INTB generated by the interrupt terminal Tint is at the H level, and when the MOS switch is in the on state, the interrupt signal INTB is at the L level. The control circuit 21 can notify an abnormal state to the outside by the interrupt signal INTB. In the case of an abnormal state, for example, the interrupt signal INTB is set to L level.

The 1 st terminals of the inductors L1(1) to L1(4) are connected to the output terminals of the driving modules 10(1) to 10(4), respectively. The 2 nd terminals of the inductors L1(1) to L1(4) are connected to the application terminal of the output voltage Vout (the high potential terminal of the load Z). Since the inductor currents IL (1) to IL (4) flow through the inductors L1(1) to L1(4), respectively, an output current Io obtained by adding the inductor currents IL (1) to IL (4) (IL (1) + IL (2) + IL (3) + IL (4)) can be supplied to the load Z.

The capacitor Co is connected between the application terminal of the output voltage Vout and the application terminal of the ground voltage PGND (between both terminals of the load Z), and smoothes the output voltage Vout.

Further, unused terminals among the control terminals Tp1 to Tp8 are externally connected to the application terminal of the internal voltage Vreg 15. In the example of fig. 1, since the control terminals Tp5 to Tp8 are not used, the control terminals are connected to the application terminal of the internal voltage Vreg 15.

The ground terminal Tgd is connected to the application terminal of the ground voltage GND.

In addition to the above-described circuit blocks, the power control device 20 may further include various protection circuits (UVLO (under voltage lock out)), OCP (over current protection ), and TSD (thermal shutdown, over temperature shutdown, etc.).

< internal construction of drive Module >

Fig. 2 is a diagram showing an internal configuration example of the drive module 10 of the switching power supply device 1. The drive module 10 may be understood as any of the 4-phase drive modules 10(1) to 10 (4). The same applies to the control signal PWM, the switching voltage SW, the inductor L1, and the inductor current IL, and corresponds to any of the control signals PWM1 to PWM4, the switching voltages SW (1) to SW (4), the inductors L1(1) to L1(4), and the inductor currents IL (1) to IL (4), respectively.

The drive module 10 of the present configuration example includes a switching output stage 11, a drive logic circuit 12, a zero-cross detection circuit 13, a logic level switching circuit 14, a logic level fixing circuit 15, an LDO16, and a power-on reset portion 17, which are integrated into a single package. The drive module 10 includes a control terminal TPWM, an enable input terminal TEN, a switch terminal TSW, a power supply terminal TCC, an input voltage terminal TVIN, and a ground terminal TGD as external terminals for establishing an electrical connection with the outside.

The switching output stage 11 includes an output transistor M1 formed of a P-channel MOS transistor as an example, and a synchronous rectification transistor M2 formed of an N-channel MOS transistor as an example. The source of the transistor M1 is connected to the application terminal of the input voltage PVin through the input voltage terminal TVIN. The drains of the transistors M1 and M2 are connected to a switch terminal TSW which is an application terminal of the switch voltage SW (i.e., an output terminal of the drive module 10). The source of the transistor M2 is connected to the application terminal of the ground voltage PGND via the ground terminal TGD.

Gate signals G1 and G2 are input to the gates of the transistors M1 and M2, respectively. The transistor M1 is turned on when G1 is L and turned off when G1 is H. The transistor M2 is off when G2 is L, and is on when G2 is H.

For example, when the transistor M1 is turned on and the transistor M2 is turned off, SW is equal to H (≈ PVin). Conversely, when the transistor M1 is turned off and the transistor M2 is turned on, SW is equal to L (≈ PGND). When both the transistors M1 and M2 are turned off, SW is HiZ (output high impedance state).

In addition, as the transistor M1, an N channel MOS transistor may be used instead of the P channel MOS transistor. However, in this case, a boosting means (a charge pump circuit or a bootstrap circuit) for making the H level of the gate signal G1 higher than the input voltage PVin is required.

In addition, the transistors M1 and M2 may be externally mounted on the rear stage of the driving module 10.

The driving logic circuit 12 generates the gate signals G1 and G2 in response to the control signal PWM and the zero-crossing detection signal ZX. The control signal PWM is input from the power supply control device 20 side via the control terminal TPWM. More specifically, the driving logic circuit 12 basically turns on the transistor M1 and turns off the transistor M2 when the PWM is H (e.g., Vcc), while turns off the transistor M2 when the PWM is H (e.g., G1 is L, and turns off the transistor M2 and turns on the transistor M2 when the PWM is L (e.g., GND).

However, when the transistor M2 is on (PWM — L, G1 — G2 — H) and the zero-crossing detection signal ZX is at the H level, for example, as the logic level at the time of zero-crossing detection, the driving logic circuit 12 is at G1 — H, G2 — L, and both the transistors M1 and M2 are off.

Zero-crossing detection circuit 13 detects a zero crossing of inductor current IL flowing when transistor M2 is in the on state (i.e., a state where inductor current IL has a value of zero or a value near the zero crossing), and generates zero-crossing detection signal ZX as a detection result. For example, the zero-crossing detection signal ZX becomes L level when no zero crossing is detected, and becomes H level when a zero crossing is detected.

The enable signal DREN is input from the power supply control device 20 side to the drive logic circuit 12 via the enable input terminal TEN. When DREN is H, the drive logic circuit 12 always operates in an operation mode in which pulse driving of the switching voltage SW is performed in response to the control signal PWM.

When DREN is equal to M, the drive logic circuit 12 sets the switch voltage SW in the output high impedance state (HiZ) at the time of zero-crossing detection of the inductor current IL, and instructs the logic level switching circuit 14 to switch the logic level. The instructed logic level switching circuit 14 switches the control signal PWM to an M level (e.g., Vcc/2) that is neither an H level (e.g., Vcc) nor an L level (e.g., GND) (details will be described later).

The logic level switching circuit 14 also performs an operation of switching the control signal PWM to the M level when the drive module 10 is started (details will be described later).

The logic level fixing circuit 15 is a mechanism for supplying identification information (for example, information for identifying whether the drive module 10 is of a large current output type or a small current output type) of each model to the power supply control device 20 (details will be described later).

LDO16 is an example of an internal voltage generator that generates internal voltage REG15 based on power supply voltage Vcc. The internal voltage REG15 is supplied to the drive logic circuit 12 and the like. The internal voltage REG15 is 1.5V, for example, and REG15 is Vcc/2.

The power-on reset unit 17 is a circuit that resets and releases the drive logic circuit 12 by a reset signal when the internal voltage REG15 that rises when the LDO16 starts reaches a predetermined voltage.

In addition, in the drive module 10, various protection circuits (UVLO, OCP, TSD, and the like) may be integrated in addition to the circuit blocks.

< logic level fixing Circuit >

As described above, the drive module 10 is provided with the pull-down (fig. 3) or pull-up (fig. 4) logic level fixing circuit 15 as a mechanism for notifying the power supply control device 20 of identification information of each model. Hereinafter, the circuit configuration and operation will be described with reference to the drawings.

Fig. 3 shows a 1 st configuration example (pull-down type) of the logic level fixing circuit 15. The logic level fixing circuit 15 of the present configuration example is a circuit block integrated in the large current output type (for example, Io 15A) drive module 10, and includes a resistor 151, an inverter 152, an N-channel MOS transistor 153, and an inverter 154.

The 1 st terminal of the resistor 151 is connected to the application terminal of the control signal PWM. The 2 nd terminal of the resistor 151 and the input terminal of the inverter 152 are connected to the drain of the transistor 153. The output of inverter 152 is connected to the input of drive logic circuit 12. The source and the back gate of the transistor 153 are connected to the application terminal of the ground voltage PGND. A gate of the transistor 153 is connected to an output terminal of the inverter 154. An input terminal of the inverter 154 is connected to the application terminal of the enable signal DREN.

When the enable signal DREN is at H level or M level (equal to a logic level at the time of starting the driving module 10, for example, Vcc or Vcc/2), the transistor 153 is turned off. Therefore, the control signal PWM is input to the drive logic circuit 12 without being pulled down.

On the other hand, when the enable signal DREN is at the L level (equal to the logic level at the time of disabling the drive module 10, for example, GND), the transistor 153 is turned on. Therefore, the control signal PWM is pulled down to L level (≈ GND).

Fig. 4 shows a configuration example 2 (pull-up type) of the logic level fixing circuit. The logic level fixing circuit 15 of the present configuration example is a circuit block integrated in the low current output (for example, Io 5A) drive module 10, and includes a resistor 151, an inverter 152, and a P-channel MOS transistor 155.

The 1 st terminal of the resistor 151 is connected to the application terminal of the control signal PWM. The 2 nd terminal of the resistor 151 and the input terminal of the inverter 152 are connected to the drain of the transistor 155. The output of inverter 152 is connected to the input of drive logic circuit 12. The source and the back gate of the transistor 155 are connected to the application terminal of the power supply voltage Vcc. A gate of the transistor 155 is connected to the application terminal of the enable signal DREN.

When the enable signal DREN is at H level or M level (equal to a logic level at the time of activation of the driver module 10, for example, Vcc or Vcc/2), the transistor 155 is turned off. Therefore, the control signal PWM is input to the drive logic circuit 12 without being pulled up.

On the other hand, when the enable signal DREN is at the L level (equal to the logic level at the time of prohibition of the drive module 10, for example, GND), the transistor 155 is turned on. Therefore, the control signal PWM is pulled up to the H level (≈ Vcc).

As such, the logic level fixing circuit 15 fixes the control signal PWM to the logic level (H level or L level) of each model during the period in which the driving module 10 is disabled (DREN ═ L), in other words, until the driving module 10 is enabled (DREN ═ H or DREN ═ M).

< logic level switching circuit (M level output circuit) >

Fig. 5 is a diagram showing an example of the configuration of the logic level switching circuit 14. Logic level switching circuit 14 includes a P-channel MOS transistor 141, a resistor 142, a P-channel MOS transistor 143, an N-channel MOS transistor 144, a P-channel MOS transistor 145, and an inverter 146.

The source and the back gate of the transistor 141 are connected to a terminal to which the power supply voltage Vcc is applied. The gate of the transistor 141 is connected to the output of the inverter 146. An input terminal of the inverter 146 is connected to the application terminal of the enable signal DREN. The drain of the transistor 141 is connected to the 1 st terminal of the resistor 142. A node N14 connecting the 2 nd terminal of the resistor 142 to the source and back gate of the transistor 143 is connected to the gate of the transistor 144. The gate of transistor 143 is connected to the output of LDO 16. That is, the internal voltage REG15 output from LDO16 is applied to the gate of transistor 143. A drain of the transistor 143 is connected to a terminal to which the ground voltage PGND is applied. The source and back gate of the transistor 145 are connected to the application terminal of the power supply voltage Vcc. A drain of transistor 145 is connected to a drain of transistor 144. The source and back gate of the transistor 144 are connected to the application terminal of the control signal PWM. The gate of the transistor 145 is driven by a gate signal G12 output from the drive logic circuit 12.

As shown in fig. 5, the zero-crossing detection circuit 13 includes a comparator 131. The non-inverting input terminal (+) of the comparator 131 is connected to the application terminal of the switching voltage SW. The inverting input terminal (-) of the comparator 131 is connected to the application terminal of the ground voltage PGND.

When the inductor current IL in the positive direction (the direction from the transistor M2 to the inductor L1) flows while the transistor M2 is on (PWM is L, and G1 is G2 is H), SW < PGND, and ZX is L. In this case, since the drive logic circuit 12 sets the gate signal G12 to H, the transistor 145 is turned off, no drain current flows through the transistor 144, and the PWM (PWM) is maintained at L (e.g., GND).

On the other hand, when the inductor current IL starts to flow in the negative direction (the direction from the inductor L1 toward the transistor M2), ZX is H since SW > PGND. In this case, since the driving logic circuit 12 sets the gate signal G12 to L, the transistor 145 is turned on, a drain current flows through the transistor 144, and the source is biased toward the intermediate voltage VM (REG 15+ Vth-Vth). By this operation, the control signal PWM is switched from the L level (GND) to the M level (VM). The M level is REG15 is Vcc/2.

When the drive module 10 is started, the drive logic circuit 12 also switches the control signal PWM to the M level. This will be described below.

< input/output Circuit >

Fig. 6 is a diagram showing an example of the configuration of the input/output circuit 22. The input/output circuit 22 of the present configuration example includes a P channel MOS transistor 221, N channel MOS transistors 222 and 223, a resistor 224, and a logic level detection unit 225.

The source and the back gate of the transistor 221 are connected to a terminal to which the power supply voltage Vcc is applied. The drains of the transistors 221 and 222 and the 1 st terminal of the resistor 224 are connected to the input/output terminal of the control signal PWM. Terminal 2 of resistor 224 is connected to the drain of transistor 223. The source and the back gate of each of the transistors 222 and 223 are connected to the application terminal of the ground voltage GND.

Further, gate signals S1 to S3 are input from the control circuit 21 to the gates of the transistors 221 to 223, respectively.

For example, when the H level of the control signal PWM is output, S1 ═ S2 ═ S3 ═ L. As a result, the transistor 221 is turned on, and the transistors 222 and 223 are turned off, so that PWM is equal to H (≈ Vcc). On the other hand, when the L level of the control signal PWM is output, S1 is H, S2 is H, and S3 is L. As a result, the transistor 222 is turned on, and the transistors 221 and 223 are turned off, so that PWM is equal to L (≈ GND).

When the input of the control signal PWM is on standby, S1 is H in S3 and L in S2. As a result, the transistors 221 and 222 are turned off, and the transistor 223 is turned on, so that the control signal PWM is pulled down through the resistor 224. Therefore, the control signal PWM is at a logic level corresponding to the operation state of the logic level switching circuit 14 (fig. 5) or the logic level fixing circuit 15 (fig. 3 and 4) (details will be described later).

When the input/output circuit 22 is in the input standby state, the logic level detection unit 225 detects the logic level (H/L/M) of the control signal PWM and outputs the detection result to the control circuit 21 as a logic level detection signal S4.

< Start-Up step >

Here, the startup procedure of the switching power supply device 1 will be described with reference to the flowchart shown in fig. 7 and the timing charts shown in fig. 8 to 10.

Fig. 8 to 10 show waveforms of the power supply voltage Vcc, the standby signal STBY, the internal voltage Vreg15 (power supply control device 20), the enable signal EN, the state of the control circuit 21, the interrupt signal INTB, the internal voltage REG15 (drive module 10), the enable signal DREN, and the control signals PWM1 to PWM8 in the order from top to bottom.

First, the timing chart shown in fig. 8 will be described with reference to the flowchart shown in fig. 7. Fig. 8 shows an example of a case where the drive module scan is determined to be normal as described below. Fig. 8 shows a case where the connection mode of the drive module 10 to the power supply control device 20 is the state shown in fig. 1 (that is, 4 drive modules 10 are connected).

At time t1 in fig. 8, the power supply voltage Vcc starts rising. Then, at time t2, when the power supply voltage Vcc reaches the UVLO release voltage, the UVLO is released in the power control device 20. Thereafter, at time t3, when the standby signal STBY rises to the H level, the internal voltage Vreg15 starts rising. Accordingly, the control signals PWM5 to PWM8 generated from the control terminals Tp5 to Tp8 connected to the application terminal of the internal voltage Vreg15 start rising. If the internal voltage Vreg15 rises to 1.5V, then along with this, the control signals PWM 5-PWM 8 also rise to 1.5V.

Also, at time t4, the control circuit 21 shifts to the drive module SCAN state (DrMOS _ SCAN) (step S1 of fig. 7).

Thereafter, at time t5, the control circuit 21 starts the drive module configuration checking process (step S2 of fig. 7). At time t5, the enable signal DREN is at the L level. Here, in the example of fig. 8, since the logic level fixing circuit 15 in the drive module 10 is of a pull-down type (fig. 3), the control signals PWM1 to PWM4 are pulled down to the L level. Control signals PWM5 to PWM8 are all at 1.5V (M level).

In the drive module configuration checking process, the control circuit 21 checks whether any of the control terminals Tp1 to Tp8 is used for connection to the drive module 10. More specifically, the control circuit 21 checks whether or not the combination of the levels of the control signals PWM1 to PWM8 matches a predetermined allowable combination. At this time, since the input-output circuit 22 of the power supply control device 20 is in the input standby state, the logic level (H/L/M) of the control signal PWM is detected.

For example, in the mode in which 1 drive module 10 is connected, only the control terminal Tp1 among the control terminals Tp1 to Tp8 is allowed to be connected, and therefore, "control signal PWM equals L or H, and" control signal other than PWM1 equals M "as an allowed combination of control signal levels. In the case of the mode in which 2 drive modules 10 are connected, only the control terminals Tp1 and Tp2 among the control terminals Tp1 to Tp8 are allowed to be connected, and therefore, "control signals PWM1 and 2 are all L or all H, and" control signals other than PWM1 and 2 are M "as an allowed combination of control signal levels. Hereinafter, similarly, allowable combinations of modes in which a maximum of 8 drive modules 10 are connected are predetermined.

In the example of fig. 8, since the level combination of the actual control signals PWM matches the allowable combination such as "PWM 1-4 is L, PWM 5-8 is M", "PWM 1-4 is all L or all H, and the control signals other than PWM 1-4 are M", it is determined that the control terminals Tp 1-Tp 4 are used for connection and the other terminals are not used.

Here, since the logic level fixing circuit 15 is of a pull-down type (fig. 3) when PWM is L, the driver module 10 can be determined to be of a large current output type, for example. On the other hand, when the PWM is H, the logic level fixing circuit 15 is of a pull-up type (fig. 4), and thus, for example, the driver module 10 can be determined to be of a low current output type. In the example of fig. 8, since the PWM signals 1 to 4 are L, it can be determined that the driver modules 10 connected to the control terminals Tp1 to Tp4 are of the high-current output type. In addition, the reason why the allowable level combinations are set to "all" or "all" as "H" as described above is to prohibit the use of some of the driver modules 10 of different models.

By performing the type determination of the drive module 10, the control parameters (such as the feedback coefficient and the phase compensation amount of the output current feedback loop) of the power supply control device 20 can be switched to the optimum values.

Since the actual number of drive phases (4 phases in the example of fig. 8) can be determined, phase shift control can be performed in accordance with the determined number (details will be described later).

In fig. 8, when the drive module configuration check processing described above is ended at time t6, and the drive module configuration is determined to be normal (Yes in step S3 of fig. 7), the control circuit 21 proceeds to the drive module connection check processing (step S4 of fig. 7).

Here, when it is determined that the drive module configuration inspection process is normal, connection failure of the control terminals (Tp1 to Tp8) may occur. For example, the connection between the control terminal and the drive module 10 may be broken, or an open failure may occur in the control terminal. In this case, when the driver module constitutes the inspection process, the level of the control signal may occasionally become a level for determining normality. In fig. 8, for example, although a connection failure actually occurs in at least one of the control terminals Tp1 to Tp4, the levels of the control signals PWM1 to PWM4 may occasionally become L.

Therefore, in the present embodiment, after the drive module configuration inspection process, the drive module connection inspection process is performed to confirm whether or not a connection failure of the control terminal has occurred. In fig. 8, if the drive module connection checking process is started, the control circuit 21 makes the enable signal DREN rise to the M level at time t 7. Then, LDP16 in the driving module 10 is activated, and the internal voltage REG15 starts to rise.

In the logic level switching circuit 14 (fig. 5), the transistor 141 is turned on by the enable signal DREN at the M level. Thereby, the constant current circuit including the transistor 141 and the resistor 142 is turned on. Further, since the internal voltage REG15 rises to 1.5V, the voltage applied to the gate of the transistor 143 in the logic level switching circuit 14 (equal to the internal voltage REG15) also rises to 1.5V.

When the internal voltage REG15 reaches a prescribed voltage lower than 1.5V, the power-on reset section 17 releases the reset of the drive logic circuit 12 with a reset signal. At this time, after the internal voltage REG15 reaches the predetermined voltage, the time for the internal processing of the power-on reset unit 17 is delayed, and the drive logic circuit 12 is released from the reset.

When the reset of the drive logic circuit 12 is released at time t8, the drive logic circuit 12 outputs the gate signal G12 of the L level to the logic level switching circuit 14. Thereby, the transistor 145 is turned on, and the control signal PWM is switched to the M level.

At this time, since the input/output circuit 22 of the power supply control device 20 is in the input standby state, the logic level (H/L/M) of the control signal PWM is detected. The control circuit 21 checks whether or not all of the control signals PWM of the control terminals determined to be used in the previous drive module configuration checking process are at the M level. If all of the control terminals are at M level, it is determined that the connection failure has not occurred in the control terminal used, and it is determined that the control terminal is in a normal state. In the example of fig. 8, all of the control signals PWM1 to PWM4 of the control terminals Tp1 to Tp4 to be used are determined to be M level, and therefore, it is determined to be in a normal state.

The drive logic circuit 12 switches the gate signal G12 to the L level and then to the H level. Then, the control signal PWM is maintained at the M level only by the source capability of the logic level switching circuit 14. Therefore, the behavior of the control signal PWM thereafter is not hindered.

In fig. 8, at time t9, the control circuit 21 makes the enable signal DREN fall to the L level, so that the LDO16 stops and the internal voltage REG15 falls. Thereby, the drive logic circuit 12 is reset by the power-on reset section 17. Since the enable signal DREN is lowered to the L level, the control signals PWM1 to PWM4 are at the L level by the logic level fixing circuit 15.

As shown in fig. 8, if it is determined to be normal in the drive module connection check process (yes in step S5 of fig. 7), the control circuit 21 transitions to the STANDBY State (STANDBY) (step S6 of fig. 7, time t 10).

Thereafter, when the enable signal EN rises to the H level, the control circuit 21 shifts to the POWER-ON state (POWER _ ON) (step S7 of fig. 7, time t 11). In fig. 8, after the power-on state is reached, at time t12, the control circuit 21 raises the enable signal DREN to the M level. Then, the internal voltage REG15 starts to rise similarly to the operation at the time t7, and the power-on reset unit 17 releases the reset of the drive logic circuit 12 at a time t13 delayed from the time t 12. Thus, the logic level switching circuit 14 switches the control signal PWM to the M level in accordance with the L level gate signal G12 outputted from the drive logic circuit 12, as described above. The drive logic circuit 12 switches the gate signal G12 to the L level and then to the H level. Then, the control signal PWM is maintained at the M level only by the source capability of the logic level switching circuit 14. Therefore, the behavior of the control signal PWM thereafter is not hindered.

At time t14 later than time t13, the control circuit 21 raises the enable signal DREN to the H level. Then, the input/output circuit 22 of the power supply control device 20 is fixed to the output state (i.e., the state in which the transistor 223 in fig. 6 is off and the logic level detection unit 225 is inactive). The drive logic circuit 12 operates in the 1 st operation mode (i.e., an operation mode in which the pulse drive of the switching voltage SW is always performed in accordance with the control signal PWM). The switching pulses of the control signal PWM are continuously generated at a fixed switching frequency, and the drive logic 12 drives the switching output stage 11 according to the level of the control signal PWM. Thus, even if the load Z becomes light, the switching power supply device 1 does not switch from the heavy load mode (PWM mode) to the light load mode (PFM mode).

Here, as shown in fig. 8, phase shift control is performed, that is, the control signal PWM is generated while shifting the phase.

Note that, although not shown in fig. 8, when the enable signal DREN is switched from the H level to the M level, the drive module 10 starts up in the 2 nd operation mode (an operation mode in which the control signal PWM is automatically switched to the M level and the switching voltage SW is automatically set to the output high impedance state (Hiz) when zero crossing of the inductor current IL is detected).

In this case, the input/output circuit 22 of the power supply control device 20 switches to the input standby state at an appropriate timing after the control signal PWM is switched from the H level to the L level, and becomes a state of detecting the logic level (H/L/M) of the control signal PWM.

Since the control signal PWM is at the L level, when the zero-crossing detection signal ZX rises to the H level while the transistor M2 is in the on state and the zero crossing of the switching voltage SW is detected, the logic level switching circuit 14 switches the control signal PWM to the M level because the drive logic circuit 12 sets the gate signal G12 to the L level.

When the control signal PWM is switched from the L level to the M level, the control circuit 21 recognizes the zero crossing of the inductor current IL detected by the driving module 10, and can shift the switching power supply device 1 from the heavy load mode (PWM mode) to the light load mode (PFW mode) without delay. Therefore, the switching pulses of the control signal PWM can be reduced, and the efficiency at the time of light load can be improved.

It is to be noted that, when the drive module 10 is activated in the 2 nd operation mode (DREN ═ M), the control signal PWM does not need to be switched to the M level as long as the zero-crossing detection signal ZX rises to the H level, and the switching power supply device 1 does not need to be switched from the heavy load mode (PWM mode) to the light load mode (PFM mode).

Next, a timing chart shown in fig. 9 will be described. In fig. 9, the drive module configuration check process is started at time t51, but at this time, the control signal PWM3 does not become the L level due to the connection failure of the control terminal Tp 3. Therefore, the control circuit 21 determines that the combination of the levels of the control signals PWM1 to PWM8 does not match any of the predetermined allowable combinations, and determines that the state is abnormal (No in step S3 in fig. 7).

Accordingly, at time t52 in fig. 9, the control circuit 21 shifts to an ERROR state (ERROR) and turns on the MOS switch 24, thereby lowering the interrupt signal INTB to the L level. An abnormality is notified to the outside by the interrupt signal INTB.

Thereafter, as shown in fig. 9, the enable signal EN rises to the H level (time t110), and the control circuit 21 is still in the error state, so that the enable signal DREN is maintained at the L level, the drive module 10 is not activated, and the switching operation of the switching power supply device 1 is not performed.

Further, even when the drive module 10 having the pull-up type logic level fixing circuit 15 is connected to the control terminal Tp3 corresponding to the control signal PWM3, for example, the control signal PWM3 is at the H level, and therefore, the drive module configuration checking process determines that the drive module is in an abnormal state.

In this way, in the drive module configuration checking process, when it is determined that the control terminal is not in the use state, the switching operation of the switching power supply device 1 can be avoided.

Next, a timing chart shown in fig. 10 will be described. In fig. 10, the drive module configuration check process is started at time t51, but at this time, all of the control signals PWM1 to PWM4 are at the L level. Therefore, the control circuit 21 determines that the combination of the levels of the control signals PWM1 to PWM8 matches the predetermined allowable combination, and determines that the state is normal (yes in step S3 in fig. 7).

However, in fig. 10, a connection failure actually occurs in the control terminal Tp4 corresponding to the control signal PWM4, and in the drive module configuration checking process, the control signal PWM4 occasionally becomes the L level.

At time t53, the drive module configuration check process ends, and the drive module connection check process starts (step S4 in fig. 7). At time t71, the enable signal DREN rises to the M level, and the logic level switching circuit 14 switches the control signal PWM to the M level by the drive logic circuit 12 released from the reset (time t 81). However, in fig. 10, since the control terminal Tp4 is connected in a poor manner as described above, the control signal PWM4 causes an abnormality in which the level is lowered from the M level. Therefore, it is determined that the control circuit 21 is in the abnormal state (no (N) of step S5 in fig. 7).

After the control circuit 21 lowers the enable signal DERN to the L level, it transits to the error state at time t82 (step S8 in fig. 7).

Since the state is shifted to the error state, even if the enable signal EN rises to the H level (at time t110), the control circuit 21 maintains the enable signal DREN at the L level, does not activate the drive module 10, and does not perform the switching operation of the switching power supply device 1.

In this way, even if a connection failure occurs in the control terminal and the drive module configuration inspection process is occasionally determined to be normal, the connection failure can be detected in the drive module connection inspection process, and the switching operation of the switching power supply device 1 can be avoided.

As described above, in the present embodiment, the driving module configuration checking process and the driving module connection checking process are performed by appropriating the control signal PWM, and it is possible to confirm the use state of the control terminal, the model number of the connected driving module, and whether or not the connection failure of the control terminal has not occurred. Further, the zero-crossing detection notification from the drive module 10 to the power supply control device 20 can be performed by using the control signal PWM. Therefore, the number of terminals of the power supply control device 20 and the drive module 10 can be suppressed from increasing.

< Multi-channel Power supply control device >

As a variation of the embodiment, the power supply control device 20 may also handle control of the drive modules 10 in multiple channels. This will be explained below.

Fig. 11 is a diagram showing a configuration of a switching power supply device 1 including an example of a power supply control device 20 that controls the drive modules 10 in multiple channels. The power control device 20 shown in fig. 11 corresponds to 2 channels as an example. The number of channels corresponds to the number of enable signals DREN that can be output.

The power supply control device 20 shown in fig. 11 has enable output terminals Tden1 and Tden2, and the control circuit 21 can output an enable signal DREN1 from the enable output terminal Tden1 and an enable signal DREN2 from the enable output terminal Tden 2. The power supply control device 20 in fig. 11 includes control terminals Tp1 to Tp4, for example, and can output control signals PWM1 to PWM4 via the control terminals Tp1 to Tp 4. That is, the power control device 20 can control the 4-phase drive module 10 using 2 channels.

In fig. 11, for example, the drive modules 10(1) to 10(3) connected to the enable output terminal Tden1(1ch) are connected to respective control terminals Tp1 to Tp 3. The control terminal Tp4 is connected to the drive module 10(4) connected to the enable output terminal Tden2(2 ch). That is, 3 phases (1ch) +1 phase (2ch) are used.

The driver modules 10(1) - (10) (3) of the same channel (1ch) are respectively connected to the 1 st terminals of the inductors L1(1) - (L1 (3), and the 2 nd terminals of the inductors L1(1) - (L1 (3) are commonly connected to the 1 st terminal of the capacitor Co 1. The 1 st terminal of the capacitor Co1 becomes the application terminal of the output voltage Vout 1. In addition, the driving modules 10(4) of the other same channels (2ch) are connected to the 1 st terminal of the inductor L1(4), and the 2 nd terminal of the inductor L1(4) is commonly connected to the 1 st terminal of the capacitor Co 2. The 1 st terminal of the capacitor Co2 becomes the application terminal of the output voltage Vout 2. That is, each channel constitutes a DC/DC converter.

In addition to the configuration shown in fig. 11, for example, a connection configuration of the driver modules 10 such as 4-phase (1ch) + 0-phase (2ch is not used), 2-phase (1ch) + 2-phase (2ch) and the like may be used. Note that, as in the above-described embodiment, the terminal not used among the control terminals Tp1 to Tp4 may be connected to the application terminal of the internal voltage Vreg15 to set the control signal PWM to the M level.

Here, fig. 12 is a timing chart showing an example of the startup procedure in the configuration shown in fig. 11. Fig. 12 shows waveforms of the internal voltage REG15, the enable signals DREN1, DREN2, and the control signals PWM1 to PWM4 in the order from top to bottom on the drive module 10 side.

At time t15 in fig. 12, the drive module configuration check process is started. At this time, since both the enable signals DREN1 and DREN2 are at the L level, the control circuit 21 is notified of the levels of the control signals PWM1 to PWM4 from the logic level fixing circuit 15 on the drive module 10 side via the input/output circuit 22 in the input standby state. Fig. 12 shows an example in which, in the configuration shown in fig. 11, each of the drive modules 10(1) to 10(4) has the pull-down logic level fixing circuit 15, and each of the control signals PWM1 to PWM4 has an L level.

In the drive module configuration checking process, as described above, the control circuit 21 checks whether or not the combination of the levels of the control signals PWM matches the allowable combination. In fig. 12, the combination of the control signals PWM1 to PWM4 all L matches the allowable combination, and therefore it is determined as the normal state. Here, if it is determined that the combination of the levels of the determination control signals PWM1 to PWM4 does not match the allowable combination, it is determined that the state is abnormal, and the control circuit 21 transitions to an error state as in the above-described embodiment.

In fig. 12, at time t16, the drive module configuration check process ends, and the drive module connection check process starts. Then, at time t17, the control circuit 21 raises only DREN1 of the enable signals DREN1 and DREN2 to the M level. Accordingly, the internal voltage REG15 in the drive modules 10(1) to 10(3) corresponding to the enable signal DREN1 rises, the reset of the drive logic circuits 12 is released, and the control signals PWM1 to PWM3 are switched to the M level by the logic level switching circuits 14. Thus, the drive module 10 capable of recognizing 1ch is connected to the control terminals Tp1 to Tp 3.

At time t19, the control circuit 21 causes the enable signal DREN1 to fall to the L level, and the control signals PWM1 to PWM3 to fall to the L level. Thereafter, at time t20, the control circuit 21 raises only DREN2 of the enable signals DREN1 and DREN2 to the M level. Accordingly, the internal voltage REG15 in the driving module 10(4) corresponding to the enable signal DREN2 rises, the reset of the driving logic circuit 12 is released, and the control signal PWM4 is switched to the M level by the logic level switching circuit 14 (time t 21). Thus, the drive module 10 capable of recognizing 2ch is connected to the control terminal Tp 4.

As described above, in the present embodiment, the number or connection terminals of the drive modules 10 per channel can be automatically identified by using the control signal PWM, and an increase in the number of terminals of the power supply control device 20 and the drive modules 10 can be suppressed. For example, the following method is also considered in the power supply control device 20: the connection mode is detected by providing a new setting terminal, applying a divided voltage to the terminal by changing the external resistance voltage division ratio, and monitoring the divided voltage by an ADC (AD converter) inside the power supply control device 20.

In this embodiment, even if the number of channels or the number of phases increases, it is not necessary to increase the number of terminals.

< others >

In addition, various technical features disclosed in the present specification may be modified in various ways in addition to the embodiments described above without departing from the gist of technical creation. That is, the embodiments are to be considered in all respects as illustrative and not restrictive, and it is understood that the technical scope of the present invention is not limited to the embodiments, and includes meanings equivalent to the claims and all changes included in the scope.

For example, in the drive module connection check process, the control circuit 21 may raise the enable signal DREN (DREN1, DREN2) to, for example, the H level, not only to the M level, but also to a level at which the drive module 10 can be activated.

The switching power supply device of the present invention is preferably mountable on a vehicle, for example. The effect of the present invention is important from the viewpoint that the control terminal-related failure detection has been required by international standard ISO26262 for electrical/electronic-related functional safety of automobiles.

[ industrial applicability ]

The present invention is applicable to a multiphase switching power supply device that supplies power to a load (CPU or the like) that consumes a large current, for example.

[ description of symbols ]

1 switching power supply device

10. 10(1) -10 (4) drive module (DrMOS)

11 switching output stage

12 drive logic circuit

13 zero crossing detection circuit

131 comparator

14 logic level switching circuit

141P channel type MOS transistor

142 resistance

143P channel MOS transistor

144N channel type MOS transistor

145P channel type MOS transistor

146 inverter

15 logic level fixing circuit

151 resistance

152 inverter

153N channel type MOS transistor

154 inverter

155P channel type MOS transistor

16 LDO

17 power-on reset part

20 Power control device (PMIC)

21 control circuit

22 input/output circuit

221P channel type MOS transistor

222. 223N channel type MOS transistor

224 resistance

225 logic level detecting section

23 internal voltage generating part

24 MOS switch (N channel type MOS transistor)

Co capacitor

L1, L1(1) -L1 (4) inductor

M1 output transistor (P channel type MO transistor)

M2 synchronous rectification transistor (N channel type MOS transistor)

Tp 1-8 control terminal

Tden, Tden1, Tden2 enable output terminal

Tcc power supply terminal

Tst standby terminal

Ten enable input terminal

Treg internal voltage output terminal

Tregin internal voltage input terminal

Tint interruption terminal

Tgd ground terminal

Ts +, Ts-feedback input terminal

TPWM control terminal

TEN enable input terminal

TCC power supply terminal

TVIN input voltage terminal

TSW switch terminal

TGD ground terminal.