阅读说明：本技术 一种中频方波等离子体激发电源 (Medium-frequency square wave plasma excitation power supply ) 是由 刘力 张小彬 于 2021-09-23 设计创作，主要内容包括：本申请涉及特种电源技术领域,特别地涉及一种中频方波等离子体激发电源,包括：电压调整模块、应力吸收与预输出电路、逆变与输出模块；其中,所述电压调整模块的输入端与外界输入信号连接,所述电压调整模块、所述应力吸收与预输出电路、所述逆变与输出模块依次电性连接；输入信号通过电压调整模块输入调整电压,经由逆变与输出模块逆变为交流电,并由应力吸收与预输出电路前端的尖峰电压稳定下一周期的逆变器输入电压。本申请中,输入信号通过电压调整模块输入调整电压,经由逆变与输出模块逆变为交流电输出方波,同时应力吸收与预输出电路吸收逆变与输出模块输入电压应力端,提高了安全性能,延长了使用寿命。(The application relates to the technical field of special power supplies, in particular to an intermediate frequency square wave plasma excitation power supply, which comprises: the device comprises a voltage adjusting module, a stress absorbing and pre-outputting circuit and an inverting and outputting module; the input end of the voltage adjusting module is connected with an external input signal, and the voltage adjusting module, the stress absorbing and pre-outputting circuit and the inverting and outputting module are sequentially and electrically connected; the input signal is input into the adjusting voltage through the voltage adjusting module, is inverted into alternating current through the inverting and outputting module, and is stabilized by the peak voltage at the front end of the stress absorbing and pre-outputting circuit. In this application, input signal passes through voltage adjustment module input adjustment voltage, via the contravariant and output module contravariant for alternating current output square wave, stress absorption and output circuit absorb contravariant and output module input voltage stress end in advance simultaneously, have improved the security performance, have prolonged life.)

1. An intermediate frequency square wave plasma excitation power supply, comprising: the device comprises a voltage adjusting module, a stress absorbing and pre-outputting circuit and an inverting and outputting module; the input end of the voltage adjusting module is connected with an external input signal, and the voltage adjusting module, the stress absorbing and pre-outputting circuit and the inverting and outputting module are sequentially connected;

the input signal is input into the adjusting voltage through the voltage adjusting module, is inverted into alternating current through the inverting and outputting module and outputs square waves, the stress absorbing and pre-outputting circuit absorbs the voltage stress of the inverting and outputting module, and the voltage stress provides stable voltage for the next period of output.

2. The mid-frequency square-wave plasma excitation power supply according to claim 1, wherein the voltage adjustment module comprises at least two voltage adjustment circuits connected in parallel.

3. The mid-frequency square wave plasma excitation power supply according to claim 1, wherein the inverting and outputting module comprises at least two inverting and outputting circuits connected in parallel.

4. The mid-frequency square wave plasma excitation power supply of claim 2, wherein the voltage regulation circuit comprises: the circuit comprises a diode D1, a rectifier tube Q1-sr, an inductor L1-a and an MOS tube Q1;

the negative electrode of the diode D1 is electrically connected with one end of a capacitor C1, the positive electrode of the diode D1 is electrically connected with one end of the inductor L1-a and the drain electrode of the MOS tube Q1, the other end of the inductor L1-a is electrically connected with the stress absorption and pre-output circuit and the inversion and output module, the source electrode of the MOS tube Q1 is electrically connected with the stress absorption and pre-output circuit, and the gate electrode of the MOS tube Q1 is connected with an external signal;

the source electrode of the rectifying tube Q1-sr is electrically connected with the anode of the diode D1, the drain electrode of the rectifying tube Q1-sr is electrically connected with the cathode of the diode D1, and the grid electrode of the rectifying tube Q1-sr is connected with an external signal.

5. The mid-frequency square-wave plasma excitation power supply according to claim 4, wherein the inverting and output circuit comprises; MOS transistor Q5, MOS transistor Q6, MOS transistor Q7, MOS transistor Q8, inductor L2 and resistor R1;

the drain of the MOS transistor Q5 is electrically connected to the cathode of the diode D1 and the drain of the MOS transistor Q6, the source of the MOS transistor Q5 is electrically connected to the drain of the MOS transistor Q7 and one end of the resistor R1, and the source of the MOS transistor Q6 is electrically connected to one end of the inductor L2 and the drain of the MOS transistor Q8;

the sources of the MOS transistor Q7 and the MOS transistor Q8 are both electrically connected with the negative electrode of the stress absorption and pre-output circuit;

the other end of the inductor L2 is electrically connected with the other end of the resistor R1;

the gates of the MOS transistor Q5, the MOS transistor Q6, the MOS transistor Q7 and the MOS transistor Q8 are all externally contacted with signals.

6. The mid-frequency square-wave plasma excitation power supply according to claim 5, further comprising a capacitor C2 or a gas to be excited into a plasma in parallel with the resistor R1.

7. The mid-frequency square-wave plasma excitation power supply according to claim 4, wherein the stress absorbing and pre-outputting circuit comprises: the diode D5, the diode D6, the capacitor C3, the resistor R4 and the resistor R5;

the anode of the diode D6 is electrically connected to the other end of the capacitor C1 and the source of the MOS transistor Q1, the cathode of the diode D6 is electrically connected to one end of the capacitor C3 and the anode of the diode D5, and the cathode of the diode D5 is electrically connected to one end of the inductor L1-a;

the cathode of the diode D5 is electrically connected with the inductor L1-a and the inversion and output module, and the other end of the capacitor C3 is electrically connected with the cathode of the diode D1 and the inversion and output module;

the resistor R5 is connected in parallel with the capacitor C3, and the resistor R4 is connected in parallel with the diode D5.

8. The mid-frequency square-wave plasma excitation power supply according to claim 1, wherein the voltage adjustment module comprises a voltage adjustment circuit.

9. The mid-frequency square-wave plasma excitation power supply according to claim 1, wherein the inverting and output module comprises an inverting and output circuit.

10. The IF square wave plasma excitation power supply according to claim 5, wherein said MOS transistor Q1, said MOS transistor Q5, said MOS transistor Q6, said MOS transistor Q7, said MOS transistor Q8 are all N-type SIC MOSFETs or IGBTs.

Technical Field

The application relates to the technical field of special power supplies, in particular to an intermediate frequency square wave plasma excitation power supply.

Background

The special power supply, i.e. a special kind of power supply, mainly has a particularly high output voltage and a particularly high output current, or has a particularly high requirement on stability, dynamic response and ripple, or requires that the voltage or current output by the power supply is pulsed or has some other requirements. This makes the design and production of such power supplies more specific and even more stringent requirements than conventional power supplies. At present, the domestic plasma excitation power supply is one of special power supplies.

Injecting a specific mixed gas into a specific container, and under the conditions of specific high pressure and high temperature, externally applying a specific electric field to discharge the gas, wherein the gas discharge can generate plasma, electrons in a part of ionized gas accelerated by the externally applied electric field collide with neutral molecules, energy obtained from the electric field is transferred to the gas, and the elastic collision of the electrons and the neutral molecules causes the increase of molecular kinetic energy, which is expressed as temperature rise; while inelastic collisions result in excitation (electrons in a molecule or atom transition from a low energy level to a high energy level), dissociation (molecules break down into atoms) or ionization (outer electrons of a molecule or atom change from a bound state to a free electron), and the hot gas transfers energy to the surrounding environment by conduction, convection and radiation. Under certain conditions, the input energy and the loss energy in a given volume are equal, the rate of energy transfer between electrons and heavy particles (ions, molecules and atoms) is proportional to the collision frequency (the number of collisions per unit time), and in dense gases, collisions are frequent, and the average (temperature) of the two types of particles is easily balanced, so the electron temperature and the gas temperature are approximately equal, which is the common situation when the gas pressure is above one atmosphere, commonly referred to as thermal plasma or equilibrium plasma. The core device for generating such plasma is the plasma excitation power supply.

Different application processes of plasma have different requirements on plasma excitation power supply, and the requirements mainly refer to the shape of pulse, how high voltage is, what frequency is, and the like. At present, the output waveform of the plasma excitation power supply is a sine wave (curve type) rather than a square wave, and the plasma excitation power supply is required to output the square wave for some special occasions such as some plasma application processes.

In view of the above, the present application provides a medium frequency square wave plasma excitation power supply.

Disclosure of Invention

In order to solve or at least partially solve the technical problem, the present application provides a mid-frequency square wave plasma excitation power supply, comprising: the device comprises a voltage adjusting module, a stress absorbing and pre-outputting circuit and an inverting and outputting module; the input end of the voltage adjusting module is electrically connected with an external input signal, and the voltage adjusting module, the stress absorbing and pre-outputting circuit and the inverting and outputting module are sequentially electrically connected;

the input signal is input into the regulating voltage through the voltage regulating module, is inverted into alternating current through the inverting and outputting module and outputs square waves, and the stress absorbing and pre-outputting circuit absorbs the voltage stress of the inverting and outputting module, and the voltage stress provides stable voltage for the next period of output, so that the overall safety performance of the device is improved.

In the scheme, the input signal is input into the adjusting voltage through the voltage adjusting module, is inverted into the alternating current output square wave through the inversion and output module, and meanwhile, the stress absorption and pre-output circuit absorbs the voltage stress at the input end of the inversion and output module, so that the safety performance is improved.

As a further aspect of the present invention, the voltage adjustment module includes at least two or more voltage adjustment circuits connected in parallel.

As a further scheme of the present invention, the inverting and outputting module comprises at least two inverting and outputting circuits connected in parallel.

As a further aspect of the present invention, the voltage adjustment circuit includes: the circuit comprises a diode D1, a rectifier tube Q1-sr, an inductor L1-a and an MOS tube Q1;

the negative electrode of the diode D1 is electrically connected with one end of a capacitor C1, the positive electrode of the diode D1 is electrically connected with one end of the inductor L1-a and the drain electrode of the MOS tube Q1, the other end of the inductor L1-a is electrically connected with the stress absorption and pre-output circuit and the inversion and output module, the source electrode of the MOS tube Q1 is electrically connected with the stress absorption and pre-output circuit, and the gate electrode of the MOS tube Q1 is connected with an external signal;

the source electrode of the rectifying tube Q1-sr is electrically connected with the anode of the diode D1, the drain electrode of the rectifying tube Q1-sr is electrically connected with the cathode of the diode D1, and the grid electrode of the rectifying tube Q1-sr is connected with an external signal.

As a further aspect of the present invention, the inverting and outputting circuit includes: MOS transistor Q5, MOS transistor Q6, MOS transistor Q7, MOS transistor Q8, inductor L2 and resistor R1;

the drain of the MOS transistor Q5 is electrically connected to the cathode of the diode D1 and the drain of the MOS transistor Q6, the source of the MOS transistor Q5 is electrically connected to the drain of the MOS transistor Q7 and one end of the resistor R1, and the source of the MOS transistor Q6 is electrically connected to one end of the inductor L2 and the drain of the MOS transistor Q8;

the sources of the MOS transistor Q7 and the MOS transistor Q8 are both electrically connected with the cathode of a diode D5 in the stress absorption and pre-output circuit;

the other end of the inductor L2 is electrically connected with the other end of the resistor R1;

the gates of the MOS transistor Q5, the MOS transistor Q6, the MOS transistor Q7 and the MOS transistor Q8 are all externally contacted with signals.

As a further scheme of the invention: and the gas plasma generating device also comprises a capacitor C2 or the gas to be excited into plasma, which is connected with the resistor R1 in parallel.

The stress absorbing and pre-outputting circuit as a further aspect of the present invention comprises: the diode D5, the diode D6, the capacitor C3, the resistor R4 and the resistor R5;

the anode of the diode D6 is electrically connected to the other end of the capacitor C1 and the source of the MOS transistor Q1, the cathode of the diode D6 is electrically connected to one end of the capacitor C3 and the anode of the diode D5, and the cathode of the diode D5 is electrically connected to one end of the inductor L1-a;

the cathode of the diode D5 is electrically connected to the inductor L1-a and the inverting and output module 3, and the other end of the capacitor C3 is electrically connected to the cathode of the diode D1 and the inverting and output module 3;

the resistor R5 is connected in parallel with the capacitor C3, and the resistor R4 is connected in parallel with the diode D5.

As a further aspect of the present invention, the voltage adjustment module includes a voltage adjustment circuit.

As a further aspect of the present invention, the inverting and outputting module includes an inverting and outputting circuit.

As a further scheme of the invention: the MOS tube Q1, the MOS tube Q5, the MOS tube Q6, the MOS tube Q7 and the MOS tube Q8 are all N-type SIC MOSFETs or IGBTs.

Has the advantages that:

1. in the application, input signals are input into regulated voltage through the voltage regulation module, the input signals are inverted into alternating current output square waves through the inversion and output module, in the process, when the output is 0 or the output voltage jumps, the inversion and output module is turned off and outputs, the stress absorption and pre-output circuit can absorb peak voltage brought by the turn-off of the inversion and output module, meanwhile, voltage stress output by the inversion and output module provides stable voltage for the next period of output, and preparation is opened for the subsequent inversion and output module.

2. The energy storage inductor is isolated from the output through the inverter bridge circuit, meanwhile, the energy stored in the inductor is provided to the input release loop (namely the signal input Vin end), various stress problems caused by the energy stored in the inductor when the output is 0V or the voltage jumps are solved, and the high-power (inductor working continuous mode) square wave output is realized.

3. In the application, a capacitor C1, a capacitor C2, an inductor L1-a, a MOS tube Q1 and a diode D1; the capacitor C1, the capacitor C2, the inductor L1-b, the MOS tube Q2 and the diode D2 jointly form a staggered BUCK; the MOS tube Q5, the MOS tube Q6, the MOS tube Q7 and the MOS tube Q8 form an inverter and output circuit; the voltage regulation and inversion are realized through Buck, the alternating current output is realized, the inverter bridge can be turned off when the output is 0V or the voltage jumps, the inductance energy can be used for charging a capacitor C3 through a diode D1 (or a diode D2) and a diode D5, or the energy is fed back to a signal input Vin end through a diode D1 (or a diode D2), a diode D6 and a diode D5, or the capacitor C1 is used as the input, and the capacitor C3 is used as the output to form the BUCK, so that various square wave outputs can be realized.

Drawings

In order to more clearly describe the embodiments of the present application, a brief description will be given below of the relevant drawings. It is to be understood that the drawings in the following description are only intended to illustrate some embodiments of the present application, and that a person skilled in the art may also derive from these drawings many other technical features and connections etc. not mentioned herein.

Fig. 1 is a schematic structural diagram of an intermediate-frequency square-wave plasma excitation power supply provided in the present application.

Fig. 2 is a schematic circuit diagram of an if square wave plasma excitation power supply according to the present application.

Fig. 3 is a steady-state timing diagram of an if square wave plasma excitation power supply according to the present application.

Fig. 4 is a schematic diagram of a first square wave output from the mid-frequency square wave plasma excitation power supply provided in the present application.

Fig. 5 is a second square wave schematic diagram of the output of the mid-frequency square wave plasma excitation power supply provided by the present application.

FIG. 6 is a third square wave schematic diagram of the output of the IF square wave plasma excitation power supply provided by the present application.

Fig. 7 is a fourth square wave schematic diagram of the output of the mid-frequency square wave plasma excitation power supply provided by the present application.

Description of reference numerals:

1. a voltage adjustment module; 11. a voltage regulation circuit; 2. a stress absorbing and pre-outputting circuit; 3. an inversion and output module; 31. an inverter and an output circuit.

Detailed Description

The present application will be described in detail below with reference to the accompanying drawings.

Implementation mode one

The applicant finds that in the technical field of plasma excitation power supplies, domestic plasma excitation power supplies have more sine waves and do not output square waves in a better mode. For some special cases, for example: the application process of the plasma has one of the requirements on a plasma excitation power supply, and the pulse needs to be square wave so as to meet the production process.

Therefore, a first embodiment of the present application provides a medium-frequency square-wave plasma excitation power supply, and referring to fig. 1, fig. 1 is a schematic structural diagram of a medium-frequency square-wave plasma excitation power supply provided by the present application, and mainly includes:

the device comprises a voltage adjusting module 1, a stress absorbing and pre-outputting circuit 2 and an inverting and outputting module 3; the input end of the voltage adjusting module 1 is electrically connected with an external input signal, and the voltage adjusting module 1, the stress absorbing and pre-outputting circuit 2 and the inversion and output module 3 are sequentially electrically connected.

The input signal is input into the adjusting voltage through the voltage adjusting module 1, and is inverted into alternating current to output square waves through the inverting and outputting module 3, in the process, when the output is 0 or the output voltage jumps, the inverting and outputting module 3 is turned off to output, the stress absorbing and pre-outputting circuit 2 can absorb the peak voltage caused by the turn-off of the inverting and outputting module 3, and meanwhile, the pre-output voltage is stabilized (namely, the inverter input voltage of the next period is stabilized) to prepare for the subsequent inverting and outputting module 3 to be turned on.

The inverter is an inverter current part in the absorption inversion and output module 3.

It can be understood that in the present embodiment, the signal is input through the capacitor C1, mainly to realize the power input.

Specifically, referring to fig. 2, fig. 2 is a schematic circuit diagram of another if square wave plasma excitation power supply provided by the present application. The voltage adjustment module 1 includes at least one voltage adjustment circuit 11. The voltage regulation circuit 11 comprises a diode D1, a rectifying tube Q1-sr, an inductor L1-a and a MOS tube Q1.

The negative electrode of the diode D1 is electrically connected to one end of a capacitor C1, the positive electrode of the diode D1 is electrically connected to one end of the inductor L1-a and the drain of the MOS transistor Q1, the other end of the inductor L1-a is electrically connected to the stress absorption and pre-output circuit 2 and the inverter and output module 3, the source of the MOS transistor Q1 is electrically connected to the stress absorption and pre-output circuit 2, and the gate of the MOS transistor Q1 is connected to an external signal;

the rectifier tube Q1-sr is connected in parallel with the diode D1, specifically, the source of the rectifier tube Q1-sr is electrically connected with the anode of the diode D1, the drain of the rectifier tube Q1-sr is electrically connected with the cathode of the diode D1, and the gate of the rectifier tube Q1-sr is connected with an external signal.

In the present embodiment, the number of the voltage adjustment circuits 11 may be one or more.

Referring to fig. 2, the number of the voltage adjusting circuits 11 is preferably four, and four voltage adjusting circuits 11 are connected in parallel in sequence.

In order to facilitate understanding that the plurality of voltage adjusting circuits 11 are connected in parallel, two examples are taken as an example in the present application, and the voltage adjusting module 1 further includes a diode D2, a rectifying tube Q2-sr, an inductor L1-b, and a MOS tube Q2.

The negative electrode of the diode D2 is electrically connected to one end of a capacitor C1, the positive electrode of the diode D2 is electrically connected to one end of the inductor L1-b and the drain of the MOS transistor Q2, the other end of the inductor L1-b is electrically connected to the stress absorption and pre-output circuit 2 and the inversion and output module 3, the source of the MOS transistor Q2 is electrically connected to the source of the MOS transistor Q1, and the gate of the MOS transistor Q2 is connected to an external signal;

the source electrode of the rectifying tube Q2-sr is electrically connected with the anode of the diode D1, the drain electrode of the rectifying tube Q2-sr is electrically connected with the cathode of the diode D1, and the grid electrode of the rectifying tube Q2-sr is connected with an external signal.

In the above scheme, the source of the MOS transistor Q1 and the source of the MOS transistor Q2 are connected, and the cathodes of the diode D1 and the diode D2 are both connected to the capacitor C1, so that the parallel connection of the two voltage adjusting circuits is realized.

Furthermore, the applicant has found; when the inverting and output module 3 is turned off, the following two problems occur:

1. a voltage spike;

2. the voltage in front of the inverter is unstable.

Above-mentioned two problems all can lead to the stress of MOS pipe to exceed standard, must lead to the whole device to damage for a long time, influences the square wave voltage stability of later stage cycle output simultaneously. Therefore, the stress absorbing and pre-outputting circuit 2 is introduced by the applicant through design, the voltage stress at the input end of the inverting and outputting module 3 can be absorbed, the voltage stress output by the inverting and outputting module 3 provides stable voltage for the next output period, and the stable square wave voltage of the later period can be realized, so that the power performance is improved, the whole circuit is protected, the service life is prolonged, and the like.

In particular, referring to fig. 2, in the present application, the stress absorbing and pre-outputting circuit 2 includes: diode D5, diode D6, electric capacity C3, resistance R4, resistance R5.

The anode of the diode D6 is electrically connected to the other end of the capacitor C1 and the source of the MOS transistor Q1, the cathode of the diode D6 is electrically connected to one end of the capacitor C3 and the anode of the diode D5, and the cathode of the diode D5 is electrically connected to one end of the inductor L1-a.

The cathode of the diode D5 is electrically connected to the inductor L1-a and the inverter and output module 3, and the other end of the capacitor C3 is electrically connected to the cathode of the diode D1 and the inverter and output module 3.

The resistor R5 is connected in parallel with the capacitor C3, and the resistor R4 is connected in parallel with the diode D5.

In the above scheme, the voltage stress at the input end of the inverter and output circuit 31 can be absorbed by the capacitor C3, and before the diode D5 is turned off, the voltage stress is absorbed by the resistors R4 and the capacitor C3, so that the overall safety performance is improved.

The voltage adjusting module adjusts voltage through an inductor, and forms an output voltage adjusting circuit with the capacitor C1 and the capacitor C3.

The inverting and outputting module 3 includes at least one inverting and outputting circuit 31. When the number of the inverter and output circuits 31 is two or more, a plurality of inverter and output circuits 31 are connected in parallel with each other.

The inverter and output circuit 31 includes a MOS transistor Q5, a MOS transistor Q6, a MOS transistor Q7, a MOS transistor Q8, an inductor L2, a resistor R1, and a capacitor C2.

Wherein the drain of the MOS transistor Q5 is electrically connected with the cathode of the diode D1 and the drain of the MOS transistor Q6, the source of the MOS transistor Q5 is electrically connected with the drain of the MOS transistor Q7 and one end of the resistor R1, the source of the MOS transistor Q6 is electrically connected with the inductor L1-b and the drain of the MOS transistor Q8,

the sources of the MOS transistor Q7 and the MOS transistor Q8 are both electrically connected with the cathode of the diode D5,

the other end of the inductor L2 is electrically connected with the other end of the resistor R1, and the resistor R1 is connected in parallel with the capacitor C2.

The gates of the MOS transistor Q5, the MOS transistor Q6, the MOS transistor Q7 and the MOS transistor Q8 are all externally connected with a trigger signal.

Meanwhile, in order to illustrate the parallel connection manner of the inverting and output circuit 31, the present application still uses two inverting and output circuits 31 for illustration:

when the number of the inverting and outputting circuits 31 is two, the inverting and outputting module further includes:

MOS transistor Q9, MOS transistor Q10, MOS transistor Q11, MOS transistor Q12, inductor L3, resistor R2 and capacitor C4

The drain of the MOS transistor Q9 is electrically connected to the cathode of the diode D1 and the drain of the MOS transistor Q10, the source of the MOS transistor Q9 is electrically connected to the drain of the MOS transistor Q11 and one end of the resistor R2, and the source of the MOS transistor Q10 is electrically connected to the inductor L1-b and the drain of the MOS transistor Q12;

the sources of the MOS transistor Q11 and the MOS transistor Q12 are both electrically connected with the cathode of the diode D5;

the other end of the inductor L3 is electrically connected with the other end of the resistor R2, and the resistor R2 is connected in parallel with the capacitor C4.

The gates of the MOS transistor Q9, the MOS transistor Q10, the MOS transistor Q11 and the MOS transistor Q12 are all externally connected with a trigger signal.

It can be seen that, in the above scheme, the drains of the MOS transistors Q9 and Q10 are connected to the drains of the MOS transistors Q5 and Q6, and the sources of the MOS transistors Q7 and Q8 are connected to the sources of the MOS transistors Q11 and Q12, so that multiple inverters are connected in parallel to the output circuit 31.

It is furthermore emphasized that the capacitors C2, C4 may also be other loads, such as resistors R1 or gases to be excited into a plasma.

Of course, in the solution of the present application, only the resistor R1 may be implemented as a load.

Meanwhile, in order to reduce the cost, in the application, the MOS transistor Q1, the MOS transistor Q5, the MOS transistor Q6, the MOS transistor Q7 and the MOS transistor Q8 are all N-type SIC MOSFETs or IGBTs, and the VDss is 1200V.

It can be understood that, the preceding stage of the present application is a multi-phase voltage adjusting circuit Ai, (i is an integer greater than or equal to 1), and the following stage is composed of a plurality of inverter bridges and a plurality of output circuits (i.e., an inverter and output module 3), each inverter bridge and the corresponding output circuit are represented by Bi (i is an integer greater than or equal to 1), and i outputs may be multiplexed (the number of output paths K, 2 ═ K ═ n) or may be combined together to be a single output, i.e., K ═ 1.

The application range is as follows:

inputting: DC600V- - -DC 1200V;

the output power is 10 KW-150 KW;

outputting square wave voltage (600-1000V) and frequency (5-150 KHZ).

Description of the working principle:

in the application, a capacitor C1, a capacitor C2, an inductor L1-a, a MOS tube Q1 and a diode D1; the capacitor C1, the capacitor C2, the inductor L1-b, the MOS tube Q2 and the diode D2 jointly form a staggered BUCK; the MOS tube Q5, the MOS tube Q6, the MOS tube Q7 and the MOS tube Q8 form an inverter and output circuit; the voltage regulation and inversion are realized through Buck, the alternating current output is realized, the inverter bridge can be turned off when the output is 0V or the voltage jumps, the inductance energy can be used for charging a capacitor C3 through a diode D1 (or a diode D2) and a diode D5, or the energy is fed back to a signal input Vin end through a diode D1 (or a diode D2), a diode D6 and a diode D5, or the capacitor C1 is used as the input, and the capacitor C3 is used as the output to form the BUCK, so that various square wave outputs can be realized.

The energy storage inductor is isolated from the output through the inverter bridge circuit 31, when the inverter bridge is turned off, the problems of voltage spikes at the input end of the inverter bridge and voltage instability at the input end of the inverter bridge when the output is 0 or the output voltage jumps are solved through the absorption and pre-output circuit, so that high-power square wave output is realized, and the capacitor C3 and the resistor R5 are used as pre-stage output or load on the premise of isolating the rear stage (namely the inverter and output module 3).

When the inverter bridge is turned off, the problems of voltage spike at the input end of the inverter bridge and unstable voltage at the input end of the inverter bridge when the output is 0 or the output voltage jumps are solved through the absorption and pre-output circuit, so that high-power square wave output is realized.

For convenience of understanding of the present invention, in the present application, the inverting and outputting module 3 includes two inverting and outputting circuits 31, the voltage adjusting module 1 includes two voltage adjusting circuits 11, as an example, fig. 3 is a steady-state timing diagram of an intermediate frequency square wave plasma excitation power supply provided by the present application, fig. 4 is a square wave schematic diagram of an intermediate frequency square wave plasma excitation power supply provided by the present application, fig. 5 is a second square wave schematic diagram of an intermediate frequency square wave plasma excitation power supply provided by the present application, fig. 6 is a third square wave schematic diagram of an intermediate frequency square wave plasma excitation power supply provided by the present application, and fig. 7 is a fourth square wave schematic diagram of an intermediate frequency square wave plasma excitation power supply provided by the present application. The following description is made with reference to fig. 3, 4 to 7:

in the charging stage of the inductor L1-a within the time t0-t1, I1 in the figure flows to a capacitor C1, a MOS tube Q6, an inductor L2, a capacitor C2 (or a load), a MOS tube Q7, an inductor L1-a, a MOS tube Q1 and a capacitor C1; meanwhile, L1-b discharges, and the flow direction of I2 is L1-b, diode D2, MOS transistor Q6, inductor L2, capacitor C2 (or load), inductor Q7 and inductor L1-b;

in the discharging stage of the inductor L1-a within the time t1-t2, I1 flows to the inductor L1-a, the diode D1, the MOS tube Q6, the inductor L2, the capacitor C2 (or a load), the MOS tube Q7 and the inductor L1-a; meanwhile, the inductor L1-b discharges, and the flow of the I2 flows to the inductor L1-b, the diode D2, the MOS tube Q6, the inductor L2, the capacitor C2 (or load), the MOS tube Q7 and the inductor L1-b;

in the charging stage of an inductor L1-b within the time t2-t3, I2 flows to a capacitor C1, a MOS tube Q6, an inductor L2, a capacitor C2 (or a load), a MOS tube Q7, an inductor L1-b, a MOS tube Q2 and a capacitor C1; meanwhile, the inductor L1-a discharges, and the flow of the I1 flows to the inductor L1-a, the diode D1, the MOS tube Q6, the inductor L2, the capacitor C2 (or load), the MOS tube Q7 and the capacitor L1-a;

in the discharging stage of the capacitor L1-a within the time t3-t4, I1 flows to the capacitor L1-a, the diode D1, the MOS tube Q6, the inductor L2, the capacitor C2 (or a load), the MOS tube Q7 and the capacitor L1-a; meanwhile, the capacitor L1-b discharges, and the flow of the I2 flows to an inductor L1-b, a diode D2, a MOS transistor Q6, an inductor L2, a capacitor C2 (or load), a MOS transistor Q7 and an inductor L1-b;

in the charging stage of an inductor L1-a within the time t4-t5, I1 flows to a capacitor C1, a MOS tube Q5, a capacitor C2 (or load), an inductor L2, a MOS tube Q8, an inductor L1-a, a MOS tube Q1 and a capacitor C inductor L; meanwhile, the inductor L1-b discharges, and the flow of I flows to the inductor L1-b, the diode D2, the MOS tube Q5, the capacitor C2 (or load), the inductor L2, the MOS tube Q8 and the inductor L1-b;

in the discharging stage of the inductor L1-b within the time t5-t6, I2 flows to the inductor L1-b, the diode D2, the MOS tube Q5, the capacitor C2 (or a load), the inductor L2, the MOS tube Q8 and the inductor L1-b; meanwhile, the inductor L1-a discharges, and the flow of the I1 flows to the inductor L1-a, the diode D1, the MOS tube Q5, the capacitor C2 (or a load), the inductor L2, the MOS tube Q8 and the inductor L1-a;

in the charging stage of the inductor L1-b within the time t6-t7, I2 flows to a capacitor C1, a MOS tube Q5, a capacitor C2 (or load), an inductor L2, a MOS tube Q8, an inductor L1-b, a MOS tube Q2 and a capacitor C1; meanwhile, the inductor L1-a discharges, and the flow of the I1 flows to the inductor L1-a, the diode D1, the MOS tube Q5, the capacitor C2 (or a load), the inductor L2, the MOS tube Q8 and the inductor L1-a;

in the discharging stage of the inductor L1-b within the time t7-8, I2 flows to an inductor L1-b, a diode D2, a MOS tube Q5, a capacitor C2 (or a load), an inductor L2, a MOS tube Q8 and an inductor L1-b; and meanwhile, the inductor L1-a discharges, and the I1 flows to the inductor L1-a, the diode D1, the MOS tube Q5, the capacitor C2 (or load), the inductor L2, the MOS tube Q8 and the inductor L1-a.

From the above, according to the relation of input and output, the duty ratio D' 0.5 of the scheme, the wave generation of the front stage and the rear stage are mutually independent, and the output end of the application always outputs square waves and can output various types of square waves.

Finally, it should be noted that those skilled in the art will appreciate that embodiments of the present application present many technical details for the purpose of enabling the reader to better understand the present application. However, the technical solutions claimed in the claims of the present application can be basically implemented without these technical details and various changes and modifications based on the above-described embodiments. Accordingly, in actual practice, various changes in form and detail may be made to the above-described embodiments without departing from the spirit and scope of the present application.