阅读说明：本技术 基于区复位行为的数据存储设备的区分配 (Zone allocation for data storage devices based on zone reset behavior ) 是由 P.鲁斯维格 Y.阿塔克尔蒂 于 2021-04-07 设计创作，主要内容包括：本发明题为“基于区复位行为的数据存储设备的区分配”。在一个具体实施中,存储器控制器包括主机接口、存储器接口和闪存转换层(FTL)。FTL被配置为从主机设备接收将数据存储在固态存储器的区中的请求。FTL还被配置为将区复位率分类确定为热分类、冷分类和正常分类中的一者。FTL还被配置为当区复位率分类是热分类时,将区分配给具有最少自由管芯块的存储器管芯。FTL还被配置为当区复位率分类是冷分类时将区分配给具有最多自由管芯块的存储器管芯。FTL被进一步配置为将数据发送到存储器管芯以存储在其中。(The invention provides zone allocation of a data storage device based on zone reset behavior. In one implementation, a memory controller includes a host interface, a memory interface, and a Flash Translation Layer (FTL). The FTL is configured to receive a request from a host device to store data in a region of solid state memory. The FTL is further configured to determine a zone reset rate classification as one of a hot classification, a cold classification, and a normal classification. The FTL is further configured to assign a region to a memory die having a least number of free die blocks when the region reset rate classification is a thermal classification. The FTL is further configured to assign a region to the memory die having the most free die blocks when the region reset rate classification is a cold classification. The FTL is further configured to transmit data to the memory die for storage therein.)

1. A memory controller, comprising:

a host interface configured to connect with the host device;

a memory interface configured to connect with a solid state memory; and

a flash translation layer coupled to the host interface and the memory interface, wherein the flash translation layer is configured to:

receiving a request from the host device through the host interface to store data in a region of the memory,

determining a zone reset rate classification for the zone as one of a hot classification, a cold classification, and a normal classification,

assigning the zones to die in the memory based on the zone reset rate classification, wherein the zones are assigned to the die having the least free die blocks when the zone reset rate classification is the thermal classification, and wherein the zones are assigned to the die having the most free die blocks when the zone reset rate classification is the cold classification, an

Sending the data to the die in the memory through the memory interface for storage in the memory.

2. The memory controller of claim 1, wherein to determine the zone reset rate classification, the flash translation layer is further configured to:

incrementing the zone reset counter each time the zone is reset,

classifying the region with the hot classification when the region reset counter is greater than a hot threshold,

classifying the zone with the cold classification when the zone reset counter is less than a cold threshold, an

Classifying the region with the normal classification when the region reset counter is between the hot threshold and the cold threshold.

3. The memory controller of claim 2, wherein the flash translation layer is further configured to determine the hot threshold and the cold threshold based on a total number of region resets for the memory.

4. The memory controller of claim 1, wherein to determine the zone reset rate classification, the flash translation layer is further configured to:

incrementing the zone reset counter each time the zone is reset,

scaling the region reset counter based on a total number of region resets of the memory to generate a scaled region reset counter,

classifying the region with the hot classification when the scaled region reset counter is greater than a hot threshold,

classifying the region with the cold classification when the scaled region reset counter is less than a cold threshold, an

Classifying the region with the normal classification when the scaled region reset counter is between the hot threshold and the cold threshold.

5. The memory controller of claim 1, wherein to determine the zone reset rate classification, the flash translation layer is further configured to determine the zone reset rate classification based on an indication received from the host device.

6. The memory controller of claim 5, wherein the flash translation layer receives the indication from the host device when the zone is opened.

7. The memory controller of claim 6, wherein when the zone reset rate is classified as the normal classification, the zone is assigned to any die in the memory having a spare die block.

8. A method, comprising:

receiving, from a host device, a request to store data in a region of solid state memory;

determining, with a flash translation layer, a zone reset rate classification of the zone as one of a hot classification, a cold classification, and a normal classification;

assigning, with the flash translation layer, the zone to a die in the memory based on the zone reset rate classification, wherein when the zone reset rate classification is the thermal classification, the zone is assigned to the die having the fewest free die blocks, and wherein when the zone reset rate classification is the cold classification, the zone is assigned to the die having the most free die blocks; and

sending the data to the die in the memory for storage therein.

9. The method of claim 8, wherein determining the zone reset rate classification further comprises:

incrementing a zone reset counter each time the zone is reset,

classifying the region with the hot classification when the region reset counter is greater than a hot threshold,

classifying the zone with the cold classification when the zone reset counter is less than a cold threshold, an

Classifying the region with the normal classification when the region reset counter is between the hot threshold and the cold threshold.

10. The method of claim 9, further comprising determining, with the flash translation layer, the hot threshold and the cold threshold based on a total number of region resets of the memory.

11. The method of claim 8, wherein determining the zone reset rate classification further comprises:

incrementing a zone reset counter each time the zone is reset,

scaling the region reset counter based on a total number of region resets of the memory to generate a scaled region reset counter,

classifying the region with the hot classification when the scaled region reset counter is greater than a hot threshold,

classifying the region with the cold classification when the scaled region reset counter is less than a cold threshold, an

Classifying the region with the normal classification when the scaled region reset counter is between the hot threshold and the cold threshold.

12. The method of claim 8, wherein determining the zone reset rate classification further comprises determining the zone reset rate classification based on an indication received from the host device.

13. The method of claim 12, wherein the indication is received from the host device when the zone is opened.

14. The method of claim 8, wherein when the zone reset rate is classified as the normal classification, assigning the zone to any die in the memory with a spare die block.

15. An apparatus, comprising:

means for receiving a request from a host device to store data in a region of solid state memory;

means for determining a zone reset rate classification for the zone as one of a hot classification, a cold classification, and a normal classification;

means for assigning the zone to the die in the memory based on the zone reset rate classification, wherein the zone is assigned to the die having the least free die blocks when the zone reset rate classification is the thermal classification, and wherein the zone is assigned to the die having the most free die blocks when the zone reset rate classification is the cold classification; and

means for sending the data to the die in the memory for storage therein.

16. The apparatus of claim 15, wherein the means for determining the zone reset rate classification is further configured to:

incrementing the zone reset counter each time the zone is reset,

classifying the region with the hot classification when the region reset counter is greater than a hot threshold,

classifying the zone with the cold classification when the zone reset counter is less than a cold threshold, an

Classifying the region with the normal classification when the region reset counter is between the hot threshold and the cold threshold.

17. The apparatus of claim 16, further comprising means for determining the hot threshold and the cold threshold based on a total number of region resets for the memory.

18. The apparatus of claim 15, wherein the means for determining the zone reset rate classification is further configured to:

incrementing the zone reset counter each time the zone is reset,

scaling the region reset counter based on a total number of region resets of the memory to generate a scaled region reset counter,

classifying the region with the hot classification when the scaled region reset counter is greater than a hot threshold,

classifying the region with the cold classification when the scaled region reset counter is less than a cold threshold, an

Classifying the region with the normal classification when the scaled region reset counter is between the hot threshold and the cold threshold.

19. The apparatus of claim 15, wherein the means for determining the zone reset rate classification is further configured to determine the zone reset rate classification based on an indication received from the host device.

20. The apparatus of claim 15, wherein the means for assigning the zone is further configured to assign the zone to any die in the memory having a spare die block when the zone reset rate is classified as the normal classification.

Background

The present application relates generally to memory devices and, more particularly, to a controller that allocates regions in a memory based on a region reset rate.

Many solid state drives use NAND flash memory for storage. In NAND flash memories, there is a mismatch between the program (string) size and the erase (block) size. This requires a flash translation layer between the host and the NAND flash to manage the problems caused by the mismatch between program and erase (e.g., write amplification, wear leveling, compression, etc.). A partition namespace ("ZNS") solid state drive is designed to be optimized for NAND flash. In some ZNS systems, the zone capacity matches the capacity of a NAND tube block (die block). This capacity matching simplifies most operations of the flash translation layer, since data is written to each region sequentially. For example, capacity matching allows a host to utilize almost all of the pipe block blocks on a solid state drive by eliminating the need for virtual blocks. While this results in a lower cost host (e.g., drive cost), it also presents new challenges for the flash translation layer. For example, each physical die does not have the same number of bad blocks. Thus, in ZNS, each die has a different capacity. Each die may reach physical fill at different times, assuming that each die has the same data write rate and the same data invalidation (i.e., zone reset) rate. If a die reaches capacity, it will go offline and reduce system performance due to reduced parallelism. Therefore, there is a need for a method for allocating zones to prevent die from reaching capacity in a ZNS system.

Disclosure of Invention

Each zone in a partitioned namespace ("ZNS") system will not be invalidated at the same rate. Some zones (referred to herein as "cold zones") will only be reset a few times, and therefore will consume tube pellet blocks for a long period of time. Some zones (referred to herein as "hot zones") will be reset multiple times and will therefore be released from the die pieces after a short time. The present disclosure provides apparatus, methods, and devices that assign cold zones to die with the highest number of free die pieces and hot zones to die with the fewest number of free die pieces. In this way, the die is prevented from reaching full capacity because die capacity is maintained based on host behavior.

The present disclosure provides a memory controller that, in one implementation, includes a host interface, a memory interface, and a flash translation layer. The host interface is configured to connect with a host device. The memory interface is configured to interface with a solid state memory. The flash translation layer is coupled to the host interface and the memory interface. The flash translation layer is configured to receive a request from a host device through a host interface to store data in a region of memory. The flash translation layer is further configured to determine a zone reset rate classification of the zone as one of a hot classification, a cold classification, and a normal classification. The flash translation layer is also configured to assign a region to a die in the memory based on the region reset rate classification. When the zone reset rate is classified as thermal, the zone is assigned to the die with the least free die block. When the zone reset rate is classified as a cold classification, the zone is assigned to the die having the most free die blocks. The flash translation layer is also configured to send data to a die in the memory through the memory interface for storage in the memory.

The present disclosure also provides a method that includes receiving a request from a host device to store data in a region of solid state memory. The method also includes determining, with the flash translation layer, a zone reset rate classification for the zone as one of a hot classification, a cold classification, and a normal classification. The method further includes assigning the zones to the dies in the memory based on the zone reset rate classifications with the flash translation layer. When the zone reset rate is classified as thermal, the zone is assigned to the die with the least free die block. When the zone reset rate is classified as a cold classification, the zone is assigned to the die having the most free die blocks. The method also includes sending the data to a die in the memory for storage therein.

The present disclosure also provides an apparatus, which in one implementation, includes: means for receiving a request from a host device to store data in a region of solid state memory; means for determining a zone reset rate classification for the zone as one of a hot classification, a cold classification, and a normal classification; means for assigning regions to dies in memory based on region reset rate classification; and means for sending the data to the die in the memory for storage therein. When the zone reset rate is classified as thermal, the zone is assigned to the die with the least free die block. When the zone reset rate is classified as a cold classification, the zone is assigned to the die having the most free die blocks.

Various aspects of the present disclosure provide for improvements to memory devices. The present disclosure may be embodied in various forms including hardware or circuitry controlled by software and/or firmware. The above summary is intended only to give a general idea of various aspects of the present disclosure, and does not limit the scope of the present disclosure in any way.

Drawings

Fig. 1 is a block diagram of one example of a system including a data storage device in accordance with some implementations of the present disclosure.

Fig. 2 is an illustration of one example of a plurality of NAND dies having different zone storage capacities in accordance with some implementations of the present disclosure.

Fig. 3 is a flow chart of an example of a method for allocating zones of a flash memory based on a zone reset rate in accordance with some implementations of the present disclosure.

Fig. 4 is a flow chart of an example of a method for determining zone reset rate classifications based on a zone reset counter in accordance with some implementations of the present disclosure.

Fig. 5 is a flow diagram of an example of a method for determining a zone reset rate classification based on a zoom zone reset counter in accordance with some implementations of the present disclosure.

Detailed Description

In the following description, numerous details are set forth, such as data storage device configurations, controller operations, etc., in order to provide an understanding of one or more aspects of the present disclosure. It will be apparent to those skilled in the art that these specific details are merely exemplary and are not intended to limit the scope of the present application. In particular, the functions associated with the flash translation layer may be performed by hardware (e.g., analog or digital circuitry), a combination of hardware and software (e.g., program code or firmware stored in a non-transitory computer readable medium for execution by a processor or control circuitry), or any other suitable means. The following description is only intended to give a general idea of various aspects of the present disclosure, and does not limit the scope of the present disclosure in any way. Furthermore, it will be apparent to those skilled in the art that although the present disclosure relates to NAND flash memory, the concepts discussed herein are applicable to other types of solid state memory, such as NOR, PCM (phase change memory), ReRAM, and the like.

FIG. 1 is a block diagram of one example of a system 100 including a data storage device 102. In some implementations, the data storage device 102 is a flash memory device. For example, the data storage device 102 is Secure DigitalA card,A card or another similar type of data storage device. The data storage device 102 shown in fig. 1 includes a flash memory 104 and a controller 106. Data storage device 102 is coupled to host device 108. The host device 108 is configured to provide data 110 (e.g., user data) to the data storage device 102 for storage in, for example, the flash memory 104. The host device 108 is also configured to request data 110 to be read from the flash memory 104. Host device 108 is, for example, a computer, a server, an access terminal, or another similar device.

The flash memory 104 of the data storage device 102 is coupled to the controller 106. In some implementations, the flash memory 104 is a NAND flash memory. The flash memory 104 shown in FIG. 1 includes a plurality of dies 112A-112N (e.g., NAND dies). Each of the plurality of dies 112A-112N includes a plurality of die blocks. For example, in fig. 1, die 112A includes representative die tile 114.

The controller 106 shown in FIG. 1 includes a host interface 116, a memory interface 118, and a flash translation layer 120. The controller 106 is shown in simplified form in fig. 1. Those skilled in the art will recognize that a controller for a flash memory will include additional modules or components than those specifically illustrated in fig. 1. Additionally, although data storage device 102 is shown in fig. 1 as including controller 106, in other implementations, controller 106 is instead located within host device 108 or is otherwise separate from data storage device 102. Thus, operations that would normally be performed by the controller 106 (e.g., wear leveling, bad block management, data scrambling, garbage collection, address mapping, etc.) may be performed by the host device 108 or another device connected to the data storage device 102.

The controller 106 is configured to send data to and receive data and instructions from the host device 108 via the host interface 116. The host interface 116 enables the host device 108 to read from and write to the flash memory 104, for example, using any suitable communication protocol. Suitable communication protocols include, for example, the universal flash storage ("UFS") host controller interface specification, the secure digital ("SD") host controller specification, and the like.

The controller 106 is also configured to send and receive data and commands to and from the flash memory 104 via the memory interface 118. As an illustrative example, the controller 106 is configured to send data and write commands to instruct the flash memory 104 to store data in a particular die block in the die 112A. The controller 106 is also configured to send a read command to the flash memory 104 to read data from a particular die block in the flash memory 104.

The flash translation layer 120 shown in fig. 1 includes a processor 122 (e.g., a microprocessor, a microcontroller, a field programmable gate array [ "FPGA" ] semiconductor, an application specific integrated circuit [ "ASIC" ] or another suitable programmable device) and a non-transitory computer readable medium or memory 124 (e.g., including random access memory [ "RAM" ] and read only memory [ "ROM" ]). Processor 122 is operatively connected to various modules within flash translation layer 120, controller 106, and data storage device 102. For example, the firmware is loaded into ROM of memory 124 as computer executable instructions. These computer-executable instructions can be retrieved from the memory 124 and executed by the processor 122 to control the operation of the flash translation layer 120 and perform the processes described herein. In some implementations, one or more modules of the flash translation layer 120 correspond to separate hardware components within the flash translation layer 120. In other implementations, one or more modules of the flash translation layer 120 correspond to software stored within the memory 124 and executed by the processor 122. The memory 124 is configured to store data used by the flash translation layer 120 during operation.

The flash translation layer 120 is configured to write data to a region of the flash memory 104. The number of pages included in one region matches the size of one die block in flash memory 104. Further, the flash translation layer 120 is configured to write data to the zones in a sequential manner (i.e., from page 0 to page n, where page n is the last page in the zone). Thus, the flash translation layer 120 is configured to fill one die block when writing data to the region. In addition, the flash translation layer 120 is configured to reset the entire die block (i.e., each page in the die block) at the reset region.

A bad slug is a slug that is no longer capable of reliably storing and retrieving data because it has been physically damaged or destroyed. Each of the plurality of dies 112A-112N in the flash memory 104 has substantially the same number of total die pellets. However, each of the plurality of dies 112A-112N in the flash memory 104 does not have the same number of bad die blocks. Thus, each of the plurality of dies 112A-112N in the flash memory 104 does not have the same number of good die blocks. As described above, one zone is filled with one pellet block. Thus, each of the plurality of dies 112A-112N in the flash memory 104 has a different zone storage capacity because each die has a different number of good die blocks. FIG. 2 shows an example of different zone storage capacities for multiple NAND dies 202 and 214. The zone storage capacity of each NAND die included in fig. 2 is represented by its height. For example, the NAND die 202 has a larger area storage capacity than the NAND die 204 because the NAND die 202 is higher than the NAND die 204. The height of each NAND die included in fig. 2 also represents the amount of good die blocks included therein. The shaded portion of each NAND die in fig. 2 represents the amount of valid data stored therein.

Assuming that each NAND die shown in fig. 2 has the same data write rate and the same data invalidation (i.e., zone reset) rate, each NAND die reaches physical fill at a different time. However, each region of the flash memory 104 will not be invalidated (i.e., reset) at the same rate. Some zones (referred to herein as "cold zones") will only be reset a few times, and therefore will consume tube pellet blocks for a long period of time. Some zones (referred to herein as "hot zones") will be reset multiple times and will therefore be released from the die pieces after a short time. The flash translation layer 120 is configured to assign the cold regions to the die with the highest number of free die pieces and assign the hot regions to the die with the least number of free die pieces. In this way, the die is prevented from reaching full capacity because die capacity is maintained based on host behavior.

FIG. 3 is a flow chart of one example of a method 300 for allocating a zone of flash memory 104 based on a zone reset rate. At block 302, a request to store data to a region of flash memory 104 is received from host device 108. For example, the flash translation layer 120 can receive a request from the host device 108 via the host interface 116. At block 304, a zone reset rate classification for the zone is determined as one of a hot classification, a cold classification, and a normal classification. The zone reset rate classification indicates the frequency with which the zone is reset by the host device 108. The hot sort is assigned to the zone that experienced a large number of zone resets. The cold classification is assigned to the zone that experienced a small number of zone resets. Normal classifications are assigned to regions that experience an average number of region resets. Various implementations for determining zone reset rate classifications are described in further detail below.

At block 306, a region is assigned to a die in the flash memory 104 based on the region reset rate classification. When the zone reset rate is classified as thermal, the flash translation layer 120 assigns a zone to the die with the least number of free die blocks. In addition, when the zone reset rate is classified as a cold classification, the flash translation layer 120 assigns a zone to the die having the most free die blocks. As used herein, the term "free pellet" refers to a good pellet that does not currently store valid data. In some implementations, the flash translation layer 120 is configured to assign a zone to any die in the flash memory 104 having a spare die block when the zone reset rate classification is a normal classification.

At block 308, the data is sent to the die in the flash memory 104 for storage therein. For example, the flash translation layer 120 sends data and write commands via the memory interface 118 to instruct the flash memory 104 to store the data in the assigned die.

In some implementations, the flash translation layer 120 is configured to determine a zone reset rate classification for the zone based on the indication received from the host device 108. For example, when host device 108 sends a request to open a zone, the request may include an indication of whether the zone is a hot zone, a cold zone, or a normal zone. Alternatively or additionally, in some implementations, the flash translation layer 120 is configured to determine a zone reset rate classification for a zone based on a total number of times the zone is reset. For example, for each zone in the flash memory 104, the flash translation layer 120 may increment a zone reset counter each time the host device 108 resets the zone, and determine a zone reset rate classification for the zone based on the zone reset counter. A separate zone reset counter may be used for each zone in the flash memory 104.

Fig. 4 is a flow diagram of one example of a method 400 for determining a zone reset rate classification for a zone based on a zone reset counter. At block 402, the flash translation layer 120 determines whether the zone reset counter is greater than a thermal threshold. When the zone reset counter is greater than the thermal threshold, the flash translation layer 120 classifies the zone with a thermal classification at block 404. Alternatively, when the zone reset counter is less than the thermal threshold, the method 400 proceeds to block 406. At block 406, the flash translation layer 120 determines whether the zone reset counter is less than the cold threshold. The cold threshold is less than the hot threshold. When the zone reset counter is less than the cold threshold, the flash translation layer 120 classifies the zone with a cold classification at block 408. Alternatively, when the zone reset counter is greater than the cold threshold, the flash translation layer 120 classifies the zone with a normal classification at block 410.

In some implementations, the flash translation layer 120 is configured to determine the hot threshold and the cold threshold based on a total number of zone resets of the flash memory 104. For example, the flash translation layer 120 may set the cold threshold to 10% of the total number of zone resets and the hot threshold to 90% of the total number of zone resets. The total number of times a zone of flash memory 104 is reset is the total number of times any zone in flash memory 104 is reset. In some implementations, the flash translation layer 120 is configured to determine the total number of zone resets for the flash memory 104 by summing the values of the zone reset counters for all zones in the flash memory 104.

In some implementations, the zone reset counter is scaled based on the total number of zone resets of the flash memory 104. Fig. 5 is a flow diagram of one example of a method 500 for determining a zone reset rate classification for a zone based on a scaled zone reset counter. At block 502, the flash translation layer 120 scales the zone reset counter based on the total number of zone resets of the flash memory 104 to generate a scaled zone reset counter. In some implementations, the flash translation layer 120 is configured to generate a scaled zone reset counter by dividing the zone reset counter by the total number of zone resets of the flash memory 104. At block 504, the flash translation layer 120 determines whether the scaled region reset counter is greater than a thermal threshold. When the scaled region reset counter is greater than the thermal threshold, the flash translation layer 120 classifies the region with thermal classification at block 506. Alternatively, when the scaled region reset counter is less than the thermal threshold, the method 500 proceeds to block 508. At block 508, the flash translation layer 120 determines whether the scaled region reset counter is less than the cold threshold. When the scaled region reset counter is less than the cold threshold, the flash translation layer 120 classifies the region with a cold classification at block 510. Alternatively, when the zone reset counter is greater than the cold threshold, the flash translation layer 120 classifies the zone with a normal classification at block 512.

In connection with the disclosed implementations, an apparatus includes means for receiving a request from a host device to store data in a region of a flash memory. The means for receiving the request may correspond to, for example, the host interface 116, the flash translation layer 120, or a combination of both. The apparatus also includes means for determining a zone reset rate classification for the zone as one of a hot classification, a cold classification, and a normal classification. The means for determining the region rate classification may correspond to, for example, the flash translation layer 120. The apparatus also includes means for assigning the zone to a die in the flash memory based on the zone reset rate classification. The means for allocating a region may correspond to, for example, the flash translation layer 120. The apparatus also includes means for sending data to a die in the flash memory for storage therein. The means for sending data may correspond to, for example, the memory interface 118, the flash translation layer 120, or a combination of both.

In some implementations, the means for determining the zone reset rate classification is configured to increment a zone reset counter each time the zone is reset, classify the zone with a hot classification when the zone reset counter is greater than a hot threshold, classify the zone with a cold classification when the zone reset counter is less than a cold threshold, and classify the zone with a normal classification when the zone reset counter is between the hot threshold and the cold threshold.

In some implementations, the apparatus further includes means for determining the hot threshold and the cold threshold based on a total number of zone resets of the flash memory. The means for determining the hot threshold and the cold threshold may correspond to, for example, the flash translation layer 120.

In some implementations, the means for determining the zone reset rate classification is configured to increment a zone reset counter each time the zone is reset, scale the zone reset counter based on a total number of zone resets of the flash memory to generate a scaled zone reset counter, classify the zone with a hot classification when the scaled zone reset counter is greater than a hot threshold, classify the zone with a cold classification when the scaled zone reset counter is less than a cold threshold, and classify the zone with a normal classification when the scaled zone reset counter is between the hot threshold and the cold threshold.

In some implementations, the means for determining a zone reset rate classification is configured to determine the zone reset rate classification based on an indication received from a host device. In some implementations, the means for assigning a zone is configured to assign the zone to any die in the flash memory having a spare die block when the zone reset rate is classified as a normal classification.

With respect to the processes, systems, methods, heuristics, etc. described herein, it should be understood that, although the steps of such processes, etc. have been described as occurring according to a certain ordered sequence, such processes could be practiced with the described steps performed in an order other than the order described herein. It is also understood that certain steps may be performed simultaneously, that other steps may be added, or that certain steps described herein may be omitted. In other words, the description of processes herein is provided for the purpose of illustrating certain implementations, and should not be construed as limiting the claims in any way.

Accordingly, it is to be understood that the above description is intended to be illustrative, and not restrictive. Many embodiments and applications other than the examples provided will be apparent upon reading the above description. Scope should be determined, not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. It is anticipated and intended that future developments will occur in the arts discussed herein, and that the disclosed systems and methods will be incorporated into such future embodiments. In sum, it should be understood that the present application is capable of modification and variation.

All terms used in the claims are intended to be given their broadest reasonable constructions and their ordinary meanings as understood by those skilled in the art to which they pertain unless an explicit indication to the contrary is made herein. In particular, use of the singular articles such as "a," "the," "said," etc. should be read to recite one or more of the indicated elements unless a claim recites an explicit limitation to the contrary.

The abstract is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of the present disclosure should not be understood to reflect such intent: the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separately claimed subject matter.