阅读说明：本技术 在半导体封装之间引导控制数据 (Directing control data between semiconductor packages ) 是由 N·J·罗伯森 R·L·努南 D·F·海因里奇 于 2021-04-15 设计创作，主要内容包括：本公开涉及在半导体封装之间引导控制数据。处理器执行固件以将描述用于总线协议引擎的传递描述符的控制数据写入到与用于总线协议引擎的传递描述符缓冲器相关联的地址。总线协议引擎根据传递描述符与从属设备执行操作；处理器是第一半导体封装的一部分；总线协议引擎是不同于第一半导体封装的第二半导体封装的一部分；并且该地址对应于第二半导体封装的存储器。第一半导体封装的第一物理接口与第二半导体封装的第二物理接口通信以将控制数据引导到存储器。(The present disclosure relates to directing control data between semiconductor packages. The processor executes firmware to write control data describing a transfer descriptor for the bus protocol engine to an address associated with a transfer descriptor buffer for the bus protocol engine. The bus protocol engine executes operation with the slave device according to the transfer descriptor; the processor is part of a first semiconductor package; the bus protocol engine is part of a second semiconductor package different from the first semiconductor package; and the address corresponds to a memory of the second semiconductor package. The first physical interface of the first semiconductor package communicates with the second physical interface of the second semiconductor package to direct the control data to the memory.)

1. A method, comprising:

a processor executing firmware to write control data describing a transfer descriptor for a bus protocol engine to an address associated with a transfer descriptor buffer for the bus protocol engine, wherein the bus protocol engine performs operations with a slave device according to the transfer descriptor, the processor is part of a first semiconductor package, the bus protocol engine is part of a second semiconductor package different from the first semiconductor package, and the address corresponds to a memory of the second semiconductor package; and

a first physical interface of the first semiconductor package communicates with a second physical interface of the second semiconductor package to direct the control data to the memory.

2. The method of claim 1, wherein:

the slave device comprises a memory device for storing memory parameters for a system memory module, wherein the slave device is coupled to a bus;

the bus and the memory device are external to the second semiconductor package; and is

The bus protocol engine initiates a transaction on the bus to read data representing the memory parameter from the memory device according to a transfer descriptor in each of the transfer descriptors.

3. The method of claim 1, wherein the slave device has a primary function other than storing system data.

4. The method of claim 1, wherein the address comprises a base address corresponding to the first physical interface and an offset address corresponding to the transfer descriptor buffer.

5. The method of claim 1, wherein the processor further executes the firmware to write control data to a second address corresponding to a control interface of the bus protocol engine, the method further comprising: the first physical interface communicates with the second physical interface to direct the control data to the control interface.

6. The method of claim 5, wherein the control data written to the second address represents a start command for initiating a bus transfer described by a transfer descriptor in each of the transfer descriptors.

7. The method of claim 5, wherein the second address comprises a base address corresponding to the first physical interface and an offset address corresponding to the control interface.

8. The method of claim 1, further comprising:

the first physical interface communicates with the second physical interface to receive an in-band virtual signal assertion provided by the bus protocol engine; and

in response to receiving the virtual signal assertion, the first physical interface asserts a signal corresponding to the virtual signal assertion.

9. The method of claim 8, wherein:

the virtual signal assertion comprises a virtual interrupt that represents completion of the operation; and is

The first physical interface asserting the signal comprises: the first physical interface generates an interrupt to notify the processor that the operation is complete.

10. The method of claim 9, further comprising:

the processor executing firmware to service the interrupt, comprising: the processor initiating a read transaction to read a result from an address, wherein the address comprises a base address corresponding to the first physical interface and an offset address corresponding to a slave interface of the bus protocol engine; and

in response to the processor initiating the read transaction, the first physical interface communicates with the second physical interface to receive data representing the result of the read transaction from the second physical interface and to provide the data to the processor.

11. The method of claim 1, wherein:

the bus protocol engine is associated with a bus; and is

The transfer includes an operation for reading data from the slave device.

12. The method of claim 1, wherein the first physical interface communicating with the second physical interface comprises: the communication is performed through a message encapsulation interface.

13. The method of claim 1, wherein:

the first physical interface communicating with the second physical interface comprises: transmitting the transaction data over the first set of communication lines; and is

The bus protocol engine has an input control and data interface with an associated second set of communication lines greater in number than the first set of communication lines.

14. A system, comprising:

a slave device;

a first semiconductor package, the first semiconductor package comprising:

a processing core to execute firmware instructions to cause the processing core to write transaction data to an address corresponding to a transaction buffer; and

a first message encapsulation interface to communicate with a second message encapsulation interface to direct the transaction data to the transaction buffer in response to a write of the transaction data; and

a second semiconductor package, the second semiconductor package comprising:

the second message encapsulation interface;

a protocol engine; and

a memory including the transaction buffer, wherein the protocol engine is to access the transaction buffer and perform a bus transfer operation with the slave device based on transaction data stored in the transaction buffer.

15. The system of claim 14, further comprising a baseboard management controller, wherein the second semiconductor package is part of the baseboard management controller.

16. The system of claim 14, further comprising:

a host processor; and

a baseboard management controller;

wherein:

the second semiconductor package is part of the baseboard management controller;

the system memory device is associated with a memory parameter;

the bus transfer operation comprises a read operation to read data representing the memory parameter; and is

The baseboard management controller transmits the data representing the memory parameters to the host processor.

17. An apparatus, comprising:

a first semiconductor package;

a processing core disposed in the first semiconductor package to write transaction data to an address associated with a transfer descriptor buffer, wherein the transaction data describes a bus transfer to be performed by a bus protocol engine; and

a bridge disposed in the first semiconductor package for providing signaling to external terminals of the first semiconductor package to direct the transaction data to a second semiconductor package including the transfer descriptor buffer and the bus protocol engine in response to writing the transaction data to the transfer descriptor buffer.

18. The apparatus of claim 17, wherein the bridge comprises a full duplex, message encapsulation, and error correction interface.

19. The apparatus of claim 17, wherein:

the bus protocol engine includes a serial bus interface;

the bus transfer comprises a transfer for reading data from a device; and is

The processing core writes the transaction data to an address comprising a base address and an offset address, the base address corresponding to the bridge and the offset address corresponding to the transfer descriptor buffer.

20. The apparatus of claim 17, further comprising a baseboard management controller, wherein the first semiconductor package is part of the baseboard management controller.

Background

An Application Specific Integrated Circuit (ASIC) is an Integrated Circuit (IC) designed for a specific use. To reduce circuit board area, embedded processing subsystems, such as subsystems including a system on chip (SoC), Baseboard Management Controller (BMC), or multi-function microprocessor, may include one or more ASICs. In general, ASICs can often be "hardened" and difficult to change once manufactured. The monetary and human resource costs of shaping (spin) a new or modified ASIC (i.e., rebuilding, including redesign and remanufacturing) can be significant.

Drawings

FIG. 1 is a schematic diagram of a computer system, according to an example embodiment.

Fig. 2 is a schematic diagram of a firmware process executed by a processing core of an Application Specific Integrated Circuit (ASIC) of fig. 1 that uses a message tunneling interface (message tunneling interface) to control access of an off-chip bus protocol engine to a slave device, according to an example embodiment.

Fig. 3 is an illustration of a transfer descriptor in accordance with an example embodiment.

Fig. 4 is a diagram of a Control and Status Register (CSR) of a bus protocol engine, according to an example embodiment.

FIG. 5 is a graphical representation of data returned as a result of a bus transfer performed by a bus protocol engine, according to an example embodiment.

Fig. 6 is a schematic diagram of a message tunneling interface of the ASIC of fig. 1, according to an example embodiment.

Fig. 7 is a flowchart depicting a process for directing control data for a bus protocol engine written by a processor on one semiconductor package to memory located on another semiconductor package, according to an example embodiment.

Fig. 8 is a schematic diagram of a system for directing transaction control data written by a processing core on one semiconductor package to a buffer on another semiconductor package, according to an example embodiment.

Fig. 9 is a schematic diagram of an apparatus in which control data for a bus protocol engine is directed from one semiconductor package to another, according to an example embodiment.

Detailed Description

The computer system may include a Baseboard Management Controller (BMC) that monitors the physical state of the computer system and may communicate with a management system over a management network. As an example of its role, the BMC may monitor sensors (e.g., temperature sensors, cooling fan speed sensors); monitoring an operating system state; monitoring the power state; recording computer system events; and providing management functions for the computer system that can be remotely controlled. In addition, the BMC may allow operations to be performed when the computer system is powered down and before the operating system has started; and the BMC may be used to perform recovery operations after a failure of the operating system or computer system.

In a pre-boot environment, the BMC may communicate with a slave device of the computer system. For example, the BMC may communicate with a Serial Presence Detect (SPD) device (e.g., an Electrically Erasable Programmable Read Only Memory (EEPROM) device) of a memory module (e.g., a dual in-line memory module (DIMM)) of the computer system for retrieving data representing information about the memory module. By way of example, the information pertains to characteristics and capabilities of the memory module, such as memory device type, module type, row and column addressing scheme, minimum cycle time, maximum cycle time, Column Address Selection (CAS) latency, minimum row precharge delay time, and so forth. The BMC may communicate this information to the host CPU so that the host CPU may establish computer system interfaces (e.g., physical memory interfaces and memory controllers).

To provide the above-described and other effects, the ASIC of the BMC may include one or more general-purpose processors (e.g., embedded processing cores). For these purposes, the BMC may use one or more communication interfaces (e.g., bus interface, s)Such as I²C-bus interface, System Management Bus (SMB) interface, peripheral component interconnect express (PCIe) interface, ethernet bus interface, etc.) communicate with the components of the computer system.

Computer technology is constantly evolving and hardware platform vendors can modify hardware platform designs to address technological advances. For example, hardware platform designs may be modified to implement new bus standards. Adapting the BMC to accommodate the new bus standard may involve updating the ASIC of the BMC to communicate using the new bus standard. For example, an ASIC may have I²C bus interface, and adapting BMC to support I³C communication may involve communicating I³C support addition to I²C bus interface or add-on I³And C, bus interface. One method for upgrading BMC to such capabilities is to re-shape the ASIC. In this context, "reforming" of an ASIC refers to the reconstruction of the ASIC, including redesign and remanufacture. In this manner, the ASIC may be redesigned and remanufactured to have new hardware components, such as support I²C bus and I³New I for both C bus protocols³C bus interface or upgraded bus interface. However, the re-molding of ASICs may have relatively large monetary and human resource costs.

Another solution for upgrading the capabilities of a BMC is to use an external third party component (e.g., third party I) with the BMC³C-bus protocol engine) to allow the unmodified BMC to support one or more new features. The challenge with the latter approach is that third party components may be untrusted. For embodiments where the BMC orchestrates the security of the computer system, the use of third party components may compromise system security. For example, for third party I³The C-bus protocol engine, the retrieval of information about the memory modules of the computer system may be under the control of an untrusted entity, rather than under the control of the BMC. Furthermore, using a third party component with the BMC may involve reading and signing the software/firmware model of the corresponding infrastructure incorporating the third party component; and the use of third party components may increase the cost of the computer system.

According to the description hereinExample embodiments, a bridge or physical communication interface (e.g., a message encapsulation tunneling interface) of an ASIC is used to communicate control data (e.g., transfer descriptors and bus protocol engine control interface data) to an "off-chip" bus protocol engine that is part of a semiconductor package other than the semiconductor package containing the ASIC. By way of example, this additional semiconductor package may contain a programmable logic device that may be trusted and that may be programmed to implement a particular interface (e.g., I) for an ASIC³C bus engine interface). Thus, instead of implementing a hardware change that may involve reshaping the ASIC or using an untrusted third party component, the firmware of the ASIC may be modified to change the addresses written by one or more general purpose processing cores of the ASIC (e.g., the address of the transfer descriptor buffer and the address of the Control and Status Register (CSR) corresponding to the bus protocol engine). In this way, the ASIC (and BMC) may be updated through firmware and trusted programmable logic devices to implement a new communication interface for BMC.

Referring to FIG. 1, as a more specific example, according to some embodiments, computer system 100 includes an ASIC160 that can perform one or more functions of the computer system. ASIC160 includes one or more general purpose processing cores 154, such as firmware, that execute machine-executable instructions in order to perform one or more of these functions. As depicted in fig. 1, ASIC160 may be part of a semiconductor package 159. In this context, "semiconductor package" refers to a housing or package containing one or more integrated circuits, such as ASIC 160. One or more integrated circuits of a semiconductor package may be disposed on one or more die; and the semiconductor package may contain leads (also referred to as "contacts," "external contacts," "terminals," "external terminals," etc.) that allow signals, voltages, currents, etc. to be communicated between one or more integrated circuits of the semiconductor package and one or more components external to the semiconductor package. The semiconductor package may take one of a variety of forms, such as a through-hole package, a surface mount package, a chip carrier package, a pin grid array package, a flat package, a small outline package (small outline package), a chip scale package, a ball grid array package, and the like.

For the embodiment depicted in FIG. 1, the ASIC160 is part of the BMC 130. According to an example embodiment, the BMC130 is an embedded subsystem that may contain one or more semiconductor packages other than the semiconductor package 159. As used herein, a "BMC" or "baseboard management controller" is a dedicated service processor that uses sensors to monitor the physical state of a server or other hardware and communicate with a management system over a management network. The baseboard management controller can also communicate with applications executing at the operating system level through an input/output controller (IOCTL) interface driver, a representational state transfer (REST) Application Program Interface (API), or some other system software agent that facilitates communication between the baseboard management controller and the applications. The baseboard management controller can have hardware-level access to hardware devices located in a server chassis that includes system memory. The baseboard management controller may be capable of directly modifying the hardware device. The baseboard management controller can operate independently of the operating system of the system in which the baseboard management controller is disposed. The baseboard management controller can be located on a motherboard or main circuit board of a server or other device to be monitored. The fact that the baseboard management controller is mounted on the motherboard of the managed server/hardware or otherwise connected or attached to the managed server/hardware does not prevent the baseboard management controller from being considered "separate" from the server/hardware. As used herein, a baseboard management controller has management capabilities for subsystems of a computing device and is separate from the processing resources executing the operating system of the computing device. The baseboard management controller is separate from the processor (e.g., central processing unit) that executes the high-level operating system or hypervisor on the system.

According to an example embodiment, the ASIC160 has been adapted or upgraded using firmware changes and an external programmable logic device 180 (e.g., a complex programmable logic device (cPLD)) to perform one or more functions of the computer system 100, the hardware of the ASIC160 not being specifically constructed to perform the one or more functions. According to further embodiments, integrated circuits other than programmable logic devices may be used to perform the functions of device 180 and used instead, such as ASICs, Field Programmable Gate Arrays (FPGAs), and the like.

According to an example embodiment, ASIC160 includes a bridge or physical communication interface 158 (e.g., a message encapsulation tunneling communication interface) that communicates with a corresponding bridge or physical communication interface 182 (e.g., a message encapsulation tunneling communication interface) of logic device 180. According to an example embodiment, communication interfaces 158 and 182 establish duplex communication link 174 between ASIC160 and logic device 180. According to an example embodiment, to upgrade features of the ASIC160 (and the BMC 130), the communication interfaces 158 and 182 enable data accesses (e.g., read operations and write operations) and signal assertions (e.g., interrupt signal assertions) to be redirected to hardware (e.g., memory and bus protocol engines) of the logic device 180. According to example embodiments, the logic device 180 may be part of the semiconductor package 179, and for these example embodiments, the communication interfaces 158 and 182 establish communication between the semiconductor packages 159 and 179.

According to an example embodiment, the logic device 180 may be programmed to implement hardware used by the ASIC160 (and BMC 130). In particular, for the example embodiment of FIG. 1, the logic device 180 is programmed to implement a bus protocol engine 186. According to an example embodiment, the firmware of ASIC160 may use bus protocol engine 186 to perform bus transfers to/from one or more slave devices of computer system 100.

More specifically, according to an example embodiment, the system memory 104 of the computer system 100 may include one or more slave devices 114 that are capable of using I³A bus transfer (e.g., a read transfer) on the C bus 105 makes the access. For these example embodiments, the slave device 114 may be an SPD device that is part of a memory module of the system memory 104 and stores information about the memory module. According to further example embodiments, ASIC160 may use bus protocol engine 186 (or another such off-chip engine, whether disposed on semiconductor package 179 or another such off-chip engineOn a semiconductor package) to communicate with slave devices 114 other than SPD devices. An SPD device storing data representing information about the memory module is an example of a slave device 114 having a primary function of storing system data. In this context, "system data" refers to content relating to one or more components of the computer system 100 other than the slave device 114, e.g., content representing information about a memory module. While a particular slave device 114 may have a primary function of storing system data according to some embodiments, a given slave device 114 may have a primary function other than a function of storing system data according to further example embodiments. As an example, according to some embodiments, a given slave device 114 may be a sensor whose primary function is not to store system data (e.g., a temperature sensor or a voltage sensor), a Power Management Integrated Circuit (PMIC) controller, a Residual Current Device (RCD), an SPD device, or the like. It should be noted that according to further embodiments, bus 105 may be other than I³C bus and the bus protocol engine 186 may transmit signals on this additional bus according to the protocol used by the additional bus.

As depicted in fig. 1, according to an example embodiment, in addition to the bus protocol engine 186, the logic device 180 also includes a local memory 184 (e.g., a Block Random Access Memory (BRAM)). As depicted in fig. 1, according to an example embodiment, logic device 180 may include a communication path 185 between communication interface 182 and memory 184; a communication path 187 between the communication interface 182 and the bus protocol engine 186; and a communication path 188 between the bus protocol engine 186 and the memory 184.

In general, the general purpose processing core 154 of the ASIC160 may be programmed by firmware execution or set up to use I by the bus protocol engine 186³C bus 105. More specifically, according to an example embodiment, the processor core 154 may write, by firmware execution, a transfer descriptor (i.e., data describing a bus transfer to be performed by the bus protocol engine) stored in a transfer descriptor buffer 183 of the memory 184, and one or moreThe plurality of processor cores 154 may execute via firmware to store data associated with the write bus transfers in the memory 184 and to read data resulting from the read bus transfers. Bus protocol engine 186 operates at I by reading and writing data to/from memory 184 and reading transfer descriptors from transfer descriptor buffer 183³The corresponding bus transfers are performed on the C bus 105 without direct involvement of the processing core 154.

As described herein, according to an example embodiment, firmware rather than hardware changes may be used to upgrade the ASIC160 (and BMC 130) to use features of the logic device 180. According to an example embodiment, ASIC160 utilizes communication link 174 to separate or decompose transaction data and control data to allow access to the hardware of logic device 180 in a manner that is transparent to the firmware of ASIC 160.

More specifically, according to an example embodiment, an old version of firmware of ASIC160 may be upgraded to access memory of ASIC160 by changing the address used by the firmware. In this context, "memory" generally refers to an addressable location that stores data, and may be, by way of example, memory of a non-volatile or volatile memory device (e.g., memory 184) or a register or register interface (e.g., register storage space of bus protocol engine 186).

According to an example embodiment, to access a slave device (e.g., slave device 114) via a bus transfer, firmware of ASIC160 writes a transfer descriptor to a transfer descriptor buffer. The old version of firmware may write the transfer descriptor to a transfer descriptor buffer corresponding to ASIC160 (e.g., to control I existing inside ASIC160²The transfer descriptor buffer of the C-bus protocol engine). Through the address change, the firmware may be updated such that the write to the transfer descriptor buffer occurs at an address corresponding to the transfer descriptor buffer 183 of the logic device 180. Further, through the address change, the firmware may be updated such that writes or reads originally directed to the slave control interface of the bus protocol engine of ASIC160 are now directed to an address corresponding to the slave interface 189 (e.g., Control and Status Register (CSR)) of bus protocol engine 186.

According to an example embodiment, the addresses of transfer descriptor buffer 183 and slave interface 189 each have two components: a base address and an offset address. According to an example embodiment, from the perspective of the updated firmware of the ASIC160, the base address of all addressable components of the logic device 180 is the address of the communications interface 158 of the ASIC160, and the offset address corresponds to the offset address within the logic device 180. In other words, according to an example embodiment, each addressable component of the logic device 180 has the same base address and a different offset address. By replacing addresses of hardware components used by the old version of firmware (e.g., pass descriptor buffer addresses, memory addresses, and slave control interface addresses) with addresses corresponding to their hardware components in the logic device 180, the ASIC160 can be upgraded to support newer technologies (e.g., upgraded to support I³C-technology or other communication protocol) without involving the reshaping of ASIC160, the use of untrusted third party components, or additional fees for using third party components. Further, according to an example embodiment, the communication interfaces 158 and 182 provide a relatively low pin count communication link 174 that effectively functions as an input/output (I/O) expander to expand the possible functions that may be performed by the ASIC160 while minimizing the pin count of the ASIC.

The transfer descriptor describes the corresponding bus transfer and is read and executed by the bus protocol engine 186. According to an example embodiment, to perform a bus transfer (or "bus operation"), firmware of ASIC160 first writes one or more transfer descriptors describing the bus transfer (e.g., read or write commands, write data, etc.) to transfer descriptor buffer 183, and then the firmware writes a "start" command to the command register field of slave interface 189 to initiate the bus transfer. Firmware may also monitor the status of bus transfers by reading one or more status register fields of slave interface 189; and the firmware may read the data resulting from the read bus transfer by reading the data from the memory 184.

Additionally, the communication interfaces 158 and 182 may communicate in-band virtual signal assertions associated with bus transfers, as further described herein. In this context, "virtual signal assertion" refers to data that represents a particular signal state (e.g., interrupt assertion). By way of example, a "signal state" may indicate whether a particular physical signal has a logic 1 level or a logic 0 level, or may indicate whether a bit is a logic 1 bit or a logic 0 bit, as another example. An "in-band" dummy signal assertion refers to a dummy signal assertion being transferred in the same channel as other data (e.g., read data, data to be written, CSR data, etc.). According to an example embodiment, in response to an assertion of a particular signal on logic device 180, a virtual signal assertion is generated on logic device 180 and transmitted to ASIC 160; and in response to receiving the virtual signal assertion, ASIC160 asserts a signal to simulate the assertion of a signal on logic device 180. As a more specific example, the bus protocol engine 186 may assert an interrupt indicating that a particular read or write operation is complete. In response to the interrupt, communication interface 182 of logic device 180 communicates data to communication interface 158 indicating the assertion of the virtual interrupt signal. The communication interface 158 asserts a corresponding interrupt (e.g., a hardware interrupt or a software interrupt) on the ASIC160 in response to the received virtual signal assertion to notify the processing core 154 of the completion of the bus transfer.

As a more specific example, according to an example embodiment, the bus protocol engine 186 may be via I³The C-bus 105 performs a bus operation or bus transfer to read the memory parameters of the system memory module from the slave device 114. To establish bus transfers, the firmware of ASIC160 may write a corresponding transfer descriptor to the description pass I³The transfer descriptor buffer 183 of the C-bus 105 to slave device 114 read transfer, the transfer descriptor and then the firmware may write a "start" command to the command register field of the slave interface 189 to initiate the start of the bus read transfer by the bus protocol engine 186. The bus protocol engine 186 then performs a read bus transfer to read the memory parameters from the slave device 114 and store the read data in the local memory 184 of the logic device 180. According to an example embodiment, at the end of a bus transfer, the bus protocol engine 186 generatesTo an interrupt to indicate completion of the operation. The corresponding virtual interrupt is then communicated through communication interfaces 158 and 182 such that receipt of the virtual interrupt through communication interface 158 causes interface 158 to generate an interrupt to notify processing core 154 of the completion of the bus transfer and the availability of data in memory 184. The processing core 154 may then service the interrupt by reading data from the memory 184.

The computer system 100 may have any of a number of different architectures and forms. By way of example, the computer system 100 may be a server, a client, a desktop computer, a laptop computer, a tablet computer, a smartphone, a wearable computer, a rack-mounted module, a networking device, and so forth.

According to an example embodiment, computer system 100 includes one or more Central Processing Units (CPUs) 102 (e.g., CPU processing cores, semiconductors containing CPU processor cores, etc.), and a memory device (e.g., a memory module) coupled to the one or more CPUs 102 to form a system memory 104. The one or more CPUs 102 can be coupled to an input/output (I/O) bridge 106, the I/O bridge 106 allowing communication between the one or more CPUs and the BMC130 as well as communication with various I/O devices (e.g., storage drive 122, one or more network interface cards 124, Universal Serial Bus (USB) device 126, etc.). Further, as also depicted in FIG. 1, computer system 100 may include one or more peripheral component interconnect express (PCIe) devices 110 (e.g., PCIe expansion cards) coupled to I/O bridge 106 through a separate PCIe bus 108.

According to an example embodiment, one or more general purpose processing cores 154 of the BMC130 may execute firmware instructions 170 stored in the non-volatile memory 168. According to an example embodiment, the firmware instructions 170 comprise instructions executed by components of the computer system 100 other than the general purpose processing core 154. According to an example embodiment, firmware instructions 170 include: instructions executed by a secure processor of the BMC130 (as part of the BMC's security plane); instructions executed by one or more general-purpose processing cores 154 of the BMC130 (i.e., corresponding to firmware that manages a firmware stack corresponding to a management plane of the BMC 130); and instructions executed by one or more CPUs 102 to boot computer system 100 and provide runtime services. The computer system 100 may also include a volatile memory 164 that may be accessed and used by the BMC 130.

In general, the memory devices forming the system memory 104, firmware memory 168, volatile memory 164, and slave device 114, as well as other memory devices described herein, may be formed of non-transitory memory devices (e.g., semiconductor memory devices, flash memory devices, memristors, phase change memory devices, combinations of one or more of the foregoing memory technologies, etc.). Further, unless otherwise specified herein, a memory device may be a volatile memory device (e.g., a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, etc.) or a non-volatile memory device (e.g., a flash memory device, a Read Only Memory (ROM) apparatus, an EEPROM device, etc.).

Generally, after power-up or reset, the BMC130 holds one or more general purpose processing cores 154 in reset. After performing the initial root of trust security checks and other checks (e.g., hardware fault checks), the baseboard management controller 130 releases the one or more general purpose processing cores 154 from reset. According to an example embodiment, the BMC130 includes a hardware root of silicon trust (SRoT) engine 143. According to an example embodiment, the BMC130 stores an immutable fingerprint that is used by the SRoT engine 143 to verify machine executable instructions.

More specifically, according to an example embodiment, in response to the BMC130 powering on or resetting, the SRoT engine 143 validates the initial portion of the firmware instructions 170 and then loads the initial portion into the memory 155 of the BMC130 so that the firmware portion is now trusted. The secure processor 142 is then allowed to boot up and execute the loaded firmware instructions. By executing the firmware instructions, the secure processor 142 may then verify another portion of the firmware instructions 170 corresponding to a portion of the BMC's management firmware stack and, after verification, load the portion of the firmware stack into the memory 155 of the BMC 130. This portion of the managed firmware stack may then be executed by one or more general purpose processing cores 154, which causes one or more processing cores 154 to load additional portions of firmware instructions 170 and place the loaded portions into memory 164. Those instructions may be executed from a verified portion of the firmware stack of the BMC in memory 155. According to an example embodiment, the BMC130 may lock the memory 155 to prevent modification or tampering with one or more verified portions stored in the memory 155.

According to an example embodiment, the firmware instructions loaded into memory 155 and executed by one or more processing cores 154 may include instructions corresponding to a firmware driver (i.e., an example of "firmware" described herein) that may use logic device 180, as an example, to communicate via I³The C bus 105 performs data transfer. More specifically, according to an example embodiment, the one or more general purpose processing cores 154 may execute firmware drivers to access the slave device 114. For example, the general purpose processing core 154 may use the bus protocol engine 186 to read memory parameters for a memory module of the system memory 104 in response to executing a firmware driver; and then the BMC130 may provide these parameters to the CPU 102 so that the CPU 102 may use the memory parameters to set up the computer system 100 (e.g., program a physical memory interface) to use the memory device.

According to an example embodiment, the general purpose processing core 154 of the BMC130 may execute firmware instructions corresponding to a firmware driver (e.g., part of the firmware loaded into the memory 155) to perform the process 200 shown in fig. 2 for accessing the slave device 114 (e.g., for reading data from the slave device 114 or writing data to the slave device 114). Referring to fig. 2 in conjunction with fig. 1, by executing the firmware driver, the processing core 154 performs a write to the transfer descriptor buffer 183 to fill the buffer 183 with one or more transfer descriptors describing bus transfers, according to block 204. Fig. 3 is a diagram 300 of example transfer descriptors 304 and 308. Referring also to fig. 3, transfer descriptors 304 and 308 may be written to a particular offset 302 within transfer descriptor buffer 183. As an example, as depicted in fig. 3, a particular transfer descriptor 304 may include commands and data. The command may be, for example, a read command or a write command; also, as an example, the data may be data for a write bus transfer. As also depicted in fig. 3, the transfer descriptor 308 may be stored in a buffer 183 containing the index and data. For example, the index may represent a link between transfer descriptors and, by way of example, the data may be data to be written. The processing core 154 writes the transfer descriptor data to an address corresponding to the address of the buffer 183. More specifically, according to an example embodiment, for this write, the address represents the sum of a base address pointing to communication interface 158 and an offset address corresponding to the offset address of buffer 183 in logic device 180.

Continuing with the example process 200 of FIG. 2, the firmware driver may then cause the processing core 154 to write (block 208) control data to the slave interface 189. Fig. 4 depicts a CSR 400 of the slave interface 189 of the bus protocol engine 186 according to an example embodiment. Referring also to FIG. 4, as depicted in FIG. 4, CSR 400 may be addressable via an offset address 402 and include a register set 410 that represents the state of a particular bus transfer, such as registers 412, 414, and 416 that represent write count, state, and read count, respectively. By way of example, CSR 400 may also include DMA write address register 420, DMA read address register 422, and address/command register 418. According to an example embodiment, execution of the firmware may cause the processing core 154 to write a start command to the register 418 to start the bus transfer represented by the transfer descriptor in the buffer 183, according to block 208. According to an exemplary embodiment, the write is directed to an address corresponding to a base address corresponding to communication interface 158 and an offset corresponding to the offset address of register 418 in logic device 180.

The bus protocol engine 186 performs the requested bus transfer, which may be included in I³Data transfer is performed on the C bus 105. Thus, as depicted at block 212, the bus protocol engine 186 retrieves commands and/or data from the buffer 183, and then at I³The transfer is performed (block 216) on the C bus 105. According to an example embodiment, upon completion of a bus transfer operation (successful or unsuccessful), the bus protocol engine 186 generates an interrupt to indicate completion and the communication interface 182 of the logic device 180 accordingly communicates a virtual in-band interrupt assertion to the ASIC160, a communication interface 158. According to an example embodiment, communication interface 158 asserts an interrupt signal in ASIC160 in response to a virtual in-band interrupt assertion to notify processing cores 154 of completion of a bus transfer operation. The interrupt service routine of the processing core 154 may then be executed by the processing core 154 to read the status register 410 (FIG. 4) bus transfer in order to read the results of the bus transfer. The reading of status register 410 by processing core 154 may be directed to an address formed by a base address corresponding to communication interface 158 and an offset address corresponding to the offset of register 410 in logic 160.

According to block 220 of process 200, the firmware driver may then cause processing core 154 to read the status of the bus transfer (i.e., access the CSR of slave interface 189 using the base address corresponding to communication interface 158 and the offset address corresponding to the CSR). If the operation is a read operation and the data in the CSR indicates that the read operation was successful, the processing core 154 may then retrieve or retrieve the read data from the memory 184. For this read, the read address is formed from a combination of the base address of communication interface 158 and an offset address corresponding to the location of the data within logic device 180 in memory 184. Fig. 5 depicts a diagram 500 in which eight bytes may be retrieved, although other data sizes may be retrieved in a read operation, according to a further embodiment.

Referring to fig. 6, according to an example embodiment, the components of the communication interface 158 are structured as a three-layer hierarchy including a physical layer 680 (lowest layer), a link layer 650 (middle layer), and a protocol layer 620 (highest layer). In general, the physical layer 680 is responsible for low-level link training, serialization/deserialization, and byte framing. The link layer 650 is responsible for correctly accumulating a particular transaction on the communications link path 174 for a series of incoming bits/nibbles/bytes originating from the protocol layer 620 for an outbound (outbound) transaction or received by the physical layer 680 for an inbound (inbound) transaction. Protocol layer 620 handles higher order transaction metadata such as source/destination routing information, end-to-end transaction timers, and message command and data queues. As also depicted in fig. 6, according to some embodiments, communication interface 158 includes clock generation and switching circuitry 616 that may generate clock signals for different layers of tunneling bridge 158.

The physical layer 680 includes a transmit serializer 682 to transmit a plurality of data bits to the communication interface 182 in synchronization with a clock signal. The physical layer 680 also includes a receive deserializer 686 that receives a plurality of data bits in synchronization with a clock signal. Physical layer 680 may also include control and status registers 683 and a training finite state machine 684. In addition, the physical layer 680 may include first-in-first-out (FIFO) buffers 659 and 663 for buffering data transferred between the physical layer 680 and the link layer 650.

According to some embodiments, the transmit serializer 682 and the receive serializer 686 transmit bi-directional data across the communication path 174 (see fig. 1) that is synchronized with the source of the transmitter. In other words, according to an example embodiment, the communication path 174 is a source synchronous bus. According to some embodiments, four data bits may be received by the receive deserializer 686 and four data bits may be transmitted by the transmit serializer 682 each bus clock cycle. However, according to alternative embodiments, fewer or more data bits may be transmitted. For example, according to some embodiments, one data bit may be transmitted in each direction, thereby reducing the interface to four signals (i.e., one clock and one data signal in each direction). According to some embodiments, the number of data bits may be scaled to allow for variable physical layer widths, I/O standards, and transceiver technologies, which means that communication interface 158 may be scaled to faster bus frequencies, new bus standards, and sizes for facilitating increased bandwidth, lower cycle delay, and improved performance.

According to an example embodiment, the link layer 650 interrogates the transaction header, which may be protected with parity information, to determine the transaction type and other significant information. Based on the header, link layer 650 constructs a raw data payload that is either sent out of physical layer 680 (via transmit serializer 682) or received by physical layer 680 (via receive deserializer 686). According to an example embodiment, each transaction transmitted across communication link 174 will be acknowledged with a response; and the link layer 650 optionally generates outbound responses and examines/expects inbound responses to outbound requests.

According to an example embodiment, the link layer 650 may include a Cyclic Redundancy Check (CRC) check engine 664 that allows the link layer 650 to perform a CRC check and, if appropriate, initiate an end-to-end retry in response to a detected error. CRC errors are an example of a number of possible error events that the link layer 650 checks to ensure message integrity. Other errors may correspond to, for example, parity errors and command consistency errors. In response to the error, according to an example embodiment, link layer 650 may initiate link retraining (via physical layer 680); and link layer 650 regenerates any outstanding transactions for which link layer 650 did not observe a successful response completion.

According to an example embodiment, the link layer 650 includes a link state and training finite state machine 660, a transport processor and data multiplexer 652, and a receive header processor and packet inspector 662. Link state and training finite state machine 660 may, for example, initiate link retraining for outstanding transactions that did not result in a successful response completion. Transport processor and data multiplexer 652 may insert CRC codes generated by CRC generation engine logic 658. The MRST generation logic 654 participates during reset and link training to generate link messages (MRST messages) that indicate to an artistic receiver (art receiver) that the link is to be retrained. The MIDLE generation logic 656 generates link messages (MDLE messages) that are sent whenever the link is idle and not transmitting other messages. The receive header handler and packet inspector 662 may interrogate the transaction header to determine the transaction type and other significant information. A link state and training finite state machine 660 may be coupled to control the state registers 638 between the link layer 650 and the protocol layer 620; and control and status registers 638 may be coupled to control status registers 636 of protocol layer 620. Further, FIFO buffer 627 may buffer incoming bits to link layer 650 (from protocol layer 620) and FIFO buffer 645 may buffer outgoing bits from link layer to protocol layer 620.

According to an example embodiment, transaction ordering and atomicity are performed by protocol layer 620. According to some embodiments, the protocol layer 620 may include an inbound response circuit 624 (receiving data from the FIFO buffer 622) and an outbound request circuit 632 on the transmit side. Circuits 624 and 632 may access FIFO buffer 624 via arbiter/mux 626. On the receive side, the protocol layer 620 includes outbound and inbound request circuits 648, an outbound response circuit 642, and a router 644 that controls the routing of data to the circuits 642 and 644. As depicted in FIG. 6, FIFO circuits 624 and 628 may buffer data incoming into circuits 624 and 632, respectively; and FIFO buffers 640 and 648 may buffer outgoing data from circuits 642 and 648, respectively.

An arbiter and switch fabric 614 couples the protocol layer 620 to one or more host interfaces 610. As an example, according to some embodiments, a particular microprocessor (μ P) interface 610-1 may be coupled to a bus, which in turn is coupled to the general purpose processing core 154. According to an example embodiment, the μ P interface 610 uses a round robin arbitration scheme to arbitrate access to the protocol layer 620 via the multi-port message passing switch to ensure fairness. According to an example embodiment, for example, the arbitration algorithm may be changed to increase the priority of a given μ P interface 610, thereby increasing the priority of a given initiator class accordingly.

As also depicted in fig. 6, according to an example embodiment, communication interface 158 includes a virtual line encoder/decoder 618 that provides low-latency, seamless playback of signals/lines at each end of communication link 174. Specifically, according to an example embodiment, on the transmit side, the virtual line encoder/decoder 618 receives (via its respective assertion) a signal (referred to in FIG. 6 as "vwout [57:0 ]") representing a virtual assertion signal that is conveyed in-band via the communication link 174. On the receive side, the virtual line encoder/decoder 618 provides a signal (referred to as "vwin [57:0 ]" in FIG. 6) that represents the received in-band virtual assert signal. This virtual line feature enables lower latency signal playback over communication link 174 by bypassing protocol layer 620.

According to an example embodiment, communication interface 182 of logic device 180 may have a design similar to that of communication interface 158.

Referring to fig. 7, according to an example embodiment, a process 800 includes a processor executing (block 704) firmware to write control data describing a transfer descriptor for a bus protocol engine to an address associated with a transfer descriptor buffer for the bus protocol engine. The bus protocol engine executes operation with the slave device according to the transfer descriptor; the processor is part of a first semiconductor package; the bus protocol engine is part of a second semiconductor package different from the first semiconductor package; and the address corresponds to a memory of the second semiconductor package. Process 700 includes a first physical interface of a first semiconductor package communicating with a second physical interface of a second semiconductor package to direct control data to a memory, as per block 708.

Referring to fig. 8, according to an example embodiment, a system 800 includes a slave device 804; a first semiconductor package 830; and a second semiconductor package 808. First semiconductor package 830 includes a processing core 834 and a first message package interface 838. Processing core 834 executes firmware instructions to cause processing core 834 to write transaction data to an address corresponding to transaction buffer 824. The first message encapsulation interface 838 communicates with the second message encapsulation interface 812 to direct transaction data to the transaction buffer in response to a write of the transaction data. Second semiconductor package 808 includes a second message package interface 812; a protocol engine 816; and a memory 820 including a transaction buffer 824. The protocol engine 816 is used to access the transaction buffer 824 and perform bus transfer operations with the slave device 804 based on the transaction data stored in the transaction buffer 824.

Referring to fig. 9, according to an example embodiment, an apparatus 900 includes a first semiconductor package 910; a processing core 914; and a bridge 918. The processing core 914 is disposed in the first semiconductor package 910 to write transaction data to an address associated with the transfer descriptor buffer. The transaction data describes bus transfers to be performed by the bus protocol engine. A bridge 918 is disposed in the first semiconductor package 910 for providing signaling to an external terminal 922 of the first semiconductor package 910 in response to writing transaction data to the transaction buffer to direct the transaction data to a second semiconductor package that includes a transfer descriptor buffer and a bus protocol engine.

According to an example embodiment, a slave device includes a memory device for storing memory parameters for a system memory module. The slave device is coupled to the bus. The bus and the memory device are external to the second semiconductor package, and the bus protocol engine initiates a transaction on the bus to read data representing the memory parameter from the memory device according to the transfer descriptor. A particular advantage is that the first semiconductor package can be upgraded to communicate using the bus without having to re-mold the first semiconductor package.

According to an example embodiment, the slave device has a primary function other than storing system data. A particular advantage is that the first semiconductor package can be updated to communicate with the slave device without having to remould the first semiconductor package.

According to an example embodiment, the address includes a base address corresponding to the first physical interface and an offset address corresponding to the transfer descriptor buffer. A particular advantage is that a first semiconductor package may be modified to use a bus protocol engine in a second semiconductor package via address changes in firmware.

According to an example embodiment, a processor may execute firmware to write control data to an address associated with a control interface of a bus protocol engine; and the first physical interface may communicate with the second physical interface to direct the control data to the control interface. A particular advantage is that instead of hardware-based changes, firmware-based changes can be used to adapt the first semiconductor package to use the bus protocol engine.

According to an example embodiment, the control data written to the second address represents a start command for initiating a bus transfer described by the transfer descriptor. A particular advantage is that instead of hardware-based changes, firmware-based changes can be used to adapt the first semiconductor package to use the bus protocol engine.

According to an example embodiment, the address associated with the control interface includes a base address corresponding to the first physical interface and an offset address corresponding to the control interface. A particular advantage is that the first semiconductor package can be modified to use the bus protocol engine of the second semiconductor package via address changes in firmware.

According to an example embodiment, a first physical interface may communicate with a second physical interface to receive an in-band virtual signal assertion provided by a bus protocol engine; and in response to receiving the virtual signal assertion, the first physical interface asserts a signal corresponding to the virtual signal assertion. A particular advantage is that instead of hardware-based changes, firmware-based changes can be used to adapt the first semiconductor package to use the bus protocol engine.

According to example embodiments, the virtual signal assertion may be a virtual interrupt that represents completion of the operation; and asserting the signal by the first physical interface may include the first physical interface generating an interrupt to notify the processor that the operation is complete. A particular advantage is that instead of hardware-based changes, firmware-based changes can be used to adapt the first semiconductor package to use the bus protocol engine.

According to an example embodiment, a processor may execute firmware to service interrupts, including: the processor initiates a read transaction to read the result and the address, wherein the address includes a base address corresponding to the first physical interface and an offset address corresponding to a slave interface of the bus protocol engine. In response to the processor initiating a read transaction, the first physical interface may communicate with the second physical interface to receive data representing the result from the second physical interface and provide the data to the processor. A particular advantage is that instead of hardware-based changes, firmware-based changes can be used to adapt the first semiconductor package to use the bus protocol engine.

According to an example embodiment, the first physical interface communicates with the second physical interface for structured data of the protocol engine. A particular advantage is that instead of hardware-based changes, firmware-based changes can be used to adapt the first semiconductor package to use the bus protocol engine.

According to an example embodiment, the first physical interface communicates with the second physical interface through a message encapsulation interface. A particular advantage is that instead of hardware-based changes, firmware-based changes can be used to adapt the first semiconductor package to use the bus protocol engine.

According to example embodiments, the first semiconductor package may be part of a baseboard management controller, and the second semiconductor package may be part of a programmable logic device. A particular advantage is that instead of changing the hardware of the first semiconductor package, the firmware of the first semiconductor package may be reprogrammed and the programmable logic device may be reprogrammed to accommodate the new interface for the baseboard management controller.

While the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art, having the benefit of this disclosure, will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations.