阅读说明：本技术 组合芯片、存储设备和对存储对象的操作方法 (Combined chip, storage device and operation method for storage object ) 是由 戴瑾 于 2021-08-25 设计创作，主要内容包括：本申请实施例提供组合芯片、存储设备和对存储对象的操作方法,所述组合芯片包括,存储处理芯片和闪存芯片；所述存储处理芯片包括中央处理器和数据处理器,所述中央处理器用于运行存储管理、闪存管理和数据处理软件,所述数据处理器用于对常用数据处理操作进行硬件加速；所述存储处理芯片和闪存芯片封装在一体形成所述组合芯片,且所述存储处理芯片和闪存芯片之间通过闪存接口通信连接,本申请提供数据处理方法是通过存储设备完成,解决了中央处理器跟不上存储扩张的现实问题,实现了靠近存储的计算,可以极大幅度地降低功耗。(The embodiment of the application provides a combined chip, a storage device and an operation method for a storage object, wherein the combined chip comprises a storage processing chip and a flash memory chip; the storage processing chip comprises a central processing unit and a data processor, wherein the central processing unit is used for running storage management, flash memory management and data processing software, and the data processor is used for carrying out hardware acceleration on common data processing operation; the storage processing chip and the flash memory chip are packaged into a whole to form the combined chip, and the storage processing chip and the flash memory chip are in communication connection through the flash memory interface.)

1. A combined chip is characterized by comprising a storage processing chip and at least one flash memory chip;

the storage processing chip comprises a central processing unit and a data processor, wherein the central processing unit is used for running storage management, flash memory management and data processing software, the data processor is used for carrying out hardware acceleration on common data processing operation, and the storage processing chip is connected with a host through a host interface arranged on the storage processing chip;

the storage processing chip and the flash memory chip are packaged and integrally formed into the combined chip, and the storage processing chip and the flash memory chip are in communication connection through a flash memory interface.

2. A storage device comprising at least one combined chip according to claim 1, wherein storage processing chips in a plurality of said combined chips are interconnected via a control network for coordinating data processing.

3. The storage device according to claim 2, wherein all the combination chips of the storage device are connected to a host through a first bridge chip, the first bridge chip selects one of the combination chips in the storage device to be connected to the host through an address requested by the host, one of the combination chips in the storage device is a master combination chip, requests of all hosts are first sent to the master combination chip, and then the master combination chip determines one or more other combination chips to complete requests of the host through coordination of a control network according to the request type of the host.

4. The storage device according to claim 2, wherein all the combined chips of the storage device are connected to the host through a second bridge chip, and the second bridge chip is responsible for processing all the requests from the host and communicating with the combined chips to coordinate the requests from the host.

5. A memory device according to claim 4, wherein the second bridge chip is connected to a dynamic random access memory for storing the physical memory address of each memory object in the flash memory.

6. A storage device according to any of claims 2 to 5, wherein the device manages the physical storage address of each storage object; for a storage object requiring a plurality of flash blocks, if the Nth flash block is required, relevant data is distributed in a combined chip different from the first N-1 flash blocks, wherein N is a nature of 2 or more.

7. An operating method for a storage object, the operating method being performed by the storage device according to claims 3 and 6, the operating method comprising,

the main combined chip manages the physical storage address of each storage object;

the host sends an input/output request to the main combined chip;

for the output request of the storage object, the main combination chip determines the combination chip for storing the relevant data through a management system of the main combination chip for the physical storage address of the storage object, informs the relevant combination chip to finish the output work through a control network, and if the storage object is the storage object which is distributed and stored, the main combination chip arranges and processes the data in parallel through the control network;

for the input request of the storage object, the main combined chip determines the combined chip which is to receive the input data through the management system of the physical storage address of the storage object, if the storage object needs to carry out distribution pattern storage, a group of combined chips is determined, the address of at least one combined chip is sent to the host, and the host carries out data input operation by using the received address.

8. A method of operating on a storage object, the method being performed by the storage device of claim 4, 5 or 6, the method comprising,

the second bridge chip is responsible for managing the physical memory address of each memory object;

the second bridge chip receives the instruction of the host computer about the memory object, through its management system to the physical memory address of the memory object, determine the combined chip responsible for processing, if the memory object is distributed and stored, determine a group of combined chips responsible for processing;

for the output request of the storage object, informing the related at least one combined chip to complete the output work; for incoming requests to store objects, the received data is forwarded to at least one associated combinatorial chip.

Technical Field

The embodiment of the invention relates to the technical field of storage, in particular to a combined chip, a storage device and a data processing method.

Background

Solid State Drives (SSDs) composed of NAND flash memories are the main storage devices of modern computers, cloud data centers and terminal devices. NAND flash is a monolithic read-write memory device with the smallest readable unit called page, the smallest erasable unit called block, a flash block often consisting of many flash pages, a typical size of a flash page being 16kB, and a typical size of a block being 4-8 MB. The pages inside the flash block after erase can be subjected to separate write operations.

As shown in fig. 1, at the software level, the architecture of file storage in cell phones and computers is generally as follows: the application software sends file opening, closing, reading and writing instructions to an operating system; the file system is an important part in operating system software and is responsible for solving the storage problem of files. It divides the file into individual memory blocks, typically each memory block corresponding to a NAND flash page. The file system part converts the instruction of reading and writing files into the instruction of reading and writing storage blocks.

The Solid State Disk (SSD) consists of a group of NAND chips for storing data and a main control chip, and a group of memory chips is also needed in most cases. Hardware interface technologies such as USF, SATA, PICe and the like are used between the solid state disk SSD and the host, an NVMe instruction protocol is also arranged on a PCIe interface, the solid state disk SSD receives a read-write instruction from the host according to a storage block address, and the solid state disk SSD has no intelligence and no information of stored contents.

However, the address received by the solid state disk SSD is only a logical address. The method is responsible for managing the flash memory, optimizing caching, writing balance and the like, converting a logic address into a physical storage address in the process, and then sending instructions such as page reading, block writing and the like to the NAND flash memory chip by using the physical storage address. Due to the complexity of flash operations, the same block of content often needs to be replaced to a different physical memory address after being modified. The translation of logical/physical memory addresses is known in the art as the FTL layer. This translation requires maintaining a large address lookup table, typically stored in DRAM.

The NAND flash memory driving and management software receives the instruction of reading and writing the memory block area, optimizes the cache, the writing balance and the like, and sends the instruction of reading pages, writing blocks and the like to the chip; in a computer, NAND flash read-write software is typically run on a solid state hard disk controller.

In addition, with the development of cloud computing and cloud storage, the file system has been gradually replaced by an object storage system. Objects have a wider scope and greater flexibility than files. A storage object comprises data and metadata, the metadata can have flexible content and format, unlike the metadata with fixed format like a file, the storage object does not need to be searched by the directory of the file.

The host of the modern storage technology uses a logical address read-write and a Solid State Disk (SSD) to perform logical physical storage address conversion, and the reason for the formation of the SSD is that the NAND flash memory has a complex operation mode and also has the requirement of being compatible with an old system. But entering the big data era, the architecture has increasingly hindered the development of storage technology. It has a number of problems.

Disclosure of Invention

The embodiment of the invention aims to provide a combined chip, a storage device and a storage method, which can share a part of big data processing work, solve the problem that a central processing unit cannot keep up with the storage expansion, realize the calculation close to storage and greatly reduce the power consumption.

In a first aspect, an embodiment of the present invention provides the storage processing chip, which includes a central processing unit and a data processor, where the central processing unit is configured to run storage management, flash memory management, and data processing software, the data processor is configured to perform hardware acceleration on common data processing operations, and the storage processing chip is connected to a host through a host interface provided on the storage processing chip;

the storage processing chip and the flash memory chip are packaged and integrally formed into the combined chip, and the storage processing chip and the flash memory chip are in communication connection through a flash memory interface.

Compared with the prior art, the combined chip provided by the embodiment of the application comprises the central processing unit and the data processor, the central processing unit in the storage processor and the special data processor are used for processing big data, the cost-efficiency ratio is higher than that of the Central Processing Unit (CPU) at the host end, the power consumption is saved, the storage processing chip and the flash memory chip are packaged together, the distance between data processing and storage is shortened to the maximum extent, and the power consumption of data transfer is saved.

In a second aspect, an embodiment of the present application further provides a storage device, where the storage device includes the combined chip provided in the first aspect, and storage processing chips in a plurality of the combined chips are connected to each other through a control network for coordinating data storage and processing.

Compared with the prior art, the storage device provided by the embodiment of the application has the data processing capacity, the problem that the development of a central processing unit of a host cannot keep up with the increase of data in reality is solved, the power consumption is greatly reduced, and the performance is greatly improved.

As a preferred embodiment of the present application, all the combination chips of the storage device are connected to a host through a first bridge chip, the first bridge chip selects one of the combination chips in the storage device to be connected to the host through an address requested by the host, one of the combination chips in the storage device is a master combination chip, requests of all the hosts are first sent to the master combination chip, and then the master combination chip determines, through coordination of a control network, one or more other combination chips to complete requests of the host according to the request type of the host.

As a preferred embodiment of the present application, all the combined chips of the storage device are connected to the host through a second bridge chip, and the second bridge chip is responsible for processing all the requests from the host and communicating with each combined chip to coordinate to complete the requests of the host.

As a preferred embodiment of the present application, the method is implemented by the above storage device, and the method includes that the device manages physical storage addresses of all storage objects in the flash memory, and stores the storage objects with capacity exceeding a set limit by using all flash memory chips in the entire storage device; for a storage object requiring a plurality of flash memory blocks, if the Nth flash memory block is required, the second bridge chip distributes relevant data in a combined chip different from the first N-1 flash memory blocks, wherein N is a natural number which is more than or equal to 2.

In a third aspect, an embodiment of the present application provides an operating method for a storage object, where the operating method is performed by the storage device as described above, the operating method includes,

the main combined chip manages the physical storage address of each storage object;

the host sends an input/output request to the main combined chip;

for the output request of the storage object, the main combined chip determines the combined chip for storing the relevant data through the management system of the physical storage address of the storage object, informs the relevant combined chip to finish the output work through the control network, and if the storage object is the storage object which is stored in a distributed mode, the main combined chip arranges and processes the data in parallel through the control network.

For the input request of the storage object, the main combined chip determines the combined chip which is to receive the input data through the management system of the physical storage address of the storage object, if the storage object needs to carry out distribution pattern storage, a group of combined chips is determined, the address of at least one combined chip is sent to the host, and the host carries out data input operation by using the received address.

In a fourth aspect, the present application provides an operating method for a storage object, which is performed by the storage device as described above, the operating method including,

the second bridge chip is responsible for managing the physical memory address of each memory object;

the second bridge chip receives the instruction of the host computer about the memory object, and determines the combined chip responsible for processing through the management system of the physical memory address of the memory object, and determines a group of combined chips responsible for processing if the memory object is distributed and stored.

For the output request of the storage object, informing the related at least one combined chip to complete the output work; for incoming requests to store objects, the received data is forwarded to at least one associated combinatorial chip.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described, by way of example, with reference to the following drawings, in which:

FIG. 1 shows a schematic diagram of a storage system architecture according to the prior art;

FIG. 2 is a schematic structural diagram of a combined chip according to an embodiment of the invention;

FIG. 3 is a schematic structural diagram of a memory device according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a memory device according to an embodiment of the present invention;

FIG. 5 is a flow chart illustrating a method of operating on a memory object according to an embodiment of the invention;

FIG. 6 is a schematic structural diagram of a memory device according to an embodiment of the present invention;

FIG. 7 is a flowchart illustrating a method for operating a storage object according to an embodiment of the present invention.

Detailed Description

In order to make the above and other features and advantages of the present invention more apparent, the present invention is further described below with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limiting, for those of ordinary skill in the art.

In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not a whole embodiment. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 2 shows a schematic structural diagram of a combined chip provided in an embodiment of the present application.

The embodiment of the application provides a combined chip, wherein the combined chip 2 comprises a storage processing chip 21 and a flash memory chip group 22;

the memory processing chip 21 includes a central processing unit and a data processing unit, the central processing unit is in communication connection with the data processing unit, the central processing unit is used for running memory management, flash memory management and data processing software, and the data processing unit is used for performing hardware acceleration on common data processing operations, including but not limited to retrieval, feature comparison, artificial intelligence Inference (AI Inference) and the like.

The utility model provides a combination chip utilizes dedicated data processor to handle big data, it is more than having the cost-effectiveness ratio with central processing unit, more save the consumption, data processor can be for can sharing some big data processing work, the reality problem that host computer central processing unit can not keep up with the storage expansion has been solved, data processor silicon chip links to each other with one or more flash memory chips, encapsulate in a combination chip, draw close to the distance of data processing and storage to the utmost, the consumption of data transfer has been saved, in this application embodiment, the flash memory chip is the NAND chip.

As shown in fig. 3, an embodiment of the present application provides a storage device, where the storage device 3 includes at least one combined chip described above, and this embodiment only shows that the storage device includes only one combined chip, where the storage processing chip 31 in the combined chip includes a central processing unit 311 and a data processing unit 312, and the central processing unit 311 and the data processing unit 312 are respectively used to process data stored in a flash memory chip; meanwhile, the storage device further comprises a host interface 314 for connecting a host, the host interface 314 is a DRAM interface for adding a DRAM in the combined chip to support more complex data calculation, and the storage processing chip uses a standard hardware interface of the storage device and the host such as: PCIe, USF, DDR, CXI, flash interface 316 is used to interface with a flash chip, and memory MRAM may be embedded in memory processing chip 31.

The storage chip that this application embodiment provided utilizes dedicated data processor to handle big data, it is more than having the cost-effectiveness with central processing unit to compare, more save the consumption, data processor can be for can sharing some big data processing work, the reality problem that host computer central processing unit can not keep up with the storage expansion has been solved, data processor silicon chip links to each other with one or more flash memory chips, the encapsulation is in a combination chip, draw close to the distance of data processing and storage to the utmost, the consumption of data transfer has been saved.

Based on the above, the following describes various embodiments of the present invention:

example 1

As shown in fig. 4, the embodiment of the present application provides a storage device, where the storage device 4 includes at least one combined chip 41 as described above, and storage processing chips 412 in a plurality of the combined chips 41 are connected to each other through a dedicated control network 42 for coordinating data storage and processing, and the storage device is provided with a host 44 interface for connecting with a host 44.

In the embodiment of the present application, a bridge connection manner is provided, which can solve the coordination problem of multiple combined chips, where the storage device is connected to a host 44 through a first bridge chip 43, the first bridge chip 43 selects one combined chip 41 in the storage device to be connected to the host 44 through an address requested by the host, one of the combined chips is a main combined chip, requests of all hosts are first sent to the main combined chip, and the main combined chip determines, through network coordination, that one or more other combined chips complete requests of the host 44 according to the request type of the host 44.

The storage device comprises N combined chips, wherein a main combined chip manages the physical storage address of each storage object; for a large-capacity object requiring a plurality of flash memory blocks, if the 2 nd flash memory block is required, distributing the flash memory block in a combined chip different from the 1 st flash memory block; if the 3 rd flash memory block is needed, the flash memory block is distributed in a combined chip different from the first two flash memory blocks, and by analogy, if the Nth flash memory block is needed, the flash memory block is distributed in a combined chip different from the first N-1 flash memory blocks, if more flash memory blocks are needed, the process is circulated, the embodiment of the application can not control a physical storage address unlike the traditional storage system, the embodiment of the application can directly control the physical storage address, large files can be uniformly distributed and stored in each channel, the advantage of parallel processing is furthest exerted, and the storage device provided by the embodiment of the application has data processing capacity, so that the problem that the development of a real central processing unit cannot keep pace with the increase of data is solved.

The storage chip that this application embodiment provided utilizes dedicated data processor to handle big data, it is more than having the cost-effectiveness with central processing unit to compare, more save the consumption, data processor can be for can sharing some big data processing work, the reality problem that host computer central processing unit can not keep up with the storage expansion has been solved, data processor silicon chip links to each other with one or more flash memory chips, the encapsulation is in a combination chip, draw close to the distance of data processing and storage to the utmost, the consumption of data transfer has been saved.

As shown in fig. 5, a method for operating a storage object by the storage device shown in fig. 4 includes:

step S51, the main combined chip manages the physical memory address of each memory object;

step S52, the host sends the input/output request to the main combined chip;

step S53, for the output request of the storage object, the main combination chip determines the combination chip storing the related data through its management system for the physical storage address of the storage object, and informs the related combination chip to complete the output work through the control network, if the storage object is the storage object stored in distributed manner, the main combination chip arranges and processes in parallel through the control network.

Step S54, for the input request of the storage object, the main combination chip determines the combination chip to receive the input data through its management system for the physical storage address of the storage object, if the storage object needs to perform distribution pattern storage, determines a group of combination chips, and sends the physical storage address of at least one combination chip to the host, and the host performs data input operation by using the received physical storage address.

Example 2

As shown in fig. 6, the storage device includes a second bridge chip 63 connected to the host, where the second bridge chip 63 is an intelligent bridge chip and is responsible for processing all host requests and connecting with each combination chip to coordinate the host requests. It should be noted that the second bridge chip and the data exchange channels of the respective combination chips also serve as the control network.

It should be noted that another bridging manner is provided, which can solve the coordination problem of the multiple combined chips 61, the second bridging chip 63 is responsible for managing the physical memory address of each memory object in the flash memory, the information of the memory address can be stored in the dynamic random access memory 65, the second bridging chip 64 receives all the instructions of the host 64 about the memory object, determines the data memory processor 612 responsible for processing according to the memory address information of the memory object, and forwards the instructions to the relevant data processor 612, if the object is a large-capacity object that is distributed and stored, the second bridging chip 63 schedules parallel processing through the control network.

In the embodiment of the present application, the storage device in the embodiment of the present application includes N combined chips, a system directly grasps a physical storage address of each storage object, and stores a large-capacity storage object whose capacity exceeds a set limit by using a whole flash memory block; for a large-capacity object requiring a plurality of flash memory blocks, if the 2 nd flash memory block is required, distributing the flash memory block in a combined chip different from the 1 st flash memory block; if the 3 rd flash memory block is needed, the flash memory block is distributed in a combined chip different from the first two flash memory blocks, and by analogy, if the Nth flash memory block is needed, the flash memory block is distributed in a combined chip different from the first N-1 flash memory blocks, if more flash memory blocks are needed, the process is circulated, the embodiment of the application can not control a physical storage address unlike the traditional storage system, the embodiment of the application can directly control the physical storage address, large files can be uniformly distributed and stored in each channel, the advantage of parallel processing is furthest exerted, and the storage device provided by the embodiment of the application has data processing capacity, so that the problem that the development of a real central processing unit cannot keep pace with the increase of data is solved.

The storage chip that this application embodiment provided utilizes dedicated data processor to handle big data, it is more than having the cost-effectiveness with central processing unit to compare, more save the consumption, data processor can be for can sharing some big data processing work, the reality problem that host computer central processing unit can not keep up with the storage expansion has been solved, data processor silicon chip links to each other with one or more flash memory chips, the encapsulation is in a combination chip, draw close to the distance of data processing and storage to the utmost, the consumption of data transfer has been saved.

As shown in fig. 7, a method for operating a storage object by the storage device shown in fig. 6 includes:

step S71, the second bridge chip is responsible for managing the physical memory address of each memory object;

in step S72, the second bridge chip receives the command from the host regarding the memory object, and determines the combined chip responsible for processing through its management system for the physical memory address of the memory object, and determines a group of combined chips responsible for processing if the memory object is stored in a distributed manner.

Step S73, for the output request of the storage object, informing the relevant at least one combined chip to complete the output work; for incoming requests to store objects, the received data is forwarded to at least one associated combinatorial chip.

The features of the above embodiments may be arbitrarily combined, and for the sake of brevity, all possible combinations of the features in the above embodiments are not described, but should be construed as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the features.

While the invention has been described in connection with the embodiments, it is to be understood by those skilled in the art that the foregoing description and drawings are merely illustrative and not restrictive of the broad invention, and that this invention not be limited to the disclosed embodiments. Various modifications and variations are possible without departing from the spirit of the invention.