阅读说明：本技术 一种ssd主控中多端口低延迟访问的sram群组的控制方法 (Control method of multi-port low-delay access SRAM group in SSD master control ) 是由 付溢华 于 2021-09-08 设计创作，主要内容包括：本发明公开一种SSD主控中多端口低延迟访问的SRAM群组的控制方法,本方法在一个具有多端口的SSD主控中将SRAM划分为多组,每组均配置一个仲裁器以及一个群组控制器,仲裁器实现对每一端口访问地址的映射,同时分配哪一端口能够访问该组中的SRAM或者控制各端口以何种顺序访问该组SRAM。本方法设置非连续地址空间的映射,即连续的逻辑地址对应的SRAM物理地址不连续,当端口进行大数据量的连续地址读写时,访问路径依次被映射在不同组的SRAM中。本方法有效解决单端口长时间占用存储空间问题以及在较少资源消耗下多端口并行访问SRAM群组的问题,实现了端口占用和高效并行访问问题之间的权衡。(The invention discloses a control method of a multiport low-delay accessed SRAM group in SSD master control, which divides the SRAM into a plurality of groups in the SSD master control with a plurality of ports, each group is provided with an arbiter and a group controller, the arbiter realizes the mapping of access addresses of each port, and simultaneously allocates which port can access the SRAM in the group or controls the sequence of accessing the SRAM in the group by each port. The method sets mapping of discontinuous address space, namely SRAM physical addresses corresponding to continuous logical addresses are discontinuous, and when ports carry out continuous address reading and writing with large data volume, access paths are mapped in different groups of SRAM in sequence. The method effectively solves the problems that a single port occupies a storage space for a long time and a plurality of ports access the SRAM group in parallel under the condition of less resource consumption, and realizes the balance between the port occupation and the efficient parallel access.)

1. A control method of an SRAM group with multi-port low-delay access in SSD master control is characterized in that: the method divides SRAM into a plurality of groups in an SSD master control with a plurality of ports, each group is provided with an arbiter and a group controller, the arbiter realizes mapping of access addresses of each port, and simultaneously allocates which port can access the SRAM in the group or controls the sequence of the ports to access the group of SRAM; because of being managed by the arbitrator, all the SRAMs in the same group are only accessed by a unique port at the same time, and because each group of the SRAMs has the respective arbitrator, each group of the SRAMs are independent from each other and can be accessed by different ports at the same time in parallel;

the method sets mapping of a discontinuous address space, namely SRAM physical addresses corresponding to continuous logical addresses are discontinuous, when ports perform continuous address reading and writing of large data volume, access paths are mapped in different groups of SRAM in sequence, even if a certain port performs long-time data access, reading and writing of other ports cannot be hindered for a long time, and therefore reading and writing speed is improved.

2. The method of claim 1 for controlling the multi-port low-latency access SRAM group in the SSD master, comprising: the arbiter of each group of SRAMs is connected to all or part of the ports of the group controller.

3. The method of claim 2, wherein the method comprises the steps of: the arbiter manages access to the different ports, including priority and access order of the ports.

4. The method of claim 1 for controlling the multi-port low-latency access SRAM group in the SSD master, comprising: the group controller is connected between the arbiter and the plurality of SRAMs in the group, and realizes management of the SRAMs in the group, including allocation of SRAM physical addresses, timing control of each access and processing of access data.

5. The method of claim 4, wherein the method comprises the steps of: the group controller's allocation of SRAM physical addresses includes accessing a sequential mapping of logical addresses to SRAM physical addresses and accessing a non-sequential mapping of logical addresses to SRAM physical addresses.

6. The method of claim 4, wherein the method comprises the steps of: timing control of the accesses by the group controller includes real-time access and delayed access.

7. The method of claim 4, wherein the method comprises the steps of: the group controller processes the access data, including that the data is directly read from or directly written into the SRAM, the access data is written into the SRAM after certain logic calculation or read out of the group controller, and the access data and original data in the SRAM are subjected to certain logic calculation during write access to obtain new data and are written into the SRAM.

8. The method of claim 4, wherein the method comprises the steps of: the non-sequential mapping relationship between the external logical address and the SRAM physical address is represented as: for a set of consecutive external logical addresses A0-AN, A0-AN 1 is mappedTo the physical address corresponding to the group controller USRAMx, A (n1+1) -An 2 is mapped to the physical address corresponding to the group controller USRAMx，，，，And M are natural integer sets, wherein M is the total number of the group controllers, and when a section of continuous external logical addresses are mapped to the same group controller, the section of addresses are defined as a same group of continuous spaces which correspond to SRAM physical addresses which are continuously or discontinuously arranged.

9. The method of claim 8, wherein the method comprises the steps of: the same set of contiguous spaces maps to the same SRAM or different SRAMs within the same group.

10. The method of claim 8, wherein the method comprises the steps of: when the external logical address spans a plurality of same group continuous spaces, the corresponding SRAM physical address is positioned in a plurality of group controllers.

Technical Field

The invention relates to the field of storage, in particular to a control method of an SRAM group with multi-port low-delay access in SSD master control.

Background

A Static Random-Access Memory (SRAM) is a volatile Memory, and has the characteristics of Static state and high speed, and because of its low integration level and its high cost, the SRAM is currently more suitable for the fields of cache Memory and the like.

In order to meet the storage and access requirements of a certain data volume, a Solid State Disk (SSD) often adopts a form of combining a plurality of SRAMs to realize a storage capacity with a larger depth. At this point, the SRAM controller is then designed to store the assignment of addresses, thereby corresponding the access of data to the SRAM physical address. When a single master accesses the SRAM group, the SRAM controller can realize the data transmission only by acquiring the address and read/write data accessed by the master. However, in the SSD, the storage area formed by the SRAM group often requires multiple interfaces to access in parallel, so as to improve the performance. At this time, it is required that there is no overlap in the address spaces accessed by each interface at the same time to prevent the access data from being overwritten or garbled. Therefore, the conversion of the access address can not be achieved in the SRAM controller.

When the SRAM controller has a plurality of master ports, the access paths and the access sequence of each interface need to be allocated by configuring the SRAM with an arbiter, thereby ensuring that the same address can be accessed by only one interface. What number of arbiters to configure for an SRAM group is a question to be explored: if all the SRAMs share the same arbiter, when a plurality of ports access to non-overlapped address ranges, the arbiter is only allocated to one port for use, so that the access speed is sharply reduced; if the arbiter is configured for each SRAM in the group, once the number of SRAMs is too large, a large number of arbiters will cause space occupation and resource waste.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a control method for accessing an SRAM group by multiple ports in SSD master control, which carries out grouping management on SRAM according to a certain rule, effectively solves the problems that a single port occupies a storage space for a long time and multiple ports access the SRAM group in parallel under less resource consumption, and realizes the balance between port occupation and efficient parallel access.

In order to solve the technical problem, the technical scheme adopted by the invention is as follows: a control method of an SRAM group with multi-port low-delay access in SSD master control is characterized in that: the method divides SRAM into a plurality of groups in an SSD master control with a plurality of ports, each group is provided with an arbiter and a group controller, the arbiter realizes mapping of access addresses of each port, and simultaneously allocates which port can access the SRAM in the group or controls the sequence of the ports to access the group of SRAM; because of being managed by the arbitrator, all the SRAMs in the same group are only accessed by a unique port at the same time, and because each group of the SRAMs has the respective arbitrator, each group of the SRAMs are independent from each other and can be accessed by different ports at the same time in parallel;

the method sets mapping of a discontinuous address space, namely SRAM physical addresses corresponding to continuous logical addresses are discontinuous, when ports perform continuous address reading and writing of large data volume, access paths are mapped in different groups of SRAM in sequence, even if a certain port performs long-time data access, reading and writing of other ports cannot be hindered for a long time, and therefore reading and writing speed is improved.

Further, the arbiter of each group of SRAMs is connected to all or a part of the ports of the group controller.

Further, the arbiter manages access to the different ports, including priority and access order of the ports.

Further, the group controller is connected between the arbiter and the plurality of SRAMs in the group, and implements management of the SRAMs in the group, including allocation of SRAM physical addresses, timing control of each access, and processing of access data.

Further, the allocation of the SRAM physical addresses by the group controller includes accessing a sequential mapping of the logical addresses to the SRAM physical addresses and accessing a non-sequential mapping of the logical addresses to the SRAM physical addresses.

Further, the timing control of the accesses by the group controller includes real-time access and delayed access.

Further, the processing of the access data by the group controller includes directly reading out the data from the SRAM or directly writing the data into the SRAM, writing the access data into the SRAM after certain logic calculation or reading out the access data to the outside of the group controller, and performing certain logic calculation on the access data and original data in the SRAM during write access to obtain new data and writing the new data into the SRAM.

Further, the non-sequential mapping relationship between the external logical address and the physical address of the SRAM is represented as: for a set of consecutive external logical addresses A0-AN, A0-AN 1 is mapped to the physical address corresponding to the group controller USRAMxA (n1+1) -An 2 is mapped to the physical address of the group controller USRAMx', wherein，，，，And M are natural integer sets, wherein M is the total number of the group controllers, and when a section of continuous external logical addresses are mapped to the same group controller, the section of addresses are defined as a same group of continuous spaces which correspond to SRAM physical addresses which are continuously or discontinuously arranged.

Further, the same set of consecutive spaces are mapped to the same SRAM or different SRAMs within the same group.

Furthermore, when the external logical address spans a plurality of same group continuous spaces, the corresponding SRAM physical address is positioned in a plurality of group controllers.

The invention has the beneficial effects that: in the traditional technical scheme, an SRAM controller arranges SRAM in sequence and adopts continuous external logic addresses to sequentially access SRAM physical addresses, and the mode can only realize access of a single port and greatly limits the access transmission speed of data.

By the method described in the patent, the physical address space is accessed by multiple ports to realize parallel data transmission, and the access speed is greatly improved. Based on a multi-port structure, the SRAM is divided into a plurality of groups for different ports to access different physical addresses at the same time. Meanwhile, in order to avoid long-time occupation of a certain port on the same group, the access performance of each port is balanced by adopting a mode of non-continuous mapping of an external logic address and an SRAM physical address, and the access efficiency of the SRAM is further improved.

Drawings

FIG. 1 is a schematic diagram of SRAM packet management and non-sequential address mapping.

Detailed Description

The invention is further described with reference to the following figures and specific embodiments.

Example 1

The embodiment discloses a control method for accessing an SRAM group by multiple ports in an SSD in a low-delay manner. Meanwhile, in order to reduce the long-time occupation of a certain storage space by the port to a greater extent, a management mode of non-continuous address mapping is adopted.

In an SRAM controller having multiple ports, the SRAM is divided into multiple groups, each of which is provided with an arbiter. At this time, all SRAMs in the same group can be accessed by only one port at the same time, managed by the arbiter. The arbiter can map the access addresses of each port while assigning which port can access the SRAM in the group or controlling the order in which the ports access the group of SRAMs. Because each group of SRAM is provided with a respective arbiter, each group of SRAM is independent from each other and can be accessed by different ports in parallel at the same time.

An important role of the SRAM controller is the mapping of the accessed logical address and the SRAM physical address, i.e. the port logical address is often not identical to the SRAM physical address, but the SRAM controller is required to map the two, so as to determine the position in the SRAM to be accessed. Each port is usually oriented to a continuous space of a series of addresses when accessing a large amount of data, and the SRAM physical addresses are also arranged in sequence in general. Therefore, when a port accesses a large amount of data at consecutive addresses, there is still a case where a certain set of SRAMs are occupied for a long time.

Therefore, the invention sets mapping of non-continuous address space, namely, SRAM physical address corresponding to continuous logical address is not continuous. When the port carries out continuous address reading and writing with large data volume, the access paths are respectively mapped in different groups of SRAM in sequence. Therefore, even if a certain port performs long-time data access, the read-write of other ports still cannot be blocked for a long time, and the read-write speed is improved.

FIG. 1 is a schematic block diagram of the present embodiment, in which an SRAM controller can implement the grouping management and non-sequential address mapping of an SRAM; the SRAM controller comprises a port M for communicating with external equipment, an arbiter Arb and a group controller USRAM, wherein a series of SRAMs (k) are controlled by M USRAMs, and each USRAM controls n SRAMs. Wherein the content of the first and second substances,，，。

secondly, each USRAM is configured with a separate arbiter Arb, each arbiter being connectable to a controller port M. The arbitrator can be connected with all ports of the controller or part of the ports.

Thirdly, the arbiter receives the access information of each connected port, and maps the access path to the corresponding USRAM, so as to realize the allocation of the access of each port and the storage space of the module.

Fourth, the arbiter can manage access to the different ports, including but not limited to priority and access order of the ports.

Fifth, the group controller USRAM enables control of the corresponding n SRAMs, including but not limited to allocation of SRAM physical addresses, timing control of each access, and processing of access data.

Sixth, when the group controller USRAM allocates the SRAM physical address, the access logical address input by the group controller may be mapped sequentially with the SRAM physical address, or may be mapped non-sequentially.

Seventh, when the group controller USRAM performs timing control on the access of its input, it can simultaneously implement the access of the SRAM and also perform the delayed access.

Eighth, the processing method of the group controller USRAM for the access data includes, but is not limited to, directly reading data from the SRAM or directly writing data into the SRAM, performing certain logic calculation on the access data and then writing the access data into the SRAM or reading the access data out of the group controller, performing certain logic calculation on the access data and original data in the SRAM during write access to obtain new data and writing the new data into the SRAM, and the like.

Ninth, the SRAM controller may map the external logical address received by the port with the SRAM physical address non-contiguously, i.e., the difference between the external logical address and the SRAM physical address is a non-fixed value.

Tenth, the non-sequential mapping relationship between the external logical addresses and the SRAM physical addresses is expressed in that, for a set of consecutive external logical addresses A0-AN, A0-AN 1 is mapped to the physical address corresponding to the group controller USRAMx, and A (n1+1) -AN 2 is mapped to the physical address corresponding to the group controller USRAMx，，，，M and M are natural integer sets.

Eleventh, when a segment of consecutive external logical addresses are all mapped to the same group controller, the segment of addresses are defined as the same set of consecutive spaces.

Twelfth, the physical addresses of the SRAMs corresponding to the same group of continuous spaces may be arranged continuously or discontinuously.

Thirteenth, mapping to multiple same group continuous spaces of the same group controller, their corresponding SRAM physical addresses may be arranged continuously or discontinuously; may map to the same SRAM within the group controller or may map to a different SRAM within the group controller.

Fourteenth, when the external logical address spans multiple same set of consecutive spaces, the corresponding SRAM physical address is located in multiple group controllers.

The foregoing description is only for the basic principle and the preferred embodiments of the present invention, and modifications and substitutions by those skilled in the art are included in the scope of the present invention.