阅读说明：本技术 用于执行纠错操作和错误校验操作的电子器件 (Electronic device for performing error correction operations and error checking operations ) 是由 崔善明 于 2020-10-13 设计创作，主要内容包括：一种电子器件包括复制延迟电路,其被配置成通过使包括第一存储区域中存储的第一数据的错误信息的第一错误校验信号延迟来生成延迟错误校验信号。该电子器件还包括错误和信号生成电路,其被配置成通过对包括第二存储区域中存储的第二数据的错误信息的第二错误校验信号和延迟错误校验信号求和来生成错误和信号。(An electronic device includes a replica delay circuit configured to generate a delayed error check signal by delaying a first error check signal including error information of first data stored in a first storage area. The electronic device further includes an error sum signal generation circuit configured to generate an error sum signal by summing a second error check signal including error information of second data stored in the second storage area and the delayed error check signal.)

1. An electronic device, comprising:

a replica delay circuit configured to generate a delayed error check signal by delaying a first error check signal including error information of first data stored in a first storage region; and

an error sum signal generation circuit configured to generate an error sum signal by summing a second error check signal and the delayed error check signal, the second error check signal including error information of the second data stored in the second storage area.

2. The electronic device of claim 1, wherein a delay amount of the replica delay circuit is set to compensate for a difference between a delay amount of transmitting the first error check signal and a delay amount of transmitting the second error check signal.

3. The electronic device of claim 1, wherein:

the first error check signal is generated by a first error correction circuit disposed adjacent to the first storage region; and

the second error check signal is generated by a second error correction circuit disposed adjacent to the second storage region.

4. The electronic device of claim 3, wherein a first distance between the first error correction circuit and the error and signal generation circuit is physically shorter than a second distance between the second error correction circuit and the error and signal generation circuit.

5. The electronic device according to claim 1, wherein the error sum signal is disabled when a number of occurrences of an error in each of the first data and the second data is equal to or greater than a predetermined number.

6. The electronic device of claim 1, further comprising:

a first error correction circuit configured to: generating the first error check signal enabled when an error occurs in the first data, correcting the error in the first data, and storing the error-corrected first data in the first storage area;

a second error correction circuit configured to: generating the second error check signal enabled when an error occurs in the second data, correcting the error in the second data, and storing the error-corrected second data in the second storage area; and

a redundancy check circuit configured to generate a flag signal that is enabled when either of the first error check signal and the second error check signal is generated at least a predetermined number of times.

7. The electronic device of claim 1, wherein the error sum signal generating circuit comprises:

a summing circuit configured to generate a sum signal by summing the second error check signal and the delayed error check signal;

a pulse signal generation circuit configured to generate a pulse signal including pulses generated from a flag signal and the sum signal in synchronization with an internal clock; and

a pulse width control circuit configured to generate the error sum signal by controlling a pulse width of the pulse signal in synchronization with the internal clock.

8. An electronic device, comprising:

a first error correction circuit configured to: generating a first error check signal enabled when an error occurs in first data stored in a first storage region, correcting the error in the first data, and storing the error-corrected first data in the first storage region;

a second error correction circuit configured to: generating a second error check signal enabled when an error occurs in second data stored in a second storage area, correcting the error in the second data, and storing the error-corrected second data in the second storage area;

a replica delay circuit configured to generate a delayed error check signal by delaying the first error check signal; and

an error sum signal generation circuit configured to generate an error sum signal by summing the second error check signal and the delayed error check signal.

9. The electronic device as set forth in claim 8,

wherein the first data and the second data are sequentially input from outside the electronic device in a write operation, an

Wherein the second error correction circuit generates the second error check signal for the second data after the first error check signal for the first data is generated.

10. The electronic device according to claim 8, wherein the replica delay circuit is set with a delay amount for compensating a timing difference between a timing of generating the first error check signal and a timing of generating the second error check signal.

11. The electronic device according to claim 8, wherein the error sum signal is disabled when a number of occurrences of an error in each of the first data and the second data is equal to or greater than a predetermined number.

12. The electronic device of claim 8, wherein the error sum signal generating circuit comprises:

a summing circuit configured to generate a sum signal by summing the second error check signal and the delayed error check signal;

a pulse signal generation circuit configured to generate a pulse signal including a pulse generated by latching a flag signal in synchronization with an internal clock; and

a pulse width control circuit configured to generate the error sum signal by controlling a pulse width of the pulse signal in synchronization with the internal clock.

13. An electronic device, comprising:

a controller configured to: outputting a clock and a command address, sequentially outputting first to fourth data, and receiving an error sum signal; and

a semiconductor module including first to fourth memory devices, the semiconductor module configured to: outputting the error sum signal by compensating for a difference in delay amounts between first to fourth error check signals including error information for the first to fourth data in a write operation according to the clock and the command address.

14. The electronic device according to claim 13, wherein the error sum signal is disabled when a number of occurrences of an error in each of the first data to the fourth data is equal to or greater than a predetermined number.

15. The electronic device of claim 13, wherein the semiconductor module further comprises an error sum signal generation circuit configured to: compensating for a difference in delay amount between the first to fourth error-checking signals, and generating the error sum signal by summing the first to fourth error-checking signals for which the difference in delay amount is compensated.

16. The electronic device of claim 15, wherein:

the first memory device has a first distance from the error sum signal generating circuit;

the second memory device has a second distance from the error sum signal generating circuit;

the third memory device has a third distance from the error sum signal generating circuit; and

the fourth memory device has a fourth distance from the error sum signal generating circuit.

17. The electronic device of claim 16, wherein:

the fourth distance is physically longer than the third distance;

the third distance is physically longer than the second distance; and

the second distance is physically longer than the first distance.

18. The electronic device as set forth in claim 13,

wherein the first memory device corrects errors in the first data and stores the error-corrected first data, and generates the first error check signal that is enabled when an error occurs in the first data,

wherein the second memory device corrects errors in the second data and stores the error-corrected second data, and generates the second error check signal that is enabled when an error occurs in the second data,

wherein the third memory device corrects errors in the third data and stores the error-corrected third data, and generates the third error check signal that is enabled when an error occurs in the third data, an

Wherein the fourth memory device corrects errors in the fourth data and stores the error-corrected fourth data, and generates the fourth error check signal that is enabled when an error occurs in the fourth data.

19. The electronic device of claim 13, wherein the error sum signal generating circuit comprises:

a redundancy check circuit configured to generate a flag signal that is enabled when any one of the first to fourth error check signals is generated at least a predetermined number of times;

a replica delay circuit configured to generate first to fourth delayed error check signals by compensating for a difference in delay amount between the first to fourth error check signals;

a summing circuit configured to generate a sum signal by summing the first to fourth delayed error check signals;

a pulse generating circuit configured to generate a pulse signal including pulses generated from the flag signal and the sum signal in synchronization with the clock; and

a pulse width control circuit configured to generate the error sum signal by controlling a pulse width of the pulse signal in synchronization with the clock.

20. An electronic device, comprising:

a controller configured to: outputting a clock and a command address, and receiving first to fourth data and an error sum signal; and

a semiconductor module including first to fourth memory devices, the semiconductor module configured to: outputting the error sum signal by compensating for a difference in delay amounts between first to fourth error check signals including error information for the first to fourth data stored in the semiconductor module in a read operation according to the clock and the command address.

Technical Field

Embodiments of the present disclosure generally relate to an electronic device that corrects errors included in data and verifies errors included in data.

Background

In order to increase the operation speed of the device semiconductor device, a scheme of inputting/outputting a plurality of data every clock cycle is used. In the case where the input/output speed of data is increased, the probability of an error occurring during the data transfer process is also increased. Therefore, a discrete device and method for ensuring reliability of data transfer are additionally used.

A method of generating an error code capable of checking occurrence of an error every time data is transmitted and transmitting the error code together with the data is used, thereby ensuring reliability of data transmission. The error codes include Cyclic Redundancy Check (CRC) codes and Error Detection Codes (EDC) capable of detecting errors that have occurred, and Error Correction Codes (ECC) capable of correcting errors by themselves when errors have occurred.

Disclosure of Invention

Embodiments relate to an electronic device that compensates for a difference in delay amount and a time difference between error check signals including error information regarding data input to and output from memory areas located at different positions, and sums and outputs error check signals for which the difference in delay amount and the time difference are compensated.

In an embodiment, an electronic device may include: a replica delay circuit configured to generate a delayed error check signal by delaying a first error check signal including error information of the first data stored in the first storage area; and an error sum signal generation circuit configured to generate an error sum signal (error sum signal) by summing a second error check signal including error information of the second data stored in the second storage area and the delayed error check signal.

In an embodiment, an electronic device may include: a first error correction circuit configured to generate a first error check signal that is enabled in a case where an error occurs in the first data stored in the first storage region, correct the error of the first data, and store the error-corrected first data in the first storage region; a second error correction circuit configured to generate a second error check signal that is enabled in a case where an error occurs in the second data stored in the second storage area, correct the error of the second data, and store the error-corrected second data in the second storage area; a replica delay circuit configured to generate a delayed error check signal by delaying the first error check signal; and an error sum signal generating circuit configured to generate an error sum signal by summing the second error check signal and the delayed error check signal.

In an embodiment, an electronic device may include: a controller configured to output a clock and a command address, sequentially output first to fourth data, and receive an error sum signal; and a semiconductor module including the first to fourth memory devices, the semiconductor module configured to output an error sum signal by compensating for a difference in delay amount between first to fourth error check signals including error information of the first to fourth data in a write operation according to a clock and a command address.

In an embodiment, an electronic device may include: a controller configured to output a clock and a command address, and to receive first to fourth data and an error sum signal; and a semiconductor module including first to fourth memory devices, the semiconductor module configured to output an error sum signal by compensating a difference in delay amount between first to fourth error check signals including error information of first to fourth data stored therein in a read operation according to a clock and a command address.

According to an embodiment of the present disclosure, an electronic device may compensate for a difference in delay amount and a time difference between error check signals including error information about input to and output from memory areas located at different positions, and may sum and output the error check signals between which the difference in delay amount and the time difference are compensated, thereby ensuring reliability of an error check operation.

Further, according to an embodiment of the present disclosure, the electronic device may compensate for a difference in delay amount and a time difference between error check signals generated in a plurality of memory devices included in the semiconductor module, and may sum and output the error check signals, between which the difference in delay amount and the time difference are compensated, to the controller, thereby allowing the controller to detect the error check operation.

Drawings

Fig. 1 is a block diagram illustrating a configuration of an electronic device according to an embodiment of the present disclosure.

Fig. 2 is a block diagram showing a configuration of a semiconductor device included in the electronic device shown in fig. 1.

Fig. 3 is a diagram for assisting in explaining the operation of the internal clock generation circuit included in the semiconductor device shown in fig. 2.

Fig. 4 is a diagram illustrating a configuration of an error and signal generating circuit included in the semiconductor device illustrated in fig. 2.

Fig. 5 is a timing diagram that assists in explaining the operation of the electronic device according to this embodiment of the present disclosure.

Fig. 6 is a block diagram illustrating a configuration of an electronic device according to another embodiment of the present disclosure.

Fig. 7 is a block diagram showing a configuration of a first memory device included in the semiconductor module shown in fig. 6.

Fig. 8 is a block diagram showing a configuration of an error and signal generating circuit included in the semiconductor module shown in fig. 6.

Fig. 9 is a circuit diagram showing a configuration of a summing circuit included in the error sum signal generating circuit shown in fig. 8.

Fig. 10 is a diagram showing a configuration of a pulse generating circuit included in the error sum signal generating circuit shown in fig. 8.

Fig. 11 is a timing diagram that assists in explaining the operation of the electronic device according to this embodiment of the present disclosure.

Fig. 12 is a block diagram showing a configuration of an electronic system to which the electronic devices shown in fig. 1 to 11 are applied.

Detailed Description

The term "preset" means that the value of a parameter is predetermined when the parameter is used in a process or algorithm. Depending on the implementation, the values of the parameters may be set at the beginning of the process or algorithm or may be set during the period of time in which the process or algorithm is executed.

Terms such as "first" and "second" used to distinguish various components are not limited by these components. For example, a first element can be termed a second element, and, conversely, a second element can be termed a first element.

When an element is described as being "coupled" or "connected" to another element, it will be understood that the one element may be directly coupled or connected to the other element or coupled or connected to the other element through intervening elements. On the other hand, the descriptions "directly coupled" and "directly connected" should be understood to mean that one element is directly coupled and connected to another element without the intervention of another element.

"logic high level" and "logic low level" are used to describe the logic levels of a signal. A signal having a "logic high level" is distinguished from a signal having a "logic low level". For example, when the signal having the first voltage corresponds to a "logic high level", the signal having the second voltage may correspond to a "logic low level". According to an embodiment, a "logic high level" may be set to a voltage higher than a "logic low level". Meanwhile, according to an embodiment, the logic level of the signal may be set to a different logic level or an opposite logic level. For example, according to an embodiment, a signal having a logic high level may be set to have a logic low level, and a signal having a logic low level may be set to have a logic high level.

Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. These embodiments are merely illustrative of the present disclosure, and the scope of the present disclosure should not be limited by these embodiments.

As shown in fig. 1, an electronic device 100 according to an embodiment of the present disclosure may include a controller 110 and a semiconductor device 120. The semiconductor device 120 may include a first error correction circuit 250, a second error correction circuit 260, a replica delay circuit 280, and an error and signal generation circuit 290.

The controller 110 may include a first control pin 11, a second control pin 31, a third control pin 51, and a fourth control pin 71. The semiconductor device 120 may include a first semiconductor pin 21, a second semiconductor pin 41, a third semiconductor pin 61, and a fourth semiconductor pin 81. The first transfer line L11 may be coupled between the first control pin 11 and the first semiconductor pin 21. The second transfer line L31 may be coupled between the second control pin 31 and the second semiconductor pin 41. The third transfer line L51 may be coupled between the third control pin 51 and the third semiconductor pin 61. The fourth transfer line 71 may be coupled between the fourth control pin 71 and the fourth semiconductor pin 81. The controller 110 may transfer the clock CLK to the semiconductor device 120 through the first transfer line L11 to control the semiconductor device 120. The controller 110 may transmit the command address CA to the semiconductor device 120 through the second transmission line L31 to control the semiconductor device 120. The controller 110 and the semiconductor device 120 may transmit and receive the DATA through the third transfer line L51. The controller 110 may receive the error SUM signal ALT _ SUM from the semiconductor device 120 through the fourth transfer line L71.

The controller 110 may output a clock CLK, a command address CA, and DATA to the semiconductor device 120 for performing a write operation. The controller 110 may output the clock CLK and the command address CA to the semiconductor device 120 for performing a read operation. The controller 110 may receive DATA from the semiconductor device 120 in a read operation. Controller 110 may receive the error and signal ALT _ SUM from semiconductor device 120 in write operations and read operations. The command addresses CA may be continuously output in synchronization with odd pulses or even pulses included in the clock CLK.

The semiconductor device 120 may perform an error correction operation and an error check operation during a write operation and a read operation. The semiconductor device 120 may perform an error correction operation of correcting errors included in the DATA and inputting and outputting the error-corrected DATA during a write operation and a read operation. The semiconductor device 120 may perform an error check operation of checking errors included in the DATA and outputting an error SUM signal ALT _ SUM to the controller 110 during a write operation and a read operation. The error correction operation may be set to an operation of correcting an error included in the DATA by using an Error Detection Code (EDC) and an Error Correction Code (ECC). The error checking operation may be set to an operation of detecting whether an error included in the DATA is correctable through cyclic redundancy checking. The case where the error SUM signal ALT _ SUM is disabled during the error check operation means that the number of occurrences of errors in the DATA exceeds the limit and thus the errors of the DATA cannot be corrected. The case where the error SUM signal ALT _ SUM is disabled during the error check operation means that a repair operation other than the error correction operation is performed through the redundant region included in the semiconductor device 120.

The first error correction circuit 250 may generate a first error check signal IALT <1> (see fig. 2) that is enabled in the case where an error occurs in the DATA during a write operation and a read operation. The first error correction circuit 250 may correct errors of the DATA and store the error-corrected DATA in the first storage area 230 (see fig. 2) during a write operation and a read operation.

The second error correction circuit 260 may generate a second error check signal IALT <2> (see fig. 2) that is enabled in the case where an error occurs in the DATA during a write operation and a read operation. The second error correction circuit 260 may correct errors of the DATA and store the error-corrected DATA in the second storage area 240 (see fig. 2) during a write operation and a read operation.

The replica delay circuit 280 may compensate for a difference in delay amount and a time difference between the first error check signal IALT <1> and the second error check signal IALT <2 >.

The error SUM signal generation circuit 290 may generate the error SUM signal ALT _ SUM from the first error check signal iatt <1> and the second error check signal iatt <2> between which the difference in delay amount and the time difference are compensated.

Fig. 2 is a block diagram showing the configuration of the semiconductor device 120 according to this embodiment. As shown in fig. 2, the semiconductor device 120 may include an internal clock generation circuit 210, a column control circuit 220, a first storage region 230, a second storage region 240, a first error correction circuit 250, a second error correction circuit 260, a redundancy check circuit 270, a replica delay circuit 280, and an error & signal generation circuit 290.

The internal clock generation circuit 210 may receive the clock CLK and generate the internal clock ICLK. The internal clock generation circuit 210 can generate the internal clock ICLK by controlling the phase of the clock CLK. The internal clock generation circuit 210 may generate the internal clock ICLK by dividing the frequency of the clock CLK. The internal clock generation circuit 210 may generate the internal clock ICLK having a frequency 1/2 times the frequency of the clock CLK. The clock CLK may be set to a periodic transition (toggle) to control signals of the operation of the electronic device 100 according to the embodiment of the present disclosure. The operation of the internal clock generation circuit 210 to generate the internal clock ICLK by dividing the frequency of the clock CLK will be described in detail below with reference to fig. 3.

The column control circuit 220 may generate the write signal WT and the read signal RD according to a logic level combination of the command addresses CA <1: M > in synchronization with the internal clock ICLK. The column control circuit 220 may generate the write signal WT including pulses generated in the case where the command addresses CA <1: M > have a logic level combination for performing a write operation in synchronization with the internal clock ICLK. The column control circuit 220 may generate a read signal RD including pulses generated in the case where the command addresses CA <1: M > have a combination of logic levels for performing a read operation in synchronization with the internal clock ICLK. The number of bits M of the command address CA <1: M > can be variously set according to the embodiment. The logic level combinations of the command addresses CA <1: M > for generating the write signal WT and the read signal RD may be variously set according to embodiments.

The first storage area 230 may store DATA <1: N > in a case where the write signal WT is input. In the case where the write signal WT is input, the first storage area 230 may store the DATA <1: N > error-corrected by the first error correction circuit 250. The first memory region 230 may output DATA <1: N > stored therein in a case where a read signal RD is input.

The second storage area 240 may store DATA <1: N > in a case where the write signal WT is input. In the case where the write signal WT is input, the second storage area 240 may store the DATA <1: N > error-corrected by the second error correction circuit 260. The second storage area 240 may output DATA <1: N > stored therein in a case where the read signal RD is input. The write operation and the read operation of the second storage area 240 may be performed after the write operation and the read operation of the first storage area 230 are performed.

The write operation and the read operation of the first and second storage areas 230 and 240 may be performed at different times, respectively, according to an embodiment. The order in which the write operation and the read operation of the first and second storage areas 230 and 240 are performed may be variously set according to embodiments.

The first error correction circuit 250 may generate the first error check signal IALT <1> that is enabled in the case where an error occurs in the DATA DATA <1: N > in a write operation. The first error correction circuit 250 may correct errors included in the DATA <1: N > in a write operation and store the error-corrected DATA <1: N > in the first storage area 230. The first error correction circuit 250 may generate the first error check signal IALT <1> that is enabled in the case where an error occurs in the DATA DATA <1: N > in a read operation. The first error correction circuit 250 may correct errors included in the DATA <1: N > in a read operation and output the error-corrected DATA <1: N > to the controller 110.

The second error correction circuit 260 may generate the second error check signal IALT <2> that is enabled in the case where an error occurs in the DATA DATA <1: N > in the write operation. The second error correction circuit 260 may correct errors included in the DATA <1: N > in a write operation and store the error-corrected DATA <1: N > in the second storage area 240. The second error correction circuit 260 may generate the second error check signal IALT <2> that is enabled in the case where an error occurs in the DATA DATA <1: N > in the read operation. The second error correction circuit 260 may correct errors included in the DATA <1: N > in a read operation and output the error-corrected DATA <1: N > to the controller 110.

The redundancy check circuit 270 may generate a FLAG signal FLAG that is enabled in a case where the write signal WT is input and either one of the first error check signal IALT <1> and the second error check signal IALT <2> is generated at least a first predetermined number of times. The redundancy check circuit 270 may generate a FLAG signal FLAG that is enabled if the write signal WT is input and the first error check signal IALT <1> is generated at least a first predetermined number of times. The redundancy check circuit 270 may generate a FLAG signal FLAG that is enabled if the write signal WT is input and the second error check signal IALT <2> is generated at least a first predetermined number of times. Redundancy check circuit 270 may generate FLAG signal FLAG, which is enabled if read signal RD is input and either one of first error check signal iatt <1> and second error check signal iatt <2> is generated at least a first predetermined number of times. Redundancy check circuit 270 may generate FLAG signal FLAG that is enabled if read signal RD is input and first error check signal IALT <1> is generated at least a first predetermined number of times. Redundancy check circuit 270 may generate FLAG signal FLAG that is enabled if read signal RD is input and second error check signal IALT <2> is generated at least a first predetermined number of times. The first predetermined number of times may be set as the number of times that any one of the first and second error check signals iatt <1> and iatt <2> is repeatedly input K times. The first predetermined number of times may mean that the number of times of error occurrences of the DATA <1: N > exceeds a limit number of times. The first predetermined number of times K may be set to a different natural number according to an embodiment.

The replica delay circuit 280 may delay the first error check signal IALT <1> and thereby generate a delayed error check signal DALT. The replica delay circuit 280 may generate the delayed error check signal DALT by delaying the first error check signal IALT <1> by a delay amount for compensating for a difference and a time difference between delay amounts of generating the first error check signal IALT <1> and the second error check signal IALT <2 >. The delay amount of the replica delay circuit 280 may be set to a delay amount for compensating for a difference between the delay amount of transmitting the first error check signal IALT <1> and the delay amount of transmitting the second error check signal IALT <2 >.

The error SUM signal generation circuit 290 may generate the error SUM signal ALT _ SUM by summing the second error check signal IALT <2> and the delayed error check signal DALT. The error SUM signal generation circuit 290 may generate the error SUM signal ALT _ SUM by summing the second error check signal IALT <2> and the delayed error check signal DALT during a period in which the FLAG signal FLAG is disabled. Error SUM signal generation circuitry 290 may inhibit generation of error SUM signal ALT _ SUM during periods when FLAG signal FLAG is enabled. In the event of errors occurring at least a first predetermined number of times in the DATA DATA <1: N >, the errors and signal ALT _ SUM may be disabled.

The distance between the first error correction circuit 250 and the error sum signal generation circuit 290 may be set to a first distance D1. The distance between the second error correction circuit 260 and the error and signal generation circuit 290 may be set to a second distance D2. The second distance D2 may be physically longer than the first distance D1.

The operation of the internal clock generation circuit 210 will be described below with reference to fig. 3.

The internal clock generation circuit 210 may generate the internal clock ICLK by dividing the frequency of the clock CLK. One period P2 of the internal clock ICLK may be set twice as long as one period P1 of the clock CLK. The frequency of the internal clock ICLK may be set to 1/2 times the frequency of the clock CLK.

As shown in fig. 4, the error sum signal generating circuit 290 according to this embodiment of the present disclosure may include a summing circuit 291, a pulse generating circuit 292, and a pulse width control circuit 293.

The summing circuit 291 may be implemented by an OR gate 291<1 >. The summing circuit 291 may generate the SUM signal SUM by summing the second error check signal IALT <2> and the delayed error check signal DALT. The summing circuit 291 may generate the SUM signal SUM by performing a logical or operation on the second error check signal IALT <2> and the delayed error check signal DALT. The summing circuit 291 may generate the SUM signal SUM of a logic high level in a case where any one of the second error check signal IALT <2> and the delayed error check signal DALT is generated as a logic high level.

The pulse generation circuit 292 may be implemented by a flip-flop 292<1>, an AND (AND) gate 292<2>, AND a NAND (NAND) gate 292<3 >.

The flip-flop 292<1> may latch the FLAG signal FLAG and output an output signal in synchronization with the internal clock ICLK. The flip-flop 292<1> may latch the FLAG signal FLAG and output an output signal during a period in which the internal clock ICLK is input at a logic high level. The and gate 292<2> may buffer the output signal of the flip-flop 292<1> during a period in which the internal clock ICLK is input at a logic high level and output the output signal. The nand gate 292<3> may invert and buffer the SUM signal SUM and output the pulse signal PUL during a period in which the output signal of the and gate 292<2> is input at a logic high level.

The pulse generation circuit 292 may generate a pulse signal PUL including pulses generated from the FLAG signal FLAG and the SUM signal SUM in synchronization with the internal clock ICLK. The pulse generation circuit 292 may generate the pulse signal PUL including a pulse of a logic low level in a case where the FLAG signal FLAG is disabled to a logic high level and the SUM signal SUM is input at a logic high level during a period in which the internal clock ICLK is input at a logic high level. The pulse generation circuit 292 may generate the pulse signal PUL of a logic high level in a case where the FLAG signal FLAG is enabled to a logic low level. The pulse generation circuit 292 may generate the pulse signal PUL of a logic high level in a case where the SUM signal SUM is input at a logic low level.

The pulse width control circuit 293 may control the pulse width of the pulse signal PUL in synchronization with the internal clock ICLK and thereby generate the error SUM signal ALT _ SUM. The pulse width control circuit 293 may generate the error SUM signal ALT _ SUM having a pulse width during a period of a second predetermined number of transitions of the internal clock ICLK from the time when the pulse of the pulse signal PUL is input at the logic low level. The second predetermined number of times may be set as the number of times the internal clock ICLK is repeatedly input L times. The second predetermined number of times L may be set to a different natural number according to an embodiment.

Hereinafter, in the write operation of the electronic device 100 according to the embodiment of the present disclosure, the following error check operation will be described with reference to fig. 5 as an example: the error SUM signal ALT _ SUM is generated by summing a difference in delay amount and a time difference between the first error check signal iatt <1> and the second error check signal iatt <2>, which compensate for error information including DATA <1: N > stored in the first memory area 230 and the second memory area 240 located at different positions, and the first error check signal iatt <1> and the second error check signal iatt <2> between which the difference in delay amount and the time difference are compensated.

At time T1, controller 110 outputs clock CLK, command addresses CA <1: M >, and DATA DATA <1: N > for performing a write operation. The DATA <1: N > output at time T1 is set as the first DATA to be stored in the first storage area 230.

The internal clock generation circuit 210 generates the internal clock ICLK by dividing the frequency of the clock CLK.

Since the command addresses CA <1: M > have a combination of logic levels for performing a write operation, the column control circuit 220 generates the write signal WT including a pulse of a logic high level in synchronization with the internal clock ICLK.

The first error correction circuit 250 generates the first error check signal IALT <1> that is enabled to a logic high level in the case where an error occurs in the DATA DATA <1: N > in a write operation. The first error correction circuit 250 corrects errors included in the DATA <1: N > in a write operation and stores the error-corrected DATA <1: N > in the first storage area 230.

At time T2, the controller 110 outputs the clock CLK and the DATA DATA <1: N > for performing a write operation. The DATA <1: N > output at time T2 is set as the second DATA to be stored in the second storage area 240.

The second error correction circuit 260 generates the second error check signal IALT <2> that is enabled to a logic high level in the case where an error occurs in the DATA DATA <1: N > in a write operation. The first error correction circuit 260 corrects errors included in the DATA <1: N > in a write operation and stores the error-corrected DATA <1: N > in the second storage area 240.

Since the write signal WT is input and each of the first and second error check signals IALT <1> and IALT <2> is input less than the first predetermined number of times, the redundancy check circuit 270 generates the FLAG signal FLAG, which is disabled to a logic high level.

The replica delay circuit 280 generates a delayed error check signal DALT of a logic high level by delaying the first error check signal IALT <1> generated at time T1 by a delay amount for compensating for a difference between delay amounts for generating the first error check signal IALT <1> and the second error check signal IALT <2> and a time difference.

The summing circuit 291 of the error SUM signal generating circuit 290 generates a SUM signal SUM of a logic high level by summing the second error check signal IALT <2> and the delayed error check signal DALT.

At time T3, since the FLAG signal FLAG is disabled to the logic high level and the SUM signal SUM is input at the logic high level during the period in which the internal clock ICLK is input at the logic high level, the pulse generation circuit 292 of the error SUM signal generation circuit 290 generates the pulse signal PUL including the pulse of the logic low level.

The pulse width control circuit 293 generates an error SUM signal ALT _ SUM having a logic high level with a pulse width PW from a time T3 at which a pulse of the pulse signal PUL is input at a logic low level to a time T4 at which the internal clock ICLK makes a transition a second predetermined number of times.

Controller 110 receives the logic high error SUM signal ALT _ SUM and detects the error checking operation accordingly. Since the error SUM signal ALT _ SUM is input at a logic high level, the controller 110 detects that the write operation has been performed by correcting an error that has occurred in the DATA <1: N >.

The electronic device according to the embodiment of the present disclosure configured as indicated above may compensate for a difference in delay amount and a time difference between error check signals including error information about data input to and output from the memory regions located at different positions, and may sum and output error check signals between which the difference in delay amount and the time difference are compensated, thereby ensuring reliability of an error check operation.

As shown in fig. 6, an electronic device 300 according to another embodiment of the present disclosure may include a controller 310 and a semiconductor module 320, the controller 310 also being referred to as a control circuit. The semiconductor module 320 may include a first memory device 410, a second memory device 420, a third memory device 430, a fourth memory device 440, a fifth memory device 450, a sixth memory device 460, a seventh memory device 470, an eighth memory device 480, and an error & signal generation circuit 490.

The controller 310 may output the clock CLK, the command address CA <1: M >, and the DATA <1: N > to the semiconductor module 320 for performing a write operation. The controller 310 may output the clock CLK and the command address CA <1: M > to the semiconductor module 320 for performing a read operation. The controller 310 may receive DATA <1: N > from the semiconductor module 320 in a read operation. Controller 110 may receive the error and signal ALT _ SUM from semiconductor module 320 in write operations and read operations. The command addresses CA <1: M > may be continuously output in synchronization with odd pulses or even pulses included in the clock CLK. The controller 310 may be implemented by a configuration that performs the same operation as the controller 110 shown in fig. 1. The controller 310 may be replaced with the controller 110 shown in fig. 1.

The first memory device 410 may correct errors of the DATA <1: N > in a write operation and store the error-corrected DATA <1: N >. The first memory device 410 may generate the first error check signal IALT <1> that is enabled in case of an error occurring in the DATA DATA <1: N > in a write operation. The first memory device 410 may correct errors of the DATA <1: N > in a read operation and output error-corrected DATA <1: N >. The first memory device 410 may generate the first error check signal IALT <1> that is enabled in case of an error occurring in the DATA DATA <1: N > in a read operation.

The second memory device 420 may correct errors of the DATA <1: N > in a write operation and store the error-corrected DATA <1: N >. The second memory device 420 may generate the second error check signal IALT <2> that is enabled in case of an error occurring in the DATA <1: N > in a write operation. The second memory device 420 may correct errors of the DATA <1: N > in a read operation and output error-corrected DATA <1: N >. The second memory device 420 may generate the second error check signal IALT <2> that is enabled in case of an error occurring in the DATA <1: N > in a read operation.

The third memory device 430 may correct errors of the DATA <1: N > in a write operation and store the error-corrected DATA <1: N >. The third memory device 430 may generate a third error check signal IALT <3> that is enabled in case of an error occurring in the DATA DATA <1: N > in a write operation. The third memory device 430 may correct errors of the DATA <1: N > in a read operation and output error-corrected DATA <1: N >. The third memory device 430 may generate a third error check signal IALT <3> that is enabled in case of an error occurring in the DATA DATA <1: N > in a read operation.

The fourth memory device 440 may correct errors of the DATA <1: N > in a write operation and store the error-corrected DATA <1: N >. The fourth memory device 440 may generate the fourth error check signal IALT <4> that is enabled in case of an error occurring in the DATA DATA <1: N > in a write operation. The fourth memory device 440 may correct errors of the DATA <1: N > in a read operation and output error-corrected DATA <1: N >. The fourth memory device 440 may generate the fourth error check signal IALT <4> that is enabled in case of an error occurring in the DATA DATA <1: N > in a read operation.

The fifth memory device 450 may correct errors of the DATA <1: N > in a write operation and store the error-corrected DATA <1: N >. The fifth memory device 450 may generate a fifth error check signal IALT <5> that is enabled in case of an error occurring in the DATA DATA <1: N > in a write operation. The fifth memory device 450 may correct errors of the DATA <1: N > in a read operation and output error-corrected DATA <1: N >. The fifth memory device 450 may generate a fifth error check signal IALT <5> that is enabled in case of an error occurring in the DATA DATA <1: N > in a read operation.

The sixth memory device 460 may correct errors of the DATA <1: N > in a write operation and store the error-corrected DATA <1: N >. The sixth memory device 460 may generate a sixth error check signal IALT <6> that is enabled in case of an error occurring in the DATA DATA <1: N > in a write operation. The sixth memory device 460 may correct errors of the DATA <1: N > in a read operation and output error-corrected DATA <1: N >. The sixth memory device 460 may generate a sixth error check signal IALT <6> that is enabled in case of an error in the DATA DATA <1: N > in a read operation.

The seventh memory device 470 may correct errors of the DATA <1: N > in a write operation and store the error-corrected DATA <1: N >. The seventh memory device 470 may generate a seventh error check signal IALT <7> that is enabled in case of an error occurring in the DATA <1: N > in a write operation. The seventh memory device 470 may correct errors of the DATA <1: N > in a read operation and output error-corrected DATA <1: N >. The seventh memory device 470 may generate a seventh error check signal IALT <7> that is enabled in case of an error occurring in the DATA <1: N > in a read operation.

The eighth memory device 480 may correct errors of the DATA <1: N > in a write operation and store the error-corrected DATA <1: N >. The eighth memory device 480 may generate an eighth error check signal IALT <8> that is enabled in case of an error occurring in the DATA DATA <1: N > in a write operation. The eighth memory device 480 may correct errors of the DATA <1: N > in a read operation and output error-corrected DATA <1: N >. The eighth memory device 480 may generate an eighth error check signal IALT <8> that is enabled in case of an error occurring in the DATA DATA <1: N > in a read operation.

The error sum signal generating circuit 490 may compensate for a difference in delay amounts between the first to eighth error check signals IALT <1:8 >. The error SUM signal generation circuit 490 may generate the error SUM signal ALT _ SUM by summing the first to eighth error check signals IALT <1:8> for which the difference in delay amount is compensated.

The fourth memory device 440 and the fifth memory device 450 may each have a first distance D1 from the error and signal generation circuit 490. The third memory device 430 and the sixth memory device 460 may each have a second distance D2 from the error and signal generation circuit 490. The second memory device 420 and the seventh memory device 470 may each have a third distance D3 from the error and signal generation circuit 490. The first memory device 410 and the eighth memory device 480 may each have a fourth distance D4 from the error and signal generation circuit 490. The fourth distance D4 may be physically longer than the third distance D3. The third distance D3 may be physically longer than the second distance D2. The second distance D2 may be physically longer than the first distance D1.

The semiconductor module 320 may perform an error correction operation and an error check operation during a write operation and a read operation. The semiconductor module 320 may perform an error correction operation of correcting errors included in the DATA <1: N > and inputting and outputting the error-corrected DATA <1: N > during a write operation and a read operation. The semiconductor module 320 may compensate for a difference in delay amount between the first to eighth error check signals IALT <1:8> including error information on the DATA <1: N > in a write operation and a read operation according to the clock CLK and the command address CA <1: M >, and may output an error SUM signal ALT _ SUM by summing the first to eighth error check signals IALT <1:8> between which the difference in delay amount is compensated. The error correction operation may be set to an operation of correcting errors included in the DATA <1: N > by using an Error Detection Code (EDC) and an Error Correction Code (ECC). The error checking operation may be set to check whether an error included in the detection DATA <1: N > is a correctable operation by cyclic redundancy checking. The case where the error SUM signal ALT _ SUM is disabled during the error checking operation means that the number of occurrences of errors in the DATA <1: N > exceeds the limit and thus the errors of the DATA <1: N > cannot be corrected. The case where the error SUM signal ALT _ SUM is disabled during the error check operation means that a repair operation other than the error correction operation is performed through the redundant region included in the semiconductor module 320.

As shown in fig. 7, the first memory device 410 according to the embodiment of the present disclosure may include an internal clock generation circuit 411, a column control circuit 412, a memory area 413, and an error correction circuit 414.

The internal clock generation circuit 411 may receive the clock CLK and generate the internal clock ICLK. The internal clock generation circuit 411 may generate the internal clock ICLK by controlling the phase of the clock CLK. The internal clock generation circuit 411 may generate the internal clock ICLK by dividing the frequency of the clock CLK. The internal clock generation circuit 411 may generate the internal clock ICLK having a frequency 1/2 times the frequency of the clock CLK. The clock CLK may be set to a signal that periodically transitions to control the operation of the electronic device 300 according to this embodiment of the present disclosure. The internal clock generation circuit 411 may be implemented by the same circuit as the internal clock generation circuit 210 shown in fig. 2 and perform the same operation. The internal clock generation circuit 411 may be replaced with the internal clock generation circuit 210 shown in fig. 2.

The column control circuit 412 may generate the write signal WT and the read signal RD according to a logic level combination of the command addresses CA <1: M > in synchronization with the internal clock ICLK. The column control circuit 412 may generate the write signal WT including pulses generated in the case where the command addresses CA <1: M > have a logic level combination for performing a write operation in synchronization with the internal clock ICLK. The column control circuit 412 may generate the read signal RD including pulses generated in the case where the command addresses CA <1: M > have a logic level combination for performing a read operation in synchronization with the internal clock ICLK. The column control circuit 412 may be implemented by the same circuit and perform the same operation as the column control circuit 220 shown in fig. 2. The column control circuit 412 may be replaced with the column control circuit 220 shown in fig. 2.

The storage area 413 may store DATA <1: N > in a case where the write signal WT is input. In the case where the write signal WT is input, the storage area 413 may store the DATA <1: N > error-corrected by the error correction circuit 414. The storage area 413 may output DATA <1: N > stored therein in a case where the read signal RD is input. The storage region 413 may be implemented by the same circuit and perform the same operation as the first storage region 230 and the second storage region 240 shown in fig. 2. The storage area 413 may be replaced with the first storage area 230 and the second storage area 240 shown in fig. 2.

The error correction circuit 414 may generate the first error check signal IALT <1> that is enabled in the event of an error in the DATA DATA <1: N > in a write operation. The error correction circuit 414 may correct errors included in the DATA <1: N > in a write operation and store the error-corrected DATA <1: N > in the storage area 413. The error correction circuit 414 may generate a first error check signal IALT <1> that is enabled in the event of an error in the DATA DATA <1: N > in a read operation. The error correction circuit 414 may correct errors included in the DATA <1: N > in a read operation and output the error-corrected DATA <1: N > to the controller 310. The error correction circuit 414 may be implemented by the same circuit as the first error correction circuit 250 and the second error correction circuit 260 shown in fig. 2 and perform the same operation. The error correction circuit 414 may be replaced with the first error correction circuit 250 and the second error correction circuit 260 shown in fig. 2.

Meanwhile, since the second memory device 420, the third memory device 430, the fourth memory device 440, the fifth memory device 450, the sixth memory device 460, the seventh memory device 470, and the eighth memory device 480 shown in fig. 6 are implemented with the same circuit and perform the same operation as the first memory device 410 shown in fig. 7 except that only input/output signals are different, their detailed description will be omitted.

As shown in fig. 8, the error sum signal generating circuit 490 according to this embodiment of the present disclosure may include a redundancy check circuit 491, a replica delay circuit 492, a summing circuit 493, a pulse generating circuit 494, and a pulse width control circuit 495.

The redundancy check circuit 491 may generate a FLAG signal FLAG that is enabled if any one of the first through eighth error check signals IALT <1:8> is generated at least a first predetermined number of times. The first predetermined number of times may be set as the number of times any one of the first to eighth error check signals IALT <1:8> is repeatedly input K times. The first predetermined number of times K may be set to a different natural number according to an embodiment. The redundancy check circuit 491 can be realized by the same circuit as the redundancy check circuit 270 shown in fig. 2 and performs the same operation, except that only the input/output signals are different. The redundancy check circuit 491 may be replaced with the redundancy check circuit 270 shown in fig. 2.

The replica delay circuit 492 may generate the first to eighth delayed error check signals DALT <1:8> by delaying the first to eighth error check signals IALT <1:8> by a delay amount for compensating a difference between delay amounts and a time difference for generating the first to eighth error check signals IALT <1:8 >. The delay amount of the replica delay circuit 492 may be set such that the first to eighth delayed error check signals DALT <1:8> are generated at the same time.

The summing circuit 493 may generate a SUM signal SUM by summing the first to eighth delayed error check signals DALT <1:8 >. The summing circuit 493 may generate the SUM signal SUM by performing a logical or operation on the first to eighth delayed error check signals DALT <1:8 >.

The pulse generation circuit 494 may generate a pulse signal PUL including pulses generated from the FLAG signal FLAG and the SUM signal SUM in synchronization with the clock CLK. The pulse generation circuit 494 may generate the pulse signal PUL including a pulse of a logic low level in a case where the FLAG signal FLAG is disabled to a logic high level and the SUM signal SUM is input at a logic high level during a period in which the clock CLK is input at a logic high level. The pulse generation circuit 494 may generate the pulse signal PUL of a logic high level in a case where the FLAG signal FLAG is enabled to a logic low level. The pulse generation circuit 494 may generate the pulse signal PUL of a logic high level in a case where the SUM signal SUM is input at a logic low level.

Pulse width control circuit 495 may control the pulse width of pulse signal PUL in synchronization with clock CLK and thereby generate error SUM signal ALT _ SUM. The pulse width control circuit 495 may generate the error SUM signal ALT _ SUM having a pulse width during a period of a second predetermined number of transitions of the clock CLK from a time when a pulse of the pulse signal PUL is input at a logic low level. The second predetermined number of times may be set as the number of times the clock CLK is repeatedly input L times. The second predetermined number of times L may be set to a different natural number according to an embodiment.

As shown in fig. 9, the summing circuit 493 according to this embodiment of the disclosure may be implemented by or gates 493<1:7 >.

The or gates 493<1:7> may generate the SUM signal SUM by summing the first to eighth delayed error check signals DALT <1:8 >. The or gates 493<1:7> may generate the SUM signal SUM by performing a logical or operation on the first to eighth delayed error check signals DALT <1:8 >. The or gates 493<1:7> may generate the SUM signal SUM of a logic high level if at least any one of the first to eighth delayed error check signals DALT <1:8> is generated as a logic high level.

As shown in fig. 10, the pulse generating circuit 494 according to the embodiment of the present disclosure may be implemented by a flip-flop 494<1>, an and gate 494<2>, and a nand gate 494<3 >.

Flip-flop 494<1> may latch FLAG signal FLAG and output an output signal in synchronization with clock CLK. The flip-flop 494<1> may latch the FLAG signal FLAG and output an output signal during a period in which the clock CLK is input at a logic high level. And gate 494<2> may buffer the output signal of flip-flop 494<1> and output the output signal during a period in which clock CLK is input at a logic high level. The nand gate 494<3> may invert and buffer the SUM signal SUM and output the pulse signal PUL during a period in which the output signal of the and gate 494<2> is input at a logic high level.

The pulse generation circuit 494 may generate a pulse signal PUL including pulses generated from the FLAG signal FLAG and the SUM signal SUM in synchronization with the clock CLK. The pulse generation circuit 494 may generate the pulse signal PUL including a pulse of a logic low level in a case where the FLAG signal FLAG is disabled to a logic high level and the SUM signal SUM is input at a logic high level during a period in which the clock CLK is input at a logic high level. The pulse generation circuit 494 may generate the pulse signal PUL of a logic high level in a case where the FLAG signal FLAG is enabled to a logic low level. The pulse generation circuit 494 may generate the pulse signal PUL of a logic high level in a case where the SUM signal SUM is input at a logic low level.

Hereinafter, in the write operation of the electronic device 300 according to the embodiment of the present disclosure, the following error checking operation will be described with reference to fig. 11 as an example: the error SUM signal ALT _ SUM is generated by compensating for the difference in delay amount and the time difference between the first to fourth error check signals iatt <1:4> generated in the first to fourth memory devices 410, 420, 430, and 440 located at different positions and by summing the first to fourth error check signals iatt <1:4> between which the difference in delay amount and the time difference are compensated.

At time T11, the fourth memory device 440, having a first distance D1 from the error sum signal generating circuit 490, generates a fourth error check signal IALT <4> that is enabled to a logic high level if an error occurs in the DATA DATA <1: N >.

At time T12, the third memory device 430, having a second distance D2 from the error sum signal generation circuit 490, generates a third error check signal IALT <3> that is enabled to a logic high level if an error occurs in the DATA DATA <1: N >.

At time T13, the second memory device 420, which has a third distance D3 from the error sum signal generation circuit 490, generates a second error check signal IALT <2> that is enabled to a logic high level if an error occurs in the DATA DATA <1: N >.

At time T14, the first memory device 410, having a fourth distance D4 from the error sum signal generating circuit 490, generates a first error check signal IALT <1> that is enabled to a logic high level if an error occurs in the DATA DATA <1: N >.

At time T15, since each of the first to fourth error check signals IALT <1:4> is input less than the first predetermined number of times, the redundancy check circuit 491 generates a FLAG signal FLAG that is inhibited from being brought to a logic high level.

The replica delay circuit 492 generates the first to fourth delayed error check signals DALT <1:4> generated at a logic high level by delaying the first to fourth error check signals IALT <1:4> by a delay amount for compensating a difference between delay amounts and a time difference between the first to fourth error check signals IALT <1:4> generated from the time T11 to the time T14.

The summing circuit 493 generates a SUM signal SUM of a logic high level by summing the first to fourth delayed error check signals DALT <1:4 >.

At time T16, since the FLAG signal FLAG is disabled to the logic high level and the SUM signal SUM is input at the logic high level during the period in which the clock CLK is input at the logic high level, the pulse generation circuit 494 generates the pulse signal PUL including pulses at the logic low level.

The pulse width control circuit 495 generates an error SUM signal ALT _ SUM having a logic high level with a pulse width PW from a time T16 at which a pulse of the pulse signal PUL is input at a logic low level to a time T17 at which the clock CLK makes a transition a second predetermined number of times.

Controller 310 receives the logic high error SUM signal ALT _ SUM and detects error checking operations accordingly. Since the error SUM signal ALT _ SUM is input at a logic high level, the controller 310 detects that the write operation has been performed by correcting errors that have occurred in the DATA <1: N > stored in the first through fourth memory devices 410, 420, 430, and 440.

Fig. 12 is a block diagram illustrating a configuration of an electronic system 1000 according to an embodiment of the present disclosure. As shown in fig. 12, the electronic system 1000 may include a host 1100 and a semiconductor system 1200.

The host 1100 and the semiconductor system 1200 may transmit signals to each other by using an interface protocol. Examples of interface protocols used between the host 1100 and the semiconductor system 1200 may include, but are not limited to, multimedia card (MMC), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), peripheral component interconnect express (PCI-E), enhanced technology attachment (ATA), serial ATA (sata), parallel ATA (pata), serial attached scsi (sas), and Universal Serial Bus (USB), among others.

The semiconductor system 1200 may include a controller 1300 and a semiconductor device 1400(K: 1). The controller 1300 may control the semiconductor devices 1400(K:1) such that each of the semiconductor devices 1400(K:1) performs a write operation and a read operation. Each of the semiconductor devices 1400(K:1) may compensate for a difference in delay amount and a time difference between error check signals including error information about input to and output from the memory regions located at different positions, and may sum and output the error check signals between which the difference in delay amount and the time difference are compensated, thereby ensuring reliability of an error check operation.

The controller 1300 may be implemented by the controller 110 shown in fig. 1 or the controller 310 shown in fig. 6. Each of the semiconductor devices 1400(K:1) may be implemented by the semiconductor device 120 shown in fig. 1 and the semiconductor module 320 shown in fig. 6. According to an embodiment, each of the semiconductor devices 1400(K:1) may be implemented by one of: dynamic Random Access Memory (DRAM), phase change random access memory (PRAM), Resistive Random Access Memory (RRAM), Magnetic Random Access Memory (MRAM) and Ferroelectric Random Access Memory (FRAM).

While various embodiments have been described above, those skilled in the art will appreciate that the described embodiments are merely examples. Accordingly, the electronic devices described herein for performing error correction operations and error checking operations should not be limited based on the described embodiments.