阅读说明：本技术 产品性能分布预测方法及装置、电子设备及存储介质 (Product performance distribution prediction method and device, electronic equipment and storage medium ) 是由 薛小帝 于 2021-11-10 设计创作，主要内容包括：一种用于集成电路的产品性能分布预测方法及装置、电子设备及存储介质。该方法包括：根据目标电流值,利用第一预测模型得到第一参数,第一参数反映集成电路的电路级性能；根据第一参数,利用拟合函数得到第二参数和漏电参数,第二参数反映集成电路的产品级性能；根据第二参数和漏电参数,利用分布模型得到目标分布,目标分布为所预测的集成电路的产品性能分布。该方法可以实现自动化流程,可以快速精准地完成硅后产品性能分布预测,能够在硅后产品所处的各个阶段进行预测,可以处理大量数据,具有较强的复用性,适用范围广。(A product performance distribution prediction method and device for an integrated circuit, an electronic device and a storage medium are provided. The method comprises the following steps: obtaining a first parameter by using a first prediction model according to the target current value, wherein the first parameter reflects the circuit level performance of the integrated circuit; according to the first parameter, obtaining a second parameter and a leakage parameter by using a fitting function, wherein the second parameter reflects the product-level performance of the integrated circuit; and obtaining target distribution by using the distribution model according to the second parameter and the leakage parameter, wherein the target distribution is the predicted product performance distribution of the integrated circuit. The method can realize an automatic process, can quickly and accurately complete the performance distribution prediction of the silicon product, can predict each stage of the silicon product, can process a large amount of data, and has strong reusability and wide application range.)

1. A method for predicting product performance distribution for an integrated circuit, comprising:

obtaining a first parameter by using a first prediction model according to a target current value, wherein the first parameter reflects the circuit level performance of the integrated circuit;

obtaining a second parameter and a leakage parameter by utilizing a fitting function according to the first parameter, wherein the second parameter reflects the product-level performance of the integrated circuit;

and obtaining target distribution by using a distribution model according to the second parameter and the leakage parameter, wherein the target distribution is the predicted product performance distribution of the integrated circuit.

2. The method of claim 1, wherein the first predictive model comprises a neural network model,

obtaining the first parameter by using the first prediction model according to the target current value, including:

and taking the target current value as the input of the neural network model, and outputting the first parameter by using the neural network model.

3. The method of claim 1, wherein the integrated circuit comprises complementary metal oxide semiconductor transistors, and the target current value comprises at least an N-type metal oxide semiconductor drive current and a P-type metal oxide semiconductor drive current.

4. The method of claim 1, further comprising:

and training the neural network by using a training sample set and testing the neural network by using a test sample set by using the neural network, wherein a neural network model obtained by training the neural network is used as the first prediction model.

5. The method of claim 4, wherein training the neural network with the set of training samples comprises:

and training the neural network by using the training sample set and adopting a gradient descent algorithm.

6. The method of claim 4, wherein testing the neural network using the set of test samples comprises:

taking the test sample set as an input, and comparing an output result of the neural network with control data;

in response to the difference between the output result and the comparison data being less than a preset error, ending the training;

and in response to the difference between the output result and the comparison data being greater than or equal to the preset error, correcting the structure of the neural network and continuing training.

7. The method of claim 6, wherein modifying the structure of the neural network and continuing training comprises:

responding to the fact that the difference between the current difference value and the previous difference value between the output result and the comparison data is larger than a preset threshold value, increasing the number of hidden layer nodes of the neural network, and continuing training;

and increasing the number of hidden layers of the neural network and continuing training in response to the difference between the current difference value and the previous difference value between the output result and the comparison data being less than or equal to the preset threshold value.

8. The method of claim 1, further comprising:

fitting the multiple groups of test data to establish the fitting function;

wherein the fitting function reflects a correspondence between the first parameter, the second parameter, and the leakage parameter.

9. The method of claim 1, wherein the distribution model comprises a binary distribution,

obtaining the target distribution by using the distribution model according to the second parameter and the leakage parameter, including:

and respectively taking the second parameter and the leakage parameter as the median of each distribution in the binary distribution to obtain the target distribution.

10. The method of claim 1, further comprising:

and respectively constructing the distribution aiming at the second parameter and the distribution aiming at the leakage parameter by utilizing multiple groups of test data, and performing joint characterization by utilizing a trigonometric function to obtain binary distribution as the distribution model.

11. The method of claim 10, wherein the binary distribution comprises a binary normal distribution represented as:

，

wherein X represents the second parameter, Y represents the leakage parameter, and A, B and theta represent variation parameters in the binary normal distribution.

12. The method of claim 1, further comprising:

classifying the integrated circuits according to classification rules based on the target distribution.

13. The method of claim 12, wherein the classification rule comprises a plurality of preset interval ranges;

classifying the integrated circuits according to the classification rules based on the target distribution, including:

and based on the preset interval ranges, according to the second parameter and the leakage parameter corresponding to each point location in the target distribution, classifying the integrated circuit corresponding to the point location into a category corresponding to one of the preset interval ranges.

14. The method of any of claims 1-13, wherein the integrated circuit further comprises a ring oscillator, the first parameter comprises at least a frequency of the ring oscillator, and the second parameter comprises at least a circuit delay derived based on the frequency of the ring oscillator.

15. The method of claim 8 or 10, wherein the plurality of sets of test data are derived based on wafer acceptance testing and/or wafer screening testing.

16. A product performance distribution prediction apparatus for an integrated circuit, comprising:

a first calculation unit configured to obtain a first parameter by using a first prediction model according to a target current value, wherein the first parameter reflects the circuit level performance of the integrated circuit;

the second calculation unit is configured to obtain a second parameter and a leakage parameter by using a fitting function according to the first parameter, wherein the second parameter reflects the product-level performance of the integrated circuit;

and the distribution calculation unit is configured to obtain target distribution by using a distribution model according to the second parameter and the leakage parameter, wherein the target distribution is the predicted product performance distribution of the integrated circuit.

17. An electronic device comprising the product performance distribution predicting apparatus for an integrated circuit according to claim 16.

18. An electronic device, comprising:

a processor;

a memory including one or more computer program modules;

wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for implementing the product performance distribution prediction method for an integrated circuit of any of claims 1-15.

19. A storage medium storing non-transitory computer-readable instructions which, when executed by a computer, implement the product performance distribution prediction method for an integrated circuit of any of claims 1-15.

Technical Field

The embodiment of the disclosure relates to a product performance distribution prediction method and device for an integrated circuit, an electronic device and a storage medium.

Background

In the field of integrated circuit (e.g., chip) design and production, there is a general division into pre-silicon and post-silicon stages. The pre-silicon stage refers to a stage before production, and in the pre-silicon stage, designers can design, simulate, optimize, verify and the like chip parameters. Thereafter, the chip is produced based on the determined parameters. The post-silicon stage refers to a stage after production, in which the chip is produced, and designers can test, count, verify and the like actual parameters, performance indexes, yield and the like of the chip. With the increasing complexity of chip design, the importance of testing, counting, verifying, etc. operations on chips at the post-silicon stage is becoming more and more prominent.

Disclosure of Invention

At least one embodiment of the present disclosure provides a product performance distribution prediction method for an integrated circuit, including: obtaining a first parameter by using a first prediction model according to a target current value, wherein the first parameter reflects the circuit level performance of the integrated circuit; obtaining a second parameter and a leakage parameter by utilizing a fitting function according to the first parameter, wherein the second parameter reflects the product-level performance of the integrated circuit; and obtaining target distribution by using a distribution model according to the second parameter and the leakage parameter, wherein the target distribution is the predicted product performance distribution of the integrated circuit.

For example, in a method provided by an embodiment of the present disclosure, the obtaining the first parameter by using the first prediction model according to the target current value includes: and taking the target current value as the input of the neural network model, and outputting the first parameter by using the neural network model.

For example, in a method provided by an embodiment of the present disclosure, the integrated circuit includes a cmos transistor, and the target current value includes at least an nmos drive current and a pmos drive current.

For example, an embodiment of the present disclosure provides a method further including: and training the neural network by using a training sample set and testing the neural network by using a test sample set by using the neural network, wherein a neural network model obtained by training the neural network is used as the first prediction model.

For example, in a method provided by an embodiment of the present disclosure, training the neural network using the training sample set includes: and training the neural network by using the training sample set and adopting a gradient descent algorithm.

For example, in a method provided by an embodiment of the present disclosure, testing the neural network using the test sample set includes: taking the test sample set as an input, and comparing an output result of the neural network with control data; in response to the difference between the output result and the comparison data being less than a preset error, ending the training; and in response to the difference between the output result and the comparison data being greater than or equal to the preset error, correcting the structure of the neural network and continuing training.

For example, in a method provided by an embodiment of the present disclosure, modifying the structure of the neural network and continuing training includes: responding to the fact that the difference between the current difference value and the previous difference value between the output result and the comparison data is larger than a preset threshold value, increasing the number of hidden layer nodes of the neural network, and continuing training; and increasing the number of hidden layers of the neural network and continuing training in response to the difference between the current difference value and the previous difference value between the output result and the comparison data being less than or equal to the preset threshold value.

For example, an embodiment of the present disclosure provides a method further including: fitting the multiple groups of test data to establish the fitting function; wherein the fitting function reflects a correspondence between the first parameter, the second parameter, and the leakage parameter.

For example, in a method provided by an embodiment of the present disclosure, the obtaining the target distribution by using the distribution model according to the second parameter and the leakage parameter includes: and respectively taking the second parameter and the leakage parameter as the median of each distribution in the binary distribution to obtain the target distribution.

For example, an embodiment of the present disclosure provides a method further including: and respectively constructing the distribution aiming at the second parameter and the distribution aiming at the leakage parameter by utilizing multiple groups of test data, and performing joint characterization by utilizing a trigonometric function to obtain binary distribution as the distribution model.

For example, in one embodiment of the disclosure, the binary distribution includes a binary normal score

And (b) the binary normal distribution is expressed as:wherein X represents the same

The second parameter, Y, represents the leakage parameter, and A, B, θ, represents the variation in the binary normal distribution.

For example, an embodiment of the present disclosure provides a method further including: classifying the integrated circuits according to classification rules based on the target distribution.

For example, in a method provided in an embodiment of the present disclosure, the classification rule includes a plurality of preset interval ranges; classifying the integrated circuits according to the classification rules based on the target distribution, including: and based on the preset interval ranges, according to the second parameter and the leakage parameter corresponding to each point location in the target distribution, classifying the integrated circuit corresponding to the point location into a category corresponding to one of the preset interval ranges.

For example, in a method provided by an embodiment of the present disclosure, the integrated circuit further includes a ring oscillator, the first parameter includes at least a frequency of the ring oscillator, and the second parameter includes at least a circuit delay obtained based on the frequency of the ring oscillator.

For example, in the method provided by an embodiment of the present disclosure, the plurality of sets of test data are obtained based on wafer acceptance tests and/or wafer screening tests.

At least one embodiment of the present disclosure also provides a product performance distribution prediction apparatus for an integrated circuit, including: a first calculation unit configured to obtain a first parameter by using a first prediction model according to a target current value, wherein the first parameter reflects the circuit level performance of the integrated circuit; the second calculation unit is configured to obtain a second parameter and a leakage parameter by using a fitting function according to the first parameter, wherein the second parameter reflects the product-level performance of the integrated circuit; and the distribution calculation unit is configured to obtain target distribution by using a distribution model according to the second parameter and the leakage parameter, wherein the target distribution is the predicted product performance distribution of the integrated circuit.

At least one embodiment of the present disclosure further provides an electronic device including the product performance distribution prediction apparatus for an integrated circuit provided in any embodiment of the present disclosure.

At least one embodiment of the present disclosure also provides an electronic device including: a processor; a memory including one or more computer program modules; wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for implementing the product performance distribution prediction method for an integrated circuit provided by any of the embodiments of the present disclosure.

At least one embodiment of the present disclosure also provides a storage medium for storing non-transitory computer-readable instructions, which when executed by a computer may implement the product performance distribution prediction method for an integrated circuit provided in any one of the embodiments of the present disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1 is a schematic diagram of post-silicon performance estimation of an integrated circuit;

FIG. 2 is a schematic flow chart diagram illustrating a method for predicting product performance distribution of an integrated circuit according to some embodiments of the present disclosure;

FIG. 3 is a schematic flow chart diagram illustrating another method for predicting product performance distribution of an integrated circuit according to some embodiments of the present disclosure;

FIG. 4 is a graph illustrating a correlation between a target current value and a first parameter provided by some embodiments of the present disclosure;

FIG. 5 is a schematic diagram of a first predictive model in a method provided by some embodiments of the present disclosure;

FIG. 6 is a schematic flow chart illustrating testing of a neural network using a test sample set in a method according to some embodiments of the present disclosure;

FIG. 7 is a schematic flow chart illustrating the process of modifying the structure of the neural network and continuing training in the method according to some embodiments of the present disclosure;

fig. 8 is a schematic diagram of a fitting function in a product performance distribution prediction method according to some embodiments of the present disclosure;

fig. 9A is a schematic distribution diagram of a second parameter in a product performance distribution prediction method according to some embodiments of the present disclosure;

fig. 9B is a schematic distribution diagram of leakage parameters in a product performance distribution prediction method provided by some embodiments of the present disclosure;

fig. 9C is a schematic distribution diagram of a second parameter and a leakage parameter in the product performance distribution prediction method provided by some embodiments of the present disclosure;

fig. 10A is a comparison table of predicted data and actual measured data obtained by the product performance distribution prediction method provided by the embodiment of the present disclosure;

fig. 10B is a comparison graph of predicted data and actual measured data obtained by the product performance distribution prediction method provided by the embodiment of the present disclosure;

FIG. 11 is a flowchart illustrating a method for predicting product performance distribution of an integrated circuit according to some embodiments of the present disclosure;

FIG. 12 is a schematic block diagram of a product performance distribution predicting apparatus for an integrated circuit according to some embodiments of the present disclosure;

fig. 13 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure;

fig. 14 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure;

fig. 15 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure;

fig. 16 is a schematic diagram of a storage medium according to some embodiments of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

In the production of integrated circuits (e.g., chips), device driving current target values are important anchoring targets for designers to communicate with the fab for production. In actual production, due to the requirement of yield window or the requirement of market demand variation, different distribution requirements may be provided for product performance, so that the device target value needs to be adjusted. However, due to the insufficient integrity of Wafer Acceptance Test (WAT) data and the difference between different fab production conditions, it is difficult to estimate the performance distribution after silicon with a new target value of the device accurately. Therefore, it is significant to perform post-silicon performance estimation of the chip based on WAT test data and Wafer Sort (WS) data.

FIG. 1 is a schematic diagram of post-silicon performance estimation of an integrated circuit. As shown in fig. 1, the general post-silicon performance estimation adopts a single-point prediction method, that is, the drive current parameters obtained by the WAT test and the product-level performance parameters and the leakage parameters obtained by the WS test are respectively subjected to correlation fitting. In this way, new device driving current target values are substituted into a correlation fitting curve function, and product-level performance parameters and leakage parameters under single-point WS test can be obtained respectively, so that the performance condition of the chip after silicon is represented.

However, in such a single-point prediction mode, the drive current parameters obtained by the WAT test are used to predict the performance by direct correlation fitting, so that the correlation is weak and the prediction accuracy is poor. Moreover, the product-level performance parameters and the leakage parameters are respectively obtained through single-point prediction, and the performance distribution information after the chip silicon cannot be provided, so that the analysis requirements cannot be met.

At least one embodiment of the disclosure provides a product performance distribution prediction method and device for an integrated circuit, an electronic device and a storage medium. The method can realize an automatic process, can quickly and accurately complete the performance distribution prediction of the silicon product, can predict each stage of the silicon product, can process a large amount of data, and has strong reusability and wide application range.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different figures will be used to refer to the same elements that have been described.

At least one embodiment of the present disclosure provides a product performance distribution prediction method for an integrated circuit. The method comprises the following steps: obtaining a first parameter by using a first prediction model according to the target current value, wherein the first parameter reflects the circuit level performance of the integrated circuit; according to the first parameter, obtaining a second parameter and a leakage parameter by using a fitting function, wherein the second parameter reflects the product-level performance of the integrated circuit; and obtaining target distribution by using the distribution model according to the second parameter and the leakage parameter, wherein the target distribution is the predicted product performance distribution of the integrated circuit.

Fig. 2 is a schematic flowchart of a product performance distribution prediction method for an integrated circuit according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 2, the method includes the following operations.

Step S10: obtaining a first parameter by using a first prediction model according to the target current value, wherein the first parameter reflects the circuit level performance of the integrated circuit;

step S20: according to the first parameter, obtaining a second parameter and a leakage parameter by using a fitting function, wherein the second parameter reflects the product-level performance of the integrated circuit;

step S30: and obtaining target distribution by using the distribution model according to the second parameter and the leakage parameter, wherein the target distribution is the predicted product performance distribution of the integrated circuit.

For example, the method is used for predicting the performance distribution of the integrated circuit (such as a chip) after silicon, and the performance distribution of the integrated circuit can be predicted to be used for subsequent product evaluation and classification, such as dividing the product into different specifications and packaging types.

For example, in step S10, the target current value is the intended current value. When the integrated circuit includes a Complementary Metal-Oxide-Semiconductor (CMOS) transistor, the target current values include at least a Negative-Metal-Oxide-Semiconductor (NMOS) drive current and a Positive-Metal-Oxide-Semiconductor (PMOS) drive current. That is, the target current value includes an expected NMOS drive current and an expected PMOS drive current. Of course, embodiments of the present disclosure are not limited thereto, and the target current value may also include other WAT test parameters.

For example, the first prediction model may be a neural network model that is pre-trained. The input of the neural network model is a target current value (e.g., NMOS drive current and PMOS drive current), and the output of the neural network model is a first parameter. For example, the integrated circuit may include a ring oscillator, the first parameter including at least a frequency of the ring oscillator, and thus, the first parameter may reflect circuit level performance of the integrated circuit. Of course, the embodiments of the present disclosure are not limited thereto, and the first parameter may also include other types of parameters, such as other physical parameters that may be selected or defined by a designer, as long as the circuit level performance of the integrated circuit can be reflected, which may be determined according to actual requirements, and the embodiments of the present disclosure are not limited thereto.

For example, in the case where the first prediction model is a neural network model, step S10 may include: and taking the target current value as the input of the neural network model, and outputting a first parameter by using the neural network model. The neural network model will be described in detail later, and will not be described in detail here. It should be noted that, in the embodiment of the present disclosure, the first prediction model is not limited to the neural network model, and may be another type of model as long as the model can obtain the first parameter based on the target current value, which may be determined according to actual needs.

For example, in step S20, after the first parameter is obtained, the second parameter and the leakage parameter may be obtained by using a fitting function. For example, the fitting function may be obtained by fitting certain data in advance. The fitting function reflects the corresponding relationship among the first parameter, the second parameter and the leakage parameter, that is, according to a known first parameter, the fitting function can be used to calculate and obtain the corresponding second parameter and the leakage parameter. In the case where the integrated circuit includes a ring oscillator, the second parameter includes at least a circuit delay based on a frequency of the ring oscillator, and thus, the second parameter may reflect product-level performance of the integrated circuit. Of course, the embodiments of the present disclosure are not limited thereto, and the second parameter may also be other types of parameters, for example, other physical parameters that may be selected or defined by a designer, as long as the product-level performance of the integrated circuit can be reflected, which may be determined according to actual requirements, and the embodiments of the present disclosure are not limited thereto. For example, in some examples, the second parameter may be a parameter calculated based on a frequency synthesis of a ring oscillator of each of the plurality of paths in the integrated circuit to reflect product-level performance. The leakage parameter may be a leakage parameter of a CMOS transistor in the integrated circuit, or may be a leakage parameter of other devices in the integrated circuit, which is not limited in this embodiment of the disclosure. Similar to the effect of the second parameter, the leakage parameter may also reflect the product-level performance of the integrated circuit.

For example, in step S30, after the second parameter and the leakage parameter are obtained, the target distribution is obtained using the distribution model. For example, the distribution model may be previously established by certain data calculation. The distribution model may be any type of distribution model, such as a normal distribution, a uniform distribution, a rayleigh distribution, an exponential distribution, a beta distribution, a gamma distribution, and the like, which is not limited by the embodiments of the present disclosure. And substituting the second parameter and the leakage parameter into the distribution model so as to obtain target distribution, wherein the target distribution is the predicted product performance distribution of the integrated circuit.

Therefore, through the steps, the performance distribution of the integrated circuit (such as a chip) after silicon can be predicted, the obtained performance distribution of the integrated circuit can reflect the performance distribution of the integrated circuit after silicon at the target current value, for example, the distribution of the second parameter and the leakage parameter of each of a plurality of integrated circuit products obtained at the same target current value, and the method can be used for subsequent product evaluation and classification. Moreover, the steps form an automatic flow, and a designer can obtain the final target distribution only by providing a target current value.

Fig. 3 is a schematic flow chart of another method for predicting product performance distribution of an integrated circuit according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 3, the method includes the following operations.

Step S40: training a neural network by using a training sample set by using the neural network, testing the neural network by using a test sample set, and taking a neural network model obtained by training the neural network as a first prediction model;

step S10: obtaining a first parameter by using a first prediction model according to the target current value, wherein the first parameter reflects the circuit level performance of the integrated circuit;

step S50: fitting the multiple groups of test data to establish a fitting function;

step S20: according to the first parameter, obtaining a second parameter and a leakage parameter by using a fitting function, wherein the second parameter reflects the product-level performance of the integrated circuit;

step S60: respectively constructing distribution aiming at the second parameter and distribution aiming at the leakage parameter by using multiple groups of test data, and performing joint characterization by using a trigonometric function so as to obtain binary distribution as a distribution model;

step S30: obtaining target distribution by using a distribution model according to the second parameter and the leakage parameter, wherein the target distribution is the predicted product performance distribution of the integrated circuit;

step S70: based on the target distribution, the integrated circuits are classified according to classification rules.

The steps S10-S30 are substantially the same as the steps S10-S30 of the method shown in FIG. 2, and are not repeated herein.

For example, in step S40, the neural network is trained using the training sample set and tested using the test sample set. And through repeated training and testing, when the performance of the neural network meets the requirement, taking the neural network model obtained through the training of the neural network as a first prediction model.

For example, both the training sample set and the test sample set are from test data. The test data includes NMOS drive current and PMOS drive current obtained by the WAT test, and may further include first parameters obtained by the WS test. For example, in some examples, the test data is shown in fig. 4, where the target current values include NMOS drive currents and PMOS drive currents, one NMOS drive current and one PMOS drive current corresponding to one first parameter (i.e., the circuit level performance parameter shown in fig. 4). For example, a product of a test lot may be tested to obtain test data, and then a portion of the test data may be used as a training sample set and another portion of the test data may be used as a test sample set. For example, when testing, WAT testing includes device drive currents, such as NMOS drive currents, PMOS drive currents, other circuit level performance parameters, and the like; the WS test includes a first parameter (i.e., a product-level performance parameter), a leakage parameter, and so on.

For example, in some examples, the first predictive model is structured as shown in fig. 5, and the first predictive model may be a neural network model. The neural network model comprises 3 hidden layers, namely a hidden layer 1, a hidden layer 2 and a hidden layer 3, wherein the hidden layer 1 is used as an input layer, the hidden layer 3 is used as an output layer, and each hidden layer comprises a plurality of neuron nodes. The NMOS drive current and the PMOS drive current are used as the input of the neural network model, and the first parameter (namely, the circuit level performance parameter) is used as the output of the neural network model. Therefore, by using the neural network model, when the NMOS drive current and the PMOS drive current are provided, the corresponding first parameters (namely circuit-level performance parameters) can be predicted.

It should be noted that the structure of the neural network model is not limited to the structure shown in fig. 5, any applicable structure may be adopted, and the number of hidden layers is not limited to 3 layers, which may be determined according to actual requirements. The neural network model may use any type of neural network, such as a feedforward neural network, a feedback network (or called a regression network), a self-organizing neural network, and the like, and the embodiments of the disclosure are not limited thereto.

For example, training a neural network with a set of training samples may include: and training the neural network by using a training sample set and adopting a gradient descent algorithm. For the description of the gradient descent algorithm, reference may be made to conventional designs, which are not described in detail herein. The algorithm used for training the neural network may also be any other suitable algorithm, and the specific training mode for the neural network may also refer to conventional design, which is not described herein again.

Fig. 6 is a schematic flowchart illustrating a method for testing a neural network by using a test sample set according to some embodiments of the present disclosure. As shown in fig. 6, in some examples, testing a neural network with a set of test samples may include the following operations.

Step S41: taking the test sample set as input, and comparing the output result of the neural network with the control data;

step S42: in response to the difference between the output result and the comparison data being less than the preset error, ending the training;

step S43: and in response to the difference between the output result and the comparison data being greater than or equal to the preset error, modifying the structure of the neural network and continuing training.

For example, in step S41, the control data may be data obtained by actual tests, or may be design data or empirical data, which may be determined according to actual requirements. In step S42, when the difference between the output result and the comparison data is smaller than the preset error, it indicates that the accuracy of the neural network meets the requirement, and thus the training is finished, and the neural network model obtained at this time is used as the first prediction model. For example, the value of the preset error may be determined empirically or according to actual requirements. In step S43, when the difference between the output result and the comparison data is greater than or equal to the preset error, it indicates that the accuracy of the neural network does not meet the requirement, and therefore it is necessary to modify the structure of the neural network and continue training. Through repeated training, parameters of the neural network are optimally adjusted to reduce errors, so that a first prediction model can be obtained, wherein the first prediction model is a prediction model aiming at circuit-level performance parameters.

Fig. 7 is a schematic flow chart illustrating the process of modifying the structure of the neural network and continuing training in the method according to some embodiments of the present disclosure. As shown in fig. 7, modifying the structure of the neural network and continuing training may include the following operations.

Step S431: in response to the fact that the difference between the current difference value and the previous difference value between the output result and the comparison data is larger than a preset threshold value, increasing the number of hidden layer nodes of the neural network, and continuing training;

step S432: and increasing the number of hidden layers of the neural network and continuing training in response to the fact that the difference between the current difference value and the previous difference value between the output result and the comparison data is smaller than or equal to a preset threshold value.

For example, in step S431, a difference between the output result and the comparison data is calculated, if a difference between the current difference and the previous difference is greater than a preset threshold, the number of hidden layer nodes of the neural network is increased to modify the structure of the neural network, and then training is continued for the modified neural network.

For example, in step S432, a difference between the output result and the comparison data is calculated, if the difference between the current difference and the previous difference is less than or equal to a preset threshold, the number of hidden layers of the neural network is increased to modify the structure of the neural network, and then training is continued for the modified neural network.

Therefore, the structure of the neural network is modified in different modes according to the size relation between the difference between the current difference and the previous difference and the preset threshold value, so that the training speed can be increased, and the neural network model meeting the requirements can be obtained as soon as possible. It should be noted that the value of the preset threshold may be determined according to actual requirements, and the embodiment of the disclosure is not limited thereto.

In some examples, the training flow is as follows. Firstly, the number of nodes of each hidden layer of the neural network is gradually increased, and the neural network is trained by adopting a training sample set to obtain network parameters of the neural network. The accuracy is then verified using the test sample set. When the error of the circuit-level performance parameter (namely, the first parameter) predicted by using the test sample set compared with the circuit-level performance parameter measured by the WAT is lower than the preset error, the optimization of the neural network parameter is finished, and the obtained neural network model is used as the first prediction model. When the error of the circuit-level performance parameter predicted by using the test sample set compared with the WAT-measured circuit-level performance parameter is higher than or equal to a preset error, if the difference between the current error and the last error is higher than a preset threshold, the number of hidden layer nodes is continuously increased, the training and verification precision is carried out again, and if the difference between the current error and the last error is not higher than the preset threshold, the number of hidden layers is increased. And until the error of the circuit-level performance parameters predicted by the test sample set compared with the circuit-level performance parameters measured by the WAT is lower than the preset error, the optimization of the neural network parameters is finished, and the obtained neural network model is used as a first prediction model.

Returning to fig. 3, in step S50, a plurality of sets of test data are fitted to establish a fitting function for calculation in a subsequent step using the fitting function. For example, the fitting function reflects the correspondence between the first parameter, the second parameter, and the leakage parameter. The sets of test data are obtained based on a wafer acceptance test (WAT test) and/or a wafer screening test (WS test). For example, a product of a trial production may be tested to obtain a plurality of sets of test data, each set of test data including a first parameter, a second parameter, and a leakage parameter. For example, any fitting method such as polynomial fitting, least squares curve fitting, function fitting of a specific type, and the like may be employed, and embodiments of the present disclosure are not limited thereto.

For example, the fitting function may include a plurality of sub-functions. In some examples, as shown in fig. 8, the first parameter (i.e., the circuit-level performance parameter), the second parameter (i.e., the product-level performance parameter), and the leakage parameter have strong correlations, and two sub-functions can be obtained by fitting. One of the subfunctions represents a correspondence between the first parameter and the second parameter, and the other subfunction represents a correspondence between the first parameter and the leakage parameter. Therefore, in the subsequent step, according to the first parameter, the second parameter and the leakage parameter can be obtained by utilizing the fitting function.

Returning to fig. 3, in step S60, a distribution for the second parameter and a distribution for the leakage parameter are respectively constructed using multiple sets of test data, and are jointly characterized using a trigonometric function, so as to obtain a binary distribution as a distribution model. For example, multiple sets of test data are derived based on the WAT test and/or WS test. For example, a product of a trial production may be tested to obtain a plurality of sets of test data, each set of test data including the second parameter and the leakage parameter.

For example, as shown in fig. 9A to 9C, under the WS test, the second parameter (i.e., the product-level performance parameter) and the leakage parameter are subject to normal distribution, and there is a certain correlation. Therefore, two independent normal distributions A, B can be constructed, and the correlation binary normal distribution X, Y can be obtained by performing joint characterization through trigonometric functions sin θ and cos θ, so as to characterize the distribution of the actual product-level performance parameters and leakage parameters.

For example, a binary normal distribution is represented as:. In the formula, X table

The second parameter, Y, and θ, represent the leakage parameters, and A, B, θ represent the variation in the bivariate normal distribution. For example, the mean value, the standard deviation and the correlation coefficient of the product-level performance parameters and the leakage parameters are calculated through WS measured data, the mean value, the standard deviation and the correlation coefficient are substituted into the model, and the mean value and the standard deviation of theta, A and B are calculated through an enumeration method, so that the model construction is completed. For a detailed description of the binary normal distribution calculation method, reference may be made to conventional design, and details are not repeated here. Therefore, by jointly representing the distribution of the second parameter and the distribution of the leakage parameter by using the trigonometric function, a binary normal distribution can be obtained to serve as a distribution model.

After obtaining the distribution model (e.g., binary distribution), step S30 may include: the second parameter and the leakage parameter are respectively used as the median (also called midle value) of each distribution in the binary distribution to obtain the target distribution. That is, the target distribution can be obtained by substituting the second parameter and the leakage parameter obtained in step S20 into the binary distribution, and by using the second parameter as the median of one distribution in the binary distribution and the leakage parameter as the median of the other distribution in the binary distribution. The target distribution is a predicted product performance distribution of the integrated circuit.

Returning to fig. 3, in step S70, the integrated circuits are classified according to the classification rule based on the target distribution. For example, the classification rule includes a plurality of preset interval ranges, which represent ranges of parameters of the integrated circuit, such as ranges of the second parameter and the leakage parameter. Therefore, step S70 may include: and based on the preset interval ranges, classifying the integrated circuits corresponding to the point positions into categories corresponding to one of the preset interval ranges according to the second parameter and the leakage parameter corresponding to each point position in the target distribution. For example, each point represents an integrated circuit product, and the second parameter and the leakage parameter of the integrated circuit product corresponding to each point are different or not identical to each other. Therefore, the integrated circuits are classified according to the second parameter and the leakage parameter, so that the integrated circuit products with the same or similar parameters can be classified into the same class, and the integrated circuit products with more different parameters can be classified into different classes to realize classification. After sorting, the integrated circuit products may be classified into different specifications and package types.

Fig. 10A is a comparison table of predicted data and actual measurement data obtained by the product performance distribution prediction method provided by the embodiment of the present disclosure, and fig. 10B is a comparison table of predicted data and actual measurement data obtained by the product performance distribution prediction method provided by the embodiment of the present disclosure. As shown in fig. 10A and 10B, in some examples, 10 preset interval ranges (i.e., classification rules 1 to 10 in the table of fig. 10A) are set, the integrated circuit products falling into each preset interval range are classified into corresponding categories, and the quantity ratio of the integrated circuit products in each category is calculated. The prediction results in the table of fig. 10A indicate the number ratio of each category calculated based on the target distribution, and the measured data indicates the number ratio of each category actually measured. Therefore, the difference between the prediction result and the actually measured data is small and is less than 10%, and therefore the target distribution obtained by the product performance distribution prediction method provided by the embodiment of the disclosure is high in precision and accuracy.

It should be noted that, when the method provided by the embodiment of the present disclosure is implemented, steps S10-S60 may be executed, so as to both establish the first prediction model, the fitting function, and the distribution model, and perform the calculation using these models and functions; in addition, only steps S10-S30 may be performed, and steps S40-S60 may not be performed, so that the calculation is performed directly using the models and functions, which need to be established in advance. Whether each step is specifically executed or not may be determined according to actual requirements, and embodiments of the present disclosure are not limited thereto.

Fig. 11 is a flowchart illustrating a method for predicting product performance distribution of an integrated circuit according to some embodiments of the present disclosure. The workflow of the method is briefly described below with reference to fig. 11.

The desired device drive current target value, i.e., the input target current value, is entered first. The target current value is substituted into the circuit level performance prediction model (i.e., the first prediction model) to obtain a predicted circuit level performance parameter (i.e., the first parameter). And then, substituting the predicted circuit-level performance parameters into the fitting function of the WAT circuit-level performance parameters and the WS product-level performance parameters/leakage parameters to obtain product-level performance parameters (namely, second parameters) and leakage parameters. And then, substituting the predicted product-level performance parameters/electric leakage parameters into a product-level performance parameter/electric leakage parameter distribution model to obtain final product performance distribution. And finally, classifying according to a certain classification rule to realize the performance distribution prediction and classification of the silicon-finished product.

In the method provided by the embodiment of the disclosure, the performance distribution prediction of the post-silicon product is realized by adopting various model combinations, so that an automatic process can be realized, and the performance distribution prediction of the post-silicon product can be quickly and accurately completed. The method can predict each stage of the silicon product, can process a large amount of data, and has strong data processing capability. In addition, the method has strong applicability and reusability, can predict different products of different wafer factories and different stages of the products, and has wide application range. The method provided by the embodiment of the disclosure can solve the problems that the precision is poor and the distribution information cannot be provided in the traditional chip post-silicon performance prediction process, and can predict the relatively accurate post-silicon performance distribution condition only by providing the target current value.

At least one embodiment of the present disclosure also provides a product performance distribution prediction apparatus for an integrated circuit. The device includes: the first calculation unit is configured to obtain a first parameter by using a first prediction model according to the target current value, wherein the first parameter reflects the circuit level performance of the integrated circuit; the second calculation unit is configured to obtain a second parameter and a leakage parameter by using a fitting function according to the first parameter, wherein the second parameter reflects the product-level performance of the integrated circuit; and the distribution calculating unit is configured to obtain target distribution by using the distribution model according to the second parameter and the leakage parameter, wherein the target distribution is the predicted product performance distribution of the integrated circuit.

The device can realize automatic flow, can accomplish the product performance distribution prediction behind the silicon fast accurately, can predict in each stage that the product is located behind the silicon, can handle a large amount of data, has stronger reusability, and application scope is wide.

Fig. 12 is a schematic block diagram of a product performance distribution predicting apparatus for an integrated circuit according to some embodiments of the present disclosure. As shown in fig. 12, the product performance distribution predicting apparatus 100 includes a first calculating unit 110, a second calculating unit 120, and a distribution calculating unit 130. The product performance distribution predicting apparatus 100 is used for predicting the product performance distribution after silicon of an integrated circuit (e.g., a chip), and can predict the product performance distribution of the integrated circuit for subsequent product evaluation and classification, for example, for classifying the product into different specifications and packaging types.

The first calculation unit 110 is configured to derive a first parameter using a first prediction model according to the target current value. The first parameter reflects a circuit level performance of the integrated circuit. For example, the first calculation unit 110 may perform step S10 of the method as shown in fig. 2. The second calculation unit 120 is configured to obtain a second parameter and a leakage parameter by using a fitting function according to the first parameter. The second parameter reflects product-level performance of the integrated circuit. For example, the second calculation unit 120 may perform step S20 of the method as shown in fig. 2. The distribution calculation unit 130 is configured to obtain the target distribution using the distribution model according to the second parameter and the leakage parameter. The target distribution is a predicted product performance distribution of the integrated circuit. For example, the distribution calculation unit 130 may perform step S30 of the method as shown in fig. 2.

For example, the first computing unit 110, the second computing unit 120, and the distributed computing unit 130 may be hardware, software, firmware, and any feasible combination thereof. For example, the first computing unit 110, the second computing unit 120, and the distributed computing unit 130 may be dedicated or general circuits, chips, or devices, and may also be a combination of a processor and a memory. The embodiments of the present disclosure are not limited in this regard to specific implementation forms of the first computing unit 110, the second computing unit 120, and the distribution computing unit 130.

It should be noted that, in the embodiment of the present disclosure, each unit of the product performance distribution predicting apparatus 100 corresponds to each step of the product performance distribution predicting method, and for the specific function of the product performance distribution predicting apparatus 100, reference may be made to the description of the product performance distribution predicting method in the foregoing, and details are not repeated here. The components and structures of the product performance distribution predicting apparatus 100 shown in fig. 12 are only exemplary and not restrictive, and the product performance distribution predicting apparatus 100 may further include other components and structures as necessary.

For example, the first predictive model includes a neural network model. The first calculation unit 110 includes a first calculation subunit configured to output a first parameter using the neural network model with the target current value as an input of the neural network model.

For example, the product performance distribution predicting apparatus 100 may further include a training unit, a fitting unit, a distribution model constructing unit, and a classifying unit.

The training unit is configured to adopt a neural network, train the neural network by using a training sample set, test the neural network by using a test sample set, and use a neural network model obtained by the neural network training as a first prediction model.

The training unit may include a training subunit and a testing subunit. The training subunit is configured to train the neural network using a gradient descent algorithm using the training sample set. The test subunit is configured to: taking the test sample set as input, and comparing the output result of the neural network with the control data; in response to the difference between the output result and the comparison data being less than the preset error, ending the training; and in response to the difference between the output result and the comparison data being greater than or equal to the preset error, modifying the structure of the neural network and continuing training.

For example, the test subunit includes a first modification unit and a second modification unit. The first correction unit is configured to increase the number of hidden layer nodes of the neural network and continue training in response to a difference between a current difference value and a previous difference value between the output result and the comparison data being greater than a preset threshold value. The second correction unit is configured to increase the number of hidden layers of the neural network and continue training in response to a difference between a current difference value between the output result and the comparison data and a previous difference value being less than or equal to a preset threshold value.

The fitting unit is configured to fit the plurality of sets of test data to establish a fitting function. For example, the fitting function reflects the correspondence between the first parameter, the second parameter, and the leakage parameter.

The distribution model building unit is configured to respectively build distribution for the second parameter and distribution for the leakage parameter by using a plurality of groups of test data, and perform joint characterization by using a trigonometric function, so as to obtain binary distribution as a distribution model. For example, a binary distribution includes a binary normal distribution, a binary normal distribution

Expressed as:wherein X represents a second parameter, Y represents a leakage parameter,

A. b and theta represent variation parameters in the binary normal distribution.

The classification unit is configured to classify the integrated circuits according to a classification rule based on the target distribution. For example, the classification rule includes a plurality of preset interval ranges. The classification unit comprises a classification subunit, and the classification subunit is configured to classify the integrated circuits corresponding to the point locations into a category corresponding to one of a plurality of preset interval ranges according to the second parameter and the leakage parameter corresponding to each point location in the target distribution based on the plurality of preset interval ranges.

For example, the integrated circuit includes a complementary metal oxide semiconductor transistor, and the target current value includes at least an nmos drive current and a pmos drive current. The integrated circuit further includes a ring oscillator, the first parameter including at least a frequency of the ring oscillator, and the second parameter including at least a circuit delay based on the frequency of the ring oscillator. For example, multiple sets of test data are obtained based on wafer acceptance testing and/or wafer screening testing.

At least one embodiment of the present disclosure also provides an electronic device. The electronic equipment can realize an automatic flow, can quickly and accurately complete the performance distribution prediction of the silicon rear product, can predict each stage of the silicon rear product, can process a large amount of data, and has strong reusability and wide application range.

Fig. 13 is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. As shown in fig. 13, the electronic device 200 includes a product performance distribution predicting apparatus 210. For example, the product performance distribution predicting apparatus 210 may be the product performance distribution predicting apparatus 100 shown in fig. 12. For the related description of the electronic device 200, reference may be made to the above description of the product performance distribution predicting apparatus 100, and details are not repeated here.

At least one embodiment of the present disclosure also provides an electronic device comprising a processor and a memory, one or more computer program modules being stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for implementing the product performance distribution prediction method provided by any of the embodiments of the present disclosure. The electronic equipment can realize an automatic flow, can quickly and accurately complete the performance distribution prediction of the silicon rear product, can predict each stage of the silicon rear product, can process a large amount of data, and has strong reusability and wide application range.

Fig. 14 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure. As shown in fig. 14, the electronic device 300 includes a processor 310 and a memory 320. Memory 320 is used to store non-transitory computer readable instructions (e.g., one or more computer program modules). The processor 310 is configured to execute non-transitory computer readable instructions, which when executed by the processor 310, may perform one or more of the steps of the product performance distribution prediction method described above. The memory 320 and the processor 310 may be interconnected by a bus system and/or other form of connection mechanism (not shown).

For example, the processor 310 may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP) or other form of processing unit having data processing capabilities and/or program execution capabilities, such as a Field Programmable Gate Array (FPGA), or the like; for example, the Central Processing Unit (CPU) may be an X86 or ARM architecture or the like. The processor 310 may be a general-purpose processor or a special-purpose processor that may control other components in the electronic device 300 to perform desired functions.

For example, memory 320 may include any combination of one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, Random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, Read Only Memory (ROM), a hard disk, an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules may be stored on the computer-readable storage medium and executed by processor 310 to implement various functions of electronic device 300. Various applications and various data, as well as various data used and/or generated by the applications, and the like, may also be stored in the computer-readable storage medium.

It should be noted that, in the embodiment of the present disclosure, reference may be made to the above description on the method for predicting the product performance distribution for specific functions and technical effects of the electronic device 300, and details are not described here.

Fig. 15 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure. As shown in fig. 15, the electronic device 400 is, for example, suitable for implementing the product performance distribution prediction method provided by the embodiment of the disclosure. The electronic device 400 may be a terminal device or a server or the like. It should be noted that the electronic device 400 shown in fig. 15 is only an example, and does not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.

As shown in fig. 15, the electronic apparatus 400 may include a processing device (e.g., a central processing unit, a graphic processor, etc.) 41, which may perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 42 or a program loaded from a storage device 48 into a Random Access Memory (RAM) 43. In the RAM 43, various programs and data necessary for the operation of the electronic apparatus 400 are also stored. The processing device 41, the ROM 42, and the RAM 43 are connected to each other via a bus 44. An input/output (I/O) interface 45 is also connected to bus 44.

Generally, the following devices may be connected to the I/O interface 45: input devices 46 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 47 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage devices 48 including, for example, magnetic tape, hard disk, etc.; and a communication device 49. The communication means 49 may allow the electronic device 400 to communicate wirelessly or by wire with other electronic devices to exchange data. While fig. 15 illustrates an electronic device 400 having various means, it is to be understood that not all illustrated means are required to be implemented or provided, and that the electronic device 400 may alternatively be implemented or provided with more or less means.

For example, the product performance distribution prediction method shown in fig. 2 may be implemented as a computer software program according to an embodiment of the present disclosure. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program comprising program code for performing the product performance distribution prediction method described above. In such an embodiment, the computer program may be downloaded and installed from a network via the communication means 49, or installed from the storage means 48, or installed from the ROM 42. When executed by the processing device 41, the computer program may implement the functions defined in the product performance distribution prediction method provided by the embodiments of the present disclosure.

At least one embodiment of the present disclosure also provides a storage medium for storing non-transitory computer readable instructions, which can implement the product performance distribution prediction method provided in any embodiment of the present disclosure when the non-transitory computer readable instructions are executed by a computer. The storage medium can realize an automatic flow, can quickly and accurately complete the performance distribution prediction of the silicon after-product, can predict each stage of the silicon after-product, can process a large amount of data, and has strong reusability and wide application range.

Fig. 16 is a schematic diagram of a storage medium according to some embodiments of the present disclosure. As shown in fig. 16, the storage medium 500 is used to store non-transitory computer readable instructions 510. For example, the non-transitory computer readable instructions 510, when executed by a computer, may perform one or more steps in a method for predicting product performance distribution as described above.

For example, the storage medium 500 may be applied to the electronic device described above. The storage medium 500 may be, for example, the memory 320 in the electronic device 300 shown in fig. 14. For example, the related description about the storage medium 500 may refer to the corresponding description of the memory 320 in the electronic device 300 shown in fig. 14, and is not repeated here.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.