阅读说明：本技术 用于掺杂区的导电通道的制造方法、沟槽型mosfet器件及其制造方法 (Manufacturing method of conductive channel for doped region, trench type MOSFET device and manufacturing method thereof ) 是由 刘坚 蔡金勇 于 2021-09-15 设计创作，主要内容包括：公开了一种用于掺杂区的导电通道的制造方法,包括：在半导体层上形成介质层,所述半导体层包括掺杂区；在所述介质层中形成开口；在所述开口的侧壁形成侧墙；经由所述开口对所述半导体层进行蚀刻,形成到达所述掺杂区的导电孔；以及在所述导电孔中填充导电材料形成导电通道,其中,所述侧墙用于减小所述导电通道的横向尺寸。本申请的用于掺杂区的导电通道的制造方法,通过在介质层中的开口的侧壁形成侧墙,缩小介质层中开口的横向尺寸,从而以更小的开口对半导体层进行蚀刻,最终获得尺寸更小的导电孔,改善器件的性能。(Disclosed is a method for fabricating a conductive channel for a doped region, comprising: forming a dielectric layer on a semiconductor layer, wherein the semiconductor layer comprises a doped region; forming an opening in the dielectric layer; forming a side wall on the side wall of the opening; etching the semiconductor layer through the opening to form a conductive hole reaching the doped region; and filling a conductive material in the conductive hole to form a conductive channel, wherein the side wall is used for reducing the transverse dimension of the conductive channel. According to the manufacturing method of the conductive channel for the doped region, the side wall is formed on the side wall of the opening in the dielectric layer, and the transverse size of the opening in the dielectric layer is reduced, so that the semiconductor layer is etched through the smaller opening, the conductive hole with the smaller size is finally obtained, and the performance of the device is improved.)

1. A method of fabricating a conductive via for a doped region, comprising:

forming a dielectric layer on a semiconductor layer, wherein the semiconductor layer comprises a doped region;

forming an opening in the dielectric layer;

forming a side wall on the side wall of the opening;

etching the semiconductor layer through the opening to form a conductive hole reaching the doped region; and

filling a conductive material in the conductive hole to form a conductive channel,

the side walls are used for reducing the transverse size of the conductive channel.

2. The method of claim 1, wherein the step of forming a sidewall on the sidewall of the opening comprises:

forming a barrier layer on the surface of the dielectric layer and in the opening;

and removing the barrier layer on the surface of the dielectric layer and the barrier layer at the bottom of the opening, wherein the barrier layer on the side wall of the opening forms a side wall.

3. The method of manufacturing of claim 1, wherein the step of forming an opening in the dielectric layer comprises:

forming a patterned mask layer on the dielectric layer;

and transferring the pattern in the mask layer to the dielectric layer through the mask layer to form an opening.

4. A method of fabricating a trench MOSFET device, comprising:

forming an epitaxial layer on a semiconductor substrate;

forming a trench structure, a body region and a source region in the epitaxial layer, wherein the body region is adjacent to the trench structure, and the source region is positioned in the body region;

forming a dielectric layer on the surface of the epitaxial layer;

forming an opening in the dielectric layer;

forming a side wall on the side wall of the opening;

etching the epitaxial layer through the opening to form a conductive hole reaching the body region; and

filling a conductive material in the conductive hole to form a conductive channel,

the side walls are used for reducing the transverse size of the conductive channel.

5. The method of manufacturing of claim 4 wherein the cell region of the trench MOSFET device is a region surrounded by an outer periphery of the body region, and wherein the conductive via abuts the outer periphery of the body region.

6. The method of claim 5, wherein the step of forming a sidewall on the sidewall of the opening comprises:

forming a barrier layer on the surface of the dielectric layer and in the opening;

and removing the barrier layer on the surface of the dielectric layer and the barrier layer at the bottom of the opening, wherein the barrier layer on the side wall of the opening forms a side wall.

7. The method of manufacturing of claim 5, wherein the trench structure comprises: a trench in the epitaxial layer; the gate structure comprises an insulating layer, a first gate conductor, a gate oxide layer and a second gate conductor, wherein the insulating layer, the first gate conductor, the gate oxide layer and the second gate conductor are located in the groove, the insulating layer surrounds the side wall of the groove and surrounds the first gate conductor, the gate oxide layer is located on the side wall of the upper portion of the groove, and the second gate conductor is located on the insulating layer on the upper portion of the groove.

8. The method of manufacturing according to claim 5, wherein after the step of filling the conductive hole with a conductive material to form a conductive via, further comprising: and forming a second conductive layer on the second surface of the substrate.

9. A trench MOSFET device formed using the method of manufacturing as claimed in any one of claims 4 to 8.

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a conductive channel for a doped region, a trench type MOSFET device and a manufacturing method thereof.

Background

Power semiconductor devices, also known as power electronic devices, include power diodes, thyristors, VDMOS (vertical double-diffused metal oxide semiconductor) field effect transistors, LDMOS (lateral-diffused metal oxide semiconductor) field effect transistors, IGBTs (insulated gate bipolar transistors), and the like. The VDMOS field effect transistor includes a source region and a drain region formed on opposite surfaces of a semiconductor substrate, and in an on state, a current flows mainly along a longitudinal direction of the semiconductor substrate.

On the basis of the VDMOS field effect transistor, a trench MOSFET is further developed, as shown in fig. 1, including a substrate 110, an epitaxial layer 120, an insulating layer 131, a first gate conductor 132, a gate oxide layer 133, a second gate conductor 135, a dielectric layer 135, a body region 121, a source region 122, a contact region 123, first conductive layers 141 and 142, and a second conductive layer 143. However, as the cell size of the trench MOSFET is reduced, the lateral size of a CONT (lead line) hole (e.g., the first conductive layer 141 in fig. 1) occupies a larger proportion of the cell size, and the influence on the channel is larger, and in order to ensure that a sufficient window is designed, the performance of the designed device will be poor, which requires reducing the size of the CONT hole, but a smaller CONT hole size requires a better machine, which increases the process cost.

Disclosure of Invention

In view of the above problems, an object of the present invention is to provide a method for manufacturing a conductive via for a doped region, in which a sidewall is formed on a sidewall of an opening in a dielectric layer, so as to reduce a lateral dimension of the opening in the dielectric layer, thereby etching a semiconductor layer with a smaller opening, and finally obtaining a conductive hole and a conductive via with smaller lateral dimensions, thereby improving performance of a device.

According to an aspect of the present invention, there is provided a method of fabricating a conductive channel for a doped region, comprising: forming a dielectric layer on a semiconductor layer, wherein the semiconductor layer comprises a doped region; forming an opening in the dielectric layer; forming a side wall on the side wall of the opening; etching the semiconductor layer through the opening to form a conductive hole reaching the doped region; and filling a conductive material in the conductive hole to form a conductive channel, wherein the side wall is used for reducing the transverse dimension of the conductive channel.

Optionally, the step of forming a sidewall on the sidewall of the opening includes: forming a barrier layer on the surface of the dielectric layer and in the opening; and removing the barrier layer on the surface of the dielectric layer and the barrier layer at the bottom of the opening, wherein the barrier layer on the side wall of the opening forms a side wall.

Optionally, the step of forming an opening in the dielectric layer includes: forming a patterned mask layer on the dielectric layer; and transferring the pattern in the mask layer to the dielectric layer through the mask layer to form an opening.

According to another aspect of the present invention, there is provided a method of manufacturing a trench MOSFET device, including: forming an epitaxial layer on a semiconductor substrate; forming a trench structure, a body region and a source region in the epitaxial layer, wherein the body region is adjacent to the trench structure, and the source region is positioned in the body region; forming a dielectric layer on the surface of the epitaxial layer; forming an opening in the dielectric layer; forming a side wall on the side wall of the opening; etching the epitaxial layer through the opening to form a conductive hole reaching the body region; and filling a conductive material in the conductive hole to form a conductive channel, wherein the side wall is used for reducing the transverse dimension of the conductive channel.

Optionally, the cell region of the trench MOSFET device is a region surrounded by an outer periphery of the body region, and the conductive channel abuts the outer periphery of the body region.

Optionally, the step of forming a sidewall on the sidewall of the opening includes: forming a barrier layer on the surface of the dielectric layer and in the opening; and removing the barrier layer on the surface of the dielectric layer and the barrier layer at the bottom of the opening, wherein the barrier layer on the side wall of the opening forms a side wall.

Optionally, the trench structure comprises: a trench in the epitaxial layer; the gate structure comprises an insulating layer, a first gate conductor, a gate oxide layer and a second gate conductor, wherein the insulating layer, the first gate conductor, the gate oxide layer and the second gate conductor are located in the groove, the insulating layer surrounds the side wall of the groove and surrounds the first gate conductor, the gate oxide layer is located on the side wall of the upper portion of the groove, and the second gate conductor is located on the insulating layer on the upper portion of the groove.

Optionally, after the step of filling the conductive hole with a conductive material to form a conductive channel, the method further includes: and forming a second conductive layer on the second surface of the substrate.

According to still another aspect of the present invention, there is provided a trench MOSFET device formed by the method for manufacturing a trench MOSFET device as described above.

According to the manufacturing method of the conductive channel for the doped region, the side wall is formed on the side wall of the opening in the dielectric layer, the transverse size of the opening in the dielectric layer is reduced, so that the semiconductor layer is etched by the smaller opening, and the conductive hole and the conductive channel with smaller transverse sizes are finally obtained, so that the influence of the size of the conductive hole is reduced when the size of the device is reduced, the performance of the device is improved, and meanwhile, the size of some devices can be further reduced.

According to the groove type MOSFET device and the manufacturing method thereof, the manufacturing method of the conductive channel for the doped region is adopted, so that the transverse sizes of the conductive hole and the conductive channel of the source region are reduced, the influence of the conductive channel on the channel in devices with smaller and smaller cell sizes is reduced, and the performance of the device is improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic view of a conductive via structure according to the prior art;

FIG. 2 shows a schematic diagram of a conductive via structure according to an embodiment of the invention;

FIGS. 3 a-3 f illustrate cross-sectional views of stages in a method of fabricating a conductive via according to an embodiment of the invention;

fig. 4 shows a schematic structural diagram of a trench MOSFET device according to an embodiment of the invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly above another layer, another area, the expression "directly above … …" or "above and adjacent to … …" will be used herein.

The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.

Fig. 2 shows a schematic diagram of a conductive path structure according to an embodiment of the invention. The structural diagram of the conductive channel is, for example, a structural diagram of a conductive channel of an extraction electrode of a source region in a trench MOSFET device.

Referring to fig. 2, the conductive via structure of the present application includes a semiconductor layer 210, a dielectric layer 220, and a conductive via 230. The semiconductor layer 210 has a doped region 211, the dielectric layer 220 has an opening therein, which is the same as the lateral dimension of the conductive hole 205 defined in the semiconductor layer 210, the conductive hole 205 extends into the doped region 211 in the semiconductor layer 210, a sidewall 203 is formed on the sidewall of the opening of the dielectric layer 220, and the sidewall 203 reduces the lateral dimension of the opening in the dielectric layer 220.

In this embodiment, when the semiconductor layer 210 is etched through the reduced opening in the dielectric layer 220, the lateral size of the formed conductive via 205 can be reduced, so as to reduce the influence of the conductive via 205 and the conductive via 230 in the conductive via 205 on other structures (not shown in the figure) in the semiconductor layer 210, thereby improving the yield and reliability of the device.

In other embodiments, for example, without doped region 211 in semiconductor layer 210, dielectric layer 220 is, for example, a hard mask layer, and after forming conductive via 230 filling conductive via 205 in semiconductor layer 210, removing dielectric layer 220 and conductive via 230 over dielectric layer 220 is further included, which also enables a conductive via structure with a reduced lateral dimension to be obtained.

In a specific device structure, such as a trench MOSFET device, the semiconductor layer 210 is, for example, an epitaxial layer or a gate conductor layer, the dielectric layer 220 is, for example, an interlayer dielectric layer on the epitaxial layer, the doped region 211 is, for example, a body region, and the conductive channel 230 is, for example, an electrode lead-out structure of a source region or a gate.

In another specific device structure, for example, a memory device requiring bonding, the semiconductor layer 210 is, for example, a bonding layer, the dielectric layer 220 is, for example, a mask layer, and the conductive via 230 is, for example, a metal conductive via for improving the bonding performance of the bonding layer, that is, the dielectric layer 220 serving as the mask layer and the conductive via located above the dielectric layer 220 are removed later.

Therefore, the present application only shows an exemplary method for reducing the lateral dimension of the conductive via, that is, forming the sidewall 203 through the sidewall of the opening for defining the lateral dimension of the conductive hole in the dielectric layer 220, so as to reduce the lateral dimension of the opening, and the lateral dimension of the conductive hole formed by etching the opening is also smaller than the lateral dimension of the original opening. In the case that the lateral dimension of the opening is already as small as possible, the method for manufacturing the conductive channel of the present application can further reduce the lateral dimension of the opening, thereby reducing the influence of the conductive channel on the device structure, and simultaneously providing a method for further miniaturization of the device.

Fig. 3a to 3f show cross-sectional views of stages of a method of manufacturing a conductive channel according to an embodiment of the invention. The conductive channel is located in the epitaxial layer of the trench MOSFET device for example.

Step 1: a dielectric layer 220 is formed on the first surface of the semiconductor layer 210 and an opening 201 is formed in the dielectric layer 220, as shown in fig. 3a and 3 b.

In this step, a dielectric layer 220 is formed on the first surface of the semiconductor layer 210 by using a chemical vapor deposition or physical vapor deposition process. Dielectric layer 220 is then patterned to form opening 201 in dielectric layer 220.

In this embodiment, a doped region 211 is formed in the semiconductor layer 210 at a side close to the first surface, the semiconductor layer 210 is an epitaxial layer formed of, for example, an N-type silicon material, and the dielectric layer 220 is an insulating material, for example, silicon oxide or silicon nitride.

The method for forming the opening 201 in the dielectric layer 220 includes: a masking layer or a photoresist layer is formed on the surface of the dielectric layer 220, the masking layer or the photoresist layer is patterned, and the dielectric layer 220 is etched through the patterned masking layer or the patterned photoresist layer to form the opening 201. The opening 201 penetrates the dielectric layer 220, exposing the surface of the semiconductor layer 210.

The lateral dimension a1 of the opening 201 formed in this step is larger than the set lateral dimension D of the opening, but the lateral dimension a1 of the opening 201 cannot be further reduced by the etching process to satisfy the set value D.

In such an embodiment of a trench MOSFET device, a dielectric layer 220 is provided as an insulating layer on the surface of the semiconductor layer 210.

Step 2: a barrier layer 202 is formed on the surface of dielectric layer 220 as shown in fig. 3 c.

In this step, a barrier layer 202 is formed on the surface of the dielectric layer 220 by using an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process or the like, and the barrier layer 202 also forms a conformal layer on the sidewall and the bottom of the opening 201 of the dielectric layer 220, so that the lateral dimension of the opening 204 is reduced.

In this embodiment, the material of the barrier layer 202 is, for example, TEOS (tetraethylorthosilicate). Barrier layer 202 is formed along the sidewalls and bottom of the opening such that the distance between the two sidewalls in opening 204 changes from a distance a1 between dielectric layers 220 to a distance a2 between barrier layers 202, and a2 is significantly smaller than a1, thereby allowing the lateral dimension of opening 204 in dielectric layer 220 to be reduced.

And step 3: the barrier layer 202 on the surface of the dielectric layer 220 and the barrier layer 202 on the semiconductor layer 210 exposed by the opening 204 are removed, and only the barrier layer 202 located on the sidewall of the opening 204 in the dielectric layer 220 remains, so as to form the sidewall spacers 203, as shown in fig. 3 d.

In this step, for example, a chemical mechanical polishing process is used to remove the barrier layer 202 located above the surface of the dielectric layer 220, and then a dry etching process using anisotropic etching is used to remove the barrier layer 202 at the bottom of the opening 201, so that only the barrier layer 202 located on the sidewall of the opening 204 remains, and the sidewall spacers 203 are formed. In this embodiment, the dry etching includes, for example, an etching process such as ion etching, mill ion etching, or the like.

When removing the barrier layer 202 at the bottom of the opening 204, the barrier layer 202 at the surface portion of the dielectric layer 220 in the opening 204 may also be etched, so as to enlarge the size of the top of the opening 204, thereby facilitating the filling of the material during the subsequent material deposition.

In this step, by controlling the deposition thickness of the barrier layer 202, the thickness of the sidewall spacers 203 may be controlled, so that the lateral dimension a2 of the opening 204 after being reduced by the sidewall spacers 203 meets the set width value D.

And 4, step 4: a conductive hole 205 extending to the doped region 211 is formed in the semiconductor layer 210 through the dielectric layer 220 and the sidewall spacers 203, as shown in fig. 3 e.

In this step, the semiconductor layer 210 is etched through the opening 204 in the dielectric layer 220 using a dry etching process of anisotropic etching, thereby forming a conductive hole 205 in the semiconductor layer 210, the bottom of the conductive hole 205 being located in the doped region 211.

In this embodiment, since the sidewall spacers 203 are formed on the sidewalls of the opening 204 in the dielectric layer 220, the lateral dimension a2 of the opening 204 in the dielectric layer 220 is reduced compared to a1, and when the semiconductor layer 210 is etched through the opening 204 in the dielectric layer 220, the lateral dimension of the conductive via 205 formed is also reduced, for example, not greater than a 2.

And 5: a conductive via 230 is formed on the surface of dielectric layer 220, which conductive via 230 also fills conductive hole 205, as shown in fig. 3 f.

In this step, the conductive via 205 is filled with a conductive material, and a conductive via 230 is formed on the surface of the dielectric layer 220 and in the conductive via 205, where the material of the conductive via 230 is, for example, a metal material.

In this step, since the lateral size of the top position of the opening 204 is large, the top opening is not easily closed first when the material is filled.

In the above embodiments, the method of reducing the lateral dimension of the conductive channel is described by taking the extraction electrode of the source region in the trench MOSFET device as an example, and in other device structures, the method of manufacturing the conductive channel shown in this application may also be used, so as to reduce the lateral dimension of the conductive channel.

Fig. 4 shows a schematic structural diagram of a trench MOSFET device according to an embodiment of the invention.

Referring to fig. 4, an epitaxial layer 320 is formed on a first surface of a substrate 310, and a trench structure is formed in the epitaxial layer, including: trenches are formed in the epitaxial layer 320, an insulating layer 331, a first gate conductor 332, a gate oxide 333 and a second gate conductor 334 are formed in the trenches, and a body region 321 and a source region 322 are formed in the epitaxial layer 320. Further, a dielectric layer 335 is formed on the surface of the front-end device, that is, the surface of the epitaxial layer 320, then an opening is formed in the dielectric layer 335, a sidewall 336 is formed on the sidewall of the opening, the epitaxial layer 320 is etched through the opening to form a conductive hole, and then a metal material is deposited to form a conductive channel 342, wherein the conductive channel 342 fills the opening in the dielectric layer 335 and the epitaxial layer 320. Further, still include: a contact layer 323 is formed in the epitaxial layer 320 via the conductive via and a second conductive layer 343 is formed on the second surface of the substrate 310.

In the trench MOSFET device shown in fig. 4, since the lateral dimension of the conductive channel is reduced, the lateral dimension of the finally formed conductive channel 341 is also reduced, so as to reduce the influence of the conductive channel 341 on the second gate conductor 334 in the trench, and provide a concept for further reducing the overall structure of the device.

According to the manufacturing method of the conductive channel for the doped region, provided by the invention, the side wall is formed on the side wall of the opening in the dielectric layer, and the transverse size of the opening in the dielectric layer is reduced, so that the semiconductor layer is etched by using a smaller opening, and the conductive hole and the conductive channel with smaller transverse sizes are finally obtained, so that the device is not influenced by the size of the conductive channel when the size is reduced, the performance of the device is improved, and some devices can be further reduced in size when the size is reduced.

According to the groove type MOSFET device and the manufacturing method thereof, the manufacturing method of the conductive channel for the doped region is adopted, so that the transverse sizes of the conductive hole and the conductive channel are reduced, the influence of the conductive channel on the channel in devices with smaller and smaller cell sizes is reduced, and the performance of the device is improved.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.