阅读说明：本技术 高压半导体装置 (High voltage semiconductor device ) 是由 谭鸿志 刘兴潮 杨晓莹 廖志成 于 2020-06-10 设计创作，主要内容包括：一种高压半导体装置,包含基底、埋层、汲极区域、源极区域、闸极以及至少一浓度调变区。该基底具有第一导电类型,该埋层设置于该基底内并具有第二导电类型。该汲极区域与源极区域设置于该基底内并位于该埋层上方,而该闸极则设置在该基底上,位于该源极区域与该汲极区域之间。该至少一浓度调变区设置在局部的埋层内,并位于该汲极区域下方,其中,该至少一浓度调变区具有该第二导电类型,且该至少一浓度调变区的掺杂浓度小于该埋层的掺杂浓度。(A high voltage semiconductor device includes a substrate, a buried layer, a drain region, a source region, a gate and at least one concentration modulation region. The substrate has a first conductivity type, and the buried layer is disposed in the substrate and has a second conductivity type. The drain region and the source region are disposed in the substrate and above the buried layer, and the gate is disposed on the substrate and between the source region and the drain region. The at least one concentration modulation region is arranged in the local buried layer and is positioned below the drain region, wherein the at least one concentration modulation region has the second conductivity type, and the doping concentration of the at least one concentration modulation region is smaller than that of the buried layer.)

1. A high voltage semiconductor device, comprising:

a substrate having a first conductivity type;

a buried layer disposed in the substrate, the buried layer having a second conductivity type, the second conductivity type being complementary to the first conductivity type;

a drain region disposed in the substrate and above the buried layer, the drain region having the first conductivity type;

a source region disposed in the substrate and over the buried layer, the source region having the first conductivity type;

a gate disposed on the substrate and between the source region and the drain region; and

at least one concentration modulation region is arranged in the local buried layer, the at least one concentration modulation region is positioned below the drain region and has the second conduction type, and the doping concentration of the at least one concentration modulation region is smaller than that of the buried layer.

2. The high voltage semiconductor device according to claim 1, wherein a doping concentration of the at least one concentration-modulated region is reduced by 10% to 20% compared to a doping concentration of the buried layer.

3. The high voltage semiconductor device according to claim 1, wherein the at least one concentration modulation region comprises at least one stripe-shaped doped region.

4. The high voltage semiconductor device according to claim 1, wherein the at least one concentration modulation region comprises a plurality of square-shaped doped regions, and the square-shaped doped regions are spaced apart and staggered.

5. The high voltage semiconductor device according to claim 1, wherein the at least one concentration modulation region comprises a plurality of square-shaped doped regions, and the square-shaped doped regions are spaced apart from each other.

6. The high voltage semiconductor device of claim 1, wherein the at least one concentration modulation region comprises at least one rectangular frame-shaped doped region.

7. The high voltage semiconductor device according to claim 1, wherein the at least one concentration modulation region is plural, the plural concentration modulation regions include a first concentration modulation region extending along a first direction, and a second concentration modulation region extending along a second direction, the second concentration modulation region crosses the first concentration modulation region, and the first direction is different from the second direction.

8. The high voltage semiconductor device of claim 1, further comprising:

a first well region disposed in the substrate, the first well region having the first conductivity type, and the drain region disposed in the first well region.

9. The high voltage semiconductor device according to claim 8, wherein the coverage area of the at least one concentration modulation region is smaller than the coverage area of the first well region.

10. The high voltage semiconductor device according to claim 8, wherein a projected range of the at least one concentration modulation region does not exceed a projected range of the first well region.

11. The high voltage semiconductor device according to claim 8, wherein the at least one concentration modulated region directly contacts the first well region.

12. The high voltage semiconductor device of claim 8, wherein a PN junction is between the buried layer and the first well region.

13. The high voltage semiconductor device of claim 8, further comprising:

and a second well region disposed in the substrate, the second well region having the second conductivity type, wherein the second well region surrounds the first well region, and the source region is disposed in the second well region.

14. The high-voltage semiconductor device as recited in claim 13, wherein a doping concentration of the buried layer is greater than a doping concentration of the second well region.

15. The high voltage semiconductor device of claim 13, wherein a side of the gate partially covers the second well region and the side of the gate abuts the source region.

16. The high voltage semiconductor device of claim 13, further comprising a body region within the second well region, the body region having the second conductivity type.

17. The high voltage semiconductor device of claim 16, wherein said body region surrounds said drain region and said source region.

18. The high voltage semiconductor device of claim 16, further comprising:

a first insulating structure disposed on the substrate and between the body region and the drain region; and

and the second insulating structure is arranged on the substrate and is positioned between the drain region and the gate, and the gate does not directly contact the drain region.

Technical Field

The present invention relates to a semiconductor device, and more particularly, to a high voltage semiconductor device.

Background

With the advance of semiconductor technology, control circuits, memories, low voltage operating circuits, high voltage operating circuits and related devices have been integrated on a single chip to reduce the cost and improve the operating performance. The transistor device, which is commonly used for amplifying current or voltage signals in a circuit, as a circuit oscillator (oscillator), or as a switching device for controlling the switching operation of the circuit, is further applied as a high power device or a high voltage device with the progress of semiconductor process technology. For example, a transistor device as a high voltage device is disposed between an internal circuit (internal circuit) and an input/output (I/O) pin of a chip to prevent a large amount of charges from entering the internal circuit through the I/O pin in a very short time and causing damage.

In the conventional transistor device as a high voltage device, the breakdown voltage (breakdown voltage) is mainly raised by reducing the lateral electric field, and the structure of the transistor device mainly includes devices such as a Double Diffused Drain MOS (DDDMOS), a lateral diffused drain MOS (LDMOS), and the like. However, how to further increase the breakdown voltage of the high voltage semiconductor device to meet the practical requirement is the subject of the present industry.

Disclosure of Invention

The present invention provides a high voltage semiconductor device, which is to add at least one concentration modulation region locally in the buried insulating layer under the drain region, wherein the at least one concentration modulation region has the same conductivity type, the same dopant and lower dopant concentration as the buried insulating layer, so as to reduce the electric field intensity under the drain region and further increase the breakdown voltage of the high voltage semiconductor device.

In order to achieve the above objectives, a preferred embodiment of the present invention provides a high voltage semiconductor device, which includes a substrate, a buried layer, a drain region, a source region, a gate and at least one concentration modulation region. The substrate has a first conductivity type, the buried layer is disposed in the substrate and has a second conductivity type, and the second conductivity type is complementary to the first conductivity type. The drain region is disposed in the substrate and above the buried layer, and the drain region has the first conductivity type. The source region is disposed in the substrate and above the buried layer, and the source region has the first conductivity type. The gate is disposed on the substrate between the source region and the drain region. The at least one concentration modulation region is disposed in the local buried layer. The at least one concentration modulation region is located below the drain region and has the second conductivity type, and the doping concentration of the concentration modulation regions is smaller than that of the buried layer.

Drawings

Fig. 1 is a schematic top view of a high voltage semiconductor device according to a first embodiment of the invention.

Fig. 2 is a schematic cross-sectional view of fig. 1 along the cut line a-a'.

Fig. 3 is a schematic diagram illustrating simulation test results of the high voltage semiconductor device according to the first embodiment of the invention.

FIG. 4 is a diagram of a high voltage semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a schematic diagram of a high voltage semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a schematic diagram of a high voltage semiconductor device according to a fourth embodiment of the present invention.

Fig. 7 is a schematic diagram of a high voltage semiconductor device according to a fifth embodiment of the invention.

Wherein the reference numerals are as follows:

100. 300, 400, 500, 600: high voltage semiconductor device

110: substrate

120. 320, 420, 520, 620: buried layer

121: density modulation zone

130: the first well region

140: second well region

150: a drain region

160: source electrode region

170: base region

190. 191, 193, 195: insulation structure

210: gate electrode

211: gate dielectric layer

213: gate electrode layer

321: density modulation zone

323: square doped region

421: density modulation zone

521. 523: density modulation zone

621. 623: density modulation zone

D1: a first direction

D2: second direction

E1, E2: curve line

Detailed Description

In order to make the present invention more comprehensible to those skilled in the art, several preferred embodiments accompanied with figures are described in detail below to explain the present invention and the intended effects. Furthermore, persons skilled in the art to which the invention pertains may also refer to the following embodiments, and substitute, recombine, mix features of several different embodiments to accomplish other embodiments without departing from the spirit of the invention.

In the present invention, the description that the first component is formed on or above the second component may mean that the first component is in direct contact with the second component, or that another component is additionally present between the first component and the second component, so that the first component and the second component are not in direct contact. Moreover, various embodiments of the present invention may use repeated reference numerals and/or letters. These repeated use of reference characters and letters are intended to provide a concise and definite description, and are not intended to indicate any relationship between the various embodiments and/or configurations. In addition, for spatially related descriptive words mentioned in the present invention, for example: the terms "under," "over," "under," "high," "under," "over," "bottom," "top," and the like are used in describing, for convenience of description, the relative relationship of one element or feature to another element or feature(s) in the drawings. In addition to the orientations shown in the drawings, these spatially relative terms are also used to describe possible orientations of the semiconductor device during fabrication, during use, and during operation. For example, when the semiconductor device is rotated 180 degrees, a component that was originally disposed "above" another component becomes disposed "below" the other component. Therefore, as the swing direction of the semiconductor device changes (rotates by 90 degrees or other angles), the spatially related descriptions for describing the swing direction should be interpreted in a corresponding manner.

Although the present invention has been described using terms such as first, second, third, etc. to describe various elements, components, regions, layers and/or sections, it should be understood that such elements, components, regions, layers and/or sections should not be limited by such terms. These terms are only used to distinguish one element, component, region, layer and/or block from another element, component, region, layer and/or block, and do not denote any order or importance, whether the element is in a sequential order or in a manufacturing method. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of embodiments of the present invention.

The term "about" or "substantially" as used herein generally means within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are approximate amounts, i.e., the meaning of "about" or "substantially" may be implied without specifically stating "about" or "substantially".

Referring to fig. 1 and fig. 2, schematic diagrams of a high voltage semiconductor device 100 according to a first embodiment of the invention are shown, wherein fig. 1 is a top view of the high voltage semiconductor device 100, and fig. 2 is a cross-sectional view of the high voltage semiconductor device 100. The high voltage semiconductor device of the present invention is a semiconductor device having an operating voltage higher than about 90 volts (V), such as a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor, which may be a laterally diffused nmos transistor or a laterally diffused pmos transistor, and in the present embodiment, the high voltage semiconductor device 100 is described as a laterally diffused pmos transistor, but not limited thereto.

First, as shown in fig. 1 and 2, the high voltage semiconductor device 100 includes a substrate 110, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, and at least one insulating structure 190 disposed on the substrate 110. In the present embodiment, the insulating structure 190 is, for example, a Field Oxide (FOX) layer formed by local oxidation of silicon (LOCOS) method, as shown in fig. 2, but not limited thereto. In another embodiment, the isolation structure may be a Shallow Trench Isolation (STI) formed by a deposition process or an isolation unit fabricated by other suitable processes. It should be noted that the insulating structure 190 is omitted in fig. 1 for clarity of showing the relative relationship of some specific doped regions in the high voltage semiconductor device 100, but those skilled in the art should easily understand the location of the insulating structure 190 according to fig. 2. In addition, the specific arrangement position and number of the insulating structures 190 according to the present invention will be described in the following paragraphs.

The substrate 110 has a first conductivity type (e.g., P-type), and a first well region 130 and a second well region 140 are respectively disposed therein. Specifically, the first well 130 has the first conductivity type (e.g., P-type), and a drain (drain) region 150 is formed in the first well 130. The drain region 150 also has the first conductivity type (e.g., P-type) and preferably has a doping concentration greater than that of the first well 130. The second well 140 surrounds the first well 130 and has a second conductivity type (e.g., N-type) complementary to the first conductivity type (e.g., P-type). In the present embodiment, the depth of the second well region 140 in the substrate 110 is, for example, greater than that of the first well region 130, as shown in FIG. 2, but not limited thereto. A source region 160 is formed in the second well region 140, and the source region 160 has the first conductivity type (e.g., P-type).

In addition, a body region 170 is formed in the second well region 140, and the body region 170 has the second conductivity type (e.g., N-type) and preferably has a doping concentration greater than that of the second well region 140. In one embodiment, the body region 170 preferably does not directly contact the drain region 150 disposed in the first well region 130. For example, the insulating structure 191 and the insulating structure 193 may be disposed on two opposite sides of the body region 170, and the insulating structure 193 and the insulating structure 195 may be disposed on two opposite sides of the drain region 150, such that the insulating structure 193 is sandwiched between the drain region 150 and the body region 170, and the drain region 150 and the body region 170 are electrically isolated from each other, as shown in fig. 2. In one embodiment, the body region 170 may be annular, such as a rectangular frame as shown in fig. 1, and may surround the periphery of the drain region 150 and the source region 160. However, it should be understood by those skilled in the art that in other embodiments, the substrate region may have other shapes, such as square, circular, racetrack-shaped, or other suitable shapes, and the like, and is not limited to the shape shown in fig. 1. In addition, a gate electrode 210 is disposed on the substrate 110, and the gate electrode 210 may include a gate dielectric layer 211 and a gate electrode layer 213 sequentially stacked on the substrate 110, wherein the gate electrode layer 213 is, for example, a polysilicon gate layer or a metal gate layer, but not limited thereto. The gate 210 is located between the source region 160 and the drain region 150. In the present embodiment, one side of the gate 210 partially covers the second well 140 in the substrate 110 and is adjacent to the source region 160, and the other side of the gate 210 partially covers the first well 130 and the insulating structure 195 without directly contacting the drain region 150.

On the other hand, a buried layer (buried layer)120 is disposed in the substrate 110 and located under the first well 130 and the second well 140. The buried layer 120 may have the second conductivity type (e.g., N-type) and a higher doping concentration than the first well region 130 and the second well region 140. In the present embodiment, the buried layer 120 and the second well region 140 in the substrate 110 together serve as an isolation layer of the high voltage semiconductor device 100, so as to prevent current from directly penetrating (punch through) the bottom or the interior of the substrate 110 from the first well region 130, thereby affecting the device performance of the high voltage semiconductor device 100. It should be noted that the high voltage semiconductor device 100 of the present embodiment further includes at least one concentration modulated region (concentration modulated region)121 partially disposed in the buried layer 120. The high voltage semiconductor device 100 of the present embodiment selects two concentration modulation regions 121 separated from each other in the local buried layer 120 as an implementation mode for illustration, but not limited thereto. It should be easily understood by those skilled in the art that the number of the concentration modulation regions may be further adjusted according to the actual device requirements, for example, only a single concentration modulation region is disposed in the local buried layer 120 or more than two concentration modulation regions are disposed.

It should be noted that the concentration modulation region 121 is preferably disposed at a portion of the high voltage semiconductor device 100 where an electric field is stronger, such as, but not limited to, a PN junction (PN junction) between the first well region 130 and the second well region 140 or a PN junction between the first well region 130 and the buried layer 120. For example, the concentration modulated region 121 may be disposed in the buried layer 120 under the drain region 150 and the first well region 130, and extend between the top surface and the bottom surface of the buried layer 120 to directly contact the first well region 130, as shown in fig. 2. In addition, each of the concentration modulation regions 121 is, for example, a stripe-shaped doped region in a top view as shown in fig. 1, and the total coverage area of the concentration modulation regions 121 is preferably smaller than the coverage area of the first well region 130, as shown in fig. 1 and fig. 2. In a preferred embodiment, the projection range of the concentration modulation region 121 in a direction (not shown) perpendicular to the substrate 110 does not exceed the projection range of the first well region 130 in the perpendicular direction. In one embodiment, the concentration-modulated region 121 is fabricated, for example, by additionally providing a mask (not shown) during the ion implantation process of the buried layer 120 and blocking a local region of the substrate 110 by the mask, so that the local region cannot be implanted with dopants during the ion implantation process, and only a small amount of dopants diffused from the buried layer 120 can be obtained during a subsequent thermal drive-in (drive-in) process. Therefore, the concentration modulation region 121 may have the same conductivity type (e.g., N-type), the same dopant, and a relatively low doping concentration as the buried layer 120. For example, the doping concentration of the concentration modulation region 121 is reduced by about 10% to about 20%, preferably about 15% compared to the doping concentration of the buried layer 120, but not limited thereto. In another embodiment, the concentration-modulated region 121 may be formed before or after the formation of the buried layer 120, for example, a doped region with a relatively low doping concentration may be formed in the substrate 110 as the concentration-modulated region by another ion implantation process, and then the buried layer 120 is formed, or a doped region with a relatively low doping concentration may be formed in the reserved space as the concentration-modulated region by another ion implantation process after the reserved space is partially reserved when the buried layer 120 is formed in the substrate 110, but not limited thereto.

In other words, the concentration-modulated region 121 is at least one opening (slot) locally disposed (below the drain region 150 and the first well region 130) in the buried layer 120, and then a small amount of dopants diffused from the buried layer 120 is obtained by a thermal drive-in process, so that the dopant concentration can be relatively low. Therefore, the concentration modulation region 121 can reduce the electric field strength at the portion, thereby improving the problem of low breakdown voltage of the high voltage semiconductor device 100 at the portion with stronger electric field strength (i.e. the portion near the PN junction or the vicinity of the drain region 150). In this configuration, the breakdown voltage of the high voltage semiconductor device 100 can be raised by about 5 volts, for example, but not limited thereto. Referring to fig. 3, the high voltage semiconductor device 100 of the present embodiment (as shown in the curve E1) can actually reduce the local electric field strength under the simulation test, and can obtain a higher breakdown voltage compared to the conventional high voltage semiconductor device (as shown in the curve E2), but not limited thereto. Therefore, the high voltage semiconductor device 100 of the present embodiment can obtain better device performance.

It should be readily apparent to one skilled in the art that other aspects of the high voltage semiconductor device of the present invention are possible without limitation to meet the actual product requirements. For example, in the above embodiments, the embodiments are described with reference to a ldmos transistor, such that the first conductivity type is P-type and the second conductivity type is N-type, but the invention is not limited thereto. In another embodiment, the first conductivity type is selected to be N-type, and the second conductivity type is selected to be P-type, so as to form different types of high voltage semiconductor devices. Further description will be made below with respect to other embodiments or modifications of the high voltage semiconductor device. For simplicity, the following description mainly refers to the differences of the embodiments, and the description of the same parts is not repeated. In addition, the same elements in the embodiments of the present invention are denoted by the same reference numerals to facilitate the comparison between the embodiments.

According to another embodiment of the present invention, a high voltage semiconductor device is provided, which can prevent the effect of the buried layer as an insulating layer from being affected by too low doping concentration at a local portion when the doping concentration of the buried layer is locally adjusted to reduce the local electric field strength. Referring to fig. 4, a top view of a high voltage semiconductor device 300 according to a second embodiment of the invention is shown. The structure of the high voltage semiconductor device 300 in this embodiment is substantially the same as that of the high voltage semiconductor device 100 in the first embodiment, and includes the substrate 110, the first well 130, the second well 140, the drain region 150, the source region 160, the body region 170, the insulating structure 190, and the like, and the description of the same parts is omitted. The main difference between the present embodiment and the previous embodiments is the specific installation conditions of the concentration modulation regions 321 in the buried layer 320, such as the installation area, the pattern design, the number and the size.

In detail, a plurality of concentration modulation regions 321 are locally disposed in the buried layer 320 of the present embodiment, and the concentration modulation regions 321 are located below the drain region 150 and the first well region 130. Also, the concentration modulation region 321 may have the same conductivity type (e.g., N-type), the same dopant, and a lower doping concentration as the buried layer 320. It should be noted that the concentration modulation region 321 of the present embodiment is, for example, a square-shaped doping region, and each of the square-shaped doping regions is spaced apart and arranged in a staggered manner on a top view as shown in fig. 4, and may be a checkerboard (checkerboard), but not limited thereto. In other words, the local buried layer 320 (i.e., the portion of the buried layer 320 under the first well region 130) of the present embodiment may also form a plurality of square-shaped doped regions 323, and the square-shaped doped regions 323 and the concentration modulation regions 321 are spaced apart and staggered from each other, as shown in fig. 4.

Thus, the concentration modulation region 321 of the present embodiment can be more uniformly distributed at the portion of the high voltage semiconductor device 300 where the electric field is stronger, so that the doping concentration of the buried layer 320 below the portion can be more uniformly reduced, for example, reduced by about 10% to 20%, preferably about 15% compared with the doping concentration of the buried layer 320 at other portions, but not limited thereto. With this configuration, the high voltage semiconductor device 300 of the present embodiment can also improve the problem of low breakdown voltage of the device at the portion with stronger electric field strength (i.e. the portion near the PN junction or the vicinity of the drain region 150), and effectively increase the breakdown voltage of the portion, for example, about 5 v, so as to obtain better device performance.

In addition, it should be easily understood by those skilled in the art that the number, the pattern (e.g., the shape of a square or a bar), and the size of each of the concentration modulating regions 321, 121 in the foregoing embodiments are only exemplary and not limited thereto. In other embodiments, the concentration modulation region may have other configuration according to the actual device requirement, so as to locally reduce the doping concentration of the buried layer more uniformly, thereby achieving the effect of reducing the electric field strength. Moreover, the whole area occupied by the concentration modulation region in the buried layer can be adjusted according to the actual element requirement, and the breakdown voltage of the element is preferably improved as much as possible on the premise of not influencing the effect of the buried layer as an insulating layer.

Referring to fig. 5 to 7, schematic top views of the high voltage semiconductor device 400/500/600 in the third, fourth and fifth embodiments of the invention are respectively shown, wherein the structure of the high voltage semiconductor device 400/500/600 is substantially the same as that of the high voltage semiconductor device 300 in the second embodiment, and thus are not repeated. The main difference between these embodiments and the second embodiment is that the concentration modulation regions can have different configuration.

In detail, in the third embodiment, the high voltage semiconductor device 400 includes a plurality of concentration modulation regions 421, and each concentration modulation region 421 is also a square-shaped doped region (with a lower doping concentration), and each square-shaped doped region is arranged in the buried layer 420 under the first well region 130 or the drain region 150 in a row (in-line arrangement) at intervals in a top view as shown in fig. 5. In the fourth embodiment, the high voltage semiconductor device 500 may include both the density modulation region 521 and the density modulation region 523. The concentration modulation region 521 and the concentration modulation region 523 can be respectively a rectangular frame-shaped doped region (with lower doping concentration) in a top view as shown in fig. 6, wherein the concentration modulation region 523 and the concentration modulation region 521 are separately located in the buried layer 520 under the first well region 130 or the drain region 150, and the concentration modulation region 523 surrounds the concentration modulation region 521. In addition, the geometric centers (geometric centers) of the concentration modulation region 523 and the concentration modulation region 521 may overlap with each other, but are not limited thereto. In the fifth embodiment, the high voltage semiconductor device 600 may include a plurality of density modulation regions 621 and a plurality of density modulation regions 623. The concentration modulation regions 621 are, for example, stripe-shaped doped regions (with lower doping concentration) parallel to each other and extending along a first direction D1, and the concentration modulation regions 623 are, for example, stripe-shaped doped regions (with lower doping concentration) parallel to each other and extending along a second direction D2, wherein the second direction D2 is different from the first direction D1. Thus, each concentration modulation region 623 may cross over the concentration modulation region 621 in a top view as shown in fig. 7, and a grid-shaped structure is present in the buried layer 620 under the first well region 130 or the drain region 150, but not limited thereto. In the fifth embodiment, the first direction D1 is, for example, perpendicular to the second direction D2, as shown in fig. 7, but not limited thereto, and in another embodiment, the first direction and the second direction may also be selected to intersect with each other but not perpendicular to each other, and still form a concentration modulation region that entirely presents a grid-like structure.

In various configurations described above, the concentration modulated regions (including the concentration modulated region 421 shown in fig. 5, the concentration modulated regions 521, 523 shown in fig. 6, and the concentration modulated regions 621, 623 shown in fig. 7) may also be more uniformly distributed in the portion of the high voltage semiconductor device 400/500/600 where the electric field is stronger, so that the doping concentration of the buried layer (including the buried layer 420 shown in fig. 5, the buried layer 520 shown in fig. 6, and the buried layer 620 shown in fig. 7) under the portion may be more uniformly reduced, for example, by about 10% to 20%, preferably by about 15%, compared with the doping concentration of the buried layer in other portions, but not limited thereto. In various embodiments, the high voltage semiconductor device 400/500/600 also improves the breakdown voltage of the device at the portion with stronger electric field strength (i.e. the portion near the PN junction or the vicinity of the drain region 150), and increases the breakdown voltage of the portion, for example, by about 5 v, thereby achieving better device performance.

It should be noted that, although the concentration modulation regions of various aspects are described as being disposed in a buried layer in the embodiments of the present invention, it should be easily understood by those skilled in the art that the concentration modulation regions of the present invention may alternatively be disposed in other electrical insulation layers of a high voltage semiconductor device, such as being formed in a deep well (deep well) or a high voltage well (HV well). Therefore, the effect of locally reducing the doping concentration of the electric insulation layer can be achieved through the concentration modulation regions, and the electric field intensity of the high-voltage semiconductor device is locally reduced.

The above description is only a preferred embodiment of the present invention, and all the equivalent changes and modifications made by the claims of the present invention should fall within the protection scope of the present invention.