阅读说明：本技术 一种铁电场效应管及其制备方法以及铁电存算器件 (Ferroelectric field effect transistor, preparation method thereof and ferroelectric memory device ) 是由 张兆浩 张青竹 许高博 殷华湘 王文武 于 2021-08-25 设计创作，主要内容包括：本发明公开一种铁电场效应管及其制备方法以及铁电存算器件,涉及半导体器件技术领域,以解决现有基于Fe-FET的布尔逻辑门实现技术中由于单一场效应机制导致的逻辑门单元复杂度高以及可重构类型少的问题。铁电场效应管包括：衬底；形成在所述衬底内的源掺杂区和漏掺杂区；依次形成在所述衬底上的阻挡层、栅介质层以及金属栅；其中,所述栅介质层为具有电畴反转以及电荷俘获能力的材料层。铁电存算器件包括：衬底；所述衬底内形成有沟道层,所述沟道层的两侧形成有源极和漏极；依次形成在所述沟道层的上的阻挡层、栅介质层以及金属栅；其中,所述栅介质层为具有电畴反转以及电荷俘获能力的材料层。(The invention discloses a ferroelectric field effect transistor, a preparation method thereof and a ferroelectric memory device, relates to the technical field of semiconductor devices, and aims to solve the problems of high logic gate unit complexity and few reconfigurable types caused by a single field effect mechanism in the existing Fe-FET-based Boolean logic gate implementation technology. The ferroelectric field effect transistor includes: a substrate; a source doped region and a drain doped region formed in the substrate; a barrier layer, a gate dielectric layer and a metal gate which are sequentially formed on the substrate; the gate dielectric layer is a material layer with electric domain inversion and charge trapping capacity. The ferroelectric memory device includes: a substrate; a channel layer is formed in the substrate, and a source electrode and a drain electrode are formed on two sides of the channel layer; a barrier layer, a gate dielectric layer and a metal gate which are sequentially formed on the channel layer; the gate dielectric layer is a material layer with electric domain inversion and charge trapping capacity.)

1. A ferroelectric field effect transistor, comprising:

a substrate;

a source doped region and a drain doped region formed in the substrate;

a barrier layer, a gate dielectric layer and a metal gate which are sequentially formed on the substrate; the gate dielectric layer is a material layer with electric domain inversion and charge trapping capacity.

2. The ferroelectric field effect transistor of claim 1, wherein the gate dielectric layer comprises a stack of one or more of a hafnium-based ferroelectric material layer, a hafnium-based antiferroelectric material layer, or a zirconium oxide antiferroelectric material layer.

3. The tffet of claim 1, wherein said barrier layer comprises a stack of one or more of a hafnium oxide layer, an aluminum oxide layer, or a lanthanum oxide layer.

4. A ferroelectric memory device, comprising:

a substrate; a channel layer is formed in the substrate, and a source electrode and a drain electrode are formed on two sides of the channel layer;

a barrier layer, a gate dielectric layer and a metal gate which are sequentially formed on the channel layer; the gate dielectric layer is a material layer with electric domain inversion and charge trapping capacity.

5. The ferroelectric memory device of claim 4, wherein the gate dielectric layer comprises a stack of one or more of a hafnium-based ferroelectric material layer, a hafnium-based antiferroelectric material layer, or a zirconium oxide antiferroelectric material layer.

6. A ferroelectric memory device as recited in claim 4, wherein the barrier layer comprises a stack of one or more of a hafnium oxide layer, an aluminum oxide layer, or a lanthanum oxide layer.

7. A ferroelectric memory device as recited In claim 4, wherein the channel layer comprises a silicon layer, a germanium-silicon layer, In_1-xGa_xAs layer or In_1-xAl_xAnd an As layer.

8. A method for preparing a ferroelectric field effect transistor, the method comprising:

providing a substrate; forming an active doping region and a drain doping region in the substrate;

forming a barrier layer, a gate dielectric layer and a metal gate on the substrate in sequence; the gate dielectric layer is a material layer with electric domain inversion and charge trapping capacity.

9. The method of claim 8, wherein the gate dielectric layer comprises a stack of one or more of a hafnium-based ferroelectric material layer, a hafnium-based antiferroelectric material layer, or a zirconium oxide antiferroelectric material layer.

Technical Field

The invention relates to the technical field of semiconductor devices, in particular to a ferroelectric field effect transistor, a preparation method thereof and a ferroelectric memory device.

Background

At present, in order to further improve the performance of future large-scale integrated circuit systems, reduce power consumption and solve the contradiction between power consumption and performance, research and development on various types of devices are widely carried out at home and abroad. In recent years, an integrated storage and computation device, as a new microelectronic device, has storage and computation functions, breaks through the problem of von neumann architecture separation at the level of a basic device, receives wide attention from academia and industry, becomes a research hotspot for reducing power consumption and improving performance, and is considered to be a future development trend by the industry and the academia. According to the storage and calculation integrated technology, data does not need a separate operation component to complete calculation, but storage and calculation are completed in a storage unit, and data access delay and power consumption are eliminated, so that the performance of a device is greatly replaced, and the power consumption of a chip is reduced.

Fe-FET (Fe-Field Effect Transistor) based Memory technologies exhibit superior array level performance characteristics compared to Magnetic Tunnel Junction (MTJ), resistive RAM (Random Access Memory), and even SRAM (Static Random Access Memory) based Memory technologies.

However, in the technology of the computing device of the Fe-FET, due to the single Fe field effect mechanism, a plurality of logic gate units (such as XNOR, XOR, etc.) with complicated device structures are required, and the complexity of the system is greatly increased. Meanwhile, due to the limitation of the single mechanism, the computing unit based on the single mechanism has the problems that reconfigurable operation is difficult to realize and the types of reconfigurable logic gates are few.

Disclosure of Invention

The invention aims to provide a ferroelectric field effect transistor, a preparation method thereof and a ferroelectric memory device, which are used for solving the problems of high logic gate unit complexity and few reconfigurable types caused by a single field effect mechanism in the existing Fe-FET-based Boolean logic gate implementation technology.

In a first aspect, the present invention provides a ferroelectric field effect transistor comprising: a substrate; a source doped region and a drain doped region formed within the substrate. A barrier layer, a gate dielectric layer and a metal gate which are sequentially formed on the substrate; the gate dielectric layer is a material layer with electric domain inversion and charge trapping capability.

Compared with the prior art, the gate dielectric layer of the ferroelectric field effect transistor provided by the invention is a material layer with electric domain inversion and charge trapping capacity. In the ferroelectric field effect transistor provided by the invention, the states of domain inversion and charge trapping of the gate dielectric layer are changed by introducing the gate dielectric layer with the electric domain inversion and charge trapping capabilities and combining the double physical processes of the electric domain inversion and the charge trapping, and the logic gate function based on the single ferroelectric field effect transistor can be realized by taking the current under the fixed gate voltage as the output.

When the ferroelectric field effect transistor provided by the invention is used for manufacturing a ferroelectric memory device, the gate voltage can be changed to realize the adjustment of the dual physical state degree of the domain inversion and the charge capture of the gate dielectric layer, so that the reconfigurable scheme design of the ferroelectric memory device can be realized, and further, various Boolean logics can be realized. The method solves the problems of high complexity and few reconfigurable types of logic gate units caused by a single field effect mechanism in the existing Fe-FET-based Boolean logic gate implementation technology.

In a second aspect, the present invention also provides a ferroelectric memory device comprising: a substrate; a channel layer is formed in the substrate, and a source electrode and a drain electrode are formed on two sides of the channel layer;

and the barrier layer, the gate dielectric layer and the metal gate are sequentially formed on the channel layer. The gate dielectric layer is a material layer with electric domain inversion and charge trapping capacity.

Compared with the prior art, the gate dielectric layer of the ferroelectric computing device provided by the invention is a material layer with electric domain inversion and charge trapping capacity. In the ferroelectric memory device, a gate dielectric layer with electric domain inversion and charge trapping capacity is introduced, the states of the electric domain inversion and the charge trapping of the gate dielectric layer are changed by externally adding a time sequence gate voltage by combining the double physical processes of the electric domain inversion and the charge trapping, and the ferroelectric memory device is realized by taking current under a fixed gate voltage as output.

The ferroelectric memory device provided by the invention can realize the adjustment of the dual physical state degree of the domain inversion and the charge trapping of the gate dielectric layer by changing the gate voltage, thereby realizing the reconfigurable scheme design of the ferroelectric memory device and further realizing various Boolean logics. The method solves the problem that the reconfigurable logic gate unit type is few due to a single field effect mechanism in the existing Fe-FET-based Boolean logic gate implementation technology.

In a third aspect, the present invention further provides a method for manufacturing a ferroelectric fet, including:

providing a substrate; forming an active doping region and a drain doping region in the substrate;

forming a barrier layer, a gate dielectric layer and a metal gate on the substrate in sequence; the gate dielectric layer is a material layer with electric domain inversion and charge trapping capacity.

Compared with the prior art, the beneficial effects of the preparation method of the ferroelectric field effect transistor provided by the invention are the same as those of the ferroelectric field effect transistor provided by the first aspect, and are not repeated herein.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

fig. 1 is a schematic structural diagram of a ferroelectric memory device according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of applying a gate voltage to a ferroelectric memory device according to an embodiment of the present invention;

fig. 3-6 are schematic diagrams of different states of a gate dielectric layer of a ferroelectric memory device under different gate voltages according to an embodiment of the present invention;

fig. 7 is a readout graph of a ferroelectric memory device according to an embodiment of the present invention.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

At present, in order to further improve the performance of future large-scale integrated circuit systems, reduce power consumption and solve the contradiction between power consumption and performance, research and development on various types of devices are widely carried out at home and abroad. In recent years, an integrated storage and computation device, as a new microelectronic device, has storage and computation functions, breaks through the problem of von neumann architecture separation at the level of a basic device, receives wide attention from academia and industry, becomes a research hotspot for reducing power consumption and improving performance, and is considered to be a future development trend by the industry and the academia. According to the storage and calculation integrated technology, data does not need a separate operation component to complete calculation, but storage and calculation are completed in a storage unit, and data access delay and power consumption are eliminated, so that the performance of a device is greatly replaced, and the power consumption of a chip is reduced.

Fe-FET based memory technologies exhibit superior array-level performance characteristics compared to Magnetic Tunnel Junction (MTJ), resistive RAM and even SRAM based memory technologies.

However, in the technology of the ferroelectric memory device of the Fe-FET, due to the single Fe field effect mechanism, a plurality of logic gate units (such as XNOR, XOR, etc.) with complicated device structures are required, which greatly increases the complexity of the system. Meanwhile, due to the existence of a single mechanism, a storage and computation unit based on the mechanism has the problems that reconfigurable operation is difficult to realize and the types of reconfigurable logic gates are few.

Accordingly, an embodiment of the present invention provides a ferroelectric field effect transistor, including: a substrate. A source doped region and a drain doped region formed within the substrate.

A barrier layer gate dielectric layer and a metal gate which are sequentially formed on the substrate; the gate dielectric layer is a material layer with electric domain inversion and charge trapping capacity. Based on the technical scheme, in the ferroelectric field effect transistor, the gate dielectric layer with electric domain inversion and charge trapping capabilities is introduced, the electric domain inversion and charge trapping states of the gate dielectric layer are changed by externally adding a time sequence gate voltage in combination with the electric domain inversion and charge trapping double physical processes, and the logic gate function based on the single ferroelectric field effect transistor can be realized by taking the current under the fixed gate voltage as output.

A metal electrode is formed on the source doped region, and the metal electrode is formed as a source electrode of the ferroelectric field effect transistor. And forming a metal electrode on the drain doping region, wherein the metal electrode is formed as a drain electrode of the ferroelectric field effect transistor. The metal gate layer may be formed as a gate of a ferroelectric field effect transistor.

In practice, the ferroelectric field effect transistor provided in the embodiment of the present invention may be a PMOS transistor or an NMOS transistor.

In the embodiments of the present invention, the specific material and doping type of the substrate, the source doping region and the drain doping region are not limited. Illustratively, the material of the substrate may be Si, and the doping type of the substrate is P-type.

Further, the gate dielectric layer includes a stack of one or more of a hafnium-based ferroelectric material layer, a hafnium-based antiferroelectric material layer, or a zirconium oxide antiferroelectric material layer.

Illustratively, the gate dielectric layer may be a hafnium-based ferroelectric material layer.

Illustratively, the gate dielectric layer may also be a stack of a hafnium-based antiferroelectric material layer and a zirconium oxide antiferroelectric material layer.

The ferroelectric field effect transistor provided by the embodiment of the invention writes data by means of the grid voltage, has no power consumption in the writing process, and is beneficial to realizing low power consumption. The ferroelectric field effect transistor utilizes the polarization state and the charge trapping/releasing state of the ferroelectric material to represent data, and can finish the polarization reversal and the charge trapping/releasing within dozens of nanoseconds due to the extremely high speed, so that the ferroelectric field effect transistor provided by the embodiment of the invention can realize the fast reading and writing speed, and simultaneously, because the voltage required by the polarization reversal and the charge trapping/releasing is very low, the ferroelectric field effect transistor does not need the assistance of peripheral circuits such as a charge pump and the like, and has lower power consumption.

In an embodiment of the present invention, the barrier layer includes a stack of one or more of a hafnium oxide layer, an aluminum oxide layer, or a lanthanum oxide layer. The blocking layer is used for blocking electric charges in the substrate from entering the metal gate so as to prevent electric leakage.

The embodiment of the invention provides a ferroelectric memory device. The ferroelectric memory device includes: a channel layer is formed in the substrate, and a source electrode and a drain electrode are formed on two sides of the channel layer;

a barrier layer, a gate dielectric layer and a metal gate which are sequentially formed on the channel layer; the gate dielectric layer is a material layer with electric domain inversion and charge trapping capability.

Illustratively, the ferroelectric memory device may be a ferroelectric fin-type memory device, and referring to fig. 1, the ferroelectric fin-type memory device includes a substrate 10. The substrate 10 has a base 101 and at least one fin 102 on the base 101; a source 103 and a drain 104 are formed in the base. The ferroelectric fin type memory device comprises a barrier layer 20, a gate dielectric layer 30 and a metal gate 40 which are sequentially formed on each fin portion 102; the gate dielectric layer 30 is a material layer having domain inversion and charge trapping capabilities.

As a specific example, the substrate may be a Silicon substrate, and may also be an SOI (Silicon-On-Insulator) substrate, and it is understood that the substrate may be made of any suitable material, which is not limited in this embodiment of the present invention.

In the case of a ferroelectric memory device in order to isolate active regions, a Shallow Trench Isolation (STI) is formed on a substrate of the ferroelectric memory device. The shallow trench isolation may be made of SiN or Si₃N₄、SiO₂Or an insulating material such as SiC.

The ferroelectric memory device provided by the embodiment of the invention is provided by combining the current CMOS manufacturing process and taking a ferroelectric field effect transistor as a basis, facing the requirement of developing a new principle device with high-performance memory integration in the future, and combining a gate dielectric layer with charge trapping and electric domain inversion capabilities and combining the double physical processes of charge trapping and electric domain inversion and adding a time-sequence gate voltage V_GSAAs an input, the timing gate voltage V_GSBAs a second input, the charge trapping or domain inversion state of the ferroelectric gate dielectric layer is changed to fix the gate voltage V_GSRAnd source-drain voltage V_DSThe lower current is output, and the ferroelectric memory device is realized. And the adjustment of the charge trapping and electric domain inversion dual physical degree can be realized by changing the amplitude or the pulse width of the grid voltage pulse, so that the reconfigurable scheme of the ferroelectric memory device is realized, and various Boolean logics are realized.

Further, the gate dielectric layer in the ferroelectric memory device provided in the embodiments of the present invention includes a stack formed by one or more of a hafnium-based ferroelectric material layer, a hafnium-based antiferroelectric material layer, or a zirconium oxide antiferroelectric material layer.

Illustratively, the gate dielectric layer may be a hafnium-based ferroelectric material layer.

Illustratively, the gate dielectric layer may also be a stack of a hafnium-based antiferroelectric material layer and a zirconium oxide antiferroelectric material layer.

The barrier layer includes a stack of one or more of a hafnium oxide layer, an aluminum oxide layer, or a lanthanum oxide layer.

Illustratively, the barrier layer may be a hafnium oxide layer.

Illustratively, the barrier layer may be a stack of a hafnium oxide layer and an aluminum oxide layer.

In an embodiment of the present invention, the channel layer includes a silicon layer, a germanium-silicon layer, In_1-xGa_xAs layer or In_1-xAl_xAnd an As layer.

Referring to fig. 2, which shows a schematic diagram of applying a gate voltage to a ferroelectric memory device, the embodiment of the present invention changes states of trapping of a gate dielectric layer and domain inversion by applying a gate voltage VGS (input a, input B), and uses a current at a fixed gate voltage as an output to implement the ferroelectric memory device.

The voltage applied to the metal gate 40 is a continuous timing gate voltage pulse, which includes a first initialization pulse (to ensure device initial state consistency), a second write pulse (input a), a third write pulse (input B), and a fourth read pulse; wherein for the write pulse, the positive voltage pulse is defined as a logic "1" and the negative voltage pulse is defined as a logic "0"; corresponding current (I) at write pulse gate voltage_{[email protected]}) For the output of logic gates, in which a fixed current reference I is defined_{DS REF}Definition of I_{[email protected]}Which satisfies I_{[email protected]}>I_{DS REF}Is a logic "1" and satisfies I_{[email protected]}<I_{DS REF}Is a logical "0".

Referring to fig. 3, 4, 5 and 6, the gate dielectric layers have different states when successive sequential gate voltage pulses are applied to the metal gate 40 of a ferroelectric memory device (taking a PMOS transistor as an example).

For example, referring to FIG. 3, when an "input A" voltage having a logic "1" and an "input B" voltage having a logic "1" are applied to metal gate 40, the gate dielectricThe layer has a first state as shown in fig. 3. At this time, the gate dielectric of the ferroelectric memory device has "ferroelectric domain direction down" and "hole empty" states, resulting in a PMOS threshold voltage (V)_T) Becomes larger (curve 1 in fig. 7). At a fixed voltage (V in FIG. 7)_GSR) Obtaining I_{[email protected]}>I_{DS REF}And an output logic "1" is obtained.

For another example, referring to fig. 4, when an "input a" voltage having a logic "1" and an "input B" voltage having a logic "0" are applied to the metal gate 40, the gate dielectric layer has a second state as shown in fig. 3. At this time, the gate dielectric of the ferroelectric memory device has "ferroelectric domain direction up" and "hole filling" states, resulting in V of PMOS_TBecomes smaller (curve 2 in fig. 7). At a fixed voltage (V in FIG. 7)_GSR) Obtaining I_{[email protected]}<I_{DS REF}Resulting in an output logic "0".

For another example, referring to fig. 5, when an "input a" voltage having a logic "0" and an "input B" voltage having a logic "1" are applied to the metal gate 40, the gate dielectric layer has a third state as shown in fig. 3. At this time, the gate dielectric of the ferroelectric memory device has "ferroelectric domain direction up" and "hole empty" states, resulting in V of PMOS_TBecomes smaller (curve 3 in fig. 7). At a fixed voltage (FIG. 7V)_GSR) Obtaining I_{[email protected]}<I_{DS REF}Resulting in an output logic "0".

For another example, referring to fig. 6, when an "input a" voltage having a logic "0" and an "input B" voltage having a logic "0" are applied to the metal gate 40, the gate dielectric layer has the first state shown in fig. 3. At this time, the gate dielectric of the ferroelectric memory device has "ferroelectric domain direction up" and "hole accumulation" states, resulting in V of PMOS_TBecomes smaller (fig. 7, curve 4). At a fixed voltage (V in FIG. 7)_GSR) Obtaining I_{[email protected]}>I_{DS REF}And an output logic "1" is obtained.

Namely, when the logic of the input voltage is '1', '1' and '0', the logic of the output voltage is '1'; when the logic of the input voltage is '1', '0' and '1', the logic of the obtained output voltage is '0'; i.e. the exclusive or logic is implemented on a single device.

V of ferroelectric memory device in embodiment of the present invention_TAs a function of the gate voltage scan range, after-5V voltage scan, the electric domain is polarized and holes are trapped in the HZO layer. V of the device due to dominant charge trapping effect_TWas moved to-1.5V. After 1V voltage sweep, V_TBegin moving (decreasing) towards positive values. The charge trapping memory window peaks when the scan voltage increases to around 3V. As the voltage continues to rise, the domain inversion behavior begins to dominate the performance of the device (V)_TA negative shift).

The ferroelectric memory device provided by the embodiment of the invention is combined with the FinFET of the current mainstream advanced CMOS process device, and the excellent array-level performance and the higher-density memory can be realized based on the FinFET device.

Based on the above analysis, the ferroelectric memory device provided by the embodiment of the present invention writes data by using the gate voltage, and the writing process has no power consumption, which is beneficial to the implementation of a low power consumption system. And the paths of the ferroelectric memory device for reading/writing are independent, and the realization of a circuit level memory system based on the Fe-FET device is facilitated by depending on the design basis of the existing CMOS circuit.

The ferroelectric memory device provided by the embodiment of the invention realizes the reconfigurable scheme by only depending on the grid voltage, not only does not cause the increase of power consumption, but also does not need additional configuration voltage, thereby greatly reducing the power consumption of the device and the system.

It is understood that the ferroelectric memory device in embodiments of the present invention may be a PMOS device or an NMOS device.

The invention also provides a preparation method of the ferroelectric field effect transistor, which comprises the following steps:

providing a substrate; forming an active doping region and a drain doping region in the substrate;

forming a barrier layer, a gate dielectric layer and a metal gate on the substrate in sequence; the gate dielectric layer is a material layer with electric domain inversion and charge trapping capacity.

Compared with the prior art, the beneficial effects of the preparation method of the ferroelectric field effect transistor provided by the invention are the same as those of the ferroelectric field effect transistor provided by the embodiment of the invention, and the details are not repeated herein.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.