阅读说明：本技术 一种衬底电荷耦合的1200v体硅ldmos及其制备方法 (1200V bulk silicon LDMOS with substrate charge coupled and preparation method thereof ) 是由 张龙 崔永久 马杰 王肖娜 袁帅 祝靖 孙伟锋 时龙兴 于 2021-09-09 设计创作，主要内容包括：本发明是一种衬底电荷耦合的1200V体硅LDMOS及其制备方法,在P型衬底上设有N型SN埋层,在N型SN埋层上方且靠近漏极侧设有N型DN埋层,在N型SN埋层上方且靠近源极侧设有5个P型BP埋层。P型BP埋层和N型DN埋层上方设有P型P-well体区、N型漂移区和N型N-well缓冲层。漂移区上方设有场氧化层、多晶硅栅、二氧化硅氧化层和金属场板,其中金属场板横跨于场氧化层上方,多晶硅栅自源极N型重掺杂区上方经过P型P-well体区,延伸至场氧化层上方。源极N型重掺杂区和源极P型重掺杂区通过源极金属和源极相连,漏极N型重掺杂区通过漏极金属和漏极相连。本发明结构在低衬底电阻率的衬底材料下即可实现1200V的耐压需求。(The invention relates to a substrate charge-coupled 1200V bulk silicon LDMOS and a preparation method thereof.A P-type substrate is provided with an N-type SN buried layer, an N-type DN buried layer is arranged above the N-type SN buried layer and close to the drain side, and 5P-type BP buried layers are arranged above the N-type SN buried layer and close to the source side. And a P-type P-well body region, an N-type drift region and an N-type N-well buffer layer are arranged above the P-type BP buried layer and the N-type DN buried layer. A field oxide layer, a polysilicon gate, a silicon dioxide oxide layer and a metal field plate are arranged above the drift region, wherein the metal field plate stretches over the field oxide layer, and the polysilicon gate passes through the P-well body region from the upper part of the source N-type heavily doped region and extends to the upper part of the field oxide layer. The source N-type heavily doped region and the source P-type heavily doped region are connected with the source through source metal, and the drain N-type heavily doped region is connected with the drain through drain metal. The structure of the invention can realize the requirement of 1200V voltage resistance under the substrate material with low substrate resistivity.)

1. The 1200V bulk silicon LDMOS with the charge-coupled substrate is characterized by comprising a P-type substrate (1), wherein an N-type SN buried layer (16) is arranged in the P-type substrate (1), an N-type DN buried layer (3) is arranged above the N-type SN buried layer (16) and close to the drain side, 5P-type BP buried layers (2) are arranged above the N-type SN buried layer (16) and close to the source side, a P-well body region (4), an N-type drift region (9) and an N-type N-well buffer layer (7) are arranged above the P-type BP buried layer (2) and the N-type DN buried layer (3), a source N-type heavily doped region (6) and a source P-type heavily doped region (5) are arranged in the P-type P-well body region (4), and a drain N-type heavily doped region (8) is arranged in the N-type N-well buffer layer (7); a field oxide layer (14), a polysilicon gate (11), a silicon dioxide oxide layer (13) and a metal field plate (12) are arranged above the N-type drift region (9), wherein the metal field plate (12) stretches over the field oxide layer (14), and the polysilicon gate (11) extends from the upper part of the source N-type heavily doped region (6) to the upper part of the field oxide layer (14) through the P-well body region (4); the source N-type heavily doped region (6) and the source P-type heavily doped region (5) are connected with the source through source metal (10), and the drain N-type heavily doped region (8) is connected with the drain through drain metal (15).

2. The substrate charge-coupled 1200V bulk silicon LDMOS as claimed in claim 1, wherein the N-type SN buried layer (16) is formed by two epitaxial ion implantations, and the thicknesses of the two epitaxial ions are 6.0-8.0 μm respectively.

3. The substrate charge-coupled 1200V bulk silicon LDMOS as claimed in claim 1 or 2, wherein the N-type SN buried layer (16) has an ion implantation window width of 2.0-2.5 μm and a spacing between adjacent ion implantation windows of 16.0-18.0 μm.

4. The method for preparing the substrate charge-coupled 1200V bulk silicon LDMOS as claimed in claim 1, comprising the specific steps of:

step 1: after N-type ion implantation is carried out on a P-type substrate (1), a P-type epitaxial layer with the thickness of 8um is grown for the first time;

step 2: after N-type ion implantation is carried out on the P-type epitaxial layer grown for the first time, the P-type epitaxial layer with the thickness of 8um is grown for the second time;

and step 3: after N-type ion implantation is carried out on the P-type epitaxial layer grown for the second time, an N-type SN buried layer (16) is formed through annealing, and then the P-type epitaxial layer with the thickness of 6um is grown for the third time;

and 4, step 4: after N-type ion implantation is carried out on the P-type epitaxial layer grown for the third time, annealing to form an N-type DN buried layer (3), after P-type ion implantation is carried out on the P-type epitaxial layer grown for the third time, annealing to form a P-type BP buried layer (2), and then growing a P-type epitaxial layer with the thickness of 6um for the fourth time;

and 5: after N-type ion implantation is carried out on the P-type epitaxial layer grown for the fourth time, annealing to form an N-type drift region (9), then continuing to carry out N-type ion implantation, and annealing to form an N-type N-well buffer layer (7);

step 6: after P-type ion implantation is carried out on the fourth-grown P-type epitaxial layer, a P-type P-well body region (4) is formed by annealing;

and 7: oxidizing and etching the surface of the silicon area to form a field oxide layer (14), oxidizing and etching to form a gate oxide layer, depositing and etching to form a polysilicon gate (11);

and 8: self-aligning N-type ion implantation is carried out on the surface of the silicon area to form a source N-type heavily doped region (6) and a drain N-type heavily doped region (8); self-aligning P-type ion implantation is carried out on the surface of the silicon area to form a source P-type heavily doped area (5);

and step 9: oxidizing and growing a silicon dioxide oxide layer (13) on the surface of the silicon area, etching the silicon dioxide oxide layer to form a contact hole, then depositing metal aluminum, and etching the metal aluminum to form a drain contact, a source contact and a metal field plate of the device;

step 10: continuously oxidizing and growing a silicon dioxide oxide layer (13) on the surface of the silicon area, etching the silicon dioxide oxide layer to form a contact hole, then depositing metal aluminum, and etching the metal aluminum to form a drain contact and a source contact of the device;

step 11: and depositing metal aluminum on the silicon dioxide oxide layer (13), and etching the metal aluminum to form a drain electrode and a source electrode of the device.

Technical Field

The invention relates to the technical field of power semiconductor devices, in particular to a 1200V bulk silicon LDMOS (lateral double-diffusion MOS transistor) with substrate charge coupling and a preparation method thereof.

Background

With the development of power semiconductor technology, high-voltage integrated circuits are widely applied to the fields of power switches, motor drives, automobile electronics, new energy power generation and the like. One of the key technical designs in high voltage integrated circuits is the design of high voltage LDMOS devices. High voltage bulk silicon LDMOS has been widely used in high voltage integrated circuits due to its relatively simple process and compatibility with other processes. For a 1200V high voltage integrated circuit, an LDMOS with a voltage class of 1200V is required to implement the level shifting function. Since the requirement for the LDMOS breakdown voltage is high in the 1200V breakdown voltage class, it is necessary to consider both the lateral breakdown voltage and the vertical breakdown voltage when designing 1200V. For the design requirement of the lateral voltage resistance, the voltage resistance can be improved by adopting a field plate, a RESURF technology, a field limiting ring and other terminal technologies. For the design of the vertical withstand voltage, the most common technology at present is to increase the substrate resistivity to meet the demand of the vertical withstand voltage. However, the substrate material with high substrate resistivity has the disadvantages of high price and poor uniformity. Therefore, 1200V bulk silicon LDMOS with high voltage endurance is urgently needed to be researched.

Disclosure of Invention

The technical problem is as follows: the invention provides a substrate charge-coupled 1200V bulk silicon LDMOS and a preparation method thereof, aiming at the problems, and the substrate charge-coupled 1200V bulk silicon LDMOS is used for preparing a 1200V bulk silicon LDMOS with high voltage endurance capability.

The technical scheme is as follows: the 1200V bulk silicon LDMOS with the charge-coupled substrate comprises a P-type substrate, wherein an N-type SN buried layer is arranged in the P-type substrate, an N-type DN buried layer is arranged above the N-type SN buried layer and close to the drain side, 5P-type BP buried layers are arranged above the N-type SN buried layer and close to the source side, a P-well body region, an N-type drift region and an N-type N-well buffer layer are arranged above the P-type BP buried layer and the N-type DN buried layer, a source N-type heavily doped region and a source P-type heavily doped region are arranged in the P-type P-well body region, and a drain N-type heavily doped region is arranged in the N-type N-well buffer layer; a field oxide layer, a polysilicon gate, a silicon dioxide oxide layer and a metal field plate are arranged above the N-type drift region, wherein the metal field plate stretches over the field oxide layer, and the polysilicon gate extends to the upper part of the field oxide layer from the upper part of the source N-type heavily doped region through the P-well body region; the source N-type heavily doped region and the source P-type heavily doped region are connected with the source through source metal, and the drain N-type heavily doped region is connected with the drain through drain metal.

The N-type SN buried layer is formed by two times of epitaxial ion implantation, and the thicknesses of the two times of epitaxy are 6.0-8.0 um respectively.

The window width of the N-type SN buried layer during ion implantation is 2.0-2.5 um, and the distance between adjacent ion implantation windows is 16.0-18.0 um.

The preparation method of the 1200V bulk silicon LDMOS with the substrate charge coupled comprises the following specific steps:

step 1: after N-type ion implantation is carried out on a P-type substrate, a P-type epitaxial layer with the thickness of 8um is grown for the first time;

step 2: after N-type ion implantation is carried out on the P-type epitaxial layer grown for the first time, the P-type epitaxial layer with the thickness of 8um is grown for the second time;

and step 3: after N-type ion implantation is carried out on the P-type epitaxial layer grown for the second time, annealing is carried out to form an N-type SN buried layer, and then the P-type epitaxial layer with the thickness of 6 microns is grown for the third time;

and 4, step 4: carrying out N-type ion implantation on the P-type epitaxial layer grown for the third time, annealing to form an N-type DN buried layer, carrying out P-type ion implantation on the P-type epitaxial layer grown for the third time, annealing to form a P-type BP buried layer, and then growing a P-type epitaxial layer with the thickness of 6um for the fourth time;

and 5: after N-type ion implantation is carried out on the P-type epitaxial layer grown for the fourth time, annealing to form an N-type drift region, then continuing to carry out N-type ion implantation, and annealing to form an N-type N-well buffer layer;

step 6: after P-type ion implantation is carried out on the fourth-grown P-type epitaxial layer, a P-type P-well body region is formed through annealing;

and 7: oxidizing and etching the surface of the silicon area to form a field oxide layer, oxidizing and etching to form a gate oxide layer, depositing and etching to form a polysilicon gate;

and 8: self-aligning N-type ion implantation is carried out on the surface of the silicon area to form a source N-type heavily doped area and a drain N-type heavily doped area; self-aligning P-type ion implantation is carried out on the surface of the silicon area to form a source P-type heavily doped area;

and step 9: oxidizing and growing a silicon dioxide oxide layer on the surface of the silicon area, etching the silicon dioxide oxide layer to form a contact hole, then depositing metal aluminum, and etching the metal aluminum to form a drain contact, a source contact and a metal field plate of the device;

step 10: continuously oxidizing and growing a silicon dioxide oxide layer on the surface of the silicon area, etching the silicon dioxide oxide layer to form a contact hole, then depositing metal aluminum, and etching the metal aluminum to form a drain contact and a source contact of the device;

step 11: and depositing metal aluminum on the silicon dioxide oxide layer, and etching the metal aluminum to form a drain electrode and a source electrode of the device.

Has the advantages that: compared with the prior art, the structure of the invention has the following advantages:

1. the invention can realize the 1200V withstand voltage requirement under the substrate material with low substrate resistivity through the substrate charge coupling structure. Under the low substrate resistivity substrate material, the longitudinal withstand voltage (BVV) of the device is less than 1200V, although the lateral withstand voltage (BVL) of the device can be improved by lengthening the drift region length of the device and adopting a termination technology, so that the value of the BVL is more than 1200V, BVV <1200V < BVL, therefore the device breaks down in vivo when the voltage is less than 1200V, the final BV of the device is less than 1200V, and therefore, a substrate material with high substrate resistivity is required to make the BV of bulk silicon LDMOS more than 1200V. By adopting the SN buried layer with charge coupling effect, the distribution of the longitudinal electric field of the drain terminal can be changed from triangular distribution to rectangular distribution on the basis of low substrate resistivity, and the longitudinal withstand voltage of the device is further improved. Therefore, the structure of the invention can realize the requirement of 1200V withstand voltage under the substrate material with low substrate resistivity.

2. The scheme of the invention reduces the cost of the substrate material and improves the uniformity of the substrate material by using the substrate material with low substrate resistivity. Meanwhile, the scheme of the invention is completely compatible with the current process, and the difficulty of the manufacturing process is not increased.

Drawings

Fig. 1 shows a structure of a 1200V bulk silicon LDMOS of the present invention.

Fig. 2 is a schematic diagram showing the longitudinal electric field distribution at the drain end of the structure of the present invention and the conventional structure.

Fig. 3 is a graph showing the breakdown characteristics of the structure of the present invention and the conventional mechanism.

The figure shows that: the structure comprises a P-type substrate 1, a P-type BP buried layer 2, an N-type DN buried layer 3, a P-type P-well body region 4, a source P-type heavily doped region 5, a source N-type heavily doped region 6, an N-type N-well buffer layer 7, a drain N-type heavily doped region 8, an N-type drift region 9, source metal 10, a polysilicon gate 11, a metal field plate 12, a silicon dioxide oxide layer 13, a field oxide layer 14, drain metal 15 and an N-type SN buried layer 16.

Detailed Description

The present invention will be described in detail with reference to the accompanying drawings.

The 1200V bulk silicon LDMOS with the substrate charge coupled comprises a P-type substrate 1, wherein an N-type SN buried layer 16 is arranged on the P-type substrate 1, an N-type DN buried layer 3 is arranged above the N-type SN buried layer 16 and close to the drain side, and 5P-type BP buried layers 2 are arranged above the N-type SN buried layer 16 and close to the source side. A P-type P-well body region 4, an N-type drift region 9 and an N-type N-well buffer layer 7 are arranged above the P-type BP buried layer 2 and the N-type DN buried layer 3, wherein a source N-type heavily doped region 6 and a source P-type heavily doped region 5 are arranged in the P-type P-well body region 4, and a drain N-type heavily doped region 8 is arranged in the N-type N-well buffer layer 7. A field oxide layer 14, a polysilicon gate 11, a silicon dioxide oxide layer 14 and a metal field plate 12 are arranged above the N-type drift region 9, wherein the metal field plate 12 crosses over the field oxide layer 14, and the polysilicon gate 11 passes through the P-well body region 4 from above the source N-type heavily doped region 6 and extends to above the field oxide layer 14. The source N-type heavily doped region 6 and the source P-type heavily doped region 5 are connected with the source through a source metal 10, and the drain N-type heavily doped region 8 is connected with the drain through a drain metal 15.

The N-type SN buried layer 16 is formed by two times of epitaxial ion implantation, and the thickness of the two times of epitaxy is 8 um.

The window width of the N-type SN buried layer 16 during ion implantation is 2.0-2.5 um, and the distance between adjacent ion implantation windows is 16.0-18.0 um.

The preparation method of the substrate charge-coupled 1200V bulk silicon LDMOS comprises the following specific steps:

step 1: after N-type ion implantation is carried out on a P-type substrate 1, a P-type epitaxial layer with the thickness of 8um is grown for the first time;

step 2: after N-type ion implantation is carried out on the P-type epitaxial layer grown for the first time, the P-type epitaxial layer with the thickness of 8um is grown for the second time;

and step 3: after N-type ion implantation is carried out on the P-type epitaxial layer grown for the second time, annealing is carried out to form an N-type SN buried layer 16, and then the P-type epitaxial layer with the thickness of 6 microns is grown for the third time;

and 4, step 4: after N-type ion implantation is carried out on the P-type epitaxial layer grown for the third time, annealing to form an N-type DN buried layer 3, after P-type ion implantation is carried out on the P-type epitaxial layer grown for the third time, annealing to form a P-type BP buried layer 2, and then growing a P-type epitaxial layer with the thickness of 6um for the fourth time;

and 5: after N-type ion implantation is carried out on the P-type epitaxial layer grown for the fourth time, annealing to form an N-type drift region 9, then continuing to carry out N-type ion implantation, and annealing to form an N-type N-well buffer layer 7;

step 6: after P-type ion implantation is carried out on the fourth-grown P-type epitaxial layer, annealing is carried out to form a P-well body region 4;

and 7: oxidizing and etching the surface of the silicon region to form a field oxide layer 14, oxidizing and etching to form a gate oxide layer, depositing and etching to form a polysilicon gate 11;

and 8: self-aligning N-type ion implantation is carried out on the surface of the silicon region to form a source N-type heavily doped region 6 and a drain N-type heavily doped region 8; self-aligning P-type ion implantation is carried out on the surface of the silicon region to form a source P-type heavily doped region 5;

and step 9: oxidizing and growing a silicon dioxide oxide layer 13 on the surface of the silicon area, etching the silicon dioxide to form a contact hole, then depositing metal aluminum, and etching the metal aluminum to form a drain contact, a source contact and a metal field plate of the device;

step 10: continuously oxidizing and growing a silicon dioxide oxide layer 13 on the surface of the silicon area, etching the silicon dioxide to form a contact hole, then depositing metal aluminum, and etching the metal aluminum to form a drain contact and a source contact of the device;

step 11: and depositing metal aluminum on the silicon dioxide oxide layer 13, and etching the metal aluminum to form a drain electrode and a source electrode of the device.

The invention is further described below with reference to the accompanying drawings.

For a bulk silicon LDMOS of 1200V, the voltage resistance of the bulk silicon LDMOS consists of a longitudinal voltage resistance (BVV) and a transverse voltage resistance (BVL). When BVV <1200V < BVL, the breakdown voltage BV of the device at this time is <1200V, and the breakdown point at this time is located within the body of the device. When BVL <1200V < BVV, the breakdown voltage BV of the device at this time is <1200V, and the breakdown point at this time is at the device surface. Therefore, for the breakdown voltage BV >1200V of the device, BVV >1200V and BVL >1200V need to be satisfied. The longitudinal withstand voltage of the device is mainly determined by the resistivity of the substrate, and the higher the resistivity of the substrate is, the higher the longitudinal withstand voltage of the device is. The substrate charge-coupled 1200V bulk silicon LDMOS provided by the invention is additionally provided with an N-type SN buried layer 16 formed by three times of ion implantation on the basis of the traditional 1200V bulk silicon LDMOS. The introduction of the SN buried layer 16 can assist the depletion between the P-type substrate 1 and the SN buried layer 16, and promote the transition of the distribution of the longitudinal electric field from the triangular electric field distribution to the rectangular electric field distribution. Fig. 2 is a schematic diagram showing the electric field distribution at the drain end of the structure of the present invention and the conventional structure, and as shown in the figure, the longitudinal electric field distribution of the structure of the present invention is more approximate to rectangular distribution than the conventional structure, and the area under the line surrounded by the electric field distribution is larger, so that the structure of the present invention has higher longitudinal withstand voltage. Under the condition of keeping the length of the drift region and the design of the terminal unchanged, the breakdown voltage of the device is obviously improved due to the improvement of the longitudinal withstand voltage of the structure. As shown in FIG. 3, under the condition of the same substrate resistivity, the breakdown voltage of the structure of the invention is 1529V, and the breakdown voltage of the traditional structure is 1094V, which is improved by 39.7 percent on a same scale.

Meanwhile, the epitaxial ion implantation technology adopted by the SN buried layer is completely compatible with the current production technology, the current production technology can be directly utilized, the difficulty of the production technology is not increased, and certain feasibility is realized.