阅读说明：本技术 一种SiC LDMOS器件及其制作方法 (SiC LDMOS device and manufacturing method thereof ) 是由 杜蕾 和巍巍 汪之涵 喻双柏 张振中 于 2021-09-26 设计创作，主要内容包括：本申请提供了一种SiC LDMOS器件及其制作方法。其中,SiC LDMOS器件包括SiC衬底、P阱区、N阱区、源区P+、源区N+、漏区N+、栅氧化层、多晶硅栅和SiN场氧层,SiN场氧层覆于SiC衬底与N阱区对应的表面,SiN场氧层靠近源区N+的边缘与N阱区靠近源区N+的边缘对齐,SiN场氧层靠近漏区N+的一侧具有斜面,SiN场氧层靠近漏区N+的边缘与漏区N+靠近源区N+的边缘对齐,栅氧化层覆于SiC衬底未覆有SiN场氧层的表面,多晶硅栅覆于栅氧化层与P阱区对应的表面,多晶硅栅靠近漏区N+的边缘与SiN场氧层靠近源区N+的边缘相接,多晶硅栅远离漏区N+的一侧与源区N+靠近漏区N+的一侧交叠。本申请能够实现更小的Cgd,甚至能够完全消除Cgd,进而能够有效地提升LDMOS器件的开关频率和性能。(The application provides a SiC LDMOS device and a manufacturing method thereof. The SiC LDMOS device comprises a SiC substrate, a P well region, an N well region, a source region P +, a source region N +, a drain region N +, a gate oxide layer, a polysilicon gate and an SiN field oxide layer, wherein the SiN field oxide layer covers the surface of the SiC substrate corresponding to the N well region, the edge of the SiN field oxide layer close to the source region N + is aligned with the edge of the N well region close to the source region N +, an inclined surface is arranged on one side of the SiN field oxide layer close to the drain region N +, the edge of the SiN field oxide layer close to the drain region N + is aligned with the edge of the drain region N + close to the source region N +, the gate oxide layer covers the surface of the SiC substrate not covered with the SiN field oxide layer, the polysilicon gate covers the surface of the gate oxide layer corresponding to the P well region, the edge of the polysilicon gate close to the drain region N + is connected with the edge of the SiN field oxide layer close to the source region N +, and one side of the polysilicon gate far away from the drain region N + is overlapped with one side of the source region N + close to the drain region N +. The method and the device can realize smaller Cgd, even eliminate Cgd completely, and further can effectively improve the switching frequency and performance of the LDMOS device.)

1. A SiC LDMOS device comprises a SiC substrate, a P well region, an N well region, a source region P +, a source region N + and a drain region N +, wherein the inside of the SiC substrate is divided into the P well region and the N well region which are connected, the source region P + and the source region N + cover the inner surface of the SiC substrate and are both positioned at the position of the P well region far away from the N well region, the source region P + and the source region N + are sequentially arranged along the direction of the P well region pointing to the N well region, the drain region N + covers the inner surface of the SiC substrate and is positioned at the position of the N well region far away from the P well region, and the N well region is a drift region of the SiC LDMOS device;

it is characterized in that the SiC LDMOS device further comprises a gate oxide layer, a polysilicon gate and a SiN field oxide layer, the SiN field oxide layer covers the surface of the SiC substrate corresponding to the N well region, the edge of the SiN field oxide layer close to the source region N + is aligned with the edge of the N well region close to the source region N +, one side of the SiN field oxide layer, which is close to the drain region N +, is provided with an inclined surface, the edge of the SiN field oxide layer, which is close to the drain region N +, is aligned with the edge of the drain region N +, which is close to the source region N +, the gate oxide layer covers the surface of the SiC substrate which is not covered with the SiN field oxide layer, the polysilicon gate covers the surface of the gate oxide layer corresponding to the P well region, the edge of the polysilicon gate close to the drain region N + is connected with the edge of the SiN field oxide layer close to the source region N +, one side of the polysilicon gate, which is far away from the drain region N +, is overlapped with one side of the source region N +, which is close to the drain region N +.

2. The SiC LDMOS device of claim 1, further comprising a first SiO₂Layer of the first SiO₂The layer covers the polysilicon gate, the SiN field oxide layer and the gate oxide layer.

3. The SiC LDMOS device of claim 2 further comprising a polysilicon field plate overlying the first SiO layer₂A surface corresponding to the SiN field oxide layer;

when the first SiO is₂When the thickness of the layer is lower than a first reference value, a preset distance is reserved between the edge of the polycrystalline silicon field plate close to the source region N + and the edge of the polycrystalline silicon gate close to the drain region N +, and the preset distance is larger than the first reference value and smaller than a second reference value; the first reference value is the thickness of the gate oxide layer, and the second reference value is the distance between the edge of the polycrystalline silicon field plate close to the drain region N + and the edge of the SiN field oxide layer close to the source region N +;

when the first SiO is₂When the thickness of the layer is higher than the first reference value, a gap is formed between the edge of the polycrystalline silicon field plate close to the source region N + and the edge of the polycrystalline silicon gate close to the drain region N +, or one side of the polycrystalline silicon field plate close to the source region N + is overlapped with one side of the polycrystalline silicon gate close to the drain region N +.

4. A method for manufacturing a SiC LDMOS device, characterized by being applied to the SiC LDMOS device of any one of claims 1 to 3; the manufacturing method of the SiC LDMOS device comprises the following steps:

forming an N well region in the SiC substrate through a deposition process, a photoetching process, an etching process and an ion implantation process, and forming a P well region in the SiC substrate through the deposition process, a chemical mechanical polishing process, a wet etching process and the ion implantation process; the N well region is connected with the P well region, and the N well region is a drift region of the SiC LDMOS device;

forming a source region P +, a source region N + and a drain region N + on the inner surface of the SiC substrate through a photoetching process, a wet etching process, an ion implantation process and an annealing process, and forming an SiN field oxide layer on the surface of the SiC substrate corresponding to the N well region; the source region P + and the source region N + are both positioned at the position, far away from the N well region, of the P well region, the source region P + and the source region N + are sequentially arranged along the direction, pointing to the N well region, of the P well region, the drain region N + is positioned at the position, far away from the P well region, of the N well region, the edge, close to the source region N +, of the SiN field oxide layer is aligned with the edge, close to the source region N +, of the N well region, the side, close to the drain region N + of the SiN field oxide layer is provided with an inclined surface, and the edge, close to the drain region N +, of the SiN field oxide layer is aligned with the edge, close to the source region N +, of the drain region N +;

forming a gate oxide layer on the surface of the SiC substrate on which the SiN field oxide layer is not formed through a gate oxidation process;

forming a polysilicon gate on the surface of the gate oxide layer corresponding to the P well region through a deposition process, a chemical mechanical polishing process, a photoetching process and a dry etching process; the edge of the polysilicon gate close to the drain region N + is connected with the edge of the SiN field oxide layer close to the source region N +, and one side of the polysilicon gate, far away from the drain region N +, is overlapped with one side of the source region N + close to the drain region N +.

5. The method for manufacturing the SiC LDMOS device as set forth in claim 4, wherein the forming of the N-well region inside the SiC substrate by the deposition process, the photolithography process, the etching process, and the ion implantation process includes:

depositing SiO on the surface of the SiC substrate by a deposition process₂Forming a second SiO₂A layer;

realizing the pattern transfer from the corresponding mask plate to the first photoresist of the N well region through a photoetching process and an etching process; wherein the first photoresist covers the second SiO₂A surface of the layer;

removing the first photoresist, and performing ion implantation to obtain the second SiO₂The layer is used as a barrier layer, nitrogen ions are injected, and the N well region is formed in the SiC substrate;

wherein the second SiO₂And the layer covers the surface of the SiC substrate, which is not corresponding to the N well region.

6. The method for manufacturing the SiC LDMOS device of claim 5, wherein the forming the P-well region inside the SiC substrate through a deposition process, a chemical mechanical polishing process, a wet etching process and an ion implantation process comprises:

depositing SiN on the surface of the SiC substrate through a deposition process to form a SiN layer; wherein the thickness of the SiN layer is higher than that of the second SiO₂Thickness of layer, the SiN layer covering the second SiO₂A layer;

grinding the SiN layer through a chemical mechanical polishing process; wherein, after grinding, the thickness of the SiN layer and the second SiO₂The SiN layers are the same, and cover the surfaces of the SiC substrate corresponding to the N well regions;

etching the second SiO layer by wet etching₂Etching the layer; wherein, after etching, the second SiO₂The layer is removed;

and forming the P well region in the SiC substrate by taking the SiN layer as a self-aligned mask of the P well region through an ion implantation process and implanting aluminum ions.

7. The method for manufacturing the SiC LDMOS device as set forth in claim 6, wherein the forming of the source region P +, the source region N + and the drain region N + on the inner surface of the SiC substrate and the forming of the SiN field oxide layer on the surface of the SiC substrate corresponding to the N well region by the photolithography process, the wet etching process, the ion implantation process and the annealing process comprises:

carrying out photoetching on N < + > through a photoetching process; wherein a second photoresist covers a portion of the surface of the SiC substrate and a portion of the SiN layer;

corroding the SiN layer by a wet corrosion process; after etching, removing the part of the SiN layer which is not covered by the second photoresist, wherein the inclined surface is formed at the joint between the reserved part and the removed part of the SiN layer, and the reserved part of the SiN layer forms a SiN field oxide layer;

injecting phosphorus ions through an ion injection process, and forming a source region N + and a drain region N + on the inner surface of the SiC substrate;

removing the second photoresist, and carrying out P + photoetching through a photoetching process; wherein a third photoresist covers a portion of the surface of the SiC substrate and the SiN field oxide layer;

injecting aluminum ions through an ion injection process, and forming a source region P + on the inner surface of the SiC substrate; wherein the edge of the source region P + close to the drain region N + is aligned with the edge of the third photoresist far from the drain region N +;

and removing the third photoresist and carrying out high-temperature annealing.

8. The method for manufacturing the SiC LDMOS device as claimed in claim 7, wherein the forming of the polysilicon gate on the surface of the gate oxide layer corresponding to the P-well region through a deposition process, a chemical mechanical polishing process, a photolithography process and a dry etching process comprises:

depositing polycrystalline silicon on the surface of the gate oxide layer through a deposition process to form a first polycrystalline silicon layer; the thickness of the first polycrystalline silicon layer is higher than that of the SiN field oxide layer, and the first polycrystalline silicon layer covers the SiN field oxide layer;

grinding the first polysilicon layer by a chemical mechanical polishing process; after grinding, the thickness of the first polycrystalline silicon layer is the same as that of the SiN field oxide layer;

photoetching the first polysilicon layer through a photoetching process; a fourth photoresist covers a part of the SiN field oxide layer and a part of the first polysilicon layer, one side of the fourth photoresist, which is far away from the drain region N +, is overlapped with one side of the source region N + which is close to the drain region N +, and a gap is formed between the edge of the fourth photoresist, which is far away from the source region N +, and the edge of the drain region N + which is close to the source region N +;

etching the first polysilicon layer by using a dry etching process and an end point detection mode as an etching stop signal, and removing the fourth photoresist; and after etching, removing the part of the first polysilicon layer which is not covered by the fourth photoresist, wherein the remained part of the first polysilicon layer forms a polysilicon gate.

9. The method for manufacturing the SiC LDMOS device set forth in claim 8, wherein after forming the polysilicon gate on the surface of the gate oxide layer corresponding to the P-well region through a deposition process, a chemical mechanical polishing process, a photolithography process and a dry etching process, further comprising:

depositing SiO on the surface of the gate oxide layer by a deposition process₂Forming a first SiO₂A layer; wherein the first SiO₂The layer covers the polysilicon gate and the SiN field oxide layer;

depositing, photoetching and dry etching on the first SiO₂Forming a polysilicon field plate on the surface of the layer corresponding to the SiN field oxide layer;

wherein when the first SiO is₂When the thickness of the layer is lower than a first reference value, a preset distance is reserved between the edge of the polycrystalline silicon field plate close to the source region N + and the edge of the polycrystalline silicon gate close to the drain region N +, and the preset distance is larger than the first reference value and smaller than a second reference value; wherein the first reference value is the thickness of the gate oxide layer, and the second reference value isThe distance between the edge of the polycrystalline silicon field plate close to the drain region N + and the edge of the SiN field oxide layer close to the source region N +;

when the first SiO is₂When the thickness of the layer is higher than the first reference value, a gap is formed between the edge of the polycrystalline silicon field plate close to the source region N + and the edge of the polycrystalline silicon gate close to the drain region N +, or one side of the polycrystalline silicon field plate close to the source region N + is overlapped with one side of the polycrystalline silicon gate close to the drain region N +.

10. The method for manufacturing the SiC LDMOS device of claim 9, wherein the first SiO is formed by a deposition process, a photolithography process and a dry etching process₂The surface of the layer corresponding to the SiN field oxide layer forms a polysilicon field plate, comprising:

by a deposition process on the first SiO₂Depositing polycrystalline silicon on the surface of the layer to form a second polycrystalline silicon layer;

photoetching the second polysilicon layer through a photoetching process; the fifth photoresist covers the surfaces of the second polycrystalline silicon layer corresponding to the SiN field oxide layer;

etching the second polysilicon layer by using a dry etching process and an end point detection mode as an etching stop signal, and removing the fifth photoresist; and after etching, removing the part of the second polysilicon layer which is not covered by the fifth photoresist, wherein the remained part of the second polysilicon layer forms a polysilicon field plate.

[ technical field ] A method for producing a semiconductor device

The application relates to the technical field of power electronic devices, in particular to a SiC LDMOS device and a manufacturing method thereof.

[ background of the invention ]

In the related art, SiC (Silicon Carbide) has more than three times of Si (Silicon Carbide) as characteristic indexes of forbidden bandwidth, critical breakdown electric Field, thermal conductivity, carrier saturation drift velocity, and the like, so SiC has become an excellent material for manufacturing power electronic devices, such as LDMOS (Metal-Diffused-Metal-Oxide-Semiconductor) devices, MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) devices, and the like. Compared with the MOSFET device, the LDMOS device has the advantages of high gain, wide linear range, small distortion and the like; moreover, the Source region, Bulk region, Gate region and Drain region of the LDMOS device are all located on the surface of the wafer, which is convenient for further manufacturing the integrated circuit.

In the traditional manufacturing method of the LDMOS device, on one hand, a well region and a FOX (Field Oxide) layer are manufactured according to two different photoetching processes, and in order to avoid mutual shielding, the well region needs to exceed the FOX by a small distance so as to ensure the normal opening of a channel; on the other hand, in order to ensure the voltage withstanding property of the lateral LDMOS device, Gate Poly (polysilicon Gate) needs to be covered on FOX for a short distance to form Resurf field plate. Due to the two reasons, a section of Cgd (staggered overlap capacitance) is formed between the Gate Poly and the well region, and the existence of the Cgd can reduce the switching frequency of the LDMOS device and affect the performance of the LDMOS device.

Therefore, there is a need for improved structures and methods of fabricating such LDMOS devices.

[ summary of the invention ]

The application provides a SiC LDMOS device and a manufacturing method thereof, and aims to solve the problems that in the related art, the switching frequency of the LDMOS device is low and the performance is poor.

In order to solve the above technical problem, a first aspect of the embodiments of the present application provides a SiC LDMOS device, including a SiC substrate, a P-well region, an N-well region, a source region P +, a source region N + and a drain region N +, where the inside of the SiC substrate is divided into the P-well region and the N-well region that are connected, the source region P + and the source region N + both cover an inner surface of the SiC substrate and are both located at a position where the P-well region is far away from the N-well region, the source region P + and the source region N + are sequentially arranged along a direction in which the P-well region points to the N-well region, the drain region N + covers an inner surface of the SiC substrate and is located at a position where the N-well region is far away from the P-well region, and the N-well region is a drift region of the SiC LDMOS device;

the SiC LDMOS device also comprises a gate oxide layer, a polysilicon gate and a SiN field oxide layer, the SiN field oxide layer covers the surface of the SiC substrate corresponding to the N well region, the edge of the SiN field oxide layer close to the source region N + is aligned with the edge of the N well region close to the source region N +, one side of the SiN field oxide layer, which is close to the drain region N +, is provided with an inclined surface, the edge of the SiN field oxide layer, which is close to the drain region N +, is aligned with the edge of the drain region N +, which is close to the source region N +, the gate oxide layer covers the surface of the SiC substrate which is not covered with the SiN field oxide layer, the polysilicon gate covers the surface of the gate oxide layer corresponding to the P well region, the edge of the polysilicon gate close to the drain region N + is connected with the edge of the SiN field oxide layer close to the source region N +, one side of the polysilicon gate, which is far away from the drain region N +, is overlapped with one side of the source region N +, which is close to the drain region N +.

A second aspect of the embodiments of the present application provides a method for manufacturing a SiC LDMOS device, which is applied to the SiC LDMOS device provided in the first aspect of the embodiments of the present application; the manufacturing method of the SiC LDMOS device comprises the following steps:

forming an N well region in the SiC substrate through a deposition process, a photoetching process, an etching process and an ion implantation process, and forming a P well region in the SiC substrate through the deposition process, a chemical mechanical polishing process, a wet etching process and the ion implantation process; the N well region is connected with the P well region, and the N well region is a drift region of the SiC LDMOS device;

forming a source region P +, a source region N + and a drain region N + on the inner surface of the SiC substrate through a photoetching process, a wet etching process, an ion implantation process and an annealing process, and forming an SiN field oxide layer on the surface of the SiC substrate corresponding to the N well region; the source region P + and the source region N + are both positioned at the position, far away from the N well region, of the P well region, the source region P + and the source region N + are sequentially arranged along the direction, pointing to the N well region, of the P well region, the drain region N + is positioned at the position, far away from the P well region, of the N well region, the edge, close to the source region N +, of the SiN field oxide layer is aligned with the edge, close to the source region N +, of the N well region, the side, close to the drain region N + of the SiN field oxide layer is provided with an inclined surface, and the edge, close to the drain region N +, of the SiN field oxide layer is aligned with the edge, close to the source region N +, of the drain region N +;

forming a gate oxide layer on the surface of the SiC substrate on which the SiN field oxide layer is not formed through a gate oxidation process;

forming a polysilicon gate on the surface of the gate oxide layer corresponding to the P well region through a deposition process, a chemical mechanical polishing process, a photoetching process and a dry etching process; the edge of the polysilicon gate close to the drain region N + is connected with the edge of the SiN field oxide layer close to the source region N +, and one side of the polysilicon gate, far away from the drain region N +, is overlapped with one side of the source region N + close to the drain region N +.

As can be seen from the above description, the present application has the following advantages compared with the related art:

covering the surface of the SiC substrate corresponding to the N well region with an SiN field oxide layer, and arranging the edge of the SiN field oxide layer close to the source region N + to be aligned with the edge of the N well region close to the source region N +, wherein one side of the SiN field oxide layer close to the drain region N + is provided with an inclined surface, and the edge of the SiN field oxide layer close to the drain region N + is aligned with the edge of the drain region N + close to the source region N +; covering the gate oxide layer on the surface of the SiC substrate which is not covered with the SiN field oxide layer; covering the surface of the gate oxide layer corresponding to the P well region with a polysilicon gate, connecting the edge of the polysilicon gate close to the drain region N + with the edge of the SiN field oxide layer close to the source region N +, and overlapping one side of the polysilicon gate far away from the drain region N + with one side of the source region N + close to the drain region N +. Therefore, the N well region does not need to exceed a small distance of the SiN field oxide layer, and the polysilicon gate does not need to cover the small distance of the SiN field oxide layer, so that smaller Cgd can be achieved, Cgd can be eliminated completely, and switching frequency and performance of LDMOS devices can be effectively improved.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions in the related art or the embodiments of the present application, the drawings needed to be used in the description of the related art or the embodiments of the present application will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, not all embodiments, and other drawings can be obtained by those skilled in the art without inventive efforts.

FIG. 1 is a schematic diagram of a first structure of a conventional LDMOS device;

FIG. 2 is a diagram illustrating a second structure of a conventional LDMOS device;

fig. 3 is a schematic view of a first structure of a SiC LDMOS device provided in an embodiment of the present application;

fig. 4 is a schematic structural diagram of a second SiC LDMOS device provided in an embodiment of the present application;

FIG. 5 is a schematic diagram of a third structure of an SiC LDMOS device provided in the embodiment of the present application;

FIG. 6 is a schematic diagram of a fourth structure of an SiC LDMOS device provided in the embodiment of the present application;

fig. 7 is a schematic structural diagram of a fifth SiC LDMOS device provided in an embodiment of the present application;

fig. 8 is a first schematic flowchart of a method for manufacturing a SiC LDMOS device according to an embodiment of the present application;

FIG. 9 is a schematic flow chart of step 801 of FIG. 8 according to an embodiment of the present application;

fig. 10 is a schematic view of a first structure of a SiC LDMOS device provided in an embodiment of the present application during a manufacturing process;

fig. 11 is a schematic structural diagram of a second SiC LDMOS device provided in an embodiment of the present application during a manufacturing process;

fig. 12 is a schematic structural diagram of a third SiC LDMOS device provided in an embodiment of the present application during a manufacturing process;

fig. 13 is a schematic diagram of a fourth structure of a SiC LDMOS device provided in an embodiment of the present application during a manufacturing process;

fig. 14 is a schematic structural diagram of a fifth SiC LDMOS device provided in an embodiment of the present application during a manufacturing process;

FIG. 15 is a flowchart illustrating step 802 of FIG. 8 according to an embodiment of the present disclosure;

fig. 16 is a schematic structural diagram of a sixth SiC LDMOS device provided in an embodiment of the present application during a manufacturing process;

fig. 17 is a schematic structural diagram of a seventh SiC LDMOS device provided in an embodiment of the present application during a manufacturing process;

fig. 18 is a schematic structural diagram of an eighth SiC LDMOS device provided in an embodiment of the present application during a manufacturing process;

fig. 19 is a schematic structural diagram of a ninth SiC LDMOS device provided in an embodiment of the present application during a manufacturing process;

fig. 20 is a schematic diagram of a tenth structure of a SiC LDMOS device provided in an embodiment of the present application during a manufacturing process;

FIG. 21 is a flowchart of step 804 of FIG. 8 according to an embodiment of the present application;

fig. 22 is a schematic diagram of an eleventh structure of a SiC LDMOS device provided in an embodiment of the present application during a manufacturing process;

fig. 23 is a schematic diagram of a twelfth structure of a SiC LDMOS device provided in an embodiment of the present application in a manufacturing process;

fig. 24 is a schematic diagram of a thirteenth structure of a SiC LDMOS device provided in an embodiment of the present application during a manufacturing process;

fig. 25 is a second flowchart illustrating a method for manufacturing a SiC LDMOS device according to an embodiment of the present application;

fig. 26 is a schematic diagram of a fourteenth structure of a SiC LDMOS device provided in an embodiment of the application in a manufacturing process;

FIG. 27 is a schematic flow chart diagram illustrating step 806 in FIG. 25 according to an exemplary embodiment of the present disclosure;

fig. 28 is a schematic diagram of a fifteenth structure of a SiC LDMOS device provided in an embodiment of the present application during a manufacturing process;

fig. 29 is a schematic diagram of a sixteenth structure of a SiC LDMOS device provided in an embodiment of the present application during a manufacturing process;

fig. 30 is a seventeenth structural schematic diagram of the SiC LDMOS device provided in the embodiment of the present application in the manufacturing process.

[ detailed description ] embodiments

In order to make the objects, technical solutions and advantages of the present application more apparent and understandable, the present application will be clearly and completely described below in conjunction with the embodiments of the present application and the corresponding drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. It should be understood that the embodiments of the present application described below are only for explaining the present application and are not intended to limit the present application, that is, all other embodiments obtained by a person of ordinary skill in the art without making creative efforts based on the embodiments of the present application belong to the protection scope of the present application. In addition, the technical features involved in the embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

In the traditional manufacturing method of the LDMOS device, on one hand, a well region and a FOX (Field Oxide) layer are manufactured according to two different photoetching processes, and in order to avoid mutual shielding, the well region needs to exceed the FOX by a small distance so as to ensure the normal opening of a channel; on the other hand, in order to ensure the voltage withstanding property of the lateral LDMOS device, Gate Poly (polysilicon Gate) needs to be covered on FOX for a short distance to form Resurf field plate. Due to the two reasons, a section of Cgd (staggered overlap capacitance) is formed between the Gate Poly and the well region, and the existence of the Cgd can reduce the switching frequency of the LDMOS device and affect the performance of the LDMOS device. Therefore, the embodiment of the application provides the SiC LDMOS device.

Before explaining the SiC LDMOS device provided in the embodiment of the present application in detail, please refer to fig. 1 and fig. 2, first briefly describe a conventional LDMOS device; fig. 1 is a schematic diagram of a first structure of a conventional LDMOS device, and fig. 2 is a schematic diagram of a second structure of the conventional LDMOS device.

As shown in FIG. 1, Source&Bulk (i.e. Source and Bulk short), Gate and Drain are all located on the surface of the wafer, so as to facilitate the fabrication of integrated circuits; the Source and Bulk may not adopt a short-circuit structure, that is, may adopt a separate structure. SiO 2₂The field oxide layer is FOX, and the adopted material is SiO₂. The NW is an N well region and is also a drift region of the traditional LDMOS device, and the distance c between the edge of the N + far away from the drain region side and the edge of the N + close to the source region side determines the withstand voltage of the traditional LDMOS device; wherein c is in positive correlation with the voltage resistance of the traditional LDMOS device, and is generally 3-70 μm. GP is polysilicon gate covered on SiO₂The existence of a small distance b (generally 1-6 μm) between the edge of the field oxide layer close to the N + on the drain region side and the edge of the NW close to the N + on the source region side enables a small RF (reduced surface field plate) to be formed on the side of GP close to the N + on the drain region side; when the conventional LDMOS device is in a reverse cut-off high voltage withstanding state and GP is in a low voltage or 0v, positive charge holes are induced at the position corresponding to b, which is equivalent to driving electrons at the positions corresponding to NW and b away from the surface of the wafer, thereby realizing the assistance of NW depletion and improving the RF effect of the conventional LDMOS device voltage withstanding state. During the manufacturing process of the traditional LDMOS device, NW and SiO are adopted₂The field oxide layer is made by two independent photoetching processes, namely SiO₂An alignment margin a (generally 0.5-4 μm) is formed between the edge of the field oxide layer, which is far away from the drain region side N +, and the edge of the NW, which is close to the source region side N +; wherein, if there is no overlay margin a, the structure of the conventional LDMOS device is shown in FIG. 2, i.e., SiO₂The side of the field oxide layer near the source side N + may extend beyond the edge of the NW near the source side N +, resulting in a conventional LDMOS device and channel (the region between the edge of the NW near the source side N + and the edge of the source side N + near the drain side N +, i.e., L and L regions)_chCorresponding region, and L_chGenerally 0.5-5 μm) corresponding to the thickness of GO (gate oxide)The change is obvious, and further the starting voltage of the traditional LDMOS device is influenced. In addition, Metal in fig. 1 and 2 both represent Metal wiring, and SPb both represent SiC substrates.

Referring to fig. 3, fig. 3 is a schematic view of a first structure of a SiC LDMOS device provided in an embodiment of the present application; in order to avoid ambiguity, the source region P +, the source region N +, and the drain region N + are not numbered any more, and will be directly represented by the source region P +, the source region N +, and the drain region N +, as shown in fig. 3, where the number 4 denotes the source region P +, the number 5 denotes the source region N +, and the number 6 denotes the drain region N +. As can be seen from fig. 3, the SiC LDMOS device provided by the embodiment of the present application includes a SiC substrate 1, a P well region 3, an N well region 2, a source region P +, a source region N + and a drain region N +; the SiC substrate 1 is internally divided into a P well region 3 and an N well region 2 which are connected, a source region P + and a source region N + both cover the inner surface of the SiC substrate 1 and are positioned at the positions, far away from the N well region 2, of the P well region 3, the source region P + and the source region N + are sequentially arranged along the direction, pointing to the N well region 2, of the P well region 3, the drain region N + covers the inner surface of the SiC substrate 1 and is positioned at the position, far away from the P well region 3, of the N well region 2, and the N well region 2 is a drift region of the SiC LDMOS device.

Further, the SiC LDMOS device further includes a gate oxide layer 9, a polysilicon gate 8, and a SiN field oxide layer 7; the SiN field oxide layer 7 covers the surface of the SiC substrate 1 corresponding to the N well region 2, the edge, close to a source region N +, of the SiN field oxide layer 7 is aligned with the edge, close to the source region N +, of the N well region 2, an inclined surface is arranged on one side, close to the drain region N +, of the SiN field oxide layer 7, the edge, close to the drain region N +, of the SiN field oxide layer 7 is aligned with the edge, close to the source region N +, of the drain region N +, a gate oxide layer 9 covers the surface, not covered with the SiN field oxide layer 7, of the SiC substrate 1, a polycrystalline silicon gate 8 covers the surface, corresponding to the gate oxide layer 9 and the P well region 3, the edge, close to the drain region N +, of the polycrystalline silicon gate 8 is connected with the edge, close to the source region N +, of the SiN field oxide layer 7, and one side, far away from the drain region N +, of the polycrystalline silicon gate 8 is overlapped with one side, close to the drain region N +. It will be appreciated that the gate oxide layer 9 is divided into two parts, one of which corresponds to the drain region N + and the other of which corresponds to the P-well region 3, the gate oxide layer 9 sandwiching the SiN field oxide layer 7.

It can be seen that the N well region 2 in the embodiment of the present application does not need to exceed the SiN field oxide layer 7 by a small distance, and the polysilicon gate 8 does not need to cover the SiN field oxide layer 7A small distance is equivalent to that a in the conventional LDMOS device is 0, or alternatively, there is no staggered overlap between the polysilicon gate 8 and the N well region 2, so that a smaller Cgd can be realized, and even the Cgd can be completely eliminated, thereby effectively improving the switching frequency and performance of the LDMOS device. In addition, the embodiment of the application also discloses SiO adopted by FOX in the traditional LDMOS device₂The SiN field oxide layer 7 is replaced with SiN for higher dielectric constant.

In some embodiments, please further refer to fig. 4, fig. 4 is a schematic diagram illustrating a second structure of the SiC LDMOS device provided in the embodiments of the present application; the SiC LDMOS device provided by the embodiment of the application can further comprise a first SiO₂Layer 10 of the first SiO₂A layer 10 overlies the polysilicon gate 8, the SiN field oxide layer 7 and the gate oxide layer 9.

Further, the SiC LDMOS device provided by the embodiment of the application may further include a polysilicon field plate 11, where the polysilicon field plate 11 covers the first SiO layer₂The surface of the layer 10 corresponding to the SiN field oxide layer 7.

As an embodiment, still referring to FIG. 4, when the first SiO₂When the thickness of the layer 10 is lower than a first reference value, a first preset distance x is formed between the edge of the polysilicon field plate 11 close to the source region N + and the edge of the polysilicon gate 8 close to the drain region N +, and the first preset distance x is larger than the first reference value and smaller than a second reference value; the first reference value is the thickness of the gate oxide layer 9, and the second reference value is the distance between the edge of the polysilicon field plate 11 close to the drain region N + and the edge of the SiN field oxide layer 7 close to the source region N +.

For this embodiment, the distance between the edge of the polysilicon field plate 11 close to the drain region N + and the edge of the SiN field oxide layer 7 close to the source region N + is b in the conventional LDMOS device, and at this time, the first preset distance x is greater than the first reference value and less than the second reference value (i.e., b); the first predetermined distance x may be 0.5 μm, or a value around 0.5 μm, for example, may be in a range from [0.5- (0.5 x 50%) ] μm to [0.5+ (0.5 x 50%) ] μm.

As another implementation manner, please further refer to fig. 5, wherein fig. 5 is a schematic diagram of a third structure of the SiC LDMOS device provided in the embodiment of the present application(ii) a When the first SiO₂When the thickness of the layer 10 is higher than a first reference value, a gap is formed between the edge of the polysilicon field plate 11 close to the source region N + and the edge of the polysilicon gate 8 close to the drain region N +, namely, a second preset distance y is formed between the edge of the polysilicon field plate 11 close to the source region N + and the edge of the polysilicon gate 8 close to the drain region N +, and the second preset distance y is not limited; or, one side of the polysilicon field plate 11 close to the source region N + is overlapped with one side of the polysilicon gate 8 close to the drain region N +.

For this embodiment, the distance between the edge of the polysilicon field plate 11 close to the drain region N + and the edge of the SiN field oxide layer 7 close to the source region N + is b in the conventional LDMOS device, at this time, since the first SiO is on the edge of the first SiO, the distance between the edge of the polysilicon field plate 11 close to the drain region N + and the edge of the SiN field oxide layer 7 close to the source region N + is b in the conventional LDMOS device₂The thickness of the layer 10 is higher than the first reference value, so there is no limitation on the value of the second preset distance y, and the value may be a positive value, that is, a gap is formed between the edge of the polysilicon field plate 11 close to the source region N + and the edge of the polysilicon gate 8 close to the drain region N +, or may be a negative value, that is, one side of the polysilicon field plate 11 close to the source region N + overlaps one side of the polysilicon gate 8 close to the drain region N +.

It should be understood that the above embodiments are only preferred implementations of the embodiments of the present application, and are not the first SiO of the embodiments of the present application₂A unique definition of the magnitude relationship between the thickness of the layer 10 and the first reference value, and the relative positional relationship between the polysilicon field plate 11 and the polysilicon gate 8; in this regard, a person skilled in the art can flexibly set the setting according to the actual application scenario on the basis of the embodiment of the present application.

In some embodiments, please further refer to fig. 6 and 7, in which fig. 6 is a fourth structural diagram of the SiC LDMOS device provided in the embodiment of the present application, and fig. 7 is a fifth structural diagram of the SiC LDMOS device provided in the embodiment of the present application; wherein FIG. 6 corresponds to FIG. 4, i.e. to the first SiO₂The case where the thickness of the layer 10 is lower/higher than the first reference value, fig. 7 corresponds to fig. 5, i.e. to the first SiO₂The thickness of the layer 10 is higher than in the case of the first reference value. In this embodiment, the present application may be implemented by an ILD (Inter Layer Dielectric) deposition process, cont (contact hole) lithography/etching process, metallization process, and the likeThe structure of the provided SiC LDMOS device is more complete, so that the normal operation of the SiC LDMOS device in practical application is ensured, namely the SiC LDMOS device provided by the embodiment of the application can further comprise an interlayer medium, a contact hole, a Metal and the like.

For this embodiment, in FIG. 6, when the first SiO₂When the thickness of the layer 10 is lower than the first reference value, the first predetermined distance x is greater than the first reference value in order to ensure that the gate region is applied with high voltage and the Source is present&When Bulk is added with low pressure, the first SiO is not used₂The thickness of the layer 10 is lower than the first reference value resulting in a breakdown leakage between the polysilicon gate 8 and the polysilicon field plate 11. In FIG. 7, due to the first SiO₂The thickness of the layer 10 is higher than the first reference value, so even if the side of the polysilicon field plate 11 close to the source region N + overlaps with the side of the polysilicon gate 8 close to the drain region N +, the gate region is not applied with high voltage and the polysilicon field plate 11 is applied with low voltage, so that the first SiO is not affected₂The position of the layer 10 leaks electricity because the gate oxide layer 9 corresponding to the polysilicon gate 8 leaks electricity in advance, and thus the value of the second predetermined distance y is not limited.

As described above, since there is no connection structure between the polysilicon gate 8 and the polysilicon field plate 11, the polysilicon gate 8 and the polysilicon field plate 11 are not fabricated by the same photolithography process, and are not connected together in electrical connection; wherein the polysilicon field plate 11 is connected to Source through cont&Bulk, a fixed low voltage or 0v can be achieved, and the effect of reducing the surface field plate when the N well region 2 is resistant to high voltage is achieved. Moreover, the distance between the edge of the N-well region 2 far from the drain region N + and the edge of the drain region N + close to the source region N + can be used as c in the conventional LDMOS device, the distance between the edge of the polysilicon field plate 11 close to the drain region N + and the edge of the N-well region 2 close to the source region N + can be used as b in the conventional LDMOS device, and the length of the channel (i.e., the distance between the edge of the N-well region 2 close to the source region N + and the edge of the source region N + close to the drain region N +) can be used as L in the conventional LDMOS device_chTherefore, parameters such as withstand voltage and turn-on voltage can be kept consistent with those of the traditional LDMOS device on the premise of realizing smaller Cgd.

Referring to fig. 8, fig. 8 is a first flowchart illustrating a method for manufacturing a SiC LDMOS device according to an embodiment of the present disclosure.

As shown in fig. 8, an embodiment of the present application further provides a method for manufacturing a SiC LDMOS device, which is applied to the SiC LDMOS device provided in the embodiment of the present application; as can be seen from fig. 8, the method for manufacturing the SiC LDMOS device includes the following steps 801 to 804.

Step 801, forming an N-well region inside the SiC substrate by a deposition process, a photolithography process, an etching process, and an ion implantation process, and forming a P-well region inside the SiC substrate by a deposition process, a chemical mechanical polishing process, a wet etching process, and an ion implantation process.

In the embodiment of the present application, it is necessary to form the N well region 2 inside the SiC substrate 1 by a deposition process, a photolithography process, an etching process, and an ion implantation process, and form the P well region 3 inside the SiC substrate 1 by a deposition process, a chemical mechanical polishing process, a wet etching process, and an ion implantation process. The N-well region 2 is connected to the P-well region 3, and the N-well region 2 is a drift region of the SiC LDMOS device provided in the embodiment of the present application.

As an embodiment, please further refer to fig. 9, where fig. 9 is a schematic flowchart of step 801 in fig. 8 according to an embodiment of the present disclosure. As can be seen from fig. 9, step 801 may include the following steps 8011 to 8017.

8011, depositing SiO on the surface of the SiC substrate by a deposition process₂Forming a second SiO₂And (3) a layer.

In this embodiment, please further refer to fig. 10, fig. 10 is a schematic view of a first structure of a SiC LDMOS device provided in an embodiment of the present application in a manufacturing process; it is necessary to deposit SiO on the surface of the SiC substrate 1 by a deposition process₂Forming a second SiO₂And (3) a layer. Wherein the second SiO₂The thickness of the layer may be 1 μm, or a value around 1 μm, for example, may be in the range of [1- (1 × 50%)]μ m to [1+ (1X 50%)]The value range of mum.

8012, the pattern transfer of the N-well region from the corresponding mask to the first photoresist is achieved by a photolithography process and an etching process.

In this embodiment, still referring to fig. 10, SiO is deposited on the surface of the SiC substrate 1₂Then, the pattern transfer of the N well region 2 from the corresponding mask to the first photoresist PR1 is also performed by a photolithography process and an etching process. Wherein the first photoresist PR1 is coated on the second SiO₂The surface of the layer.

8013, the first photoresist is removed and the second SiO is applied by ion implantation₂The layer serves as a barrier layer, and nitrogen ions are implanted to form an N well region in the SiC substrate.

In this embodiment, please further refer to fig. 11, fig. 11 is a schematic diagram of a second structure of the SiC LDMOS device provided in the embodiment of the present application in the manufacturing process; after the pattern transfer from the corresponding mask to the first photoresist PR1 is realized in the N well region 2, the first photoresist PR1 needs to be removed, and the second SiO is used for the pattern transfer through an ion implantation process₂The layer serves as a barrier layer, and nitrogen ions are implanted to form N well regions 2 in the SiC substrate 1. Wherein the second SiO₂Overlying the surface of the SiC substrate 1 not corresponding to the N-well region 2, i.e. if the desired location of the N-well region 2 is to the right of the interior of the SiC substrate 1, then SiO is deposited in step 8011₂When, SiO should be added₂Deposited on the left side of the surface of the SiC substrate.

For this embodiment, when the ion-implanted element is nitrogen, the temperature of the SiC substrate 1 needs a high temperature (e.g., 400 ℃); when the ion-implanted element is not nitrogen, the temperature of the SiC substrate 1 may be normal temperature or room temperature, and may even be in a cooled state below 15 ℃. Typically, a deeper N-well region 2 (e.g. 2-10 μm) is required, and therefore, a selective implantation of relatively lighter nitrogen ions makes it easier to achieve a deeper N-well region 2. Since the first photoresist PR1 is carbonized and failed at a high temperature, the first photoresist PR1 needs to be removed before ion implantation.

8014, a SiN layer is formed by depositing SiN on the surface of the SiC substrate by a deposition process.

In this embodiment, referring to fig. 12, fig. 12 is a third junction of the SiC LDMOS device provided in the embodiment of the present application in the manufacturing processA schematic diagram; after the N well region 2 is formed inside the SiC substrate 1, SiN is deposited on the surface of the SiC substrate 1 by a deposition process to form a SiN layer. Wherein the thickness of the SiN layer is higher than that of the second SiO₂Thickness of the layer, i.e. SiN layer on the second SiO₂On the layer.

For this embodiment, the thickness of the SiN layer may be 1.2 μm, or a value around 1.2 μm, for example, may be in the range of [1.2- (1.2 x 50%) ] μm to [1.2+ (1.2 x 50%) ] μm.

8015, the SiN layer is polished by a chemical mechanical polishing process.

In this embodiment, please further refer to fig. 13, fig. 13 is a schematic diagram of a fourth structure of the SiC LDMOS device provided in the embodiment of the present application in the manufacturing process; after the SiN layer is deposited on the surface of the SiC substrate 1, the SiN layer is further polished by a Chemical Mechanical Polishing (CMP) process to make the thickness of the SiN layer equal to that of the second SiO layer₂The layers are the same, in which case the SiN layer is on the second SiO₂The layers are connected, and the SiN layer covers the surface of the SiC substrate 1 corresponding to the N well region 2.

For this embodiment, when the second SiO₂When the layer thickness is 1 μm and the SiN layer thickness is 1.2 μm, the second SiO layer is lost to the SiC substrate 1 due to the chemical mechanical polishing process₂The thickness of the layer is actually less than 1 μm (e.g. 0.8 μm, and correspondingly the thickness of the SiN layer is also 0.8 μm).

8016, second SiO is etched by wet etching process₂The layer is etched.

In this embodiment, please further refer to fig. 14, fig. 14 is a schematic diagram of a fifth structure of the SiC LDMOS device provided in the embodiment of the present application in the manufacturing process; after the SiN layer is ground, a wet etching process is needed to etch the second SiO layer₂Etching the layer to etch the second SiO₂Removing the layer; the solution used in the wet etching process may include, but is not limited to, boe (buffered Oxide etch) solution. It should be noted that, since the etching rate of SiN by a solution similar to boe (buffered Oxide etch) solution is low, the SiN layer is remainedTo do so.

8017, an ion implantation process is performed to form a P-well region in the SiC substrate by using the SiN layer as a self-aligned mask of the P-well region and performing aluminum ion implantation.

In this embodiment, for the second SiO₂After the layer is etched, the SiN layer is used as a self-aligned mask of the P-well region 3 through an ion implantation process, and aluminum ions are implanted to form the P-well region 3 inside the SiC substrate 1. The energy of ion implantation can be 1500-1900keV, which means that the implanted aluminum ions are high-energy ions.

It should be understood that the foregoing embodiments are only preferred implementations of the embodiments of the present application, and are not the only limitations of the embodiments of the present application on the specific flow of step 801; in this regard, a person skilled in the art can flexibly set the setting according to the actual application scenario on the basis of the embodiment of the present application.

Step 802, forming a source region P +, a source region N + and a drain region N + on the inner surface of the SiC substrate through a photoetching process, a wet etching process, an ion implantation process and an annealing process, and forming an SiN field oxide layer on the surface of the SiC substrate corresponding to the N well region.

In the embodiment of the present application, after the N-well region 2 and the P-well region 3 are formed in the SiC substrate 1, a source region P +, a source region N + and a drain region N + are formed on the inner surface of the SiC substrate 1 through a photolithography process, a wet etching process, an ion implantation process and an annealing process, and the SiN field oxide layer 7 is formed on the surface of the SiC substrate 1 corresponding to the N-well region 2. Wherein, source region P + and source region N + all are located the position that P well region 3 kept away from N well region 2, source region P + and source region N + set gradually along the directional N well region 2's of P well region 3 direction, drain region N + is located the position that P well region 3 was kept away from to N well region 2, the edge that SiN field oxygen layer 7 is close to source region N + aligns with the edge that N well region 2 is close to source region N +, one side that SiN field oxygen layer 7 is close to drain region N + has the inclined plane, the edge that SiN field oxygen layer 7 is close to drain region N + aligns with the edge that drain region N + is close to source region N +.

As an embodiment, please further refer to fig. 15, where fig. 15 is a flowchart illustrating step 802 in fig. 8 according to an embodiment of the present disclosure. As can be seen in fig. 15, step 802 may include steps 8021 to 8026 as follows.

Step 8021, performing N + photolithography by photolithography.

In this embodiment, please further refer to fig. 16, fig. 16 is a schematic diagram of a sixth structure of the SiC LDMOS device provided in the embodiment of the present application in the manufacturing process; it is necessary to perform N + photolithography by photolithography. Wherein the second photoresist PR2 covers part of the surface of the SiC substrate 1 and part of the SiN layer.

Step 8022, the SiN layer is etched by a wet etching process.

In this embodiment, please further refer to fig. 17, where fig. 17 is a schematic diagram of a seventh structure of the SiC LDMOS device provided in the embodiment of the present application in the manufacturing process; after the SiN layer is etched, the SiN layer is also etched through a wet etching process, so that the part of the SiN layer which is not covered by the second photoresist PR2 is removed; since the wet etching process has the characteristic of lateral etching, a slope is formed at the joint between the reserved part of the SiN layer (i.e., the part of the SiN layer covered by the second photoresist PR 2) and the removed part, and at this time, the reserved part of the SiN layer constitutes the SiN field oxide layer 7.

Step 8023, implanting phosphorus ions by an ion implantation process to form a source region N + and a drain region N + on the inner surface of the SiC substrate.

In this embodiment, still referring to fig. 17, after the SiN layer is etched, phosphorus ions are implanted by an ion implantation process to form a source region N + and a drain region N + on the inner surface of the SiC substrate 1. The energy for ion implantation may be 1300-.

Step 8024, removing the second photoresist, and performing P + lithography through a lithography process.

In this embodiment, please further refer to fig. 18, fig. 18 is a schematic diagram of an eighth structure of the SiC LDMOS device provided in the embodiment of the present application in the manufacturing process; after forming the source region N + and the drain region N + on the inner surface of the SiC substrate 1, the second photoresist PR2 needs to be removed, and P + is subjected to photolithography through a photolithography process. Wherein the third photoresist PR3 covers part of the surface of the SiC substrate 1 and the SiN field oxide layer 7.

Step 8025, implanting aluminum ions by an ion implantation process to form a source region P + on the inner surface of the SiC substrate.

In this embodiment, still referring to fig. 18, after the photolithography of P + is performed, it is necessary to perform implantation of aluminum ions by an ion implantation process to form a source region P + on the inner surface of the SiC substrate 1. The edge of the source region P + close to the drain region N + is aligned with the edge of the third photoresist PR3 far from the drain region N +, and the energy during ion implantation may be 1700-2000 keV.

Step 8026, removing the third photoresist, and performing high temperature annealing.

In this embodiment, please further refer to fig. 19, where fig. 19 is a schematic diagram of a ninth structure of the SiC LDMOS device provided in the embodiment of the present application in the manufacturing process; after forming the source region P + on the inner surface of the SiC substrate 1, it is also necessary to remove the third photoresist PR3 and perform high temperature activation annealing. It is understood that after removing the third photoresist PR3 and performing the high-temperature activation annealing, SiO of the surface of the SiC substrate 1₂Having been completely removed, only the SiN field oxide layer 7 is present on the surface of the SiC substrate 1.

It should be understood that the foregoing embodiments are only preferred implementations of the embodiments of the present application, and are not the only limitations of the embodiments of the present application on the specific flow of step 802; in this regard, a person skilled in the art can flexibly set the setting according to the actual application scenario on the basis of the embodiment of the present application.

And 803, forming a gate oxide layer on the surface of the SiC substrate on which the SiN field oxide layer is not formed through a gate oxide process.

In the embodiment of the present application, please further refer to fig. 20, where fig. 20 is a schematic diagram of a tenth structure of the SiC LDMOS device provided in the embodiment of the present application in the manufacturing process; after forming a source region P +, a source region N + and a drain region N + on the inner surface of the SiC substrate 1 and forming an SiN field oxide layer 7 on the surface of the SiC substrate 1 corresponding to the N well region 2, a gate oxide layer 9 is formed on the surface of the SiC substrate 1 where the SiN field oxide layer 7 is not formed through a gate oxidation process. It is necessary to explain here that the thickness of the gate oxide layer 9 may vary according to different product requirementsTo have different thicknesses, such as 0.02-0.2 μm; the conditions of the gate oxidation process may be in a nitrogen-containing atmosphere (e.g., containing NO or N)₂O atmosphere) oxidation; the gate oxidation process is to oxidize the surface of the SiC substrate 1 not covered with the SiN field oxide layer 7 to form SiO₂To form the gate oxide layer 9, while the SiN field oxide layer 7 is not oxidized.

And 804, forming a polysilicon gate on the surface of the gate oxide layer corresponding to the P well region through a deposition process, a chemical mechanical polishing process, a photoetching process and a dry etching process.

In the embodiment of the present application, after the gate oxide layer 9 is formed on the surface of the SiC substrate 1 where the SiN field oxide layer 7 is not formed, the polysilicon gate 8 is further formed on the surface of the gate oxide layer 9 corresponding to the P-well region 3 through a deposition process, a chemical mechanical polishing process, a photolithography process, and a dry etching process. The edge of the polysilicon gate 8 close to the drain region N + is connected with the edge of the SiN field oxide layer 7 close to the source region N +, and one side of the polysilicon gate 8 far away from the drain region N + is overlapped with one side of the source region N + close to the drain region N +.

As an embodiment, please further refer to fig. 21, where fig. 21 is a flowchart illustrating step 804 in fig. 8 according to an embodiment of the present disclosure. As can be seen in fig. 21, step 804 may include steps 8041 to 8044 as follows.

8041, depositing polysilicon on the surface of the gate oxide layer by a deposition process to form a first polysilicon layer.

In this embodiment, please further refer to fig. 22, where fig. 22 is a schematic diagram of an eleventh structure of the SiC LDMOS device provided in the embodiment of the present application in the manufacturing process; it is necessary to deposit polysilicon on the surface of the gate oxide layer 9 by a deposition process to form a first polysilicon layer. Here, it is necessary to say that the thickness of the first polysilicon layer is higher than the thickness of the SiN field oxide layer 7 so that the first polysilicon layer covers the SiN field oxide layer 7; the thickness of the first polysilicon layer may be 0.8 μm, or a value around 0.8 μm, for example, may be in a range from [0.8- (0.8 x 50%) ] μm to [0.8+ (0.8 x 50%) ] μm.

8042, the first polysilicon layer is polished by a chemical mechanical polishing process.

In this embodiment, please further refer to fig. 23, fig. 23 is a schematic diagram of a twelfth structure of the SiC LDMOS device provided in the embodiment of the present application in the manufacturing process; depositing polycrystalline silicon on the surface of the gate oxide layer 9, and grinding the first polycrystalline silicon layer through a chemical mechanical polishing process after the first polycrystalline silicon layer is formed, so that the thickness of the first polycrystalline silicon layer is the same as that of the SiN field oxide layer 7; the first polysilicon layer after grinding is divided into two parts, wherein one part corresponds to the drain region N +, the other part corresponds to the P-well region 3, and the SiN field oxide layer 7 is sandwiched between the two parts of the first polysilicon layer.

Step 8043, by a photolithography process, photolithography of the first polysilicon layer is performed.

In this embodiment, still referring to fig. 23, after the first polysilicon layer is polished, the first polysilicon layer is further subjected to photolithography by a photolithography process; wherein, the fourth photoresist PR4 covers part of the SiN field oxide layer 7 and part of the first polysilicon layer, a side of the fourth photoresist PR4 away from the drain region N + overlaps (e.g., overlaps 0.5 μm) a side of the source region N + close to the drain region N +, and a gap (e.g., has 0.5-2 μm) is provided between an edge of the fourth photoresist PR4 away from the source region N + and an edge of the drain region N + close to the source region N +.

For this embodiment, the purpose that the side of the fourth photoresist PR4 away from the drain region N + overlaps with the side of the source region N + close to the drain region N + is to facilitate the channel of the SiC LDMOS device provided by the embodiment of the present application to be normally opened; the gap is formed between the edge of the fourth photoresist PR4 far from the source region N + and the edge of the drain region N + near the source region N +, so that when the first polysilicon layer is etched subsequently, the portion of the first polysilicon layer not covered by the fourth photoresist PR4 can be etched cleanly.

Step 8044, by using a dry etching process, etching the first polysilicon layer by using an end point detection method as an etching stop signal, and removing the fourth photoresist.

In this embodiment, please further refer to fig. 24, fig. 24 is a schematic diagram of a thirteenth structure of the SiC LDMOS device provided in the embodiment of the present application in the manufacturing process; after the first polysilicon layer is subjected to photoetching through a photoetching process, etching of the first polysilicon layer is carried out through a dry etching process by taking an end point detection mode as an etching stop signal, and the fourth photoresist PR4 is removed; after etching, the portion of the first polysilicon layer not covered by the fourth photoresist PR4 is removed, and the remaining portion of the first polysilicon layer constitutes the polysilicon gate 8.

For this embodiment, since the etching gas of the dry etching process will only etch the first polysilicon layer and will not etch the fourth photoresist PR4 and the SiN field oxide layer 7, the SiN field oxide layer 7 and the portion of the first polysilicon layer covered by the fourth photoresist PR4 will be left.

It should be understood that the foregoing embodiments are only preferred implementations of the embodiments of the present application, and are not the only limitations of the embodiments of the present application on the specific flow of step 804; in this regard, a person skilled in the art can flexibly set the setting according to the actual application scenario on the basis of the embodiment of the present application.

In some embodiments, please further refer to fig. 25, and fig. 25 is a second flowchart illustrating a method for manufacturing a SiC LDMOS device according to an embodiment of the present disclosure. As can be seen in fig. 25, step 804 may be followed by steps 805 to 806 as follows.

Step 805, depositing SiO on the surface of the gate oxide layer by a deposition process₂Forming a first SiO₂And (3) a layer.

In this embodiment, please further refer to fig. 26, fig. 26 is a schematic diagram illustrating a fourteenth structure of the SiC LDMOS device provided in the embodiment of the present application in the manufacturing process; after the polysilicon gate 8 is formed on the surface of the gate oxide layer 9 corresponding to the P-well region 3, a deposition process is required to deposit SiO on the surface of the gate oxide layer 9₂Forming a first SiO₂A layer 10; wherein, the first SiO₂A layer 10 covers the polysilicon gate 8 and the SiN field oxide layer 7.

Step 806, depositing, photolithography, and dry etching on the first SiO layer₂The polysilicon field plate is formed on the surface of the layer corresponding to the SiN field oxide layer.

In this embodiment, inSiO is deposited on the surface of the gate oxide layer 9₂Forming a first SiO₂After the layer 10, a deposition process, a photolithography process and a dry etching process are required to form a layer on the first SiO₂The surface of layer 10 corresponding to the SiN field oxide layer 7 forms a polysilicon field plate 11.

For this example, the first SiO₂The thickness of the layer 10 has two cases. Wherein the first case is a first SiO₂The thickness of the layer 10 is lower than a first reference value, in the second case a first SiO₂The thickness of the layer 10 is higher than the first reference value, see the structure class embodiments described above.

As an implementation manner, please further refer to fig. 27, in which fig. 27 is a schematic flowchart of step 806 in fig. 25 according to an embodiment of the present disclosure. As can be seen in fig. 27, step 806 may include steps 8061 to 8063 as follows.

8061 depositing on the first SiO layer₂And depositing polysilicon on the surface of the layer to form a second polysilicon layer.

In this embodiment, please further refer to fig. 28, fig. 28 is a schematic diagram of a fifteenth structure of the SiC LDMOS device provided in the embodiment of the present application in the manufacturing process; firstly, the first SiO is deposited by a deposition process₂Polysilicon is deposited on the surface of layer 10 to form a second polysilicon layer. The thickness of the second polysilicon layer is not particularly required, and may be selected from 0.2-1.0 μm, for example.

Step 8062, performing photolithography on the second polysilicon layer by photolithography.

In this embodiment, please further refer to fig. 29, where fig. 29 is a schematic diagram of a sixteenth structure of a SiC LDMOS device provided in an embodiment of the present application in a manufacturing process; in the first SiO₂Depositing polycrystalline silicon on the surface of the layer 10, and after forming a second polycrystalline silicon layer, carrying out photoetching on the second polycrystalline silicon layer through a photoetching process; wherein, the fifth photoresist PR5 covers the surface of the second polysilicon layer corresponding to the SiN field oxide layer 7.

Step 8063, by using a dry etching process, etching the second polysilicon layer by using an end point detection mode as an etching stop signal, and removing the fifth photoresist.

In this embodiment, please further refer to fig. 30, where fig. 30 is a schematic diagram of a seventeenth structure of a SiC LDMOS device provided in an embodiment of the present application in a manufacturing process; after the second polysilicon layer is subjected to photoetching through a photoetching process, etching of the second polysilicon layer is carried out through a dry etching process by taking an end point detection mode as an etching stop signal, and the fifth photoresist PR5 is removed; wherein after etching, the portion of the second polysilicon layer not covered by the fifth photoresist PR5 is removed, and the remaining portion of the second polysilicon layer (i.e. the portion of the second polysilicon layer covered by the fifth photoresist PR 5) constitutes the polysilicon field plate 11.

It should be understood that the foregoing embodiments are merely preferred implementations of the embodiments of the present application, and are not the only limitations on the specific flow of step 806 in the embodiments of the present application; in this regard, a person skilled in the art can flexibly set the setting according to the actual application scenario on the basis of the embodiment of the present application.

In addition, after the step 806, steps such as an ILD deposition process, a cont lithography/etching process, a metallization process, and the like may be further included, so that the structure of the SiC LDMOS device provided in the embodiment of the present application is more complete, and normal operation of the SiC LDMOS device in practical application is ensured.

It should be noted that, the embodiments in the present disclosure are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.

It is further noted that, within the context of this application, relational terms such as first and second, and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.