阅读说明：本技术 一种超结屏蔽栅沟槽mosfet结构及制作方法 (Super junction shielding gate trench MOSFET structure and manufacturing method ) 是由 王彩琳 汤雨欣 苏乐 杨武华 于 2021-09-27 设计创作，主要内容包括：本发明公开了一种超结屏蔽栅沟槽MOSFET结构,衬底的N～(+)漏区上设有N～(-)辅助层,N～(-)辅助层上方两侧为超结区,每侧超结区上方的P体区靠内设有一个N～(+)源区,在P体区和N～(+)源区的上表面共同设有源极电极S；两个N柱区及其上方的P体区中央设有深沟槽,深沟槽底部位伸进N～(-)辅助层内；深沟槽内的上方设有栅极G,其四周为二氧化硅层；下方设有屏蔽栅极SG,其两侧及底部为二氧化硅层,且屏蔽栅极SG在三维方向上与源极S相连；在N～(+)漏区下表面设有漏极电极D。本发明还公开了另一种SJSGT*结构及该两种结构的制作方法。本发明在保证击穿电压和雪崩耐量的前提下,明显降低器件导通电阻和栅电荷,获得快开关速度和低功耗。(The invention discloses a super junction shielding grid groove MOSFET structure, N of a substrate + N is arranged on the drain region ‑ Auxiliary layer, N ‑ Two sides above the auxiliary layer are provided with super junction regions, and a P body region rest above the super junction region on each side is provided with an N + Source region between P body region and N + The upper surfaces of the source regions are provided with a source electrode S together; the centers of the two N column regions and the P body region above the two N column regions are provided with deep trenches, and the bottoms of the deep trenches extend into the N ‑ In the auxiliary layer; a grid G is arranged above the deep groove, and a silicon dioxide layer is arranged around the grid G; a shielding grid SG is arranged below the source S, the two sides and the bottom of the shielding grid SG are silicon dioxide layers, and the shielding grid SG is connected with the source S in the three-dimensional direction; in N + Lower surface of drain regionA drain electrode D is provided. The invention also discloses another SJSGT structure and a manufacturing method of the two structures. On the premise of ensuring breakdown voltage and avalanche tolerance, the invention obviously reduces the on-resistance and gate charge of the device, and obtains fast switching speed and low power consumption.)

1. A super junction shielding grid groove MOSFET structure which characterized in that: comprising N as a substrate⁺Drain region at N⁺The upper surface of the drain region is provided with N^-Auxiliary layer, N^-Both sides above the auxiliary layer are provided with super junction regions, and the super junction region on each side comprises a P column region and an N column region; a P body area is arranged above the super junction area on each side, and an N body area is arranged in each P body area⁺Source region on the upper surface of the P body region and N⁺The upper surfaces of the source regions are provided with a source electrode S together; the centers of the two N column regions and the P body region above the two N column regions are provided with deep trenches, and the bottoms of the deep trenches extend into the N^-In the auxiliary layer;

the deep groove is internally provided with an upper part of polycrystalline silicon and a lower part of polycrystalline silicon, and is filled with a silicon dioxide layer; the polysilicon above is called grid G, and silicon dioxide layers are arranged around the grid G; the polysilicon below is called a shielding grid SG, two sides and the bottom of the shielding grid SG are silicon dioxide layers, and the shielding grid SG is connected with the source S in the three-dimensional direction;

the silicon dioxide layer on the upper surface of the deep groove isolates the source S from the grid G; in N⁺And a drain electrode D is arranged on the lower surface of the drain region.

2. The superjunction shielded gate trench MOSFET structure of claim 1, wherein: the width W of the gate G_GThickness T of silicon dioxide layer on both sides_GOXSum of the sum and width W of shield gate SG_SGWith thickness T of silicon dioxide layer on both sides_SGOXThe sum being equal, i.e. W_G+2T_GOX＝W_SG+2T_SGOX。

3. The method for manufacturing the super junction shielded gate trench MOSFET structure according to claim 1, wherein the method is implemented according to the following steps:

step 1, manufacturing a substrate: low resistance<100>N⁺Silicon substrate → epitaxial N^-An auxiliary layer;

step 2, manufacturing a super junction column region: epitaxial P column region → photoetching → deep groove etching → sacrificial oxide film growth → phosphorus ion oblique angle injection → sacrificial oxide layer removal → annealing and advancing to form N column region;

step 3, manufacturing an SGT structure: thermally growing a silicon dioxide field oxide layer → depositing polysilicon and doping to fill the trench → etching the cell area → etching the polysilicon in the trench to form a shield gate → etching the cell area → wet etching to remove the silicon dioxide field oxide layer on the silicon surface and the sidewall of the trench → using high density plasma chemical vapor deposition to isolate the oxide film and the gate oxide layer → depositing polysilicon gate in the trench → etching the cell area and the shield gate lead-out area → boron ion implantation and propulsion to form a P body area → etching the cell area → phosphorus ion implantation in the P body area to form an N⁺A source region;

step 4, manufacturing a front electrode structure: forming a phosphosilicate glass layer by chemical vapor deposition → photoetching → etching to form a groove type contact hole → depositing refractory metal in the contact hole → adopting CMP surface planarization → depositing a surface metal layer → photoetching pressure welding point → etching to form electrodes of a front grid and a source electrode;

step 5, manufacturing a back electrode structure: thinning the back N⁺Silicon substrate → backside multilayer metallization.

4. A super junction shielding grid groove MOSFET structure which characterized in that: comprising N as a substrate⁺Drain region at N⁺The upper surface of the drain region is provided with N^-Auxiliary layer, N^-Both sides above the auxiliary layer are provided with super junction regions, and each side is provided with a super junctionThe regions each include a P-pillar region and an N-pillar region; a P body area is arranged above the super junction area on each side, and an N body area is arranged in each P body area⁺Source region on the upper surface of the P body region and N⁺The upper surfaces of the source regions are provided with a source electrode S together; the centers of the two N column regions and the P body region above the two N column regions are provided with deep trenches, and the bottoms of the deep trenches extend into the N^-In the auxiliary layer;

a shielding grid SG is vertically arranged at the central position in the deep groove, two sides of the upper part of the shielding grid SG are respectively provided with a grid G, the two grids G and the shielding grid SG are arranged in a left-middle-right layout, and the middle of the grids G is isolated by a silicon dioxide layer; and the shielding grid SG is connected with the source S in the three-dimensional direction;

the silicon dioxide layer on the upper surface of the deep groove isolates the source S from the grid G; in N⁺And a drain electrode D is arranged on the lower surface of the drain region.

5. The method for manufacturing the super junction shielded gate trench MOSFET structure of claim 4, wherein the method is implemented according to the following steps:

step 1, manufacturing a substrate: low resistance<100>N⁺Silicon substrate → epitaxial N^-An auxiliary layer;

step 2, manufacturing a super junction column region: epitaxial P column region → photoetching → deep groove etching → sacrificial oxide film growth → phosphorus ion oblique angle injection → sacrificial oxide layer removal → annealing and advancing to form N column region;

step 3, manufacturing an SGT structure: thermally growing silicon dioxide field oxide layer in the groove → depositing polysilicon in the groove and doping → photoetching → etching the surface of the silicon wafer and the polysilicon in the groove to form a shielding grid under the silicon surface → photoetching → wet etching to remove the silicon dioxide field oxide layer on the surface of the silicon wafer and in the groove to form a grid groove → thermally growing silicon dioxide gate oxide layer → depositing polysilicon and doping → photoetching → etching the polysilicon grid under the silicon surface → implanting boron ions and advancing to form a P body area → implanting arsenic ions to form an N body area in the annealing of the P body area⁺A source region;

step 4, manufacturing a front electrode structure: forming a phosphosilicate glass layer by chemical vapor deposition → photoetching → etching to form a contact hole of a source electrode and a shielding grid → depositing a surface metal layer → photoetching pressure welding spot → etching to form an electrode of a front grid electrode and the source electrode;

step 5, manufacturing a back electrode structure: thinning the back N⁺Silicon substrate → backside multilayer metallization.

6. The superjunction shielded gate trench MOSFET structure of claim 1 or 4, wherein: the thickness of the P column region is equal to that of the N column region, the doping of the P column region is equal to that of the N column region, and the width W of the N column region_NIs slightly wider than the width W of the P column region_PWithin a range of difference Δ W ═ W_N-W_PIs 0.1-1 μm, i.e. Δ W is 0.1-1 μm.

7. The superjunction shielded gate trench MOSFET structure of claim 1 or 4, wherein: the bottom N^-The thickness of the auxiliary layer increases with the breakdown voltage of the device, N^-The thickness of the auxiliary layer ranges from 2 to 10 μm.

8. The superjunction shielded gate trench MOSFET structure of claim 1 or 4, wherein: the groove of the shielding grid SG extends into the bottom auxiliary layer, and the deviation delta L from the bottom of the super junction is controlled within 3 mu m, namely, the delta L is more than 0 mu m and less than or equal to 3 mu m.

Technical Field

The invention belongs to the technical field of power semiconductor devices, relates to a super junction shielding gate trench MOSFET structure, and further relates to a manufacturing method of the super junction shielding gate trench MOSFET structure.

Background

The power MOSFET is used in large amount in electric vehicles and vehicle charging piles, and needs to work outdoors for a long time, so that the requirements on static and dynamic characteristics and reliability of devices are high. Although the breakdown voltage of the common power MOSFET can be improved by increasing the thickness of the drift region, the on-resistance of the common power MOSFET is increased, and the common power MOSFET have an irreconcilable contradiction, so that the static power consumption of the common power MOSFET is larger. The deep-groove super-junction MOSFET reduces the on-resistance to a certain extent, but cannot overcome the defect of large gate-drain capacitance. A shielding gate electrode which is separated from a gate and is externally added with a source potential is introduced into a traditional deep groove gate MOSFET structure, so that the gate leakage charge of the shielding gate MOSFET can be reduced, the switching speed of a device is improved, and the breakdown voltage of the shielding gate MOSFET is lower. Therefore, the conventional power MOSFET structure has a disadvantage in static or dynamic characteristics, which limits the application of the conventional power MOSFET structure in a motor driving system, an inverter system and a power management system in the fields of new energy electric vehicles, novel photovoltaic power generation, energy-saving household appliances and the like.

Disclosure of Invention

The invention aims to provide a super-junction shielding grid groove MOSFET structure (hereinafter referred to as SJSGT structure or SJSGT structure) which solves the problem that static and dynamic characteristics of the conventional deep groove grid super-junction MOSFET and shielding grid SGT are difficult to meet the requirements of practical application.

The invention further aims to provide a manufacturing method of the super junction shielded gate trench MOSFET structure.

The invention adopts the technical scheme that a super junction shielding grid groove MOSFET structure comprises N serving as a substrate⁺Drain region at N⁺The upper surface of the drain region is provided with N^-Auxiliary layer, N^-The super junction area is arranged on two sides above the auxiliary layer, namely the super junction area comprises a P column area and an N column area; a P body area is arranged above the super junction area on each side, and an N body area is arranged in each P body area⁺Source region on the upper surface of the P body region and N⁺Upper surface of the source regionA source electrode S is provided together; the centers of the two N column regions and the P body region above the two N column regions are provided with deep trenches, and the bottoms of the deep trenches extend into the N^-In the auxiliary layer; the deep groove is internally provided with an upper part of polycrystalline silicon and a lower part of polycrystalline silicon, and is filled with a silicon dioxide layer; the polysilicon above is called grid G, and silicon dioxide layers are arranged around the grid G; the polysilicon below is called a shielding grid SG, two sides and the bottom of the shielding grid SG are silicon dioxide layers, and the shielding grid SG is connected with the source S in the three-dimensional direction; the silicon dioxide layer on the upper surface of the deep groove isolates the source S from the grid G; in N⁺And a drain electrode D is arranged on the lower surface of the drain region.

The invention adopts another technical scheme that the manufacturing method of the super junction shielding gate trench MOSFET structure is implemented according to the following steps:

step 1, manufacturing a substrate: low resistance<100>N⁺Silicon substrate → epitaxial N^-An auxiliary layer;

step 2, manufacturing a super junction column region: epitaxial P column region → photoetching → deep groove etching → sacrificial oxide film growth → phosphorus ion oblique angle injection → sacrificial oxide layer removal → annealing and advancing to form N column region;

step 3, manufacturing an SGT structure: thermally growing a silicon dioxide field oxide layer → depositing polysilicon and doping to fill the trench → etching the cell area → etching the polysilicon in the trench to form a shield gate → etching the cell area → wet etching to remove the silicon dioxide field oxide layer on the silicon surface and the sidewall of the trench → using high density plasma chemical vapor deposition to isolate the oxide film and the gate oxide layer → depositing polysilicon gate in the trench → etching the cell area and the shield gate lead-out area → boron ion implantation and propulsion to form a P body area → etching the cell area → phosphorus ion implantation in the P body area to form an N⁺A source region;

step 4, manufacturing a front electrode structure: forming a phosphosilicate glass layer by chemical vapor deposition → photoetching → etching to form a groove type contact hole → depositing refractory metal in the contact hole → adopting CMP surface planarization → depositing a surface metal layer → photoetching pressure welding point → etching to form electrodes of a front grid and a source electrode;

step 5, manufacturing a back electrode structure: thinning the back N⁺Silicon substrate → backside multilayerAnd (6) metallization.

The invention has the advantages that the shield grid SG is introduced into the traditional deep-trench-gate super-junction MOSFET, so that the device has high breakdown voltage and low on-resistance under the condition of ensuring the dynamic avalanche tolerance, and the switching speed is greatly accelerated, thereby obtaining low power consumption.

Drawings

Fig. 1 is a schematic cross-sectional view of a conventional deep trench gate super junction MOS structure;

FIG. 2 is a schematic cross-sectional view of a conventional SGT structure;

fig. 3 is a schematic cross-sectional view of a SJSGT structure according to a first embodiment of the present invention;

fig. 4 is a schematic cross-sectional view of a SJSGT structure according to a second embodiment of the present invention;

FIG. 5 is a comparison of the longitudinal electric field distribution of the SJSGT structure of the present invention along the junction of the P column region and the N column region with the longitudinal electric field distribution of a conventional SGT, conventional deep trench gate super junction MOS;

FIG. 6 is a comparison of the breakdown characteristics of the SJSGT structure of the present invention with conventional deep trench gate super junction MOS, conventional SGT at different temperatures;

fig. 7 is a comparison of the conduction characteristics of the SJSGT structure of the present invention with conventional deep trench gate super junction MOS, conventional SGT at different temperatures;

FIG. 8 is a comparison of the gate charge test curves for the SJSGT structure of the present invention versus conventional deep trench gate super junction MOS, conventional SGT;

fig. 9 is a comparison of the turn-off characteristic curves of the SJSGT structure of the present invention with conventional deep trench gate super junction MOS, conventional SGT at different temperatures;

fig. 10 is a comparison of voltage and current curves for the dynamic avalanche of the SJSGT structure of the present invention with conventional deep trench gate super junction MOS, conventional SGT;

fig. 11 is a graph comparing breakdown voltage and on-resistance values of the SJSGT structure and SJSGT structure of the present invention with conventional deep trench gate super junction MOS and conventional SGT;

fig. 12 is a comparison graph of static and dynamic figure of merit for the SJSGT structures and SJSGT structures of the present invention versus conventional deep trench gate super junction MOS and conventional SGT;

FIG. 13 shows SJSGT structure and SJSGT structure according to the present inventionDeviation delta L between the bottom position of the groove and the bottom of the super junction to breakdown voltage BV and characteristic on-resistance R_on,spThe influence of (a);

FIG. 14 is a SJSGT structure and the bottom auxiliary layer thickness T of the SJSGT structure of the present invention_N-For breakdown voltage BV and characteristic on-resistance R_on,spThe influence of (c).

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

Fig. 1 is a schematic cross-sectional view of a conventional deep trench gate super junction MOS (hereinafter referred to as con. dtsj for short in text and drawings) structure, in which a super junction formed by alternately arranging P-pillar regions and N-pillar regions is used as a drift region in a voltage-resistant layer, a trench having the same depth as the pillar regions is formed in the center of the N-pillar regions, and a dielectric layer and polysilicon are filled in the trench to separate the N-pillar regions on both sides. When reverse blocking is carried out, the P column region and the N column region are mutually exhausted, higher breakdown voltage can be obtained, and meanwhile, lower on-resistance is caused due to higher doping concentration of the N column region, so that the traditional deep trench gate super junction MOS obtains good compromise between breakdown voltage and on-resistance, and the on-resistance R of the traditional deep trench gate super junction MOS is_onAnd breakdown voltage BV is R_on∝BV^1.32. With the deep trench structure, although charge balance of the super junction P-column region and the N-column region is facilitated, the gate-drain capacitance is still large.

Fig. 2 is a schematic cross-sectional view of a conventional SGT (hereinafter referred to as con. SGT) structure, in which a shield gate SG is introduced under a gate G of a conventional deep trench gate MOS, and the shield gate SG is separated from the gate G and connected to a source potential, thereby reducing a gate-drain capacitance (Q)_g) And gate drain charge (Q)_gd) The switching speed of the device is increased, and therefore the switching power consumption is reduced.

The invention is improved on the basis of the two structures, and provides two new super-junction SGT structures, namely an SJSGT structure for short and an SJSGT structure for short, which are discussed in detail below.

FIG. 3 is a cross-sectional view of a SJSGT structure according to a first embodiment of the present invention, which is based on Con. DTSJ structure and ensures original N⁺Source region, P base region, trench gate G and N⁺The drain region is unchanged, a shield gate SG separated from the gate and narrower is introduced just below the gate G in the trench, and the width of the N-pillar region is slightly increased since the shield gate SG facilitates depletion of the N-pillar region when blocking.

Referring to fig. 3, the SJSGT structure of the first embodiment of the present invention is a SJSGT structure including N as a substrate⁺Drain region at N⁺The upper surface of the drain region is provided with N^-Auxiliary layer, N^-Both sides above the auxiliary layer are super junction regions, and the super junction region on each side comprises a P column region and an N column region; a P-body region (P-body region in the figure) is arranged above the super junction region on each side, and an N-body region is arranged in each P-body region⁺Source region on the upper surface of the P body region and N⁺The upper surfaces of the source regions are provided with a source electrode S together; the centers of the two N column regions and the P body region above the two N column regions are provided with deep trenches, and the bottoms of the deep trenches extend into the N^-In the auxiliary layer; the deep groove is internally provided with an upper part of polycrystalline silicon and a lower part of polycrystalline silicon, and is filled with a silicon dioxide layer; the polysilicon above is called as grid G, and the silicon dioxide layer around the grid G is thinner; the polysilicon below is called a shielding grid SG, the silicon dioxide layers at the two sides and the bottom of the shielding grid SG are thicker, and the shielding grid SG is connected with the source S in the three-dimensional direction; the silicon dioxide layer on the upper surface of the deep groove isolates the source S from the grid G; in N⁺And a drain electrode D is arranged on the lower surface of the drain region.

In the first SJSGT structure of the present invention, the following specific features are also included:

1) width W of gate G_GThickness T of silicon dioxide layer on both sides_GOXSum of the sum and width W of shield gate SG_SGWith thickness T of silicon dioxide layer on both sides_SGOXThe sum being equal, i.e. W_G+2T_GOX＝W_SG+2T_SGOX；

2) The thickness of the P column region is equal to that of the N column region, the doping of the P column region is equal to that of the N column region, and the width W of the N column region_NIs slightly wider than the width W of the P column region_PWithin a range of difference Δ W ═ W_N-W_PIs 0.1 to 1 mu m, namely delta W is more than or equal to 0.1 mu m and less than or equal to 1 mu m;

3) bottom N^-Thickness of auxiliary layer increasing with breakdown voltage of devicePlus and increase, N^-The thickness range of the auxiliary layer is 2-10 mu m;

4) the bottom of the trench of the shielding grid SG extends into the bottom auxiliary layer, and the deviation delta L from the position of the super junction bottom is controlled within 3 mu m, namely, the delta L is more than 0 mu m and less than or equal to 3 mu m.

The manufacturing method of the SJSGT structure in the first embodiment of the invention is implemented according to the following steps:

step 1, manufacturing a substrate: low resistance<100>N⁺Silicon substrate → epitaxial N^-An auxiliary layer;

step 2, manufacturing a super junction column region: epitaxial P column region → photoetching → deep groove etching → sacrificial oxide film growth → phosphorus ion oblique angle injection → sacrificial oxide layer removal → annealing and advancing to form N column region;

step 3, manufacturing an SGT structure: thermally growing a silicon dioxide field oxide layer → depositing polysilicon and doping to fill the trench → etching a cellular region of the cell (masking a gate lead-out region with photoresist) → etching the polysilicon in the trench to form a gate shield → etching the cellular region of the cell → wet etching to remove the silicon dioxide field oxide layer on the surface of the silicon wafer and on the sidewall of the trench → using High Density Plasma Chemical Vapor Deposition (HDPCVD) to isolate the oxide film and the gate oxide layer → depositing a polysilicon gate in the trench → etching the cellular region of the cell and the gate lead-out region of the gate shield → injecting boron ions and propelling to form a P body region → etching the cellular region of the cell → injecting phosphorus ions in the P body region to form an N body region⁺A source region;

step 4, manufacturing a front electrode structure: forming a layer of phosphosilicate glass (PSG) by chemical vapor deposition → photoetching → forming a groove type contact hole by etching → depositing refractory metal in the contact hole → adopting CMP surface planarization → depositing a surface metal (AlCu) layer → photoetching pressure welding point → etching to form electrodes of a front grid and a source electrode;

step 5, manufacturing a back electrode structure: thinning the back N⁺Silicon substrate → backside multilayer (TiNiAg) metallization.

Referring to fig. 4, which is a cross-sectional view of a second embodiment SJSGT structure (for convenience of distinguishing between two embodiment structures, abbreviated as SJSGT in the respective drawings) of the present invention, the second embodiment SJSGT structure differs from the first SJSGT structure as follows: the shielding grid SG is vertically arranged at the central position in the deep groove, two sides of the upper part of the shielding grid SG are respectively provided with a grid G, the two grids G and the shielding grid SG are arranged in a left-middle-right layout, and the middle of the grids G is isolated by a silicon dioxide layer.

The key parameters of the second SJSGT structure are consistent with those of the first SJSGT structure; the following specific features may be further selected:

1) the thickness of the P column region is equal to that of the N column region, the doping of the P column region is equal to that of the N column region, and the width W of the N column region_NIs slightly wider than the width W of the P column region_PWithin a range of difference Δ W ═ W_N-W_PIs 0.1 to 1 mu m, namely delta W is more than or equal to 0.1 mu m and less than or equal to 1 mu m;

2) bottom N^-The thickness of the auxiliary layer increases with the breakdown voltage of the device, N^-The thickness range of the auxiliary layer is 2-10 mu m;

3) the groove of the shielding grid SG extends into the bottom auxiliary layer, and the deviation delta L from the bottom of the super junction is controlled within 3 mu m, namely, the delta L is more than 0 mu m and less than or equal to 3 mu m.

The process flow of the second SJSGT structure of the invention is simpler than that of the first SJSGT structure of the invention, and the difference is mainly that the SGT and the front electrode structure are different in manufacture, and the process flow is implemented according to the following steps:

step 1, manufacturing a substrate: low resistance<100>N⁺Silicon substrate → epitaxial N^-An auxiliary layer;

step 2, manufacturing a super junction column region: epitaxial P column region → photoetching → deep groove etching → sacrificial oxide film growth → phosphorus ion oblique angle injection → sacrificial oxide layer removal → annealing and advancing to form N column region;

step 3, manufacturing an SGT structure: thermally growing silicon dioxide field oxide layer in the groove → depositing polysilicon in the groove and doping → photoetching → etching the surface of the silicon chip and the polysilicon in the groove to form a shielding grid under the silicon surface → photoetching → wet etching to remove the silicon dioxide field oxide layer on the surface of the silicon chip and in the groove to form a grid groove → thermally growing silicon dioxide gate oxide layer → depositing polysilicon and doping → photoetching → etching the polysilicon gate to the bottom of the silicon surface → boronIon implantation and drive-in to form P body region → arsenic ion implantation to form N in P body region⁺A source region;

step 4, manufacturing a front electrode structure: forming a layer of phosphosilicate glass (PSG) by chemical vapor deposition → photoetching → forming a contact hole of a source electrode and a shielding gate by etching → depositing a surface metal layer → photoetching pressure welding spot → etching to form an electrode of a front grid electrode and the source electrode;

step 5, manufacturing a back electrode structure: thinning the back N⁺Silicon substrate → backside multilayer (TiNiAg) metallization.

Performance evaluation:

in order to facilitate comparison and evaluation of performances of the SJSGT structure and the SJSGT structure of the invention, models of the respective structures are established according to fig. 1, fig. 2, fig. 3 and fig. 4, the set parameters such as longitudinal thickness, cell width, bottom auxiliary layer concentration, source drain region concentration and channel concentration are the same, the column region thickness and product of the column region concentration and the column region width of the con.dtsj are the same as those of the SJSGT structure and the SJSGT structure, but the deep trench of the con.dtsj hardly exhausts the N column region, so that the P column region and the N column region of the con.dtsj have the same width, and the P column region of the SJSGT structure and the SJSGT structure are slightly wider; the drift region concentration of sgt is the same as that of the bottom auxiliary layer of the SJSGT structure and the SJSGT structure, and the vertical size of the shield gate is also the same, and a voltage class of 200V is used as an example for comparison.

(1) Electric field distribution at breakdown

Fig. 5 is a graph comparing the inventive SJSGT structure with the longitudinal electric field distribution of con.dtsj and con.sgt at T300K along the junction of P and N column regions. As can be seen from fig. 5, the electric field distribution of the three parts is composed of two parts, wherein the electric field peaks of the inventive SJSGT structure and con.sgt both appear at the interface of the super junction region and the bottom auxiliary layer (Y ═ 9 μm), which is due to the electric field peaks at the corners of the shielding gate SG; the electric field peak of con.dtsj appears at the super junction portion. In comparison, the electric field of the SJSGT structure in the super junction region is approximately in rectangular distribution, the auxiliary layer and the drain region at the bottom are in trapezoidal distribution, and the electric field intensity is enclosed to be the largest in area, so that the voltage resistance is highest.

(2) Breakdown characteristic

Fig. 6 is a comparison of the SJSGT structure of the present invention with the breakdown characteristics of con.dtsj and con.sgt at different temperatures. As can be seen from FIG. 6, the current density at T300K for the three devices is 0.1mA/cm²Avalanche breakdown happens, at the moment, the breakdown voltage of the SJSGT structure is 237.3V, the breakdown voltage of Con.DTSJ is 181.2V, and the breakdown voltage of Con.SGT is 204.9V, so that compared with the Con.DTSJ and Con.SGT, the breakdown voltage of the SJSGT structure is improved by 31% and 15.8% respectively; three devices at a current density of 0.1A/cm under the condition of T-400K²Avalanche breakdown occurs, at the moment, the breakdown voltage of the SJSGT structure is 273.8V, the breakdown voltage of Con.DTSJ is 219.6V, and the breakdown voltage of Con.SGT is 236V, so that compared with Con.DTSJ and Con.SGT, the breakdown voltage of the SJSGT structure is improved by 24.7% and 16%, respectively. Under the voltage of 200V, the leakage current density of the SJSGT structure is J when T is 300K_DSS＝0.77μA/cm²(ii) a Leakage current density is J when T is 400K_DSS＝400μA/cm²。

(3) Conduction characteristic

Fig. 7 is a comparison of the SJSGT structure of the present invention with the conduction characteristics of con.dtsj and con.sgt at 330K and 400K. As can be seen from fig. 7, the characteristic on-resistance R of the SJSGT structure of the present invention when T is 300K_on，sp＝5.472mΩ·cm²(ii) a R when T is 400K_on，sp＝7.956mΩ·cm²(ii) a Con.DTSJ R when T300K_on，sp＝5.812mΩ·cm²(ii) a R when T is 400K_on，_sp＝9.235mΩ·cm²(ii) a C. sgt when T300K, R_on，sp＝7.804mΩ·cm²(ii) a R when T is 400K_on，sp＝12.847mΩ·cm². Compared with Con.DTSJ, the characteristic on-resistance of the SJSGT structure is reduced by 5.85% and 13.85% when T is 300K and T is 400K respectively; compared with con.sgt, the SJSGT structure of the present invention has a 29.9% reduction in characteristic on-resistance at both T300K and T400K.

(4) Grid charge

Gate charge Q_gFinger gate current I_gAnd gate capacitance charging time t_gProduct of (d), gate drain charge Q_gdFinger gridPolar current I_gAnd gate-drain capacitance charging time t_gdThe product of (a). Q_gAnd Q_gdThe larger the switching characteristic, the worse the switching characteristic. Fig. 8 is a comparison of the SJSGT structure of the present invention with gate charge test curves for con.dtsj and con.sgt at T300K. As can be seen from FIG. 8, in I_gQ of SJSGT structure of the invention was calculated at 5mA_g33nC and Q_gd8.5 nC; q of Con. DTSJ_g32.5nC and Q_gd14 nC; q of Con. SGT_g32.5nC and Q_gd8 nC. Therefore, the gate-to-drain charge of the SJSGT structure of the present invention is 39.2% lower than that of con.dtsj, which is almost the same as the gate charge of con.sgt.

(5) Switching characteristics

Fig. 9 is a shutdown characteristic comparison curve of the SJSGT structure of the present invention versus con.dtsj and con.sgt at T300K and 400K. As can be seen from fig. 9, the SJSGT structure of the present invention is T when T is 300K_d(off)77 ns; t when T is 400K_d(off)When the turn-off delay time is 79ns, the turn-off delay time is not different from that of Con.SGT, but the turn-off delay time is respectively reduced by 13.5% and 13.2% compared with that of Con.DTSJ at the same temperature, so that the turn-off speed is greatly accelerated.

(6) Dynamic avalanche characteristic

Fig. 10 is a dynamic avalanche contrast curve for the SJSGT structure of the present invention versus con.dtsj and con.sgt at T300K. As can be seen from fig. 10, when the load inductance L is 0.2mH, the avalanche current I of the SJSGT structure of the present invention is_ASThe avalanche tolerance E was calculated as 72.1A_AS693.1 mJ; avalanche current I of Con.DTSJ_ASThe avalanche capacity E was calculated as 71.9A_AS689.1 mJ; avalanche current I of con. sgt_ASThe avalanche capacity E was calculated as 71.8A_AS687.4 mJ. In comparison, the avalanche tolerance of the SJSGT structure of the present invention is slightly improved.

(7) Key characteristics and figure of merit comparison

Fig. 11 shows breakdown voltage versus on resistance for SJSGT structures and SJSGT structures of the present invention compared to con.dtsj and con.sgt. As can be seen from fig. 11, the SJSGT structures and SJSGT structures of the present invention have higher breakdown voltages and lower on-resistances at 300K and 400K (outside the dashed box) compared to con.dtsj and con.sgt.

FIG. 12 is a static merit (BV) of the SJSGT structure and Con.DTSJ and Con.SGT of the present invention²/R_on,sp) And dynamic figure of merit (R)_on·Q_gd) Comparison of (1). As can be seen from fig. 12, at T300K, the SJSGT structures and SJSGT structures of the present invention have higher static figure of merit and lower dynamic figure of merit compared to con.dtsj and con.sgt, and thus have more excellent static and dynamic performance.

(8) Critical structural parameters

The position change of the bottom of the shielding grid has great influence on the characteristics of the device. The dimension Δ L (as shown in fig. 3 and 4) of the shield gate trench bottom beyond the bottom of the super junction is defined as the longitudinal dimension Δ L if the shield gate is too short (Δ L)<0) A part of the bottom of the super junction N column region can not be effectively depleted by the shielding grid, so that a longitudinal electric field is enhanced, and the breakdown voltage of the device is reduced; if the longitudinal dimension of the shielding grid is too long (Δ L)>0) Since the peak value of the electric field at the corners of the shielding gate is high, the electric field of the bottom auxiliary layer is modulated, so that the electric field of the bottom auxiliary layer is enhanced, and the device is easy to break down at the position. In order to ensure the charge balance of the super junction, the bottom position of the shielding grid needs to be strictly controlled. See fig. 13 for a deviation Δ L between trench bottom position and super junction bottom for SJSGT structures and SJSGT structures of the present invention versus breakdown voltage BV and characteristic on-resistance R_on,spThe influence of (c). As can be seen from fig. 13, when Δ L is taken from-0.3 μm to 1 μm, the breakdown voltage increases first and then decreases, but the on-resistance increases all the time. When Δ L is 0.2 μm, the breakdown voltage of the SJSGT structure of the present invention is large, the on-resistance is low, and the static merit value (BV) is low²/R_on,sp) Maximum; the static figure of merit for the SJSGT structure of the present invention is greatest when Δ L is 0.4 μm.

Thickness T of the bottom auxiliary layer_N-Too thin T, which also has a large influence on the static characteristics of the device_N-The breakdown voltage of the device can not meet the design requirement, but the T is too thick_N-Although the breakdown voltage of the device is guaranteed, this results in an increase in the characteristic on-resistance, so T_N-The reasonable value of the threshold voltage is important for coordinating the contradiction between the breakdown voltage and the characteristic on-resistance of the device. See FIG. 14, thickness T of bottom auxiliary layer of SJSGT structure and SJSGT structure of the invention_N-Breakdown voltage BV and characteristic on-resistance R_on,spThe influence of (c). As can be seen from FIG. 14, the static merit (BV) was calculated²/R_on,sp) It follows that for the SJSGT structure of the present invention, T_N-The optimal value of (A) is about 7 mu m; for the SJSGT structure of the present invention, T_N-The optimal value of (A) is about 7 mu m.

In summary, the SJSGT structure and the SJSGT structure of the present invention not only have the advantages of high breakdown voltage, low on-resistance and fast switching speed, but also have slightly high dynamic avalanche tolerance, and can completely replace the structures of the conventional deep trench gate super junction MOS and the conventional SGT.