阅读说明：本技术 一种新型分离栅mosfet器件 (Novel separation grid MOSFET device ) 是由 刘锋 周祥瑞 殷允超 于 2021-09-29 设计创作，主要内容包括：本发明公开了一种新型分离栅MOSFET器件,其技术方案要点是：包括MOSFET管,所述MOSFET管包括有底层的N+衬底,所述N+衬底的上层设有epi1层,所述epi1层的上层设有epi2层,所述epi1层和所述epi2层内通过刻蚀硅形成沟槽,所述沟槽中有源区内深度刚好穿透epi2层,所述沟槽中终端区内深度穿透epi2层的深度为0.5um,所述沟槽的内部分别淀积有第一多晶硅、第二多晶硅和第三多晶硅,所述epi2层的上层注入P型杂质B+。本发明采用新型分离栅结构,底部的epi1较浓,顶部的epi2较淡,有源区沟槽底部深入到epi1界面上,此处掺杂浓度比较浓,硅的雪崩临界电场随掺杂浓度增加而增加,有利于提升耐压,以40V器件为例,RSP达到6.5mohm.mm2。(The invention discloses a novel separation grid MOSFET device, which has the technical scheme main points that: including the MOSFET pipe, the MOSFET pipe is including the N + substrate of bottom, the upper strata of N + substrate is equipped with epi1 layer, the upper strata on epi1 layer is equipped with epi2 layer, epi1 layer with form the slot through the sculpture silicon in the epi2 layer, the depth just pierces through epi2 layer in the active area in the slot, the depth that the depth pierces through epi2 layer in the terminal area is 0.5um in the slot, the inside of slot is deposited respectively first polycrystalline silicon, second polycrystalline silicon and third polycrystalline silicon, P type impurity B + is injected into to the upper strata on epi2 layer. The invention adopts a novel separation gate structure, the epi1 at the bottom is thicker, the epi2 at the top is thinner, the bottom of the groove of the active region is deeper to an epi1 interface, the doping concentration is thicker, the avalanche critical electric field of silicon is increased along with the increase of the doping concentration, the withstand voltage is favorably improved, and the RSP reaches 6.5mohm.mm2 by taking a 40V device as an example.)

1. The utility model provides a novel separation bars MOSFET device, includes the MOSFET pipe, its characterized in that: the MOSFET comprises an N + substrate (1) with a bottom layer, an epi1 layer (2) is arranged on the upper layer of the N + substrate (1), and the MOSFET is characterized in thatThe upper strata of epi1 layer (2) is equipped with epi2 layer (3), epi1 layer (2) with form slot (4) through etching silicon in epi2 layer (3), the depth that the active area in the slot (4) is interior just pierces through epi2 layer (3), the depth that the depth pierces through epi2 layer (3) in the termination region is 0.5um in slot (4), the inside of slot (4) is deposited respectively first polycrystalline silicon (5) and second polycrystalline silicon (6), the upper end of first polycrystalline silicon (5) still deposits third polycrystalline silicon (7), the upper strata injection P type impurity B + (8) of epi2 layer (3), the one end of P type impurity B + (8) forms N + injection region (9) through the photoetching, N⁺N is injected into the injection region (9)⁺(10) The P-type impurity B⁺(8) A dielectric deposition layer (11) is deposited on the substrate, and a metal deposition layer (12) is deposited on the dielectric deposition layer (11).

2. The novel split-gate MOSFET device of claim 1, wherein: the two ends of the MOSFET tube are divided into a Cell region (13) and a Ring region (14), the bottom end of the trench (4) in the Cell region (13) is positioned at the junction of the epi1 layer (2) and the epi2 layer (3), and the bottom end of the trench (4) in the Ring region (14) is positioned inside the epi1 layer (2).

3. The novel split-gate MOSFET device of claim 1, wherein: the P-type impurity B⁺(8) Advancing the formation of P-type impurity B on said epi2 layer (3)⁺An implantation region (15), the P-type impurity B⁺The junction depth of the implanted region (15) is 0.7 um.

4. The novel split-gate MOSFET device of claim 1, wherein: an oxidation layer (16) is arranged on the inner wall of the groove (4), and the oxidation layer (16) is a thermally grown thin oxidation layer 500A and a CVD deposition oxidation layer 1000A-1500A.

5. The novel split-gate MOSFET device of claim 1, wherein: the epi1 layer (2) has a higher silicon doping concentration than the epi2 layer (3), the epi2 layer (3) has an RSP of up to6.5mohm.mm²。

6. The novel split-gate MOSFET device of claim 1, wherein: the first polysilicon (5) forms a source, the third polysilicon (7) forms a gate, and the second polysilicon (6) forms a drain.

7. The novel split-gate MOSFET device of claim 1, wherein: one end of the metal deposition layer (12) penetrates and is embedded in the medium deposition layer (11) and the P-type impurity B⁺(8) And said N⁺(10) An end portion of (a).

8. The novel split-gate MOSFET device of claim 2, wherein: the Cell area (13) inside the degree of depth of slot (4) is 2-3um, the Ring area (14) inside the degree of depth of slot (4) is 2.3-3.5um, epi1 layer (2) with the thickness of epi2 layer (3) is 2-3 um.

Technical Field

The invention relates to the field of MOSFET devices, in particular to a novel split gate MOSFET device.

Background

Taking a 40V device as an example, a low-voltage mosfet device in the prior art generally adopts a high-density Trench structure as shown in fig. 1, a material generally adopts a red phosphorus substrate sub doped with a relatively high concentration, two layers of epitaxy are grown on the red phosphorus substrate sub, generally epi1 is doped with a relatively high concentration, so as to reduce the concentration difference between epi1 and the substrate sub and further reduce the degree of substrate back-expansion, and epi2 is doped with a relatively low concentration and is used for supporting device voltage resistance.

Referring to the prior chinese patent with publication number CN208400855U, a split-gate MOSFET device structure is disclosed, which includes an active region, the active region includes a plurality of device cell units connected in parallel, each device cell unit includes a first conductive type substrate and a first conductive type drift region, a second conductive type well region is disposed on the upper portion of the first conductive type drift region, a first type trench and a second type trench located at two sides of the first type trench are disposed between the second conductive type well regions, the trenches extend from the surface of the first conductive type drift region to the inside of the first conductive type drift region, the first type trench is filled with a split-gate polysilicon, a thick oxide layer and a masking oxide layer, the second type trench is filled with a gate polysilicon and a gate oxide layer, and the inner side of the gate polysilicon is adjacent to the thick oxide layer.

The manufacturing process of the split gate MOSFET device structure is simple, the photoetching times are few, the cost is low, meanwhile, the width and the depth of the trench of the split gate device are easy to control, the voltage resistance of the device is better, and the on-resistance is lower. The split gate MOSFET device structure described above still has a high RSP.

Disclosure of Invention

In view of the problems mentioned in the background, it is an object of the present invention to provide a novel split gate MOSFET device to solve the problems mentioned in the background.

The technical purpose of the invention is realized by the following technical scheme:

a novel split gate MOSFET device comprises MOSFET tubes including bottom N⁺Substrate, said N⁺The upper strata of substrate is equipped with epi1 layer, the upper strata on epi1 layer is equipped with epi2 layer, the epi1 layer with form the slot through sculpture silicon in the epi2 layer, the depth that the active area in the slot is interior just pierces through epi2 layer, the depth that the depth pierces through epi2 layer in the termination region in the slot is 0.5um, the inside deposit respectively of slot has first polycrystalline silicon and second polycrystalline silicon, the last layer of epi1 layer is equipped with epi2 layer, the epi1 layer with the epi2 in situ, the depth that the depth pierces through epi2 layer in the termination region is 0.5um, the inside of slot deposits respectively has first polycrystalline silicon and second polycrystalline silicon, the last layer of epi is equipped with the first polycrystalline silicon and second polycrystalline siliconThe upper end of the first polysilicon is also deposited with a third polysilicon, and the upper layer of the epi2 layer is implanted with P-type impurity B⁺The P-type impurity B⁺Is formed into N by photolithography⁺An implanted region of said N⁺The injection region is internally injected with N⁺The P-type impurity B⁺Having a dielectric deposition layer deposited thereon, said dielectric deposition layer having a metal deposition layer deposited thereon.

By adopting the technical scheme, the 40V MOSFET device adopts a novel separation gate structure, double-layer epitaxy is also adopted, the epi1 at the bottom is thicker, the back-expansion degree of a substrate is reduced on one hand, on the other hand, the bottom of a deep groove is just positioned on an epi1 and epi2 epitaxial interface, the doping concentration of silicon at the interface is lighter than epi1 and thicker than epi2, the avalanche critical electric field of the silicon is increased along with the increase of the doping concentration, and the withstand voltage is improved; the epi2 at the top is lighter than the epi1 at the bottom (thicker than the epi2 of the common Trench product), and the charge balance principle is applied to increase the withstand voltage, so that better RSP is obtained, and the RSP reaches 6.5mohm²。

Preferably, the two ends of the MOSFET tube are divided into a Cell region and a Ring region, the bottom end of the trench in the Cell region is located at the junction of the epi1 layer and the epi2 layer, and the bottom end of the trench in the Ring region is located inside the epi1 layer.

By adopting the technical scheme, the depth difference of the grooves on the two sides is 0.3-0.5um, the withstand voltage of the Ring region can be ensured to be larger than that of the cell region after the device is formed, and the reliability of the device is ensured.

Preferably, the P-type impurity B⁺Advancing formation of P-type impurity B on said epi2 layer⁺An implanted region of the P-type impurity B⁺The junction depth of the implanted region is 0.7 um.

By adopting the technical scheme, the P-type impurity B⁺The conductivity of the MOSFET can be effectively improved.

Preferably, an oxide layer is arranged on the inner wall of the groove, and the oxide layer is a thermally grown thin oxide layer 500A and a CVD deposited oxide layer 1000A-1500A.

By adopting the technical scheme, the oxide layer can effectively inhibit high-density electron and hole traps which can introduce a fast interface state to cause charge instability under bias voltage and temperature stress, reduce the generation of tensile stress caused by different thermal expansion coefficients of silicon and silicon dioxide to cause more defects of the oxide layer near the silicon, and reduce small spots and oxide layer pinholes caused by uneven local growth rate of the oxide layer.

Preferably, the silicon doping concentration of the epi1 layer is higher than that of the epi2 layer, and the RSP of the epi2 layer reaches 6.5mohm²。

By adopting the technical scheme, the withstand voltage is improved by utilizing the increase of the avalanche critical electric field of the silicon along with the increase of the doping concentration; the concentration of the top epi2 layer is lighter than that of the epi1 layer (the epi2 layer is thicker than that of the common Trench product), and the charge balance principle is applied to increase the withstand voltage, so that better RSP is obtained, and the RSP reaches 6.5mohm²。

Preferably, the first polysilicon forms a source, the third polysilicon forms a gate, and the second polysilicon forms a drain.

By adopting the technical scheme, an effective external circuit connector can be formed, and the connection and use of the circuit are facilitated.

Preferably, one end of the metal deposition layer penetrates through and is embedded in the medium deposition layer and the P-type impurity B⁺And said N⁺An end portion of (a).

By adopting the technical scheme, effective line connection can be formed, and the MOSFET tube is convenient to use.

Preferably, the depth of the groove inside the Cell area is 2-3um, the depth of the groove inside the Ring area is 2.3-3.5um, and the thicknesses of the epi1 layer and the epi2 layer are both 2-3 um.

By adopting the technical scheme, after the device is formed, the withstand voltage of the Ring region can be ensured to be larger than that of the cell region, and the reliability of the device is ensured.

In summary, the invention mainly has the following beneficial effects:

the 40V MOSFET device adopts a novel separation gate structure and also adopts double layersEpitaxy is carried out, the epi1 at the bottom is thicker, the back-expansion degree of the substrate is reduced on one hand, on the other hand, the bottom of the deep groove is just positioned on an epi1 and epi2 epitaxial interface, the doping concentration of silicon at the interface is lighter than epi1 but thicker than epi2, the avalanche critical electric field of the silicon is increased along with the increase of the doping concentration, and the withstand voltage is improved; the epi2 at the top is lighter than the epi1 at the bottom (thicker than the epi2 of the common Trench product), and the charge balance principle is applied to increase the withstand voltage, so that better RSP is obtained, and the RSP reaches 6.5mohm²。

Drawings

FIG. 1 is a schematic diagram of a prior art MOSFET structure of the present invention;

fig. 2 is a schematic diagram of a MOSFET structure of the present invention.

Reference numerals: 1. n is a radical of⁺A substrate; 2. epi1 layers; 3. epi2 layers; 4. a trench; 5. a first polycrystalline silicon; 6. a second polycrystalline silicon; 7. a third polycrystalline silicon; 8. p-type impurity B⁺；9、N⁺An implantation region; 10. n is a radical of⁺(ii) a 11. A dielectric deposition layer; 12. a metal deposition layer; 13. a Cell area; 14. a Ring region; 15. p-type impurity B⁺An implantation region; 16. and oxidizing the layer.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Examples

Referring to fig. 1-2, a novel split-gate MOSFET device includes a MOSFET transistor including a bottom layer of N⁺Substrate 1, N⁺An epi1 layer 2 is arranged on the upper layer of the substrate 1, an epi2 layer 3 is arranged on the upper layer of the epi1 layer 2, a groove 4 is formed in the epi1 layer 2 and the epi2 layer 3 through silicon etching, the depth of an active area in the groove 4 just penetrates through the epi2 layer 3, the depth of a terminal area in the groove 4 penetrating through the epi2 layer 3 is 0.5 mu m, first polycrystalline silicon 5 and second polycrystalline silicon 5 are deposited inside the groove 4 respectivelySilicon 6, a third polysilicon 7 deposited on the upper end of the first polysilicon 5, an epi2 layer 3, and P-type impurity B implanted on the upper layer⁺8, P-type impurity B⁺An N + injection region 9 is formed at one end of the N + injection region 8 through photoetching, N +10 is injected into the N + injection region 9, a dielectric deposition layer 11 is deposited on the P type impurity B +8, and a metal deposition layer 12 is deposited on the dielectric deposition layer 11.

By adopting the technical scheme, the 40V MOSFET device adopts a novel separation gate structure, double-layer epitaxy is also adopted, the epi1 layer 2 at the bottom is thicker, the back-expansion degree of a substrate is reduced on one hand, on the other hand, the bottom of a deep groove is just positioned on an epitaxial interface of the epi1 layer 2 and the epi2 layer 3, the doping concentration of silicon at the interface is lighter than that of the epi1 layer 2 and thicker than that of the epi2 layer 3, the avalanche critical electric field of the silicon is increased along with the increase of the doping concentration, and the withstand voltage is improved; the epi2 layer 3 at the top is lighter than the epi1 layer 2 at the bottom, compared with the epi2 layer 3 of the common Trench product, and the charge balance principle is applied to increase the withstand voltage, so that better RSP is obtained, and the RSP reaches 6.5mohm²。

In this embodiment, it is preferable that both ends of the MOSFET tube are divided into a Cell region 13 and a Ring region 14, the bottom end of the trench 4 in the Cell region 13 is located at the junction of the epi1 layer 2 and the epi2 layer 3, and the bottom end of the trench 4 in the Ring region 14 is located inside the epi1 layer 2. The effect is that the depth difference of the grooves 4 on the two sides is 0.3-0.5um, after the device is formed, the withstand voltage of the Ring region 14 can be ensured to be larger than that of the cell region 13, and the reliability of the device can be ensured.

In this embodiment, preferably, the P-type impurity B⁺8 drive-in P-type impurity B on epi2 layer 3⁺Implantation of region 15, P-type impurity B⁺The junction depth of the implanted region 15 is 0.7 um. The effect is that the P-type impurity B⁺The conductive performance of the MOSFET can be effectively improved by setting the number 8.

In this embodiment, it is preferable that the inner wall of the trench 4 is provided with an oxide layer 16, and the oxide layer 16 is a thermally grown thin oxide layer 500A and a CVD-deposited oxide layer 1000A-1500A. The effect is that the oxide layer 16 can effectively inhibit high-density electron and hole traps, which can introduce fast interface states to cause charge instability under bias and temperature stress, and reduce tensile stress generated by different thermal expansion coefficients of silicon and silicon dioxide to cause more defects of the oxide layer near the silicon, and reduce small spots and oxide layer pinholes caused by uneven local growth rate of the oxide layer.

In this embodiment, it is preferable that the silicon doping concentration of the epi1 layer 2 is higher than that of the epi2 layer 3, and the RSP of the epi2 layer 3 reaches 6.5mohm². The effect is that the avalanche critical electric field of silicon is increased along with the increase of the doping concentration, so that the withstand voltage is improved; the concentration of the epi2 layer 3 at the top relative to the epi1 layer 2 is lighter than that of epi2 of a common Trench product, and the charge balance principle is applied to increase the withstand voltage, so that better RSP is obtained, and the RSP reaches 6.5mohm²。

In this embodiment, preferably, the first polysilicon 5 forms a source, the third polysilicon 7 forms a gate, and the second polysilicon 6 forms a drain. The effect does, can form effectual external circuit and connect, is convenient for carry out the connection of circuit and use.

In this embodiment, it is preferable that one end of the metal deposition layer 12 is embedded in the dielectric deposition layer 11 and the P-type impurity B⁺8 and N⁺10 at one end thereof. The effect is, can form effectual line connection, the use of the MOSFET pipe of being convenient for.

In this embodiment, it is preferable that the depth of the trench 4 inside the Cell region 13 is 2 to 3um, the depth of the trench 4 inside the Ring region 14 is 2.3 to 3.5um, and the thicknesses of the epi1 layer 2 and the epi2 layer 3 are both 2 to 3 um. The effect is that after the device is formed, the withstand voltage of the Ring region 14 can be ensured to be larger than that of the cell region 13, and the reliability of the device can be ensured.

The preparation method comprises the following steps:

the first step is as follows: in N⁺Growing an N epitaxial layer, namely epi1 layer 2, on the substrate 1, and growing epi2 layer 3 on epi1 layer 2, for example, using a 40VN red phosphorus substrate, the resistivities of epi1 layer 2 and epi2 layer 3 are 0.01-0.08ohm.cm and 0.1-0.2ohm.cm respectively, and the epitaxial thickness is 2-3 um;

the second step is that: depositing silicon dioxide on the epi2 layer 3, taking the silicon dioxide as a masking layer with the thickness of 0.6um, and photoetching and etching the masking layer to form a pattern;

the third step: the silicon dioxide masking layer is used as a barrier to etch silicon to form a groove 4, the trench CD of the Ring region 14 is larger than that of the cell region 13, and the etching rate is high, so that the depth of the groove 4 of the Ring region 14 exceeds 0.3-0.5um of the cell region 13, after a device is formed, the withstand voltage of the Ring region 14 can be ensured to be larger than that of the cell region 13, and the reliability of the device can be ensured;

the fourth step: forming a thermally grown thin oxide layer 500A + CVD deposited oxide layer 1000A-1500A on the surface of the epi2 layer 3 and in the trench 4;

the fifth step: depositing polycrystalline silicon, then etching the polycrystalline silicon, forming the polycrystalline silicon at the bottom of the groove 4, and removing the upper part of the oxide layer;

the fifth step: then HDP deposition oxide layer, CMP, and etching back to the isolation oxide layer with thickness of 2500-3000A;

and a sixth step: then carrying out gate oxidation, polysilicon deposition and polysilicon back etching;

the seventh step: implanting P-type impurity B +8 on epi2 layer 3 and advancing to form P-type impurity B⁺Implant region 15 with a junction depth of about 0.7 um;

eighth step: then, N + photoetching is carried out at one end of the P type impurity B +8 to form N⁺Injecting the region 9, and then injecting the N + 10;

the ninth step: performing medium deposition on the P-type impurity B +8 to form a medium deposition layer 11, and performing medium photoetching and hole corrosion;

the tenth step: then, a metal deposition layer 12 is deposited on the medium deposition layer 11, photoetching and corrosion are carried out, a grid electrode, a source electrode, back thinning, back silicon corrosion and back metallization are respectively led out, and a drain electrode is formed.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.