Boss grid SiC MOSFET device and manufacturing method thereof

文档序号：1955691 发布日期：2021-12-10 浏览：26次中文

阅读说明：本技术 一种凸台栅SiC MOSFET器件及其制造方法 (Boss grid SiC MOSFET device and manufacturing method thereof ) 是由许海东谌容王曦于 2021-11-12 设计创作，主要内容包括：本发明公开了一种凸台栅SiC MOSFET器件及其制造方法,应用于半导体器件技术领域；所述器件包括SiC MOSFET器件中心设置的n型漂移区、n型电阻调制区以及n型电阻调制区上方设有的p阱区、n+源区、p+接触区、p+屏蔽区、栅氧化层、栅下介质层、多晶硅栅、隔离介质层、钝化层、源极；n型漂移区的下方设有n型缓冲层和n型衬底,n型衬底的下表面和p+结区的下表面设置有漏极；本发明通过设置凸台状栅介质与复合型结势垒屏蔽源极,提高了栅极可靠性的同时,使SiC MOSFET器件在逆向偏置状态能够更容易导通,提高了SiC MOSFET器件的性能。(The invention discloses a boss grid SiC MOSFET device and a manufacturing method thereof, which are applied to the technical field of semiconductor devices; the device comprises an n-type drift region, an n-type resistance modulation region and a p-well region, an n + source region, a p + contact region, a p + shielding region, a gate oxide layer, a gate lower dielectric layer, a polysilicon gate, an isolation dielectric layer, a passivation layer and a source electrode, wherein the n-type drift region and the n-type resistance modulation region are arranged in the center of the SiC MOSFET device; an n-type buffer layer and an n-type substrate are arranged below the n-type drift region, and drain electrodes are arranged on the lower surface of the n-type substrate and the lower surface of the p + junction region; according to the invention, the boss-shaped gate dielectric and the composite junction barrier are arranged to shield the source electrode, so that the reliability of the gate electrode is improved, the SiC MOSFET device can be more easily conducted in a reverse bias state, and the performance of the SiC MOSFET device is improved.)

1. The utility model provides a boss gate SiC MOSFET device, its characterized in that includes n type substrate (1), n type buffer layer (2), n type drift region (3), n type resistance modulation district (4), p well region (5), n + source region (6), p + contact region (7), p + shielding region (8), under gate dielectric layer (9), gate oxide (10), polycrystalline silicon gate (11), isolation dielectric layer (12), source electrode (13), drain electrode (14) and passivation layer (15), wherein:

an n-type buffer layer (2) is arranged below the n-type drift region (3), an n-type substrate (1) is arranged below the n-type buffer layer (2), and a drain electrode (14) is arranged on the lower surface of the n-type substrate (1);

an n-type resistance modulation region (4) is arranged above the n-type drift region (3), a plurality of p well regions (5) are uniformly wrapped in the upper surface of the n-type resistance modulation region (4), n + source regions (6) are wrapped on the inner sides of the upper surfaces of the p well regions (5), p + contact regions (7) are arranged on the inner sides of the n + source regions (6), each p well region (5), each n + source region (6) and each p + contact region (7) are in a hollow closed shape in the horizontal direction, and the inner side boundary of a structure formed by the p + contact regions (7) and the p well regions (5) is in a step shape;

the upper surface of an n-type resistance modulation region (4) between p well regions (5) is uniformly wrapped with p + shielding regions (8), in the p + shielding regions (8), the p + shielding regions (8) in the regions opposite to the p well regions (5) arranged along the central axis direction of the device and along the direction vertical to the central axis direction of the device are first p + shielding regions (81), and the rest p + shielding regions (8) are second p + shielding regions (82);

the upper surfaces of the first p + shielding regions (81) and the n-type resistance modulation region (4) positioned between the first p + shielding regions (81) are covered with a gate lower dielectric layer (9); the upper surface of the part of the n + source region (6), the upper surface of the p well region (5), the upper surface of the n-type resistance modulation region (4) exposed between the p well region (5) and the p + shielding region (8) are covered with a gate oxide layer (10), the upper surface of the gate lower dielectric layer (9) is higher than the upper surface of the gate oxide layer (10), the upper surfaces of the gate lower dielectric layer (9) and the gate oxide layer (10) are covered with a polysilicon gate (11), and the section of the polysilicon gate (11) is in a boss shape;

an isolation dielectric layer (12) covers the upper surface of the polysilicon gate (11), the side wall of the polysilicon gate (11) and the side wall of the gate oxide layer (10); the upper surface of the isolation dielectric layer (12), the side wall of the isolation dielectric layer (12), the upper surface of the n-type resistance modulation region (4) and the upper surface of the p + contact region (7) between the isolation dielectric layer (12), the upper surface of the n + source region (6) and the upper surface of the p + shielding region (8) are covered with a source electrode (13); the source electrode (13) and the n-type resistance modulation region (4), the p + contact region (7), the n + source region (6) and the p + shielding region (8) present ohmic contact characteristics; the upper surface of the source electrode (13) is covered with a passivation layer (15), and at least 2 hollow-out areas exist in the passivation layer (15).

2. A mesa-gated SiC MOSFET device as claimed in claim 1, characterized in that the number of first p + shield regions (81) per row arranged in a direction perpendicular to the central axis of the device between adjacent p-well regions (5) is increasing from the central axis in both directions and is in the range from 3 to 20.

3. The mesa-gated SiC MOSFET device as recited in claim 1, wherein the first p + shielding region (81) has a horizontally oriented cross-sectional shape of a stripe, and the first p + shielding region (81) is in a horizontal vertical relationship with an outer edge of the p-well region (5);

each row of first p + shielding regions (81) arranged along the central axis direction of the device, the number of the first p + shielding regions between adjacent p well regions (5) being 1;

each row of first p + shielding regions (81) arranged in a direction perpendicular to the central axis of the device has a number of 1 between adjacent p-well regions (5) and a length in the direction perpendicular to the central axis of the device increasing from the central axis to both sides, the length ranging from 1.0 μm to 20 μm.

4. The mesa-gated SiC MOSFET device as claimed in claim 1, characterized in that the first p + shielding regions (81) of each row, which are arranged in a direction perpendicular to the central axis of the device, have a cross-sectional pattern between adjacent p-well regions (5) which is a combination of stripes and other shapes, wherein the first p + shielding regions (81) having a cross-sectional pattern of stripes are in a horizontal perpendicular relationship with the outer edges of the p-well regions (5), and the lengths thereof in the direction perpendicular to the central axis of the device exhibit an increasing rule from the central axis to the two sides, the lengths ranging from 1.0 μm to 20 μm.

5. A raised-mesa SiC MOSFET device as claimed in claim 4, wherein the number of first p + shield regions (81) per row arranged in a direction perpendicular to the central axis of the device between adjacent p-well regions (5) is 3, and two first p + shield regions (81) having a square cross-sectional image sandwich a first p + shield region (81) having a stripe cross-sectional image.

6. The SiC MOSFET device with raised mesa gate of claim 1, wherein the n-type resistance modulation region (4) has a decreasing impurity concentration from the bottom surface to the top surface.

7. A method for manufacturing a convex grid SiC MOSFET device is characterized by comprising the following steps:

selecting a 4H-SiC wafer as an n-type substrate (1);

sequentially extending an n-type buffer layer (2), an n-type drift region (3) and an n-type resistance modulation region (4) on the silicon surface of an n-type substrate (1) by a chemical vapor deposition method;

manufacturing a p-well region (5) on the upper surface of the n-type resistance modulation region (4) by an ion implantation and annealing method, manufacturing an n + source region (6) on the upper surface of the p-well region (5), manufacturing a p + contact region (7) on the inner side of the n + source region (6), and manufacturing a p + shielding region (8) on the upper surface of the n-type resistance modulation region (4) between the p-well regions (5);

manufacturing a gate lower dielectric layer (9) by a low-pressure chemical vapor deposition method, and patterning the gate lower dielectric layer (9) by a photoetching method;

manufacturing a gate oxide layer (10) by a high-temperature oxidation and nitrogen passivation method;

manufacturing a polysilicon gate (11) by a chemical vapor deposition method;

manufacturing an isolation medium layer (12) by a method of combining low-pressure chemical vapor deposition with plasma enhanced chemical vapor deposition;

respectively manufacturing a source electrode (13) and a drain electrode (14) by a vacuum evaporation and rapid thermal annealing method;

and manufacturing a passivation layer (15) on the upper surface of the finished device by a deposition and photoetching method.

8. A method for manufacturing a convex grid SiC MOSFET device is characterized by comprising the following steps:

selecting a 4H-SiC wafer as an n-type substrate (1);

sequentially extending an n-type buffer layer (2) and an n-type drift region (3) on the carbon surface of an n-type substrate (1) by a chemical vapor deposition method;

extending an n-type resistance modulation region (4) on the upper surface of the n-type drift region (3) through an ion implantation method;

sequentially manufacturing a p well region (5) on the upper surface of the n-type resistance modulation region (4) by a method of combining high-temperature ion implantation with high-temperature annealing, manufacturing an n + source region (6) on the upper surface of the p well region (5), manufacturing a p + contact region (7) on the inner side of the n + source region (6), and manufacturing a p + shielding region (8) on the upper surface of the n-type resistance modulation region (4) between the p well regions (5);

manufacturing a gate lower dielectric layer (9) by a high-temperature thermal oxidation method, and patterning the gate lower dielectric layer (9) by a photoetching method;

manufacturing a gate oxide layer (10) by a high-temperature oxidation and nitrogen passivation method;

manufacturing a polysilicon gate (11) by a chemical vapor deposition method;

manufacturing an isolation dielectric layer (12) by a plasma enhanced chemical vapor deposition method;

manufacturing a source electrode (13) by a method of combining vacuum evaporation and rapid thermal annealing;

manufacturing a drain electrode (14) by a method of combining vacuum evaporation and laser local thermal annealing;

and manufacturing a passivation layer (15) on the upper surface of the finished device by combining a plasma enhanced chemical vapor deposition method with a spin-on photoetching method.

9. A method for manufacturing a convex grid SiC MOSFET device is characterized by comprising the following steps:

selecting an n-type wafer of 4H-SiC as an n-type drift region (3);

sequentially extending an n-type buffer layer (2) and an n-type substrate (1) on the silicon surface of the n-type drift region (3) by a chemical vapor deposition method;

manufacturing an n-type resistance modulation region (4) on the carbon surface of the n-type drift region (3) by a high-temperature ion implantation method;

manufacturing a gate lower dielectric layer (9) by a plasma enhanced chemical vapor deposition method, and patterning the gate lower dielectric layer (9) by a photoetching method;

manufacturing a gate oxide layer (10) by a high-temperature oxidation and nitrogen passivation method, and manufacturing a polysilicon gate (11) by a chemical vapor deposition method;

manufacturing an isolation dielectric layer (12) by a plasma enhanced chemical vapor deposition method;

respectively manufacturing a source electrode (13) and a drain electrode (14) by a vacuum evaporation and rapid thermal annealing method;

and manufacturing a passivation layer (15) on the upper surface of the finished device by a spin coating and photoetching method.

10. The method of manufacturing a raised gate SiC MOSFET device as recited in any one of claims 7 to 9, further comprising: the thickness of the n-type substrate (1) is reduced by a method of grinding combined with chemical mechanical polishing and plasma etching.

Technical Field

The invention belongs to the technical field of semiconductor devices, and particularly relates to a convex grid SiC MOSFET device and a manufacturing method thereof.

Background

Silicon carbide (SiC) metal oxide field effect transistors (MOSFETs) have the advantages of high withstand voltage, reduced on-state voltage, fast switching speed, etc., and are widely used in power electronics as switching devices. Due to excellent switching characteristics and low power consumption characteristics, SiC MOSFETs have gradually become competitors to Insulated Gate Bipolar Transistors (IGBTs), and the market scale has been increasingly expanded, and have begun to gradually replace IGBTs in a plurality of fields such as motor control, power transmission, and power conversion. However, when the switching device is applied to power electronic circuits, due to the existence of circuit stray parameters, the SiC MOSFET often needs an anti-parallel SiC diode for freewheeling. The additional use of a diode for freewheeling increases both the cost of using the SiC MOSFET and the size of the module. Although the SiC MOSFET itself has a body diode, the use of the body diode of the SiC MOSFET itself for freewheeling can avoid the problem of volume increase caused by the additional provision of a freewheeling diode, but the SiC MOSFET has a large forbidden band width and an incomplete impurity ionization problem, and the switching performance of the SiC MOSFET itself is difficult to satisfy the demand of the SiC MOSFET. Aiming at the problems, a Junction Barrier Schottky (JBS) diode is integrated in the SiC MOSFET, a Schottky barrier is formed by drain metal and SiC, and conduction is realized under a reverse bias state, so that the problems of the volume and the cost of an additional freewheeling diode are solved, and the problem of insufficient performance of a body diode of the SiC MOSFET is solved. However, because the preparation process temperature of the SiC gold-half schottky junction is not matched with the preparation process temperature of the SiC MOSFET source ohmic contact metal, follow current is performed by adopting the technical scheme of integrating the SiC gold-half schottky junction, and additional process steps are required to be added to realize the integration of the SiC gold-half schottky junction, which causes the problems of increased complexity of the device manufacturing process, increased manufacturing cost of the device and the like. Therefore, there is a need to develop a high performance integrated freewheeling technique that does not require the use of SiC gold-half schottky junctions.

Disclosure of Invention

The purpose of the invention is as follows: aiming at the follow current problem defect of the SiC MOSFET device in the prior art, the invention further improves the reverse conduction performance of the SiC MOSFET device, and discloses the boss grid SiC MOSFET device and the manufacturing method thereof, wherein the boss-shaped grid medium and the composite junction barrier shield source electrode are arranged, so that the SiC MOSFET device can be more easily conducted in a reverse bias state, and the better reverse conduction performance is obtained, and the follow current problem defect is solved; meanwhile, the reliability of the grid electrode is further improved due to the arrangement of the boss-shaped grid medium, the overall performance of the SiC MOSFET device is further improved, and the problems that the volume cost of an additional freewheeling diode of the SiC MOSFET device is large and the performance of a body diode and an integrated JBS diode is insufficient are finally solved.

The technical scheme is as follows: in order to achieve the technical purpose, the invention adopts the following technical scheme:

the utility model provides a boss gate SiC MOSFET device, its characterized in that includes n type substrate, n type buffer layer, n type drift region, n type resistance modulation region, p well region, n + source region, p + contact region, p + shielding region, medium layer, gate oxide layer, polycrystalline silicon gate, isolation medium layer, source electrode, drain electrode and passivation layer under the bars, wherein:

an n-type buffer layer is arranged below the n-type drift region, an n-type substrate is arranged below the n-type buffer layer, and a drain electrode is arranged on the lower surface of the n-type substrate;

an n-type resistance modulation region is arranged above the n-type drift region, a plurality of p well regions are uniformly wrapped in the upper surface of the n-type resistance modulation region, n + source regions are wrapped in the inner sides of the upper surfaces of the p well regions, p + contact regions are arranged on the inner sides of the n + source regions (6), each p well region, each n + source region and each p + contact region are all in a hollow closed shape in the horizontal direction, and the inner side boundary of a structure formed by the p + contact regions and the p well regions is in a step shape;

the upper surface of an n-type resistance modulation region between p well regions is uniformly wrapped with p + shielding regions, wherein in the p + shielding regions, the p + shielding regions in the regions opposite to the p well regions arranged along the central axis direction of the device and along the direction vertical to the central axis direction of the device are first p + shielding regions, and the rest p + shielding regions are second p + shielding regions;

the upper surfaces of the first p + shielding regions and the n-type resistance modulation region positioned between the first p + shielding regions are covered with a gate lower dielectric layer; the upper surface of the n + source region part, the upper surface of the p well region, and the upper surface of the n-type resistance modulation region exposed between the p well region and the p + shielding region are covered with a gate oxide layer, the upper surface of the gate lower dielectric layer is higher than the upper surface of the gate oxide layer, the upper surfaces of the gate lower dielectric layer and the gate oxide layer are covered with polysilicon gates, and the cross section of each polysilicon gate is in a boss shape;

an isolation dielectric layer covers the upper surface of the polysilicon gate, the side wall of the polysilicon gate and the side wall of the gate oxide layer; the upper surface of the isolation dielectric layer, the side wall of the isolation dielectric layer, the upper surface of the n-type resistance modulation region and the upper surface of the p + contact region between the isolation dielectric layers, the upper surface of the n + source region and the upper surface of the p + shielding region are covered with source electrodes; the source electrode and the n-type resistance modulation region, the p + contact region, the n + source region and the p + shielding region present ohmic contact characteristics; the upper surface of the source electrode is covered with a passivation layer, and at least 2 hollow-out areas exist in the passivation layer.

Preferably, the number of the first p + shielding regions in each row arranged in a direction perpendicular to the central axis of the device increases from the central axis to both sides, and ranges from 3 to 20.

Preferably, the cross-sectional view of the first p + shielding region in the horizontal direction is a stripe, and the first p + shielding region and the outer edge of the p-well region are in a vertical relationship in the horizontal direction;

each row of first p + shielding regions is arranged along the central axis direction of the device, and the number of the first p + shielding regions between adjacent p well regions is 1;

and the number of the first p + shielding regions in each row arranged along the direction vertical to the central axis of the device is 1, the length of the first p + shielding regions along the direction vertical to the central axis of the device increases from the central axis to two sides, and the length ranges from 1.0 mu m to 20 mu m.

Preferably, each row of the first p + shielding regions arranged along the direction perpendicular to the central axis of the device has a cross-sectional pattern of a combination of a stripe shape and other shapes between adjacent p-well regions, wherein the cross-sectional pattern is that the stripe-shaped first p + shielding regions and the outer edges of the p-well regions are in a vertical relationship in the horizontal direction, and the length of the stripe-shaped first p + shielding regions along the direction perpendicular to the central axis of the device increases from the central axis to two sides, and the length ranges from 1.0 μm to 20 μm.

Preferably, each row of first p + shield regions arranged in a direction perpendicular to the central axis of the device, the number of which between adjacent p-well regions is 3, is formed by two first p + shield regions whose cross-sectional images are square sandwiching one first p + shield region whose cross-sectional image is strip-shaped.

Preferably, the impurity concentration of the n-type resistance modulation region is in a decreasing distribution rule from the lower surface to the upper surface.

A method for manufacturing a convex grid SiC MOSFET device is characterized by comprising the following steps:

selecting a 4H-SiC wafer as an n-type substrate;

sequentially extending an n-type buffer layer, an n-type drift region and an n-type resistance modulation region on the silicon surface of an n-type substrate by a chemical vapor deposition method;

manufacturing a p-well region on the upper surface of the n-type resistance modulation region by an ion implantation and annealing method, manufacturing an n + source region on the upper surface of the p-well region, manufacturing a p + contact region on the inner side of the n + source region, and manufacturing a p + shielding region on the upper surface of the n-type resistance modulation region between the p-well regions;

manufacturing a gate lower dielectric layer by a low-pressure chemical vapor deposition method, and patterning the gate lower dielectric layer by a photoetching method;

manufacturing a gate oxide layer by a high-temperature oxidation and nitrogen passivation method;

manufacturing a polysilicon gate by a chemical vapor deposition method;

manufacturing an isolation dielectric layer by a method of combining low-pressure chemical vapor deposition with plasma enhanced chemical vapor deposition;

respectively manufacturing a source electrode and a drain electrode by a vacuum evaporation and rapid thermal annealing method;

and manufacturing a passivation layer (15) on the upper surface of the finished device by a deposition and photoetching method.

A method for manufacturing a convex grid SiC MOSFET device is characterized by comprising the following steps:

selecting a 4H-SiC wafer as an n-type substrate;

sequentially extending an n-type buffer layer and an n-type drift region on the carbon surface of the n-type substrate by a chemical vapor deposition method;

extending the n-type resistance modulation region outside the upper surface of the n-type drift region by an ion implantation method;

sequentially manufacturing a p-well region on the upper surface of the n-type resistance modulation region, manufacturing an n + source region on the upper surface of the p-well region, manufacturing a p + contact region on the inner side of the n + source region, and manufacturing a p + shielding region on the upper surface of the n-type resistance modulation region between the p-well regions by a high-temperature ion implantation and high-temperature annealing method;

manufacturing a gate lower dielectric layer by a high-temperature thermal oxidation method, and patterning the gate lower dielectric layer by a photoetching method;

manufacturing a gate oxide layer by a high-temperature oxidation and nitrogen passivation method;

manufacturing a polysilicon gate by a chemical vapor deposition method;

manufacturing an isolation dielectric layer by a plasma enhanced chemical vapor deposition method;

manufacturing a source electrode by a method of combining vacuum evaporation and rapid thermal annealing;

manufacturing a drain electrode by a method of combining vacuum evaporation with laser local thermal annealing;

and manufacturing a passivation layer on the upper surface of the finished device by combining a plasma enhanced chemical vapor deposition method with a spin-coating photoetching method.

A method for manufacturing a convex grid SiC MOSFET device is characterized by comprising the following steps:

selecting an n-type wafer of 4H-SiC as an n-type drift region;

sequentially extending an n-type buffer layer and an n-type substrate on the silicon surface of the n-type drift region by a chemical vapor deposition method;

manufacturing an n-type resistance modulation region on the carbon surface of the n-type drift region by a high-temperature ion implantation method;

manufacturing a gate lower dielectric layer by a plasma enhanced chemical vapor deposition method, and patterning the gate lower dielectric layer by a photoetching method;

manufacturing a gate oxide layer by a high-temperature oxidation and nitrogen passivation method, and manufacturing a polysilicon gate by a chemical vapor deposition method;

manufacturing an isolation dielectric layer by a plasma enhanced chemical vapor deposition method;

respectively manufacturing a source electrode and a drain electrode by a vacuum evaporation and rapid thermal annealing method;

and manufacturing a passivation layer on the upper surface of the finished device by a spin coating and photoetching method.

Preferably, the method further comprises the following steps: and the thickness of the n-type substrate is reduced by grinding combined with chemical mechanical polishing and plasma etching.

Has the advantages that: compared with the prior art, the invention has the following beneficial effects:

1. the boss-shaped gate dielectric comprises the gate lower dielectric layer and the gate oxide layer, the gate leakage capacitance of the SiC MOSFET device is reduced, the boss-shaped gate dielectric on the surface of the n-type resistance modulation region can resist a higher electric field, the allowable distance between p well regions in the SiC MOSFET device can be larger, and a larger design window is provided for a composite junction barrier source electrode.

2. According to the invention, the p + shielding region is arranged under the boss-shaped gate dielectric, so that the boss-shaped gate dielectric can be shielded outside a high electric field in a blocking state of the SiC MOSFET device; meanwhile, the strip p + shielding region is perpendicular to the edge of the p-well region, so that the influence of the p + shielding region on the on-resistance of the SiC MOSFET device is reduced; the p + shielding region and the n-type resistance modulation region between the p + shielding regions are in ohmic contact with the source electrode, and another junction barrier source electrode is formed, so that the SiC MOSFET device is easier to conduct in a reverse bias state.

3. According to the invention, the p + contact region and the inner side edge of the p well region are arranged in a step shape, the impurity concentration of the n-type resistance modulation region is arranged in a descending distribution rule from the lower surface to the upper surface, and the exposed n-type resistance modulation region at the inner side of the p + contact region and the source electrode are arranged in an ohmic contact property, so that the composite junction barrier shielding source electrode is formed, the composite junction barrier shielding source electrode does not pass through current under a forward bias state, and the composite junction barrier source electrode conducts current to the drain electrode through the n-type resistance modulation region or the p + contact region under a reverse bias state, so that the reverse starting voltage of the SiC MOSFET device is reduced, and the reverse surge resistance of the SiC MOSFET device is improved.

4. According to the invention, the on-resistance of the SiC MOSFET device is reduced by thinning the n-type 4H-SiC substrate.

Drawings

Fig. 1a to fig. 1d are schematic structural diagrams of a mesa-gate SiC MOSFET device according to a first embodiment, where fig. 1a is a top view, AA ' represents a cut-off line perpendicular to a central axis of the device, CC ' represents a cut-off line parallel to the central axis of the device, and BB ' represents a cut-off line forming an angle of 45 ° with the central axis of the device; FIG. 1b is a cross-sectional view taken along line AA' of FIG. 1 a; FIG. 1c is a cross-sectional view taken along line BB' in FIG. 1 a; FIG. 1d is a cross-sectional view taken along line CC' of FIG. 1 a;

2 a-2 b are partial top plan and partial top perspective views of a raised-gate SiC MOSFET device in accordance with one embodiment, wherein FIG. 2b is a partial perspective view of portion D of FIG. 2a, and OO' represents a line taken between center points of adjacent p-well regions;

FIG. 3 is a schematic partial cross-sectional view of FIG. 2b taken along the cut-off line OO';

4 a-4 k are schematic flow charts of a method for fabricating a raised mesa SiC MOSFET device according to one embodiment;

fig. 5a to 5d are schematic structural diagrams of a mesa-gate SiC MOSFET device according to a second embodiment, wherein fig. 5a is a top view, AA ' represents a cut-off line perpendicular to a central axis of the device, CC ' represents a cut-off line parallel to the central axis of the device, and BB ' represents a cut-off line forming an angle of 45 ° with the central axis of the device; FIG. 5b is a cross-sectional view taken along line AA' of FIG. 5 a; FIG. 5c is a cross-sectional view taken along line BB' in FIG. 5 a; FIG. 5d is a cross-sectional view taken along section line CC' of FIG. 5 a;

fig. 6 a-6 b are partial top plan and partial top perspective views of a mesa-gated SiC MOSFET device according to a second embodiment, wherein fig. 6b is a partial perspective view of portion E of fig. 6a, and OO' represents an intercept line between center points of adjacent p-well regions;

FIG. 7 is a schematic partial cross-sectional view of FIG. 6b taken along the cut-off line OO';

FIGS. 8a to 8l are schematic flow charts of a method for manufacturing a raised mesa SiC MOSFET device according to the second embodiment;

fig. 9a to 9d are schematic structural diagrams of a mesa-gate SiC MOSFET device according to a third embodiment, where fig. 9a is a top view, AA ' represents a cut-off line perpendicular to a central axis of the device, CC ' represents a cut-off line parallel to the central axis of the device, and BB ' represents a cut-off line forming an angle of 45 ° with the central axis of the device; FIG. 9b is a cross-sectional view taken along line AA' of FIG. 9 a; FIG. 9c is a cross-sectional view taken along line BB' in FIG. 9 a; FIG. 9d is a cross-sectional view taken along section line CC' of FIG. 9 a;

10 a-10 b are partial top and partial top perspective views of a mesa-gated SiC MOSFET device in accordance with a third embodiment, wherein FIG. 10b is a partial perspective view of portion F of FIG. 10a and OO' represents a line taken between center points of adjacent p-well regions;

FIG. 11 is a schematic partial cross-sectional view of FIG. 10b taken along the line OO';

12 a-12 k are flow charts illustrating a method of fabricating a mesa-gate SiC MOSFET device according to a third embodiment;

FIG. 13 is a graph of the on-current-voltage characteristics of a raised mesa SiC MOSFET device of one of the first embodiments;

in the figure, a 1-n type substrate, a 2-n type buffer layer, a 3-n type drift region, a 4-n type resistance modulation region, a 5-p well region, a 6-n + source region, a 7-p + contact region, an 8-p + shielding region, an 81-first p + shielding region, an 82-second p + shielding region, a 9-grid lower dielectric layer, a 10-grid oxide layer, an 11-polysilicon grid, a 12-isolation dielectric layer, a 13-source electrode, a 14-drain electrode and a 15-passivation layer.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below, and it is apparent that the described embodiments are a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making creative efforts based on the embodiments of the present invention, shall fall within the protection scope of the present invention.

The first embodiment is as follows:

as shown in fig. 1a to 1d, fig. 2a to 2b, and fig. 3, the mesa-gate SiC MOSFET device provided in this embodiment improves the reliability of the gate, and at the same time, enables the SiC MOSFET device to be more easily turned on in a reverse bias state, solves the problem of freewheeling, and improves the performance of the SiC MOSFET device. Specifically, the SiC MOSFET device comprises an n-type substrate 1, an n-type buffer layer 2, an n-type drift region 3, an n-type resistance modulation region 4, a p well region 5, an n + source region 6, a p + contact region 7, a p + shielding region 8, a gate lower dielectric layer 9, a gate oxide layer 10, a polysilicon gate 11, an isolation dielectric layer 12, a source electrode 13, a drain electrode 14 and a passivation layer 15. The p + shielding region 8 has a horizontal cross-sectional pattern, i.e., a top view pattern, which is a square, a circle, a regular hexagon, a regular octagon, or a stripe.

An n-type buffer layer 2 is arranged below the n-type drift region 3, an n-type substrate 1 is arranged below the n-type buffer layer 2, and a drain electrode 14 is arranged on the lower surface of the n-type substrate 1. An n-type resistance modulation region 4 is arranged above the n-type drift region 3, and the impurity concentration of the n-type resistance modulation region 4 is in a descending distribution rule from the lower surface to the upper surface; a plurality of p-well regions 5 are uniformly wrapped in the upper surface of the n-type resistance modulation region 4, the p-well regions 5 are uniformly arranged along the central axis direction of the device and the direction vertical to the central axis direction of the device, the upper surface of each p-well region 5 is flush with the upper surface of the n-type resistance modulation region 4, and the section of each p-well region 5 in the horizontal direction is in a hollow closed shape; the inner side of the upper surface of the p well region 5 is wrapped with n + source regions 6, the upper surface of each n + source region 6 is flush with the upper surface of the p well region 5, the lower surface of each n + source region 6 is higher than the lower surface of the p well region 5, the section of each n + source region 6 in the horizontal direction is in a hollow closed shape, the inner side boundary of each n + source region 6 is arranged outside the inner side boundary of the p well region 5, the outer side boundary of each n + source region 6 is arranged inside the outer side boundary of the p well region 5, namely the inner side boundary and the outer side boundary of each n + source region 6 are both arranged between the inner side boundary and the outer side boundary of the p well region 5;

a p + contact region 7 is arranged on the inner side of the n + source region 6, the upper surface of the p + contact region 7 is flush with the upper surface of the n + source region 6, the lower surface of the p + contact region 7 is higher than the lower surface of the p well region 5, the lower surface of the p + contact region 7 is flush with the lower surface of the n + source region 6, the section of the p + contact region 7 in the horizontal direction is in a hollow closed shape, the inner side of the p + contact region 7 is connected with the n-type resistance modulation region 4, the outer side boundary of the p + contact region 7 is positioned outside the inner side boundary of the p well region 5 and is in contact with the inner side boundary of the n + source region 6, the inner side boundary of the p + contact region 7 is positioned inside the inner side boundary of the p well region 5, namely the inner side boundary of the p well region 5 is positioned between the inner side boundary and the outer side boundary of the p + contact region 7, and the inner side boundary of a structure formed by the p + contact region 7 and the p well region 5 is in a step shape;

the upper surfaces of the first p + shielding regions 81 and the n-type resistance modulation region 4 positioned between the first p + shielding regions 81 are covered with a gate lower dielectric layer 9; a gate oxide layer 10 covers the partial outer edge of the upper surface of the exposed n + source region 6 positioned outside the gate lower dielectric layer 9, the upper surface of the exposed p-well region 5, and the upper surface of the exposed n-type resistance modulation region 4 between the p-well region 5 and the p + shielding region 8; the lower surface of the gate lower dielectric layer 9 and the lower surface of the gate oxide layer 10 are both flush with the upper surface of the n-type resistance modulation region 4, the upper surface of the gate lower dielectric layer 9 is higher than the upper surface of the gate oxide layer 10, and the section of the structure formed by the gate oxide layer 10 and the gate lower dielectric layer 9 in the vertical direction is in a boss shape; the upper surface of the gate lower dielectric layer 9 and the upper surface of the gate oxide layer 10 are covered with a polysilicon gate 11, the section of the polysilicon gate 11 in the vertical direction is in a boss shape, namely, the lower surface and the upper surface of the polysilicon gate 11 are partially protruded upwards;

an isolation dielectric layer 12 covers the upper surface of the polysilicon gate 11, the side wall of the polysilicon gate 11 and the side wall of the gate oxide layer 10; the upper surface of the isolation dielectric layer 12, the side wall of the isolation dielectric layer 12, the upper surface of the exposed n-type resistance modulation region 4 and the upper surface of the exposed p + contact region 7 between the isolation dielectric layer 12, the upper surface of the exposed n + source region 6 and the upper surface of the exposed p + shielding region 8, namely the upper surface of the second p + shielding region 82 are covered with a source electrode 13; the source electrode 13, the n-type resistance modulation region 4, the p + contact region 7, the n + source region 6 and the p + shielding region 8 all have ohmic contact characteristics; the upper surface of the source electrode 13 is covered with a hollowed-out passivation layer 15, and at least 2 hollowed-out regions exist in the passivation layer 15 and are used for conducting wire bonding during packaging.

As shown in fig. 4a to 4k, the present embodiment further proposes a method for manufacturing a mesa-gate SiC MOSFET device, comprising the steps of: selecting a 4H-SiC wafer as the n-type substrate 1, as shown in FIG. 4 a;

sequentially extending an n-type buffer layer 2 and an n-type drift region 3 on the silicon surface of an n-type substrate 1 by a chemical vapor deposition method; extending an n-type resistance modulation region 4 on the upper surface of the n-type drift region 3 by a chemical vapor deposition method, as shown in FIG. 4 b;

manufacturing a p-well region 5 on the upper surface of the n-type resistance modulation region 4 by a method of combining high-temperature ion implantation and high-temperature annealing, as shown in fig. 4 c; manufacturing an n + source region 6 on the upper surface of the p-well region 5 by a method of high-temperature ion implantation combined with high-temperature annealing, as shown in fig. 4 d; a p + contact region 7 is made inside the n + source region 6 by a method of high temperature ion implantation combined with high temperature annealing, as shown in fig. 4 e; manufacturing a p + shielding region 8 on the upper surface of the n-type resistance modulation region 4 by a method of combining high-temperature ion implantation and high-temperature annealing, as shown in fig. 4 f;

manufacturing the gate lower dielectric layer 9 by a Low Pressure Chemical Vapor Deposition (LPCVD) method, and patterning the gate lower dielectric layer 9 by a photolithography etching method, as shown in fig. 4 g; manufacturing a gate oxide layer 10 by a high-temperature oxidation and nitrogen passivation method, as shown in fig. 4 h; manufacturing a polysilicon gate 11 by a chemical vapor deposition method, as shown in fig. 4 i; fabricating the isolation dielectric layer 12 by a method of Low Pressure Chemical Vapor Deposition (LPCVD) in combination with Plasma Enhanced Chemical Vapor Deposition (PECVD), as shown in fig. 4 j;

respectively manufacturing a source electrode 13 and a drain electrode 14 by a vacuum evaporation and rapid thermal annealing method, as shown in fig. 4 k;

and manufacturing a polyimide passivation layer 15 on the upper surface of the device completed in the above operation by a deposition and photoetching method.

In this embodiment, the n-type substrate 1 is made of 4H-SiC material, and is disposed below the n-type buffer layer 2, and has a thickness of 100 μm to 500 μm.

In this embodiment, the n-type buffer layer 2 is disposed between the n-type substrate 1 and the n-type drift region 3, has a thickness of 0.5 μm to 3.0 μm, and has a doping concentration of 1 × 10¹⁷cm^-3~1×10¹⁹cm^-3. In this embodiment, the n-type drift region 3 is disposed above the n-type buffer layer 2, and the n-type drift region 3 is dopedThe impurity concentration is 1X 10¹⁵cm^-3~5×10¹⁶cm^-3The thickness of the n-type drift region 3 is 5.0 μm to 50 μm. In this embodiment, the n-type resistance modulation region 4 is disposed above the n-type drift region 3, the impurity concentration of the n-type resistance modulation region 4 is distributed in a decreasing manner from the lower surface to the upper surface, and the doping concentration of the contact surface between the n-type resistance modulation region 4 and the n-type drift region 3, i.e., the lower surface of the n-type resistance modulation region 4, is 1 × 10¹⁵cm^-3~5×10¹⁶cm^-3The doping concentration of the upper surface of the n-type resistance modulation region 4 is 1 x 10¹⁴cm^-3~ 5×10¹⁵cm^-3The thickness of the n-type resistance modulation region 4 is 0.5 μm to 5.0 μm. The doping concentration of the p-well region 5 in this embodiment is 5 × 10¹⁶cm^-3~8×10¹⁷cm^-3The junction depth is 0.5-1.0 μm; the doping concentration of the n + source region 6 is 1 × 10¹⁸cm^-3~1×10¹⁹cm^-3The junction depth is 0.2-0.4 μm; the doping concentration of the p + contact region 7 is 1 × 10¹⁸cm^-3~2×10¹⁹cm^-3The junction depth is 0.3 μm to 0.8 μm.

The doping concentration of the p + shielding region 8 in this embodiment is 1 × 10¹⁸cm^-3~2×10¹⁹cm^-3The junction depth is 0.3-0.8 μm, and the horizontal cross-sectional pattern of the p + shielding region 8 is a square, a circle, a regular hexagon, a regular octagon or a strip. The p + shielding regions 8 are uniformly disposed on the upper surface of the n-type resistance modulation region 4 between the p-well regions 5, wherein the number of the first p + shielding regions 81 in each row disposed along the direction perpendicular to the central axis of the device increases from the central axis to the two sides between the adjacent p-well regions 5, and the number ranges from 3 to 20.

In the embodiment, the under-gate dielectric layer 9 is one or a combination of more of SiO2, Al2O3 and HfO2, and the thickness is 100nm to 1000 nm; in the embodiment, the gate oxide layer 10 is SiO2, and the thickness is 10 nm-100 nm; in the embodiment, the thickness of the polysilicon gate 11 is 200nm to 1000nm, the isolation dielectric layer 12 is made of one or a combination of more of SiO2 and Si3N4, and the thickness of the isolation dielectric layer 12 is 500nm to 5 μm; in this embodiment, the source electrode 13 and the drain electrode 14 are made of one or a combination of Ti, W, Ni, Ag, Al, Au, Ta, etc., and have a thickness of 500nm to 5 μm; in this embodiment, the passivation layer 15 is made of polyimide and has a thickness of 1.0 μm to 5 μm.

Example two:

as shown in fig. 5a to 5d, fig. 6a to 6b, and fig. 7, the mesa-gate SiC MOSFET device provided in this embodiment improves the reliability of the gate, and at the same time, enables the SiC MOSFET device to be more easily turned on in a reverse bias state, solves the problem of freewheeling, and improves the performance of the SiC MOSFET device. Specifically, the SiC MOSFET device comprises an n-type substrate 1, an n-type buffer layer 2, an n-type drift region 3, an n-type resistance modulation region 4, a p well region 5, an n + source region 6, a p + contact region 7, a p + shielding region 8, a gate lower dielectric layer 9, a gate oxide layer 10, a polysilicon gate 11, an isolation dielectric layer 12, a source electrode 13, a drain electrode 14 and a passivation layer 15. The p + shielding region 8 has a horizontal cross-sectional pattern, i.e., a top view pattern, which is a square, a circle, a regular hexagon, a regular octagon, or a stripe.

As shown in fig. 8a to 8l, the present embodiment also proposes a method for manufacturing a mesa-gate SiC MOSFET device, including the steps of: selecting a 4H-SiC wafer as the n-type substrate 1, as shown in FIG. 8 a;

sequentially extending an n-type buffer layer 2 and an n-type drift region 3 on the carbon surface of an n-type substrate 1 by a chemical vapor deposition method, as shown in FIG. 8 b;

manufacturing an n-type resistance modulation region 4 on the upper surface of the n-type drift region 3 by an ion implantation method, as shown in fig. 8 c; sequentially manufacturing a p well region 5, an n + source region 6, a p + contact region 7 and a p + shielding region 8 on the upper surface of the n-type resistance modulation region 4 by a method of combining high-temperature ion implantation and high-temperature annealing, as shown in fig. 8 d; manufacturing the under-gate dielectric layer 9 by a high-temperature thermal oxidation method, and patterning the under-gate dielectric layer 9 by a photoetching method, as shown in fig. 8 e; manufacturing a gate oxide layer 10 by a high-temperature oxidation and nitrogen passivation method, as shown in fig. 8 f; manufacturing a polysilicon gate 11 by a chemical vapor deposition method, as shown in fig. 8 g; manufacturing the isolation dielectric layer 12 by a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, as shown in FIG. 8 h;

manufacturing the source electrode 13 by a method of vacuum evaporation combined with rapid thermal annealing, as shown in fig. 8 i;

the thickness of the n-type substrate 1 is reduced by grinding combined with chemical mechanical polishing and plasma etching, and the on-resistance is reduced, as shown in fig. 8 j;

manufacturing the drain electrode 14 by a method of vacuum evaporation combined with laser local thermal annealing, as shown in fig. 8 k;

the passivation layer 15 is made on the upper surface of the device by depositing SiO2 by PECVD and spin-coating polyimide and photolithography, that is, a SiO2 passivation layer is made on the upper surface of the device by PECVD, and then a polyimide passivation layer is made on the upper surface of the SiO2 passivation layer by spin-coating photolithography, as shown in fig. 8 l.

In this embodiment, the n-type substrate 1 is made of 4H-SiC material, and is disposed below the n-type buffer layer 2, and has a thickness of 20 μm to 200 μm. In this embodiment, the n-type buffer layer 2 is disposed between the n-type substrate 1 and the n-type drift region 3, has a thickness of 0.5 μm to 3.0 μm, and has a doping concentration of 1 × 10¹⁷cm^-3~1×10¹⁹cm^-3. In this embodiment, the n-type drift region 3 is disposed above the n-type buffer layer 2, and the doping concentration of the n-type drift region 3 is 1 × 10¹⁴cm^-3~1×10¹⁶cm^-3The thickness of the n-type drift region 3 is 5.0 μm to 150 μm. In this embodiment, the n-type resistance modulation region 4 is disposed above the n-type drift region 3, the impurity concentration of the n-type resistance modulation region 4 is distributed in a decreasing manner from the lower surface to the upper surface, and the doping concentration of the contact surface between the n-type resistance modulation region 4 and the n-type drift region 3, i.e., the lower surface of the n-type resistance modulation region 4, is 1 × 10¹⁵cm^-3~1×10¹⁷cm^-3The doping concentration of the upper surface of the n-type resistance modulation region 4 is 1 x 10¹⁴cm^-3~ 1×10¹⁶cm^-3The thickness of the n-type resistance modulation region 4 is 0.5 μm to 5.0 μm. The doping concentration of the p-well region 5 in this embodiment is 5 × 10¹⁶cm^-3~8×10¹⁷cm^-3The junction depth is 0.5-1.0 μm; the doping concentration of the n + source region 6 is 1 × 10¹⁸cm^-3~1×10¹⁹cm^-3The junction depth is 0.2-0.4 μm; the doping concentration of the p + contact region 7 is 1 × 10¹⁸cm^-3~2×10¹⁹cm^-3The junction depth is 0.3 μm to 1.0 μm.

The doping concentration of the p + shielding region 8 in this embodiment is 1 × 10¹⁸cm^-3~2×10¹⁹cm^-3The junction depth is 0.3 μm to 1.0 μm, and the horizontal cross-sectional pattern of the p + shielding region 8, i.e., the plan view pattern, is a square or a stripe. The p + shielding regions 8 are uniformly arranged on the upper surface of the n-type resistance modulation region 4 between the p-well regions 5, wherein each row of the first p + shielding regions 81 arranged along the central axis direction of the device is adjacent to the adjacent p + shielding regionsThe number between p-well regions 5 is constant at 1; each row of the first p + shielding regions 81 arranged in a direction perpendicular to the central axis of the device has a constant number of 1 between adjacent p-well regions 5, and has a length in a direction perpendicular to the central axis of the device that increases from the central axis to both sides, ranging from 1.0 μm to 20 μm.

In the embodiment, the gate dielectric layer 9 is SiO2, and the thickness is 80nm to 800 nm; in the embodiment, the gate oxide layer 10 is SiO2, and the thickness is 20 nm-80 nm; in the embodiment, the thickness of the polysilicon gate 11 is 300nm to 1000nm, the isolation dielectric layer 12 is made of one or a combination of more of SiO2 and Si3N4, and the thickness of the isolation dielectric layer 12 is 500nm to 5 μm; in this embodiment, the source electrode 13 and the drain electrode 14 are made of one or a combination of Ti, W, Ni, Ag, Al, Au, Ta, etc., and have a thickness of 500nm to 5 μm; in this embodiment, the passivation layer 15 is formed by laminating SiO2 and polyimide, and has a thickness of 1.0 μm to 5 μm.

Example three:

as shown in fig. 9a to 9d, fig. 10a to 10b, and fig. 11, the mesa-gate SiC MOSFET device proposed in this embodiment improves the reliability of the gate, and at the same time, enables the SiC MOSFET device to be more easily turned on in a reverse bias state, solves the problem of freewheeling, and improves the performance of the SiC MOSFET device. Specifically, the SiC MOSFET device comprises an n-type substrate 1, an n-type buffer layer 2, an n-type drift region 3, an n-type resistance modulation region 4, a p well region 5, an n + source region 6, a p + contact region 7, a p + shielding region 8, a gate lower dielectric layer 9, a gate oxide layer 10, a polysilicon gate 11, an isolation dielectric layer 12, a source electrode 13, a drain electrode 14 and a passivation layer 15; the p + shielding region 8 has a horizontal cross-sectional pattern, i.e., a top view pattern, which is a square, a circle, a regular hexagon, a regular octagon, or a stripe.

the upper surface of the n-type resistance modulation region 4 positioned between the p well regions 5 is wrapped with a plurality of p + shielding regions 8, the upper surface of each p + shielding region 8 is flush with the upper surface of the n-type resistance modulation region 4, the lower surface of each p + shielding region 8 is flush with the lower surface of each p + contact region 7, and the cross section of each p + shielding region 8 in the horizontal direction is square or strip-shaped; wherein, the p + shielding region 8 in the opposite region between the edges of the upper surfaces of the adjacent p-well regions 5 arranged along the central axis direction of the device and the p + shielding region 8 in the opposite region between the edges of the upper surfaces of the adjacent p-well regions 5 arranged along the direction perpendicular to the central axis direction of the device are defined as a first p + shielding region 81, and the other p + shielding regions 8 are second p + shielding regions 82; each row of the first p + shielding regions 81 is arranged along the direction vertical to the central axis of the device, and the cross section pattern between the adjacent p well regions 5 is a combination of a strip shape and a square shape, wherein the cross section pattern is that the strip-shaped first p + shielding regions 81 are in a vertical relation with the outer edges of the p well regions 5 in the horizontal direction, and the length of the cross section pattern along the direction vertical to the central axis of the device presents an increasing rule from the central axis to the two side directions; each row of the first p + shielding regions 81 is arranged along the central axis direction of the device, and the cross-sectional pattern is square; the cross-sectional pattern of the second p + shielding region 82 is square.

The upper surfaces of the first p + shielding regions 81 and the n-type resistance modulation region 4 positioned between the first p + shielding regions 81 are covered with a gate lower dielectric layer 9; a gate oxide layer 10 covers the partial outer edge of the upper surface of the exposed n + source region 6 positioned outside the gate lower dielectric layer 9, the upper surface of the exposed p-well region 5, and the upper surface of the exposed n-type resistance modulation region 4 between the p-well region 5 and the p + shielding region 8; the lower surface of the gate lower dielectric layer 9 and the lower surface of the gate oxide layer 10 are both flush with the upper surface of the n-type resistance modulation region 4, the upper surface of the gate lower dielectric layer 9 is higher than the upper surface of the gate oxide layer 10, and the section of the structure formed by the gate oxide layer 10 and the gate lower dielectric layer 9 in the vertical direction is in a boss shape; the upper surface of the gate lower dielectric layer 9 and the upper surface of the gate oxide layer 10 are covered with a polysilicon gate 11, the section of the polysilicon gate 11 in the vertical direction is in a boss shape, namely, the lower surface and the upper surface of the polysilicon gate 11 are partially protruded upwards;

As shown in fig. 12a to 12k, the present embodiment also proposes a method for manufacturing a mesa-gate SiC MOSFET device, including the steps of: a 4H-SiC wafer was selected as the n-type drift region 3, as shown in fig. 12 a;

sequentially extending an n-type buffer layer 2 and an n-type substrate 1 on the silicon surface of the n-type drift region 3 by a chemical vapor deposition method, as shown in FIG. 12 b;

manufacturing an n-type resistance modulation region 4 on the carbon surface of the n-type drift region 3 by an ion implantation method, as shown in fig. 12 c; sequentially manufacturing a p-well region 5 and an n + source region 6 on the upper surface of the n-type resistance modulation region 4 by a method of combining ion implantation and high-temperature annealing, as shown in fig. 12 d; a p + contact region 7 is formed on the upper surface of the p well region 5 and inside the n + source region 6 by a method of ion implantation combined with high temperature annealing, as shown in fig. 12 e; manufacturing a p + shielding region 8 on the upper surface of the n-type resistance modulation region 4 by a method of combining ion implantation and high-temperature annealing, as shown in fig. 12 f;

manufacturing the under-gate dielectric layer 9 by a PECVD method, and patterning the under-gate dielectric layer 9 by a photoetching method, as shown in FIG. 12 g; manufacturing a gate oxide layer 10 by a high-temperature oxidation and nitrogen passivation method, and manufacturing a polysilicon gate 11 by a chemical vapor deposition method, as shown in fig. 12 h; manufacturing an isolation dielectric layer 12 by a PECVD method, as shown in FIG. 12 i;

respectively manufacturing a source electrode 13 and a drain electrode 14 by a vacuum evaporation and rapid thermal annealing method, as shown in fig. 12 j;

and (5) manufacturing a polyimide passivation layer 15 on the upper surface of the device completed in the above operation by a spin coating and photoetching method, and shown in fig. 12 k.

In the embodiment, the n-type substrate 1 is arranged below the n buffer layer 2, and the thickness is 2-20 μm. In the embodiment, the n buffer layer 2 is arranged between the n-type substrate 1 and the n-type drift region 3, has a thickness of 0.5-3.0 μm, and has a doping concentration of 1 × 10¹⁷cm^-3~1×10¹⁹cm^-3. In this embodiment, the n-type drift region 3 is made of 4H-SiC material and is disposed above the n-type buffer layer 2, and the doping concentration of the n-type drift region 3 is 1 × 10¹⁴cm^-3~1×10¹⁵cm^-3The thickness of the n-type drift region 3 is 80 μm to 300 μm. In this embodiment, the n-type resistance modulation region 4 is disposed above the n-type drift region 3, the impurity concentration of the n-type resistance modulation region 4 is distributed in a decreasing manner from the lower surface to the upper surface, and the doping concentration of the contact surface between the n-type resistance modulation region 4 and the n-type drift region 3, i.e., the lower surface of the n-type resistance modulation region 4, is 1 × 10¹⁵cm^-3~1×10¹⁷cm^-3The doping concentration of the upper surface of the n-type resistance modulation region 4 is 1 x 10¹⁴cm^-3~ 1×10¹⁶cm^-3N typeThe thickness of the resistance modulation region 4 is 0.5 μm to 5.0 μm. The doping concentration of the p-well region 5 in this embodiment is 5 × 10¹⁶cm^-3~8×10¹⁷cm^-3The junction depth is 0.5-1.0 μm; the doping concentration of the n + source region 6 is 1 × 10¹⁸cm^-3~1×10¹⁹cm^-3The junction depth is 0.2-0.4 μm; the doping concentration of the p + contact region 7 is 1 × 10¹⁸cm^-3~2×10¹⁹cm^-3The junction depth is 0.3 μm to 1.0 μm.

The doping concentration of the p + shielding region 8 in this embodiment is 1 × 10¹⁸cm^-3~2×10¹⁹cm^-3The junction depth is 0.3 μm to 1.0 μm, and the horizontal cross-sectional pattern of the p + shielding region 8, i.e., the plan view pattern, is a square or a stripe. The p + shielding regions 8 are uniformly arranged on the upper surface of the n-type resistance modulation region 4 between the p well regions 5, wherein the number of the first p + shielding regions 81 in each row arranged along the direction vertical to the central axis of the device is 3 between the adjacent p well regions 5, the cross-sectional pattern is a combination of square, strip and square, namely, two first p + shielding regions 81 with square cross-sectional images sandwich one first p + shielding region 81 with strip cross-sectional images, and the length of the p + shielding regions along the direction vertical to the central axis of the device presents an increasing rule from the central axis to the two sides, and the length range is 1.0 mu m to 20 mu m; each row of first p + shielding regions 81 arranged along the central axis direction of the device, the number of the first p + shielding regions between adjacent p well regions 5 is 3, and the cross-sectional pattern is square; the cross-sectional pattern of the second p + shielding region 82 is square.

In the embodiment, the gate dielectric layer 9 is Al2O3, and the thickness is 200nm to 600 nm; in the embodiment, the gate oxide layer 10 is SiO2, and the thickness is 20 nm-80 nm; in the embodiment, the thickness of the polysilicon gate 11 is 300nm to 1000nm, the isolation dielectric layer 12 is made of one or a combination of more of SiO2 and Si3N4, and the thickness of the isolation dielectric layer 12 is 500nm to 5 μm; in this embodiment, the source electrode 13 and the drain electrode 14 are made of one or a combination of Ti, W, Ni, Ag, Al, Au, Ta, etc., and have a thickness of 500nm to 5 μm; in this embodiment, the passivation layer 15 is made of polyimide and has a thickness of 1.0 μm to 5.0 μm.

In the above three embodiments, by the arrangement of the boss-shaped gate dielectric (including the gate dielectric layer 9 and the gate oxide layer 10), the step-shaped arrangement of the p + contact region 7 and the inner side edge of the p-well region 5, the arrangement of the n-type resistance modulation region 4 with the decreasing distribution rule from the lower surface to the upper surface, the arrangement of the p + shielding region 8 under the gate dielectric, the arrangement of the strip-shaped p + shielding region 8 perpendicular to the edge of the p-well region 5, the arrangement of the n-type resistance modulation region 4 between the p + shielding region 8 and the source electrode 13 with the ohmic contact property, the composite junction shielding source electrode is formed, the gate reliability is improved, the on-resistance of the SiC MOSFET device is reduced, so that the SiC MOSFET device can be conducted more easily in the reverse bias state, the performance of the SiC MOSFET device is improved. Specifically, the method comprises the following steps:

according to the invention, the p + contact region and the inner side edge of the p well region are arranged in a step shape, the impurity concentration of the n-type resistance modulation region is arranged in a descending distribution rule from the lower surface to the upper surface, and the exposed n-type resistance modulation region at the inner side of the p + contact region and the source electrode are arranged in an ohmic contact property, so that the composite junction barrier shielding source electrode is formed, the composite junction barrier shielding source electrode does not pass through current under a forward bias state, and the composite junction barrier source electrode conducts current to the drain electrode through the n-type resistance modulation region or the p + contact region under a reverse bias state, so that the reverse starting voltage of the SiC MOSFET device is reduced, and the reverse surge resistance of the SiC MOSFET device is improved;

the boss-shaped gate dielectric provided by the invention comprises a gate lower dielectric layer and a gate oxide layer, so that the gate-drain capacitance of a SiC MOSFET device is reduced, the boss-shaped gate dielectric on the surface of an n-type resistance modulation region can resist a higher electric field, the allowable distance between p well regions in the SiC MOSFET device can be set to be larger, and a larger design window is provided for a composite junction barrier source electrode: the larger the distance between the p well regions is, the larger the electric field intensity on the lower surface of the boss-shaped gate dielectric is, and the electric field intensity cannot exceed the highest electric field which can be borne by the boss-shaped gate dielectric; in order to improve the reverse conduction performance of the SiC MOSFET device, the p-well region interval needs to be larger; in order to obtain larger p-well region spacing, the boss-shaped gate dielectric is arranged between the p-well regions, so that the electric field intensity born by the gate dielectric is increased, and the p-well region spacing can be further larger;

according to the invention, the p + shielding region is arranged under the boss-shaped gate dielectric, so that the boss-shaped gate dielectric can be shielded outside a high electric field in a blocking state of the SiC MOSFET device; meanwhile, the strip-shaped p + shielding region is perpendicular to the edge of the p-well region, so that the influence of the p + shielding region on the on-resistance of the SiC MOSFET device is reduced; the p + shielding region and the n-type resistance modulation region between the p + shielding regions are in ohmic contact with the source electrode, and another junction barrier source electrode is formed, so that the SiC MOSFET device is easier to conduct in a reverse bias state;

according to the invention, the on-resistance of the SiC MOSFET device is reduced by thinning the n-type 4H-SiC substrate.

To illustrate the performance of the present invention with the mesa-shaped gate dielectric, the SiC MOSFET device of example one was prepared experimentally, and the on-characteristics of the prepared SiC MOSFET device are shown in fig. 13. As can be seen from fig. 13, the reverse turn-on voltage of the mesa-gate SiC MOSFET device of the present invention is 0.35V, which is significantly lower than the reverse turn-on voltage of the conventional SiC MOSFET device of 0.7V to 2.7V, indicating that the present invention has a lower reverse turn-on voltage and is more easily reversely turned on, because the present invention has the beneficial effects of the mesa-shaped gate dielectric, the composite junction barrier shielding structure, the non-uniform doping resistance modulation region, the all-ohm contact source, and the like; it can also be seen from FIG. 13 that when the drain-source voltage V is reversed_DSAfter the reverse on-resistance of the SiC MOSFET device is increased to a certain value (inflection point), the reverse on-resistance of the SiC MOSFET device is further reduced, and the reverse on-surge resistance of the SiC MOSFET device can be obviously enhanced due to the fact that the stepped hollow closed p + contact region and the p well region are arranged on one side of the source electrode.

The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.

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Boss grid SiC MOSFET device and manufacturing method thereof

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