阅读说明：本技术 一种薄膜晶体管、制备方法以及显示面板 (Thin film transistor, preparation method and display panel ) 是由 徐苗 李民 陈禧 李洪濛 庞佳威 周雷 于 2021-09-03 设计创作，主要内容包括：本发明实施例公开了一种薄膜晶体管、制备方法以及显示面板。该薄膜晶体管包括：衬底；叠层设置在衬底表面的有源层、栅极、源极和漏极；有源层包括源区、漏区和沟道区,源区与源极连接,漏区与漏极连接,且源区、沟道区和漏区的导电率相等；源极和漏极,至少有1个在衬底上的投影和栅极在衬底上的投影无交叠；有源层的载流子浓度大于或等于10～(18)/cm～(3),且小于或等于10～(20)/cm～(3)。本发明实施例提供的技术方案,无需对有源层进行高导化处理,简化了薄膜晶体管的制备工艺,降低了薄膜晶体管的制作成本。(The embodiment of the invention discloses a thin film transistor, a preparation method and a display panel. The thin film transistor includes: a substrate; the active layer, the grid electrode, the source electrode and the drain electrode are arranged on the surface of the substrate in a laminated mode; the active layer comprises a source region, a drain region and a channel region, the source region is connected with the source electrode, the drain region is connected with the drain electrode, and the electric conductivities of the source region, the channel region and the drain region are equal; the source and the drain, at least 1 projection on the substrate and projection of grid on the substrate are not overlapped; the carrier concentration of the active layer is greater than or equal to 10 18 /cm 3 And is less than or equal to 10 20 /cm 3 . According to the technical scheme provided by the embodiment of the invention, high conductivity treatment is not required to be carried out on the active layer, the preparation process of the thin film transistor is simplified, and the manufacturing cost of the thin film transistor is reduced.)

1. A thin film transistor, comprising:

a substrate;

the active layer, the grid electrode, the source electrode and the drain electrode are arranged on the surface of the substrate in a laminated mode;

the active layer comprises a source region, a drain region and a channel region, the source region is connected with the source electrode, the drain region is connected with the drain electrode, and the electric conductivities of the source region, the channel region and the drain region are equal;

the source electrode and the drain electrode are provided, and at least 1 projection on the substrate and a projection of the grid electrode on the substrate do not overlap;

the carrier concentration of the active layer is greater than or equal to 10¹⁸/cm³And is less than or equal to 10²⁰/cm³。

2. The thin film transistor of claim 1, wherein the active layer has a carrier mobility of greater than or equal to 20cm²V.s, and less than or equal to 100cm²/(V·s)。

3. The thin film transistor according to claim 1 or 2, wherein the active layer comprises (AO)_x(BO)_y(RO)_zWherein x + y + z is 1; x is more than or equal to 0.5 and less than or equal to 0.8, y is more than or equal to 0 and less than or equal to 0.3, z is more than or equal to 0.00001 and less than or equal to 0.05, A comprises indium and/or tin, B comprises at least one of zinc, gallium, tantalum and bismuth, and RO comprises at least one of praseodymium oxide, terbium oxide, dysprosium oxide and ytterbium oxide.

4. The thin film transistor of claim 1, wherein at least 1 of the source electrode and the drain electrode is formed of the same material as the gate electrode.

5. The thin film transistor according to claim 4, further comprising a gate insulating layer;

the active layer is positioned on the surface of the substrate;

the gate insulating layer is positioned on the surface, far away from the substrate, of the active layer, and is provided with a first via hole and a second via hole which are arranged at intervals;

the grid, the source electrode and the drain electrode are located on the surface, far away from the substrate, of the grid insulating layer, the grid is located between the source electrode and the drain electrode, the source electrode is connected with the source region through a first through hole, and the drain electrode is connected with the drain region through a second through hole.

6. The thin film transistor according to claim 5, further comprising a gate insulating layer;

the grid electrode, the source electrode and the drain electrode are positioned on the surface of the substrate, and the grid electrode is positioned between the source electrode and the drain electrode;

the grid electrode insulating layer is positioned on the surface, far away from the substrate, of the grid electrode and covers the source electrode and the drain electrode, and the grid electrode insulating layer is provided with a first via hole and a second via hole which are arranged at intervals;

the active layer is located on the surface, far away from the substrate, of the gate insulating layer, the source region is connected with the source electrode through the first through hole, and the drain region is connected with the drain electrode through the second through hole.

7. The thin film transistor of claim 5, wherein at least 1 of the source electrode and the drain electrode is spaced from the projection of the substrate by a distance greater than or equal to 0.5um and less than or equal to 10 um.

8. The thin film transistor of claim 5, wherein a projection of the gate on the substrate is spaced from a projection of the drain on the substrate by a distance equal to a projection of the gate on the substrate is spaced from a projection of the source on the substrate.

9. A method for manufacturing a thin film transistor includes:

providing a substrate;

forming an active layer, a grid electrode, a source electrode and a drain electrode which are arranged in a stacked mode on the surface of the substrate;

the active layer comprises a source region, a drain region and a channel region, the source region is connected with the source electrode, the drain region is connected with the drain electrode, and the electrical conductivities of the source region, the channel region and the drain region are equal;

the source electrode and the drain electrode are provided, and at least 1 projection on the substrate and a projection of the grid electrode on the substrate do not overlap;

the carrier concentration of the active layer is greater than or equal to 10¹⁸/cm³And is less than or equal to 10²⁰/cm³。

10. A display panel comprising the thin film transistor according to any one of claims 1 to 8.

Technical Field

The embodiment of the invention relates to the technical field of semiconductors, in particular to a thin film transistor, a preparation method and a display panel.

Background

The thin film transistor is used as a key device of a liquid crystal display and an organic display, and plays an important role in the working performance of a display device.

The conventional thin film transistor includes a substrate, and an active layer, a gate electrode, a source electrode, and a drain electrode stacked on the substrate surface, and it is generally required to perform a conductivity enhancement process on a portion of the active layer connected to the source electrode and a portion of the drain electrode connected to the active layer to increase conductivity of the portion of the active layer connected to the source electrode and the portion of the active layer connected to the drain electrode, so as to increase a response rate of the thin film transistor. However, the process of performing highly conductive processing on the active layer is complicated, which results in an excessively high manufacturing cost of the thin film transistor.

Disclosure of Invention

In view of this, embodiments of the present invention provide a thin film transistor, a manufacturing method thereof, and a display panel, so as to simplify a manufacturing process of the thin film transistor and reduce a manufacturing cost of the thin film transistor.

An embodiment of the present invention provides a thin film transistor, including:

a substrate;

the active layer, the grid electrode, the source electrode and the drain electrode are arranged on the surface of the substrate in a laminated mode;

the active layer comprises a source region, a drain region and a channel region, the source region is connected with the source electrode, the drain region is connected with the drain electrode, and the electric conductivities of the source region, the channel region and the drain region are equal;

the source electrode and the drain electrode are provided, and at least 1 projection on the substrate and a projection of the grid electrode on the substrate do not overlap;

the carrier concentration of the active layer is greater than or equal to 10¹⁸/cm³And is less than or equal to 10²⁰/cm³。

Optionally, the carrier mobility of the active layer is greater than or equal to 20cm²V.s, and less than or equal to 100cm²/(V·s)。

Optionally, the active layer comprises (AO)_x(BO)_y(RO)_zWherein x + y + z is 1; x is more than or equal to 0.5 and less than or equal to 0.8, y is more than or equal to 0 and less than or equal to 0.3, z is more than or equal to 0.00001 and less than or equal to 0.05, A comprises indium and/or tin, B comprises at least one of zinc, gallium, tantalum and bismuth, and RO comprises at least one of praseodymium oxide, terbium oxide, dysprosium oxide and ytterbium oxide.

Optionally, at least 1 of the source electrode and the drain electrode is located in the same layer as the gate electrode, and the materials are the same.

Optionally, the device further comprises a gate insulating layer;

the active layer is positioned on the surface of the substrate;

the gate insulating layer is positioned on the surface, far away from the substrate, of the active layer, and is provided with a first via hole and a second via hole which are arranged at intervals;

the grid, the source electrode and the drain electrode are located on the surface, far away from the substrate, of the grid insulating layer, the grid is located between the source electrode and the drain electrode, the source electrode is connected with the source region through a first through hole, and the drain electrode is connected with the drain region through a second through hole.

Optionally, the device further comprises a gate insulating layer;

the grid electrode, the source electrode and the drain electrode are positioned on the surface of the substrate, and the grid electrode is positioned between the source electrode and the drain electrode;

the grid electrode insulating layer is positioned on the surface, far away from the substrate, of the grid electrode and covers the source electrode and the drain electrode, and the grid electrode insulating layer is provided with a first via hole and a second via hole which are arranged at intervals;

the active layer is located on the surface, far away from the substrate, of the gate insulating layer, the source region is connected with the source electrode through the first through hole, and the drain region is connected with the drain electrode through the second through hole.

Optionally, the source electrode and the drain electrode have at least 1 projection on the substrate and a distance between projections on the substrate and the gate electrode, which is greater than or equal to 0.5um and less than or equal to 10 um.

Optionally, a distance between a projection of the gate on the substrate and a projection of the drain on the substrate is equal to a distance between a projection of the gate on the substrate and a projection of the source on the substrate.

The embodiment of the invention also provides a preparation method of the thin film transistor, which comprises the following steps:

providing a substrate;

forming an active layer, a grid electrode, a source electrode and a drain electrode which are arranged in a stacked mode on the surface of the substrate;

the active layer comprises a source region, a drain region and a channel region, the source region is connected with the source electrode, the drain region is connected with the drain electrode, and the electrical conductivities of the source region, the channel region and the drain region are equal;

the source electrode and the drain electrode are provided, and at least 1 projection on the substrate and a projection of the grid electrode on the substrate do not overlap;

the carrier concentration of the active layer is greater than or equal to 10¹⁸/cm³And is less than or equal to 10²⁰/cm³。

The embodiment of the invention also provides a display panel which comprises the thin film transistor in any technical scheme.

According to the technical scheme provided by the embodiment of the invention, when at least 1 projection of the source electrode and the drain electrode on the substrate and the projection of the grid electrode on the substrate are not overlapped, although the effect of an electric field is small in a region where the projection of the grid electrode on the substrate and the projection of the drain electrode on the substrate are overlapped with the projection of the active layer on the substrate under the electrification of the thin film transistor, the carrier concentration of the active layer is greater than or equal to 1018/cm3 and less than or equal to 1020/cm3 which are far greater than the carrier concentration in the active layer adopted in the prior art, the carriers can be supported to move at a high speed, and the thin film transistor is ensured to have a high response speed. Therefore, high conductivity processing is not needed to be carried out on the source region and the drain region of the active layer, the preparation process of the thin film transistor is simplified, and the manufacturing cost of the thin film transistor is further reduced.

Drawings

FIG. 1 is a schematic diagram of a TFT in the prior art;

fig. 2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention;

fig. 6 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present invention;

FIG. 7 is a schematic flow chart of the process involved in step 120 of FIG. 6;

FIG. 8 is another schematic flow chart included in step 120 of FIG. 6;

fig. 9-13 are cross-sectional views corresponding to steps of a method for fabricating a thin film transistor according to an embodiment of the present invention;

fig. 14 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention;

fig. 15 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As described in the background art, the conventional thin film transistor has a complicated manufacturing process, which results in a high manufacturing cost of the thin film transistor. Fig. 1 is a schematic structural diagram of a thin film transistor in the prior art. Referring to fig. 1, the inventors have found through careful study that the thin film transistor includes a substrate 10, a gate electrode 20, an active layer 30, a source electrode 40, a drain electrode 50, and a gate insulating layer 60, and the active layer 30 includes a channel region 31, a source region 32, and a drain region 33. Since the carrier concentration of the active layer 30 is not so high, in order to improve the response speed of the thin film transistor, the source region 32 and the drain region 33 of the active layer 30 need to be highly conductive, so that the conductivity of the source region 32 is greater than that of the channel region 31, and the conductivity of the drain region 33 is greater than that of the channel region 31. Specifically, the process of performing the high conductivity treatment on the source region 32 and the drain region 33 in the active layer 30 is as follows: a mask covering the channel region 31, the source region 32 and the drain region 33 needs to be formed on the surface of the active layer 30 away from the substrate 10 before the source electrode 40 and the drain electrode 50 are prepared; then, ion doping is carried out on the source region 32 and the drain region 33 by adopting an ion implantation process, so that the conductivity of the source region 32 is greater than that of the channel region 31, and the conductivity of the drain region 33 is greater than that of the channel region 31; finally, the mask on the surface of the active layer 30 needs to be removed. As described above, in the thin film transistor of the related art, the process of performing the high conductivity treatment on the source region 32 and the drain region 33 in the active layer 30 is complicated, and the manufacturing cost of the thin film transistor is excessively high.

In view of the above technical problems, an embodiment of the present invention provides the following technical solutions:

fig. 2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention. Fig. 3 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention. Referring to fig. 2 and 3, the thin film transistor includes: a substrate 10; an active layer 30, a gate 20, a source 40 and a drain 50 stacked on the surface of the substrate 10; the active layer 30 comprises a source region 32, a drain region 33 and a channel region 31, the source region 32 is connected with the source electrode 40, the drain region 33 is connected with the drain electrode 50, and the electrical conductivities of the source region 32, the channel region 31 and the drain region 33 are equal; a source electrode 40 and a drain electrode 50, at least 1 projection of which on the substrate 10 is not overlapped with the projection of the gate electrode 20 on the substrate 10; the carrier concentration of the active layer 30 is 10 or more¹⁸/cm³And is less than or equal to 10²⁰/cm³。

Exemplarily, fig. 2 and 3 show that the projection of the gate 20 on the substrate 10 has no overlap with the projection of the drain 50 on the substrate 10; and the projection of the gate 20 on the substrate 10 is not overlapped with the projection of the source 40 on the substrate 10. The embodiment of the invention also comprises that the projection of the grid 20 on the substrate 10 is not overlapped with the projection of the drain 50 on the substrate 10; or, the projection of the gate 20 on the substrate 10 and the projection of the source 40 on the substrate 10 are not overlapped.

It is to be noted that the carrier concentration of the active layer 30 is 10 or more¹⁸/cm3, and less than or equal to 10²⁰The concentration of/cm 3 is far greater than that of carriers in an active layer adopted in the prior art, and the carriers can be supported to move at a higher speed, so that the thin film transistor is ensured to have a high response speed.

Specifically, the active layer 30 includes a source region 32, a drain region 33, and a channel region 31, and the source region 32, the channel region 31, and the drain region 33 have equal conductivities, that is, the high conductivity treatment for the source region 32 and the drain region 33 is not required.

When the projection of at least 1 of the source electrode 40 and the drain electrode 50 on the substrate 10 is not overlapped with the projection of the gate electrode 20 on the substrate 10, under the condition that the thin film transistor is electrified, the influence of an electric field on a part, where the projection of the gate electrode 20 on the substrate 10 is separated from the projection of the drain electrode 50 on the substrate 10 and the projection of the active layer 30 on the substrate 10 are less, is less if the carrier concentration of the active layer 30 is less than 10¹⁸/cm³The region where the projection of the gate 20 on the substrate 10 is spaced from the projection of the drain 50 on the substrate 10 and the portion where the projection of the active layer 30 on the substrate 10 overlaps each other do not support the fast migration of carriers because the carrier concentration is not high, and even the carriers cannot migrate between the source region 32 and the drain region 33, so that the response speed of the thin film transistor is relatively slow and the usage requirement cannot be met.

According to the technical scheme provided by the embodiment of the invention, when at least 1 projection of the source electrode 40 and the drain electrode 50 on the substrate 10 is not overlapped with the projection of the grid electrode 20 on the substrate 10, although the projection of the grid electrode 20 on the substrate 10 and the projection of the drain electrode 50 on the substrate 10 are less influenced by an electric field in a region where the projection of the grid electrode 20 and the projection of the active layer 30 on the substrate 10 are overlapped under the condition that the thin film transistor is electrified, the carrier concentration of the active layer 30 is more than or equal to 10¹⁸/cm³And is less than or equal to 10²⁰/cm³Is far greater than the carrier concentration in the active layer adopted in the prior art, and can support the carriers to be fasterThe speed of the thin film transistor is shifted, and therefore the thin film transistor is guaranteed to have a fast response speed. Therefore, high conductivity processing of the source region 32 and the drain region 33 of the active layer 30 is not required, the manufacturing process of the thin film transistor is simplified, and the manufacturing cost of the thin film transistor is reduced.

It should be noted that when at least 1 projection of the source electrode 40 and the drain electrode 50 on the substrate 10 overlaps with a projection of the gate electrode 20 on the substrate 10, the active layer 30 provided by the embodiment of the present invention may also be used to further increase the response speed of the thin film transistor.

Alternatively, referring to fig. 2 and 3, the carrier mobility of the active layer 30 is greater than or equal to 20cm²V.s, and less than or equal to 100cm²/(V·s)。

Specifically, the carrier concentration of the active layer 30 is 10 or more¹⁸/cm³And is less than or equal to 10²⁰/cm³The carrier concentration in the active layer is far greater than that in the prior art, and the carrier can be supported to move at a higher speed, so that the thin film transistor is ensured to have a high response speed. In the embodiment of the present invention, the carrier mobility of the active layer 30 is limited to 20cm or more²V.s, and less than or equal to 100cm²In the range of V · s, it is further ensured that the carriers are supported to move at a high speed without performing the high conductivity treatment process on the active layer 30, and the thin film transistor is ensured to have a high response speed.

Alternatively, referring to fig. 2 and 3, the active layer 30 includes (AO)_x(BO)_y(RO)_zWherein x + y + z is 1; x is more than or equal to 0.5 and less than or equal to 0.8, y is more than or equal to 0 and less than or equal to 0.3, z is more than or equal to 0.00001 and less than or equal to 0.05, A comprises indium and/or tin, B comprises at least one of zinc, gallium, tantalum and bismuth, and RO comprises at least one of praseodymium oxide, terbium oxide, dysprosium oxide and ytterbium oxide.

Specifically, the thin film transistor formed by the metal oxide semiconductor active layer formed by at least one of indium and/or tin, zinc, gallium, tantalum and bismuth and the metal oxide semiconductor active layer has excellent piezoelectric, photoelectric, gas-sensitive and pressure-sensitive performances and the like, and has wide development prospects in the field of semiconductors. The active layer composed of the metal oxide semiconductor and the oxide (at least one of praseodymium oxide, terbium oxide, dysprosium oxide and ytterbium oxide) composed of rare earth elements can greatly improve the carrier concentration and carrier migration efficiency of the active layer 30, so that in the thin film transistor, the projection of the gate electrode 20 on the substrate 10 and the projection of the drain electrode 50 on the substrate 10 do not overlap; and/or when the projection of the gate 20 on the substrate 10 does not overlap with the projection of the source 40 on the substrate 10, although the projection of the gate 20 on the substrate 10 and the projection of the drain 50 on the substrate 10 are less affected by the electric field when the thin film transistor is powered on, and the overlapped part of the projection of the active layer 30 on the substrate 10 is less affected by the electric field, the carrier concentration of the active layer 30 is sufficient to support the carriers to migrate at a faster speed, thereby ensuring that the thin film transistor has a fast response speed. Therefore, high conductivity processing of the source region 32 and the drain region 33 of the active layer 30 is not required, the manufacturing process of the thin film transistor is simplified, and the manufacturing cost of the thin film transistor is reduced. It should be noted that the active layer 30 according to the embodiment of the present invention may further include another rare earth oxide other than at least one of praseodymium oxide, terbium oxide, dysprosium oxide, and ytterbium oxide.

Alternatively, referring to fig. 2 and 3, at least 1 of the source electrode 40 and the drain electrode 50 is located at the same layer as the gate electrode 20 and is made of the same material.

Exemplarily, fig. 2 and 3 show that the gate 20 and the source 40 are located at the same layer and have the same material, and the gate 20 and the drain 50 are located at the same layer and have the same material. The embodiment of the invention also comprises that the grid electrode 20 and the source electrode 40 are positioned on the same layer and are made of the same material; or, the gate 20 and the drain 50 are located in the same layer and have the same material.

Specifically, the gate 20 and the source 40 are located in the same layer and made of the same material, and when the gate 20 and the source 40 are formed, a metal film layer where the gate 20 and the source 40 are located can be patterned by using a mask to obtain the gate 20 and the source 40 which are arranged at intervals.

The gate 20 and the drain 50 are located in the same layer and are made of the same material, and when the gate 20 and the drain 50 are formed, a metal film layer where the gate 20 and the drain 50 are located can be patterned by using a mask to obtain the gate 20 and the drain 50 which are arranged at intervals.

The gate 20, the source 40 and the drain 50 are located in the same layer, and the materials are the same, when the gate 20, the source 40 and the drain 50 are formed, a mask can be used for patterning a metal film layer where the gate 20, the source 40 and the drain 50 are located to obtain the gate 20, the source 40 and the drain 50 which are arranged at intervals, compared with the technical scheme that the gate 20, the source 40 and the drain 50 are not manufactured in the same layer, the technical scheme provided by the embodiment of the invention further reduces the use times of the mask, further simplifies the manufacturing process of the thin film transistor, and further reduces the manufacturing cost of the thin film transistor.

Fig. 4 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention. Referring to fig. 4, the gate electrode 20, the source electrode 40, and the drain electrode 50 are located at the same layer and have the same material, and the thin film transistor further includes a gate insulating layer 60; the active layer 30 is located on the surface of the substrate 10; the gate insulating layer 60 is positioned on the surface of the active layer 30 away from the substrate 10, wherein the gate insulating layer 60 is provided with a first via 61 and a second via 62 which are arranged at intervals; the gate 20, the source 40 and the drain 50 are located on a surface of the gate insulating layer 60 away from the substrate 10, the gate 20 is located between the source 40 and the drain 50, the source 40 is connected to the source region 32 through a first via 61, and the drain 50 is connected to the drain region 33 through a second via 62.

Specifically, the gate 20, the source 40 and the drain 50 are in the same layer and located on a surface of the gate insulating layer 60 away from the substrate 10, the gate insulating layer 60 is used for insulating the active layer 30 and the gate 20, the source 40 is connected to the source region 32 through the first via 61, and the drain 50 is connected to the drain region 33 through the second via 62, so that carriers can migrate between the source region 32 and the drain region 33 in a power-on state of the thin film transistor, so that the thin film transistor can operate quickly and normally.

Fig. 5 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention. Referring to fig. 5, the gate electrode 20, the source electrode 40, and the drain electrode 50 are located at the same layer and have the same material, and the thin film transistor further includes a gate insulating layer 60; the gate 20, the source 40 and the drain 50 are positioned on the surface of the substrate 10, and the gate 20 is positioned between the source 40 and the drain 50; the gate insulating layer 60 is positioned on the surface of the gate 20 away from the substrate 10 and covers the source electrode 40 and the drain electrode 50, wherein the gate insulating layer 60 is provided with a first via 61 and a second via 62 which are arranged at intervals; the active layer 30 is located on the surface of the gate insulating layer 60 away from the substrate 10, the source region 32 is connected to the source electrode 40 through a first via 61, and the drain region 33 is connected to the drain electrode 50 through a second via 62.

Specifically, the gate 20, the source 40 and the drain 50 are in the same layer and located on the surface of the substrate 10, the gate insulating layer 60 is used for insulating the active layer 30 and the gate 20, the source region 32 is connected to the source 40 through the first via 61, the drain region 33 is connected to the drain 50 through the second via 62, and in a power-on state of the thin film transistor, carriers can migrate between the source region 32 and the drain region 33, so that the thin film transistor can operate quickly and normally.

Optionally, referring to fig. 4 and 5, the source 40 and the drain 50 have at least 1 projection on the substrate 10 and at least 10um, and the distance between the projection on the substrate of the gate 20 and the projection on the substrate is greater than or equal to 0.5 um.

Specifically, the gate 20, the source 40 and the drain 50 are located in the same layer, and the materials are the same, or the gate 20 and the drain 50 are located in the same layer, and the materials are the same, and the projection of the gate 20 on the substrate 10 and the projection of the drain 50 on the substrate 10 are not overlapped, and the spaced distance L1 is less than 0.5um, so that the accuracy of the mask patterns of the corresponding masks of the gate 20 and the drain 50 formed by the photolithography, development and exposure processes is not easily ensured. The projection of the gate electrode 20 on the substrate 10 and the projection of the drain electrode 50 on the substrate 10 are separated by a distance L1 larger than 10um without overlapping, which results in a lateral dimension of the thin film transistor that is too large to facilitate the formation of a miniaturized thin film transistor. Therefore, the distance L1 between the projection of the gate 20 on the substrate 10 and the projection of the drain 50 on the substrate 10 is greater than or equal to 0.5um and less than or equal to 10um, which can improve the accuracy of the mask pattern of the mask corresponding to the gate 20 and the drain 50 formed by the photolithography, development and exposure processes, and ensure the miniaturization of the thin film transistor.

Specifically, the gate 20, the source 40 and the drain 50 are located in the same layer and have the same material, or the gate 20 and the source 40 are located in the same layer and have the same material, and the projection of the gate 20 on the substrate 10 and the projection of the source 40 on the substrate 10 are separated by a distance L2 smaller than 0.5um without overlapping, so that the accuracy of forming the mask patterns of the corresponding masks of the gate 20 and the source 40 through the photolithography, development and exposure processes is not easily ensured. The projection of the gate electrode 20 on the substrate 10 is separated from the projection of the source electrode 40 on the substrate 10 by a distance L2 greater than 10um without overlapping, resulting in a lateral dimension of the tft that is too large to facilitate the formation of a miniaturized tft. Therefore, the distance L2 between the projection of the gate 20 on the substrate 10 and the projection of the source 40 on the substrate 10 is greater than or equal to 0.5um and less than or equal to 10um, so that on one hand, the accuracy of forming the mask patterns of the corresponding masks of the gate 20 and the source 40 through the photolithography, development and exposure processes can be improved, and on the other hand, the miniaturization of the thin film transistor can be ensured.

Alternatively, referring to fig. 2-5, the projection of the gate 20 on the substrate 10 is spaced apart from the projection of the drain 50 on the substrate 10 by a distance L1 equal to the projection of the gate 20 on the substrate 10 is spaced apart from the projection of the source 40 on the substrate 10 by a distance L2.

Specifically, the distance L1 between the projection of the gate 20 on the substrate 10 and the projection of the drain 50 on the substrate 10 is equal to the distance L2 between the projection of the gate 20 on the substrate 10 and the projection of the source 40 on the substrate 10, which simplifies the layout complexity of the gate 20, the source 40 and the drain 50.

Fig. 14 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention. Fig. 15 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention. Referring to fig. 14 and 15, the thin film transistor further includes a first passivation layer 70, a second passivation layer 71, a pixel defining layer 80, and a pixel electrode 90. The pixel defining layer 80 serves to define a light emitting unit of the display panel.

Illustratively, the first passivation layer 70 may be an inorganic layer, such as SiO with a thickness of 2000 nm₂. The second passivation layer 71 may be an organic layer having a thickness of 1.2 micrometers. The pixel electrode 90 may be a conductive glass (ITO), or a metal film layer such as metallic nickel and metallic copper. The pixel defining layer 80 may be an organic layer having a thickness of 1-3 microns.

The embodiment of the invention also provides a flow chart of a preparation method of the thin film transistor. Fig. 6 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present invention. Fig. 9-fig. 13 are cross-sectional views corresponding to steps of a method for manufacturing a thin film transistor according to an embodiment of the invention. Referring to fig. 6, the method for manufacturing the thin film transistor includes the steps of:

step 110, providing a substrate.

Referring to fig. 9, a substrate 10 is provided. The substrate 10 is used for support.

And 120, forming an active layer, a grid electrode, a source electrode and a drain electrode which are arranged in a stacked mode on the surface of the substrate.

The active layer comprises a source region, a drain region and a channel region, the source region is connected with the source electrode, the drain region is connected with the drain electrode, and the electric conductivities of the source region, the channel region and the drain region are equal.

And at least 1 projection of the source electrode and the drain electrode on the substrate is not overlapped with the projection of the grid electrode on the substrate.

The carrier concentration of the active layer is greater than or equal to 10¹⁸/cm³And is less than or equal to 10²⁰/cm³。

Referring to fig. 2 and 3, an active layer 30, a gate electrode 20, a source electrode 40, and a drain electrode 50 are formed on a surface of a substrate 10 in a stacked manner. The active layer 30 comprises a source region 32, a drain region 33 and a channel region 31, the source region 32 is connected with the source electrode 40, the drain region 33 is connected with the drain electrode 50, and the electrical conductivities of the source region 32, the channel region 31 and the drain region 33 are equal; a source electrode 40 and a drain electrode 50, at least 1 projection of which on the substrate 10 is not overlapped with the projection of the gate electrode 20 on the substrate 10; the carrier concentration of the active layer 30 is 10 or more¹⁸/cm³And is less than or equal to 10²⁰/cm³。

Illustratively, the gate electrode 20 is a Mo electrode, an Al/Mo stacked electrode or a Mo/Cu stacked electrode, wherein the thickness of the Mo electrode is 2000 nm; in the Al/Mo laminated electrode, the thickness of Al is 3000 nanometers, and the thickness of Mo is 300 nanometers; in the Mo/Cu laminated electrode, the thickness of Mo is 200 nm, and the thickness of Cu is 5000 nm. The thickness of the active layer 30 is 3000 nm.

According to the technical scheme provided by the embodiment of the invention, the projection of the grid 20 on the substrate 10 is not overlapped with the projection of the drain 50 on the substrate 10; and/or when the projection of the gate 20 on the substrate 10 is not overlapped with the projection of the source 40 on the substrate 10, although the projection of the gate 20 on the substrate 10 and the projection of the drain 50 on the substrate 10 are separated from each other and the projection of the active layer 30 on the substrate 10 is less influenced by the electric field under the power-on of the thin film transistor, the carrier concentration of the active layer 30 is greater than or equal to 10¹⁸/cm³And is less than or equal to 10²⁰/cm³The carrier concentration in the active layer is far greater than that in the prior art, and the carrier can be supported to move at a higher speed, so that the thin film transistor is ensured to have a high response speed. Therefore, high conductivity processing of the source region 32 and the drain region 33 of the active layer 30 is not required, the manufacturing process of the thin film transistor is simplified, and the manufacturing cost of the thin film transistor is reduced.

Fig. 7 is a schematic flow chart of the process included in step 120 in fig. 6. Alternatively, referring to fig. 7, the step 120 of forming an active layer, a gate electrode, a source electrode and a drain electrode stacked on the surface of the substrate includes:

step 1201, forming an active layer on the surface of the substrate.

Referring to fig. 10, an active layer 30 is formed on a surface of a substrate 10.

Step 1202, forming a gate insulating layer on the surface of the active layer far away from the substrate, wherein the gate insulating layer comprises a first via hole and a second via hole which are arranged at intervals.

Referring to fig. 11, a gate insulating layer 60 is formed on a surface of the active layer 30 away from the substrate 10, wherein the gate insulating layer 60 includes a first via 61 and a second via 62 which are spaced apart from each other.

And 1203, forming a gate, a source and a drain on the surface of the gate insulating layer far away from the substrate, wherein the gate is located between the source and the drain, the source is connected with the source region through a first via hole, and the drain is connected with the drain region through a second via hole.

Referring to fig. 4, a gate 20, a source 40 and a drain 50 are formed on a surface of the gate insulating layer 60 away from the substrate 10, wherein the gate 20 is located between the source 40 and the drain 50, the source 40 is connected to the source region 32 through a first via 61, and the drain 50 is connected to the drain region 33 through a second via 62.

Fig. 8 is another schematic flow chart included in step 120 in fig. 6. Alternatively, referring to fig. 8, step 120 of forming an active layer, a gate electrode, a source electrode and a drain electrode stacked on the surface of the substrate includes:

and 1204, forming a gate, a source and a drain on the surface of the substrate, wherein the gate is positioned between the source and the drain.

Referring to fig. 12, a gate 20, a source 40, and a drain 50 are formed on a surface of a substrate 10, wherein the gate 20 is positioned between the source 40 and the drain 50.

And 1205, forming a gate insulating layer on the surface of the gate, which is far away from the substrate, wherein the gate insulating layer covers the source electrode and the drain electrode, and the gate insulating layer is provided with a first via hole and a second via hole which are arranged at intervals.

Referring to fig. 13, a gate insulating layer 60 is formed on a surface of the gate 20 away from the substrate 10, wherein the gate insulating layer 60 covers the source electrode 40 and the drain electrode 50, and the gate insulating layer 60 is provided with a first via 61 and a second via 62 which are arranged at intervals.

And 1206, forming an active layer on the surface of the gate insulating layer far away from the substrate, wherein the source region is connected with the source electrode through the first through hole, and the drain region is connected with the drain electrode through the second through hole.

Referring to fig. 5, an active layer 30 is formed on a surface of the gate insulating layer 60 away from the substrate 10, wherein the source region 32 is connected to the source electrode through a first via 61, and the drain region 33 is connected to the drain electrode 50 through a second via 62.

In summary, in the process of forming the active layer 30 in step 1201 and step 1206, no active layer is formedThe layer 30 is subjected to a high conductivity treatment because the carrier concentration of the active layer 30 is 10 or more¹⁸/cm³And is less than or equal to 10²⁰/cm³The carrier concentration in the active layer is far greater than that in the prior art, and the carrier can be supported to move at a higher speed, so that the thin film transistor is ensured to have a high response speed. Therefore, high conductivity processing of the source region 32 and the drain region 33 of the active layer 30 is not required, the manufacturing process of the thin film transistor is simplified, and the manufacturing cost of the thin film transistor is reduced.

Illustratively, the gate insulator layer 60 is selected from SiN_xLaminated film of/SiO or SiO₂Film of SiN_xIs 3000 nm, the thickness of SiO is 1000 nm, SiO₂Has a thickness of 1000 nm.

Alternatively, referring to fig. 2 and 3, the carrier mobility of the active layer 30 is greater than or equal to 20cm²V.s, and less than or equal to 100cm²/(V·s)。

Specifically, the carrier concentration of the active layer 30 is 10 or more¹⁸/cm³And is less than or equal to 10²⁰/cm³The carrier concentration in the active layer is far greater than that in the prior art, and the carrier can be supported to move at a higher speed, so that the thin film transistor is ensured to have a high response speed. In the embodiment of the present invention, the carrier mobility of the active layer 30 is limited to 20cm or more²V.s, and less than or equal to 100cm²In the range of V · s, it is further ensured that the carriers are supported to move at a high speed without performing the high conductivity treatment process on the active layer 30, and the thin film transistor is ensured to have a high response speed.

Alternatively, referring to FIGS. 2 and 3, the active layer includes (AO)_x(BO)_y(RO)_zWherein x + y + z is 1; x is more than or equal to 0.5 and less than or equal to 0.8, y is more than or equal to 0 and less than or equal to 0.3, z is more than or equal to 0.00001 and less than or equal to 0.05, A comprises indium and/or tin, B comprises at least one of zinc, gallium, tantalum and bismuth, and RO comprises at least one of praseodymium oxide, terbium oxide, dysprosium oxide and ytterbium oxide.

Specifically, the thin film transistor formed by the metal oxide semiconductor active layer formed by at least one of indium and/or tin, zinc, gallium, tantalum and bismuth and the metal oxide semiconductor active layer has excellent piezoelectric, photoelectric, gas-sensitive and pressure-sensitive performances and the like, and has wide development prospects in the field of semiconductors. The active layer composed of the metal oxide semiconductor and the oxide (at least one of praseodymium oxide, terbium oxide, dysprosium oxide and ytterbium oxide) composed of rare earth elements can greatly improve the carrier concentration and carrier migration efficiency of the active layer 30, so that in the thin film transistor, the projection of the gate electrode 20 on the substrate 10 and the projection of the drain electrode 50 on the substrate 10 do not overlap; and/or when the projection of the gate 20 on the substrate 10 does not overlap with the projection of the source 40 on the substrate 10, although the projection of the gate 20 on the substrate 10 and the projection of the drain 50 on the substrate 10 are less affected by the electric field when the thin film transistor is powered on, and the overlapped part of the projection of the active layer 30 on the substrate 10 is less affected by the electric field, the carrier concentration of the active layer 30 is sufficient to support the carriers to migrate at a faster speed, thereby ensuring that the thin film transistor has a fast response speed. Therefore, high conductivity processing of the source region 32 and the drain region 33 of the active layer 30 is not required, the manufacturing process of the thin film transistor is simplified, and the manufacturing cost of the thin film transistor is reduced. It should be noted that the active layer 30 according to the embodiment of the present invention may further include another rare earth oxide other than at least one of praseodymium oxide, terbium oxide, dysprosium oxide, and ytterbium oxide.

The embodiment of the invention also provides a display panel. The display panel includes the thin film transistor described in any of the above technical aspects.

The display panel provided by the embodiment of the invention can be applied to display equipment with a display function, such as mobile phones, computers, intelligent wearable equipment and the like, and the embodiment of the invention is not limited to the display equipment.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.