阅读说明：本技术 一种低功耗的振荡器电路 (Low-power-consumption oscillator circuit ) 是由 钱春 于 2021-09-08 设计创作，主要内容包括：本发明公开一种低功耗的振荡器电路,包括：振荡器,振荡器用于生成输出时钟信号；鉴频器,鉴频器接收使能信号、基准时钟信号以及输出时钟信号,并生成比较信号；电荷泵,电荷泵的输入端连接鉴频器的输出端,并输出控制电压；保电模块,保电模块的输入端连接电荷泵的输出端,保电模块还用于将控制电压存储在一保电电容中。本发明的有益效果在于：通过设置保电模块实现了在鉴频器和电荷泵停止工作的状态下仍能够驱动振荡器产生输出时钟信号,实现了电源的间断运行,进而使得振荡器整体功耗降低。通过对保电模块的电路设计使得保电电容漏电电流减小,更易于产生高精度的输出时钟信号。(The invention discloses an oscillator circuit with low power consumption, which comprises: an oscillator for generating an output clock signal; a frequency discriminator which receives the enable signal, the reference clock signal and the output clock signal and generates a comparison signal; the input end of the charge pump is connected with the output end of the frequency discriminator and outputs control voltage; and the input end of the power protection module is connected with the output end of the charge pump, and the power protection module is also used for storing the control voltage in a power protection capacitor. The invention has the beneficial effects that: the power-preserving module is arranged to drive the oscillator to generate an output clock signal under the condition that the frequency discriminator and the charge pump stop working, so that the discontinuous operation of a power supply is realized, and the overall power consumption of the oscillator is reduced. Through the circuit design of the power-keeping module, the leakage current of the power-keeping capacitor is reduced, and the high-precision output clock signal is easier to generate.)

1. An oscillator circuit with low power consumption, comprising:

an oscillator for generating an output clock signal;

a frequency discriminator receiving an enable signal and a reference clock signal input from the outside, and receiving an output clock signal output from an output terminal of the oscillator, and generating a comparison signal according to the output clock signal and the reference clock signal;

the input end of the charge pump is connected with the output end of the frequency discriminator and is used for outputting control voltage according to the comparison signal and the enabling signal;

the input end of the power protection module is connected with the output end of the charge pump and used for outputting the control voltage to the input end of the oscillator;

the oscillator generates the output clock signal under the driving of the control voltage;

the power protection module is further used for storing the control voltage in a power protection capacitor, and the control voltage is formed through the power protection capacitor under the control of the enabling signal, so that low-power-consumption operation is realized.

2. The oscillator circuit of claim 1, wherein the power conservation module comprises:

a first field effect transistor, wherein a grid electrode of the first field effect transistor receives the enabling signal;

the source electrode of the first field effect transistor is connected with the output end of the charge pump;

the drain electrode of the first field effect tube is connected with the negative input end of the amplifier and the output end of the amplifier;

the positive input end of the amplifier is connected to the output end of the power protection module;

a second field effect transistor, wherein a grid electrode of the second field effect transistor receives the enabling signal through a NOT gate;

the source electrode of the second field effect transistor is connected with the output end of the power protection module;

the drain electrode of the second field effect transistor is connected with the output end of the charge pump;

and the base electrode of the second field effect transistor is connected with the negative input end of the amplifier.

3. The oscillator circuit of claim 2, wherein the amplifier comprises:

a first amplifying field effect transistor, wherein the grid electrode of the first amplifying field effect transistor is connected to the positive input end of the amplifier;

the source electrode of the first amplifying field effect transistor is grounded;

the drain electrode of the first amplifying field effect transistor is connected to the drain electrode and the grid electrode of the second amplifying field effect transistor;

the source electrode of the second amplifying field effect transistor is connected to the source electrode of the third amplifying field effect transistor;

the grid electrode of the third amplifying field effect transistor is connected to the grid electrode of the second amplifying field effect transistor;

the drain electrode of the third amplifying field effect transistor is connected to the drain electrode of the fourth amplifying field effect transistor and the output end of the amplifier;

the grid electrode of the fourth amplifying field effect transistor is connected to the negative input end of the amplifier;

and the source electrode of the fourth amplifying field effect transistor is connected to the source electrode of the first amplifying field effect transistor.

4. The oscillator circuit according to claim 1, wherein one end of the charge holding capacitor is connected to the output end of the charge holding module, and the other end of the charge holding capacitor is grounded.

5. The oscillator circuit of claim 1, wherein the charge pump adjusts the magnitude of the control voltage according to the comparison signal;

the comparison signal is a voltage rising signal and is used for controlling the charge pump to rise the control voltage;

or, a voltage drop signal for controlling the charge pump to drop the control voltage.

6. The oscillator circuit of claim 1, wherein the oscillator is a voltage controlled oscillator configured to adjust the frequency of the output clock signal according to the magnitude of the control voltage.

7. The oscillator circuit according to claim 1, wherein when the enable signal is low, the frequency discriminator stops operating, and the power-maintaining module outputs the control voltage.

8. The oscillator circuit according to claim 2, wherein the first fet, the second amplifier fet, and the third amplifier fet are N-channel fets;

the first amplifying field effect transistor and the fourth amplifying field effect transistor are P-channel type field effect transistors.

Technical Field

The invention relates to the technical field of oscillating circuits, in particular to an oscillator circuit with low power consumption.

Background

Oscillators are electronic components that generate repetitive electrical signals (usually sinusoidal or square waves). The circuit formed by the circuit is called an oscillating circuit. An electronic circuit or device capable of converting direct current into alternating current signals with certain frequency and outputting the alternating current signals. The device has a plurality of types, and can be divided into a self-excited oscillator and an independent-excited oscillator according to an oscillation excitation mode; the circuit can be divided into a resistance-capacitance oscillator, an inductance-capacitance oscillator, a crystal oscillator, a tuning fork oscillator and the like according to the circuit structure; the oscillator can be divided into sine wave, square wave, sawtooth wave and other oscillators according to the output waveform. The method is widely applied to the aspects of electronic industry, medical treatment, scientific research and the like.

In the prior art, an oscillator circuit usually outputs a stable voltage from a current source to drive an oscillator, so that the oscillator outputs a frequency with high precision. This results in a relatively high overall power consumption of the oscillator circuit, which is not well suited for low power consumption applications.

Disclosure of Invention

In view of the above problems in the prior art, an oscillator circuit with low power consumption is provided.

The specific technical scheme is as follows:

an oscillator circuit with low power consumption, comprising:

an oscillator for generating an output clock signal;

a frequency discriminator receiving an enable signal and a reference clock signal input from the outside, and receiving an output clock signal output from an output terminal of the oscillator, and generating a comparison signal according to the output clock signal and the reference clock signal;

the input end of the charge pump is connected with the output end of the frequency discriminator and is used for outputting control voltage according to the comparison signal and the enabling signal;

the input end of the power protection module is connected with the output end of the charge pump and used for outputting the control voltage to the input end of the oscillator;

the oscillator generates the output clock signal under the driving of the control voltage;

the power protection module is further used for storing the control voltage in a power protection capacitor, and the control voltage is formed through the power protection capacitor under the control of the enabling signal, so that low-power-consumption operation is realized. Preferably, the power protection module comprises:

a first field effect transistor, wherein a grid electrode of the first field effect transistor receives the enabling signal;

the source electrode of the first field effect transistor is connected with the output end of the charge pump;

the drain electrode of the first field effect tube is connected with the negative input end of the amplifier and the output end of the amplifier;

the positive input end of the amplifier is connected to the output end of the power protection module;

a second field effect transistor, wherein a grid electrode of the second field effect transistor receives the enabling signal through a NOT gate;

the source electrode of the second field effect transistor is connected with the output end of the power protection module;

the drain electrode of the second field effect transistor is connected with the output end of the charge pump;

and the base electrode of the second field effect transistor is connected with the negative input end of the amplifier.

Preferably, the amplifier comprises:

a first amplifying field effect transistor, wherein the grid electrode of the first amplifying field effect transistor is connected to the positive input end of the amplifier;

the source electrode of the first amplifying field effect transistor is grounded;

the drain electrode of the first amplifying field effect transistor is connected to the drain electrode and the grid electrode of the second amplifying field effect transistor;

the source electrode of the second amplifying field effect transistor is connected to the source electrode of the third amplifying field effect transistor;

the grid electrode of the third amplifying field effect transistor is connected to the grid electrode of the second amplifying field effect transistor;

the drain electrode of the third amplifying field effect transistor is connected to the drain electrode of the fourth amplifying field effect transistor and the output end of the amplifier;

the grid electrode of the fourth amplifying field effect transistor is connected to the negative input end of the amplifier;

and the source electrode of the fourth amplifying field effect transistor is connected to the source electrode of the first amplifying field effect transistor.

Preferably, one end of the electricity-keeping capacitor is connected to the output end of the electricity-keeping module, and the other end of the electricity-keeping capacitor is grounded.

Preferably, the charge pump adjusts the magnitude of the control voltage according to the comparison signal;

the comparison signal is a voltage rising signal and is used for controlling the charge pump to rise the control voltage;

or, a voltage drop signal for controlling the charge pump to drop the control voltage.

Preferably, the oscillator is a voltage-controlled oscillator, and is configured to adjust the frequency of the output clock signal according to the magnitude of the control voltage.

Preferably, when the enable signal is at a low level, the frequency discriminator stops working, and the power-maintaining module outputs the control voltage.

Preferably, the first field effect transistor, the second amplifying field effect transistor and the third amplifying field effect transistor are N-channel field effect transistors;

the first amplifying field effect transistor and the fourth amplifying field effect transistor are P-channel type field effect transistors.

The technical scheme has the following advantages or beneficial effects: the power-preserving module is arranged to drive the oscillator to generate an output clock signal under the condition that the frequency discriminator and the charge pump stop working, so that the discontinuous operation of a power supply is realized, and the overall power consumption of the oscillator is reduced. Through the circuit design of the power-keeping module, the leakage current of the power-keeping capacitor is reduced, and the high-precision output clock signal is easier to generate.

Drawings

Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.

FIG. 1 is an overall schematic diagram of an embodiment of the present invention;

FIG. 2 is a diagram illustrating parasitic capacitance of a second FET according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an amplifier according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of signal comparison according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.

The invention comprises the following steps:

an oscillator circuit with low power consumption, as shown in fig. 1, comprises:

a frequency discriminator 1, wherein the frequency discriminator 1 receives an enable signal EN and a reference clock signal CLK _ IN which are input from outside and an output clock signal CLK _ OUT which is output from the output end of the oscillator 4, and generates a comparison signal;

the input end of the charge pump 2 is connected with the output end of the frequency discriminator 1, and the charge pump 2 outputs a control voltage VCTRL according to the comparison signal and the enable signal EN;

the input end of the power protection module 3 is connected with the output end of the charge pump 2 and is used for outputting a control voltage VCTRL to the oscillator 4;

the oscillator 4 generates an output clock signal CLK _ OUT under the driving of a control voltage;

the power-saving module 3 is further configured to store the control voltage VCTRL in the power-saving capacitor CAP1, and form the control voltage VCTRL through the power-saving capacitor CAP1 under the control of the enable signal EN, so as to implement low-power operation.

Specifically, according to the technical scheme, the oscillator circuit integrally has two working states by switching the enable signal EN. When the enable signal EN is set to 1, the frequency discriminator 1 receives the output clock signal CLK _ OUT fed back from the oscillator 4 and compares the output clock signal CLK _ OUT with the reference clock signal CLK _ IN for reference, determines whether the frequency of the output clock signal CLK _ OUT is higher or lower than the frequency of the reference clock signal CLK _ IN, and controls the control voltage VCTRL output by the charge pump according to the determination result, thereby realizing the control of the output clock signal CLK _ OUT of the oscillator 4. When the enable signal EN is set to 0, the whole oscillator circuit enters a low power consumption operation state, and at this time, the power supply of the oscillator 4 is maintained only by the power retention module 3, and the frequency discriminator 1 stops controlling the frequency of the output clock signal CLK _ OUT, so that the power consumption of the whole circuit is reduced.

In a preferred embodiment, the power conservation module 3 comprises:

the gate of the first field effect transistor MP1, MP1 receives the enable signal;

the source electrode of the first field effect transistor MP1 is connected with the output end of the charge pump 2;

the drain electrode of the first field effect transistor MP1 is connected with the negative input end of the amplifier U1 and the output end of the amplifier U1;

the positive input end of the amplifier U1 is connected to the output end of the power protection module 3;

the gate of the second fet MP2, the second fet MP2 receives the enable signal through a not gate U2;

the source electrode of the second field effect transistor MP2 is connected with the output end of the power protection module 3;

the drain electrode of the second field effect transistor MP2 is connected with the output end of the charge pump 2;

the base of the second field effect transistor MP2 is connected to the negative input terminal of the amplifier U1.

Specifically, the power-maintaining module 3 is composed of an amplifier U1, a first fet MP1, a second fet MP2, and a power-maintaining capacitor CAP1, and is configured to store the control voltage VCTRL output by the charge pump 2 in the power-maintaining capacitor CAP1, so as to generate the control voltage VCTRL through the power-maintaining capacitor CAP1 when the enable signal EN is set to 0 and the frequency discriminator and the charge pump are not in operation, and further enable the oscillator 4 to normally generate the output clock signal CLK _ OUT. Meanwhile, the not gate U2 is used to invert the enable signal EN, that is, when the enable signal EN is 0, the signal output by the not gate U2 to the second fet MP2 is 1, which corresponds to the VDD terminal in fig. 2.

Further, as shown in fig. 2, the parasitic capacitance distribution in the second fet MP2 is:

the source electrode and the gate electrode have a parasitic capacitance CGS therebetween, the gate electrode and the drain electrode have a parasitic capacitance CGD therebetween, the drain electrode and the base electrode have a parasitic capacitance CDB therebetween, and the source electrode and the base electrode have a pair of parasitic capacitances CGB and CSB therebetween in parallel. The parasitic capacitors CGD and CDB are connected to the capacitor CAP1, and the base, drain and source of the second fet MP2 are at the same potential. The parasitic capacitance between the control voltage VTCRL and other potentials is reduced by connecting the base, drain and source of the second fet MP2 to the control voltage VCTRL so that it is equipotential. At this time, there may be only parasitic capacitances CGS and CGD between VCTRL and VDD in the path of the leakage. In the off state, the parasitic capacitances CGS and CGD of the second fet MP2 are the smallest, which can effectively prevent the capacitor CAP1 from leaking electricity, and further the capacitor CAP1 can effectively maintain the output of the oscillator 4, so as to achieve the overall low power consumption effect of the oscillator circuit.

In a preferred embodiment, the amplifier U1 includes:

a first amplifying field effect transistor Q1, wherein the gate of the first amplifying field effect transistor Q1 is connected to the positive input end of the amplifier U1;

the source electrode of the first amplifying field effect transistor Q1 is grounded;

the drain electrode of the first amplifying field effect transistor Q1 is connected to the drain electrode and the grid electrode of the second amplifying field effect transistor Q2;

the source electrode of the second amplifying field effect transistor Q2 is connected to the source electrode of the third amplifying field effect transistor Q3;

the gate of the third amplifying field effect transistor Q3 is connected to the gate of the second amplifying field effect transistor Q2;

the drain electrode of the third amplifying field effect transistor Q3 is connected to the drain electrode of the fourth amplifying field effect transistor Q4 and the output end of the amplifier U1;

the gate of the fourth amplifying field effect transistor Q4 is connected to the negative input terminal of the amplifier U1;

the source of the fourth mosfet Q4 is connected to the source of the first mosfet Q1.

In particular, the amplifier U1 has a lower power consumption through the above design.

In a preferred embodiment, one end of the capacitor CAP1 is connected to the output terminal of the power protection module 3, and the other end of the capacitor CAP1 is grounded.

In a preferred embodiment, the charge pump 2 adjusts the magnitude of the control voltage VCTRL according to the comparison signal.

In a preferred embodiment, the oscillator 4 is a voltage-controlled oscillator for adjusting the frequency of the output clock signal according to the magnitude of the control voltage.

In a preferred embodiment, when the enable signal EN is low, the frequency discriminator 1 stops working and the power protection module 3 outputs the control voltage.

In a preferred embodiment, the first fet MP1, the second fet MP2, the second amplifier fet Q2, and the third amplifier fet Q3 are N-channel fets;

the first amplifying field effect transistor Q1 and the fourth amplifying field effect transistor Q4 are P-channel field effect transistors.

In a preferred embodiment, the comparison signal is a voltage UP signal UP for controlling the charge pump 2 to raise the control voltage VCTRL; or, a voltage drop signal for controlling the charge pump 2 to drop the control voltage VCTRL.

Specifically, as shown in fig. 4, the oscillator circuit according to the present invention controls the operation state of the entire oscillator circuit by the enable signal EN.

When the enable signal EN is 1, the frequency discriminator 1 receives the output clock signal CLK _ OUT generated from the oscillator and the reference clock signal CLK _ IN input from the outside, and generates a comparison signal by comparing the frequencies of the output clock signal CLK _ OUT and the reference clock signal CLK _ IN, that is: when the frequency of the output clock signal CLK _ OUT is lower than the frequency of the reference clock signal CLK _ IN, the voltage rising signal UP is output to the charge pump 2, so that the charge pump 2 raises the control voltage VCTRL, and then the frequency of the output clock signal CLK _ OUT generated by the oscillator 4 is increased; and when the frequency of the output clock signal CLK _ OUT is higher than the frequency of the reference clock signal CLK _ IN, the voltage drop signal DOWN is output to the charge pump 2, so that the charge pump 2 lowers the control voltage VCTRL and then the frequency of the output clock signal CLK _ OUT generated by the oscillator 4 is reduced, thereby achieving the effect of accurately generating the output clock signal CLK _ OUT. Meanwhile, when the enable signal EN is 1, the power protection module 3 also stores the control voltage in the power protection capacitor CAP 1.

When the enable signal EN is 0, the control voltage VCTRL is only output from the capacitor CAP1, and the frequency discriminator 1 does not operate, and the oscillator 4 operates at a fixed frequency.

Through the design, the overall power consumption of the oscillator circuit is divided into two parts, namely static power consumption and dynamic power consumption, wherein the static power consumption is the power consumption of the power protection module 3 and the oscillator 4, and the static power consumption is not changed along with the working state or the setting of an enable signal EN to be 0 and the setting to be 1; the dynamic power consumption includes power consumption of an external circuit for generating the reference clock signal CLK _ IN, power consumption of the frequency discriminator, and power consumption of the charge pump. Make the oscillator circuit have dynamic, adjustable consumption through enable signal EN to through the reduction of the electric leakage of the design realization power protection capacity CAP1 to power protection module 3, thereby reduced dynamic consumption size, and then make the whole consumption of oscillator reduce.

The power supply circuit has the advantages that the power protection module is arranged, so that the oscillator can still be driven to generate an output clock signal under the condition that the frequency discriminator and the charge pump stop working, the discontinuous operation of the power supply is realized, and the overall power consumption of the oscillator is further reduced. Through the circuit design of the power-keeping module, the leakage current of the power-keeping capacitor is reduced, and the high-precision output clock signal is easier to generate.

Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

Similarly, the terms "frequency discriminator", "charge pump" and "oscillator" in the present invention may also be understood as one or more Application Specific Integrated Circuits (ASICs), DSPs, Programmable Logic Devices (PLDs), Complex Programmable Logic Devices (CPLDs), Field Programmable Gate Arrays (FPGAs), general purpose processors, controllers, micro-controllers (MCUs), microprocessors (microprocessors), or other electronic device implementations.

While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.