阅读说明：本技术 用于旋转行波振荡器的设备和方法 (Apparatus and method for rotating traveling wave oscillator ) 是由 V·K·西拉拉 D·D·道尔顿 C·G·莱登 于 2021-06-10 设计创作，主要内容包括：描述用于旋转行波振荡器的设备和方法(RTWO)。在某些实施方案中,RTWO系统,包括：携带行波的RTWO环；多个可选电容器,分布在所述RTWO环周围,并且每个在选择状态和未选择状态下可操作；和解码器系统,基于频率调谐码来控制对所述多个可选电容器的选择。频率调谐码包括精细调谐码和粗略调谐码,并且解码器系统可操作以维持恒定数量的电容器,该电容器针对所述精细调谐码的每个值切换状态。(An apparatus and method (RTWO) for rotating a traveling wave oscillator is described. In certain embodiments, an RTWO system, comprises: an RTWO ring carrying a traveling wave; a plurality of selectable capacitors distributed around the RTWO ring and each operable in a selected state and an unselected state; and a decoder system that controls selection of the plurality of selectable capacitors based on a frequency tuning code. The frequency tuning code comprises a fine tuning code and a coarse tuning code, and the decoder system is operable to maintain a constant number of capacitors that switch states for each value of the fine tuning code.)

1. A Rotary Traveling Wave Oscillator (RTWO) system comprising:

a first RTWO loop configured to carry a traveling wave;

a plurality of selectable capacitors distributed around the first RTWO ring, wherein each of the plurality of selectable capacitors is operable in a selected state and an unselected state; and

a decoder system configured to control selection of the plurality of selectable capacitors based on a frequency tuning code comprising a fine tuning code and a coarse tuning code,

wherein the decoder system is configured to maintain a constant number of capacitors that switch states for each value of the fine tuning code.

2. The RTWO system of claim 1, wherein the decoder system comprises a transition control decoder configured to control a first portion of the plurality of selectable capacitors, wherein the transition control decoder is configured to select a plurality of capacitors in state transition in the first portion based on a value of the fine tuning code.

3. The RTWO system of claim 2, wherein the transition control decoder operates a constant number of capacitors in a selected state for each value of the fine tuning code.

4. The RTWO system of claim 2, wherein the decoder system further comprises a frequency control decoder configured to control a second portion of the plurality of selectable capacitors based on the fine tuning code, wherein the transition control decoder compensates for a difference between a transition density of the frequency control decoder and the fine tuning code.

5. The RTWO system of claim 4, wherein a sum of a first number of transitions provided by the transition control decoder and a second number of transitions provided by the frequency control decoder is constant for each value of the fine tuning code.

6. The RTWO system of claim 2, wherein the transition control decoder selects a set of capacitors for transition control for a given fine tuning code value.

7. The RTWO system of claim 6, wherein the transition control decoder is controlled by a clock signal, wherein a selected set of capacitors for transition control changes each cycle of the clock signal.

8. The RTWO system of claim 7, wherein the selected set of capacitors for transition control rotate.

9. The RTWO system of claim 6, wherein the transition control decoder is implemented to provide at least one transition for each value of the fine tuning code.

10. The RTWO system of claim 1, wherein the decoder system is controlled by a clock signal, wherein when a frequency tuning code is fixed to a given value, the total number of capacitors in a selected state is constant, but the particular selection of the plurality of selectable capacitors changes each cycle of the clock signal.

11. The RTWO system of claim 1, further comprising a second RTWO ring coupled to the first RTWO ring.

12. A method of rotating traveling wave oscillations, the method comprising:

propagating a traveling wave around the RTWO ring;

controlling a delay of the traveling wave around the RTWO ring using a plurality of selectable capacitors distributed around the first RTWO ring, wherein each of the plurality of selectable capacitors is operable in a selected state and an unselected state;

controlling selection of the plurality of selectable capacitors based on a frequency tuning code using a decoder system, wherein the frequency tuning code includes a fine tuning code and a coarse tuning code; and

maintaining a constant number of capacitors of the plurality of selectable capacitors that switch states for each value of the fine tuning code using the decoder system.

13. The method of claim 12, wherein the decoder system includes a transition control decoder configured to control a first portion of the plurality of selectable capacitors, the method further comprising selecting a plurality of capacitors in state transition in the first portion based on the value of the fine tuning code.

14. The method of claim 13, further comprising operating a constant number of capacitors in a selected state for each value of the fine tuning code.

15. The method of claim 13, wherein the decoder system further comprises a frequency control decoder configured to control a second portion of the plurality of selectable capacitors based on the fine tuning code, the method further comprising using the transition control decoder to compensate for a difference between a transition density of the frequency control decoder and the fine tuning code.

16. The method of claim 15, wherein a sum of a first number of transitions provided by the transition control decoder and a second number of transitions provided by the frequency control decoder is constant for each value of the fine tuning code.

17. The method of claim 13, further comprising selecting a set of capacitors for transition control for a given fine tuning code value using the transition control decoder.

18. The method of claim 17, wherein the transition control decoder is controlled by a clock signal, the method further comprising a selected set of capacitors for transition control changing each cycle of the clock signal.

19. The method of claim 18, further comprising providing at least one transition for each value of the fine tuning code using the transition control decoder.

20. A Rotary Traveling Wave Oscillator (RTWO) system comprising:

an RTWO loop configured to carry a traveling wave;

a plurality of selectable capacitors distributed around the RTWO ring, wherein each of the plurality of selectable capacitors is operable in a selected state and an unselected state; and

a decoder system configured to control selection of the plurality of selectable capacitors based on a frequency tuning code comprising a fine tuning code and a coarse tuning code, wherein the decoder system comprises means for maintaining a constant number of capacitors that switch states for each value of the fine tuning code.

Technical Field

Embodiments of the present invention relate to electronic systems, and more particularly, to a Rotary Traveling Wave Oscillator (RTWO).

Background

Rotary Traveling Wave Oscillators (RTWO) may be used in a variety of applications including, for example, telecommunications systems, optical networks, and/or chip-to-chip communications. For example, an RTWO may be included in a frequency synthesizer to generate an output clock signal having a controlled phase and frequency relationship to a reference clock signal.

Disclosure of Invention

Rotary Traveling Wave Oscillator (RTWO) systems are described herein. In certain embodiments, an RTWO system, comprises: an RTWO ring carrying a traveling wave; a plurality of selectable capacitors distributed around the RTWO ring and each operable in a selected state and an unselected state; and a decoder system that controls selection of the plurality of selectable capacitors based on a frequency tuning code. The frequency tuning code comprises a fine tuning code and a coarse tuning code, and the decoder system is operable to maintain a constant number of capacitors that switch states for each value of the fine tuning code. By implementing an RTWO system in this manner, code-related frequency errors are reduced or eliminated.

In one aspect, an RTWO system comprises: a first RTWO loop configured to carry a traveling wave; a plurality of selectable capacitors distributed around the first RTWO ring, and each of the plurality of selectable capacitors operable in a selected state and an unselected state; and a decoder system configured to control selection of the plurality of selectable capacitors based on a frequency tuning code comprising a fine tuning code and a coarse tuning code. The decoder system is configured to maintain a constant number of capacitors that switch states for each value of the fine tuning code.

In another aspect, a method of rotating traveling wave oscillations is provided. The method comprises the following steps: propagating a traveling wave around the RTWO ring; controlling a delay of the traveling wave around the RTWO ring using a plurality of selectable capacitors distributed around the first RTWO ring, each operable in a selected state and an unselected state; controlling selection of the plurality of selectable capacitors based on a frequency tuning code using a decoder system, the frequency tuning code including a fine tuning code and a coarse tuning code; and maintaining a constant number of capacitors of the plurality of selectable capacitors using the decoder system, the capacitors switching states for each value of the fine tuning code.

In another aspect, an RTWO system includes: an RTWO loop configured to carry a traveling wave; a plurality of selectable capacitors distributed around the RTWO ring and each operable in a selected state and an unselected state; and a decoder system configured to control selection of the plurality of selectable capacitors based on a frequency tuning code comprising a fine tuning code and a coarse tuning code. The decoder system includes means for maintaining a constant number of capacitors that switch states for each value of the fine tuning code.

Drawings

Fig. 1 is a schematic diagram of one implementation of an all-digital phase-locked loop (ADPLL).

Fig. 2 is a schematic diagram of one embodiment of a Rotary Traveling Wave Oscillator (RTWO).

Figure 3A is a schematic diagram of another implementation of an RTWO.

Figure 3B is a schematic diagram of one implementation of the RTWO segment.

Fig. 4 illustrates one implementation of an RTWO with segmented decoding.

Figure 5 illustrates one implementation of a tuned decoder for a multi-loop RTWO.

Fig. 6A and 6B illustrate one implementation of dynamic element matching for segment selection for RTWO.

Fig. 7A and 7B illustrate another implementation of dynamic element matching for segment selection for RTWO.

Figure 8A is a schematic diagram of one embodiment of an RTWO system including four coupled RTWO rings.

Fig. 8B is an example of a graph of transitions versus fine input codes for the RTWO system of fig. 8A.

Fig. 8C is a diagram of one example of a switching time mismatch for the RTWO system of fig. 8A.

Fig. 8D is a graph of an example of the gain error of the RTWO system of fig. 8A.

Fig. 8E is a schematic diagram of a varactor circuit for the RTWO segment according to one embodiment.

FIG. 9 is a diagram of one example of a transition for transition controlled Dynamic Element Matching (DEM).

Fig. 10 is an example of a standby group operation diagram of the transition control DEM.

FIG. 11 is an example of a transition control group operation.

Fig. 12A is a diagram of one example of a switching time mismatch for an RTWO system with transition control.

Fig. 12B is a graph of one example of gain error for an RTWO system with transition control.

Fig. 13A is a graph of another example of gain error for an RTWO system with transition control, where varactor gain mismatch is also modeled.

Fig. 13B is a graph of another example of gain mismatch and transition control.

Fig. 14A is another example of an operation diagram for transition control of the spare group of the DEM.

FIG. 14B is an exemplary graph of open loop gain in which switching time and gain mismatch are modeled.

Fig. 15A is a graph simulating one example of a baseband diagram.

Figure 15B is a diagram of another simulated baseband diagram example.

Fig. 16 is a graph of measured baseband with and without transition control.

Detailed Description

The following detailed description of certain embodiments presents various descriptions of specific embodiments of the invention. The invention may, however, be embodied in many different forms as defined and covered by the claims. In the description, reference is made to the drawings wherein like reference numbers may indicate identical or functionally similar elements. It will be understood that the elements shown in the figures are not necessarily drawn to scale. Further, it should be understood that certain embodiments may include more elements than the subset of elements shown in the figures and/or figures. Furthermore, some embodiments may incorporate any suitable combination of features from two or more of the figures.

As will be understood by those of ordinary skill in the art, a Rotary Traveling Wave Oscillator (RTWO) may include a differential transmission line connected in a ring having an odd number of one or more crossover points, and a plurality of regenerative circuits electrically connected along the path of the differential transmission line. In addition, each frequency divider may reverse the polarity of the wave propagating along the differential transmission line, and the regenerative circuit may energize the wave to compensate for the loss of the differential transmission line. Additional details of the RTWO may be found in U.S. Pat. No. 6,556,089 entitled "ELECTRONIC CIRCUITRY" granted on 29/4/2003, which is incorporated herein by reference in its entirety.

Example of an all-digital phase-locked loop with a rotating traveling wave oscillator

In certain configurations herein, an all-digital phase-locked loop (ADPLL) is provided that includes a Rotating Traveling Wave Oscillator (RTWO). ADPLLs can be used in a variety of applications including, but not limited to, radar (e.g., automotive radar), telecommunications, chip-to-chip communications, and/or automatic test equipment. In one example, an ADPLL generates an output clock signal having a plurality of frequency ramp profiles and/or rates.

In contrast, an analog PLL with a charge pump may be affected by supply voltage variations, narrow tuning voltage ranges, and/or loop dynamics. These drawbacks may be exacerbated in implementations using relatively small geometry processes (e.g., fine line CMOS processes). Although the ADPLL architecture can provide many advantages, the teachings herein are also applicable to RTWO used in other electronic systems, such as analog PLLs using RTWO.

In certain implementations, the ADPLL includes an RTWO that operates as both a Digitally Controlled Oscillator (DCO) and a time-to-digital converter (TDC). Implementing an RTWO to provide multiple functions may enhance the compactness of the design by using the RTWO for multiple purposes.

By using RTWO in the ADPLL, a low figure of merit (FOM) can be achieved. The excellent FOM part is achieved by the fine resolution of the TDC of RTWO.

Although the RTWO described herein may be used in an ADPLL, RTWO implemented in accordance with the teachings herein may be used in a wide variety of electronic systems and applications.

Fig. 1 is a schematic diagram of one implementation of an all-digital phase-locked loop (ADPLL) 10. The ADPLL 10 includes a fractional accumulator 1, a digital filter 2, a combined Digitally Controlled Oscillator (DCO) and time-to-digital converter (TDC)4, a counter 5, a counter latch 6, a multiplier 7, a subtraction block 11, and an addition block 12. The combined DCO and TDC4 includes RTWO15 and TDC latch 16.

As shown in fig. 1, the ADPLL 10 includes a fractional accumulator 1 that is clocked by a reference clock signal CLK_REFRate of (2) accumulating the digital tuning word or code N_freq. Digital tuning code N_freqMay be used to control the output frequency of the ADPLL 10. In the illustrated embodiment, CLK is asserted for the reference clock signal_REFThe subtraction block 11 generates a difference signal based on the difference between the output of the fractional accumulator 1 and the number of DCO clocks NUM _ DCO generated in part by the RTWO 15. The DCO clock number NUM _ DCO corresponds to a digital code expressed in the form of an integer and a decimal.

As shown in fig. 1, the RTWO15 and TDC latches 16 operate to generate a fractional DCO clock FRAC _ DCO, and the addition block 12 combines with an integer number of DCO clocks INT _ DCO to generate a number DCO clocks NUM _ DCO. In particular, RTWO15 generates K clock phases, which are provided to the TDC latch 16. The TDC latch 16 is based on a reference clock signal CLK_REFProcesses the K clock phases from RTWO15 to determine the fraction of the DCO clock FRAC _ DCO. The K clock phases have the same oscillation frequency as each other but are different in phase. In one embodiment, RTWO outputs 64 or more phases to the TDC latch 16. However, other implementations are possible.

Although the TDC latch 16 is shown as a separate block from the RTWO15, in some embodiments the TDC latch 16 is integrated into the layout of the RTWO15, for example into the layout of the segments of the RTWO.

With continued reference to FIG. 1, RTWO15 outputs a DCO clock signal CLK_DCOWhich in some embodiments may correspond to one of K clock phases. In the illustrated embodiment, the DCO clock signal CLK_DCOUsed as input to a multiplier 7, the multiplier 7 multiplying the DCO clock signal CLK_DCOMultiplying by a multiplication factor M to produce an output clock signal CLK_OUT. Comprising a multiplier 7 for controlling the output clock signal CLK by expansion_OUTTo enhance the flexibility of the ADPLL 10. For example, the multiplier 7 may be used to control the output clock signal CLK_OUTIs a frequency greater than the maximum oscillation frequency of RTWO15, therebyCan be used as a frequency multiplier.

In one example, RTWO is multiplied by a multiplication factor M. In another example, the multiplier is omitted.

As shown in FIG. 1, the DCO clock signal CLK_DCOIs provided to an integer counter 5 which operates in conjunction with a counter latch 6 to generate an integer number of DCO periods INT DCO. In the illustrated embodiment, the integer counter 5 pairs of DCO clock signals CLK_DCOIs counted. For example, the integer counter 5 may be loaded with an initial value of 1 and then CLK for the DCO clock signal_DCOIs incremented by 1.

The difference signal generated by the subtraction block 11 is filtered by the digital filter 2. Furthermore, in this embodiment, the filtered difference signal is used to tune RTWO15 with an integer digital tuning code INT and a fractional digital tuning code F.

The RTWO15 in fig. 1 is tuned by an integer digital tuning code INT and a fractional digital tuning code F to change the basic oscillation frequency of the RTWO. In some embodiments, RTWO15 may employ additional tuning including, for example, coarse tuning and/or process, voltage, and temperature (PVT) tuning.

Thus, in certain embodiments, the fractional digital tuning code F provides fine fractional tuning of RTWO15, while the integer digital tuning code INT provides fine integer tuning.

RTWO15 may be implemented to include one or more features disclosed herein.

ADPLL 10 illustrates one example of an electronic system that can include an RTWO implemented in accordance with the teachings herein. However, the RTWO described herein may be used in a variety of electronic systems, including but not limited to a variety of data translators and/or frequency synthesizers.

Examples of rotary traveling wave oscillators

Figure 2 is a schematic diagram of one embodiment of the RTWO 30. RTWO 30 comprises a differential transmission line comprising a first conductor 31 and a second conductor 32. As shown in fig. 2, the differential transmission lines 31, 32 are connected in a closed loop or ring and include a frequency divider 33 to provide inversion of the travelling wave propagating around the ring. The RTWO 30 of fig. 3 also includes a plurality of segments 35, each segment including a regeneration circuit.

In this example, the RTWO 30 shown includes one crossover circuit and thirty-two regeneration circuits, each implemented using back-to-back inverters. However, other configurations are possible, including, for example, configurations using a different number of dividers, more or less segments, more or less regenerative circuits, and/or regenerative circuits implemented in other ways. Further, RTWO 30 may include other circuits including, but not limited to, tuning capacitors, latches, buffers, and/or other circuits in segment 35.

As shown in fig. 2, the differential transmission lines of the RTWO are connected in a closed loop manner and folded at each of four corners. However, the differential transmission line of the RTWO may be implemented in other ways, including for example different implementations of the folding and/or routing of the conductors 31, 32. For example, the teachings herein are applicable not only to RTWO implemented using rectangular or square rings, but also to RTWO including otherwise shaped transmission lines. Thus, while the illustrated RTWO includes four sides, the teachings herein are applicable to RTWO's that include more or fewer sides as well as RTWO's having curved loops.

In the illustrated embodiment, RTWO 30 includes segments 35, each segment including regenerative circuits distributed at substantially regular intervals around a differential transmission line. The uniformly distributed regenerative circuits help maintain a uniform characteristic impedance and a substantially constant wave velocity of the differential transmission line. Although each segment 35 includes a pair of back-to-back inverters, the teachings herein are applicable to segments that include other numbers of regeneration circuits and/or different embodiments of regeneration circuits.

In the illustrated embodiment, each side of the RTWO 30 is divided into 8 segments. Because each of conductors 31, 32 provides a clock signal phase, 32 illustrated segments 35 operate with a total of 64 clock signal phases. However, other implementations are possible.

Oscillation frequency f of RTWO 30_OSCBased on the speed of a traveling wave propagating along the transmission line divided by the total length or distance the wave has traveled in one cycle. In certain embodiments, the oscillation frequency fOSC of RTWO 30 is given by equation 1 below, where v is_pIs the wave phase velocity, L is the length of the transmission line loop or ring, L_TLIs a transmission line inductance, C_TLIs the transmission line capacitance.

Equation 1

In certain configurations herein, a segment of the RTWO (e.g., segment 35 of RTWO 30) includes one or more tuning capacitors having a digitally controllable capacitance to set the oscillation frequency of the RTWO.

It is difficult to meet the RTWO specification in terms of tuning range and frequency tuning step size. Such challenges may be exacerbated in configurations where the RTWO is specified to operate at relatively high oscillation frequencies. For example, an RTWO with a higher oscillation frequency may have shorter transmission line loops and thus may be limited by available layout resources, such as available transistor active areas and/or metal routing channels.

For example, RTWO 30 may be included in the ADPLL 10 of fig. 1. However, in some applications, it may be desirable for the ADPLL 10 to oscillate at a relatively high frequency f_OSC(e.g., 10GHz or higher), with a relatively wide tuning range (e.g., 625MHz or higher) and a relatively fine tuning resolution (e.g., 200kHz or lower).

The segments of the RTWO may include a variety of circuits including, for example, regenerative circuits (e.g., sustain amplifiers), tuning capacitors, latches, buffers, and/or other circuits. In a first example, to achieve a sufficient tuning range, each RTWO segment may comprise a plurality of tuning capacitor banks, for example three or more tuning capacitor banks. In a second example, a segment of the RTWO includes a TDC latch to provide a time-to-digital transition. In a third example, each segment of the RTWO includes at least one tap buffer (e.g., in-phase or anti-phase buffer) for retrieving or extracting a clock signal of a particular phase from the ring of the RTWO.

Although it is desirable for the segments of the RTWO to include a large number of circuits and/or relatively large sized circuits, the RTWO may be limited by the available layout resources (e.g., available active area and/or routing tracks). Furthermore, providing additional layout resources by increasing the length of the RTWO segments may increase the length of the RTWO loop, thereby reducing the oscillation frequency of the RTWO.

In certain configurations herein, the RTWO includes a segment having a metallic stub extending from a differential transmission line of the RTWO. The metal stub provides a connection to other layout resources. For example, the segment layout may be relatively wide (e.g., in a first dimension substantially perpendicular to a local portion of the RTWO transmission line) and may include tuning capacitors and other circuitry connected to the metal stubs. However, the length of the segment layout is relatively short (e.g., in a second dimension substantially parallel to a local portion of the RTWO transmission line), and thus the transmission line loop of the RTWO is relatively short to provide a high oscillation frequency, e.g., 10GHz or higher.

Thus, the metal stubs extend from the differential transmission lines of the RTWO to provide connections to tuning capacitors and/or other circuitry, which helps achieve a wide tuning range, fine frequency steps, high oscillation frequencies, and/or provide additional functionality to the RTWO, such as time-to-digital conversion functionality and/or segment programmability.

Fig. 3A is a schematic diagram of another embodiment of RTWO 70. RTWO 70 comprises a differential transmission line comprising a first conductor 31, a second conductor 32 and a crossover 33. The RTWO 70 also includes a plurality of segments 75.

In the illustrated embodiment, RTWO 70 includes one intersection and thirty-two segments. However, other configurations are possible, including, for example, configurations using a different number of intersections and/or more or fewer segments. Furthermore, in the illustrated embodiment, the differential transmission lines of the RTWO are connected in a closed loop fashion and folded at each of the four corners. However, the differential transmission line of the RTWO may be implemented in other ways, including for example different implementations of the folding and/or routing of the conductors 31, 32. For example, the teachings herein are applicable not only to RTWO implemented using rectangular or square loops, but also to RTWO including otherwise shaped transmission lines. Thus, while the illustrated RTWO 70 includes four edges, the teachings herein are applicable to RTWO that include more or fewer edges.

In the illustrated embodiment, RTWO 70 includes segments 75, each segment including a first metal stub 81 and a second metal stub 82 extending from first conductor 31 and second conductor 32, respectively. First and second metal stubs 81, 82 are used to provide local clock phase signals from the differential transmission lines of the RTWO to the circuitry of segment 75.

In the illustrated embodiment, each section 75 includes a TDC latch 91, a tuning capacitor 92, and a regeneration circuit 93 that operates using both the clock signal phase from the first conductor 31 and the clock signal phase from the second conductor 32. However, other implementations are possible. Although illustrated as being connected between the first and second conductors 31, 32 of the RTWO ring, in another example, the regenerative circuit 93 is connected between the first and second metal stubs 81, 82. In the illustrated embodiment, each segment 75 includes a first tap buffer 94 tapping the first conductor 31 to obtain a first clock signal phase and a second tap buffer 95 tapping the second conductor 32 to obtain a second clock signal phase.

Although one particular implementation of a segmented circuit is shown in fig. 3A, other implementations of a segmented circuit are possible, including configurations that include more or fewer circuits and/or different circuits. For example, in another embodiment, the first and second sets of tuning capacitors are connected to the first and second conductors 31, 32, respectively. In yet another embodiment, the segments include circuitry that provides segment programmability.

By including first and second metallic stubs 81, 82 extending from the differential transmission lines 31, 32 of the RTWO, the segments 75 of the RTWO can be implemented with a wide layout that provides active area and routing resources suitable for the segment circuit. In addition, the RTWO includes the differential transmission lines 31, 32 in a relatively short loop, and thus the RTWO 70 has a relatively high oscillation frequency.

In one embodiment, the RTWO has a total loop length of less than 7,500 μm, and the stub length of each of the first and second metal stubs 81, 82 is at least 25 μm. For example, with respect to the rectangular ring shown in FIG. 3A, in one embodiment, the RTWO of FIG. 3A hasHas a first length L of less than about 1,875 μm_RING-XAnd a second length L of less than about 1,875 μm_RING-Y。

The stub length may be expressed in terms of a fraction of the wavelength of the RTWO travelling wave. In one embodiment, first and second metal stubs 81 and 82 each have a length of at least about 0.05 λ, where λ is the wavelength of RTWO. The skilled person will appreciate that the wavelength of the RTWO may be expressed as the ratio of the wave phase velocity of the RTWO to the oscillation frequency of the RTWO, or v_p/f_osc。

In one embodiment, the segments 75 have a length less than about 25 μm and a width of at least about 25 μm.

In one embodiment, the RTWO comprises at least 1 segment per 25 μm ring.

Figure 3B is a schematic diagram of one implementation of RTWO segment 100. The RTWO segment 100 is connected to a first transmission line conductor 101 and a second transmission line conductor 102 of the RTWO ring.

For clarity of the drawing, only a portion of the first transmission line conductor 101 and the second transmission line conductor 102 is shown in fig. 3B. However, the first transmission line conductor 101 and the second transmission line conductor 102 operate as part of a differential transmission line of an RTWO connected in a ring.

The RTWO segment 100 of fig. 7 includes a PVT tuned capacitor bank 111, a coarse tuned capacitor bank 112, a fine tuned capacitor bank 113, a regeneration circuit 115, a TDC latch 117, a first tap buffer 118a, a second tap buffer 118b, a first metal stub 131 and a second metal stub 132.

The PVT tuning capacitor bank 111 includes optional capacitors for compensating for process, temperature, and/or voltage variations. In addition, coarse tuning capacitor bank 112 includes selectable capacitors for providing coarse tuning of the RTWO oscillation frequency. In addition, the trim capacitor bank 113 includes selectable capacitors for providing trimming of the RTWO oscillation frequency. The tuning capacitor bank may be implemented using any suitable tunable capacitor structure, including but not limited to a group of parallel capacitor elements that are digitally selectable by switches.

Although an example of an RTWO segment including three tuned capacitor banks is shown in fig. 3B, the teachings herein are applicable to RTWO tuned using more or fewer capacitor banks.

In the illustrated embodiment, the PVT tuned capacitor bank 111 operates using a three-bit PVT tuning code, the coarse tuned capacitor bank 112 operates using a seven-bit coarse tuning code, and the fine tuned capacitor bank 113 operates using a 31-bit fine tuning integer tuning code. Although one specific example of bit widths is shown, the teachings herein are applicable to tuning in a variety of bit widths. Thus, other implementations are possible. In some embodiments, the trim capacitor bank 113 is controlled via a PLL feedback loop. For example, the fine integer tuning code may be controlled by a digital filter of the PLL.

The RTWO segment 100 shown also includes a TDC latch 117 for detecting the passage of travelling waves travelling along the first and second transmission line conductors 101, 102. For example, the outputs of TDC latches around an RTWO ring can be processed to generate a digital representation of the time instances that a travelling wave passes through different locations around the ring. For example, the output of the TDC latch can be used to determine the fraction of the clock cycles that have passed.

As shown in FIG. 3B, TDC latch 117 receives a reference clock signal CLK_REF. In some embodiments, the reference clock signal CLK_REFIs provided to RTWO segment 100 via a clock distribution tree.

In the illustrated embodiment, the first and second tap buffers 118a and 118b are implemented using inverters. The first and second tap buffers 118a and 118b are used to generate clock signal phases that are separated from each other by approximately 180 °. By providing tap buffers at different positions along the RTWO-loop, a set of clock signals of a desired phase can be obtained. Although fig. 7 illustrates a configuration in which the taps are provided using inverters, RTWO may include tap buffer circuits implemented in a variety of ways.

In the illustrated embodiment, the regeneration circuit 115 includes a first inverter 116a and a second inverter 116 b. Further, an input terminal of the first inverter 116a is electrically connected to an output terminal of the second inverter 116b, and an output terminal of the first inverter 116a is electrically connected to an input terminal of the second inverter 116 b. However, the RTWO segment may include a regeneration circuit implemented in other ways.

First and second metal stubs 131, 132 provide a local clock phase from the loop of the RTWO to the circuitry of RTWO segment 100. By using first and second metal stubs 131, 132, the length of the RTWO segment 100 can be relatively short, which in turn results in a relatively short RTWO ring and a correspondingly high RTWO oscillation frequency.

In certain configurations herein, the RTWO segment includes a routing channel 133 for providing a channel for routing tracks through the RTWO segment.

As shown in fig. 3B, first and second metal stubs 131, 132 provide connections from the first transmission line conductor 101 and the second transmission line conductor 102, respectively, to the circuitry of the RTWO segment 100. For example, first and second metal stubs 131, 132 connect the ring of the RTWO to tuning capacitors and other circuitry of the RTWO segment 100.

The first and second metal stubs 131, 132 provide capacitive loading that operates as part of the transmission line characteristic impedance Zo. In certain embodiments, the metal stubs can be implemented at about equal lengths and can be distributed at substantially uniform intervals around the ring of the RTWO. Although the stub is shown as being substantially the same for each segment, in other configurations, the stub may be implemented differently for one or more segments. In one example, the design rules of the process limit the layout of the transistors to one direction, and the stubs along the top and bottom of the RTWO differ from the implementation of the stubs located on the left and right sides of the RTWO.

As shown in fig. 3B, a first metal stub 131 is connected to the first transmission line conductor 101 (e.g., through a via) and extends from the first transmission line conductor 131 to provide a connection to the circuitry of the RTWO segment 100. In the illustrated embodiment, a first metal stub 131 connects a first end of the PVT tuning capacitor bank 111, a first end of the coarse tuning capacitor bank 112, a first end of the fine tuning capacitor bank 113, an input 118a of the first tap buffer, and to a first input of the TDC latch 117. In the illustrated embodiment, the end of the first metal stub 131 is bent before being connected to the first input of the TDC latch 117. However, other embodiments are possible.

With continued reference to fig. 3B, the second metal stub 132 is connected to the second transmission line conductor 102 (e.g., through a via). After the initial rotation or bending, a second metal stub 132 extends from the second transmission line conductor 132 to provide a connection to the circuitry of the RTWO segment 100. In the illustrated embodiment, the second metal stub 132 connects the second terminal of the PVT tuning capacitor bank 111, the second terminal of the coarse tuning capacitor bank 112, the second terminal of the fine tuning capacitor bank 113, the input 118b of the second tap buffer, and the second input of the TDC latch 117. However, other implementations are possible.

In one embodiment, first and second metal stubs 101 and 102 each have a length (including a bend) of at least about 25 μm. In one example, the length of the stubs 101, 102 is about 95 μm, corresponding to about 6% of the wavelength (or 0.06 λ) of an RTWO operating at 10 GHz.

As shown in fig. 3B, the transmission line conductors 101, 102 of the RTWO ring have a width W and are spaced apart from each other by a spacing S. The width W and spacing S may be any suitable value, for example, W-12 um and S-8 um.

In some embodiments, the transmission line conductors 101, 102 are located on different metal layers relative to the metal stubs 131, 132. In one example, the transmission line conductors 101, 102 of the RTWO differential transmission line are implemented on two or more adjacent upper metal layers (e.g., a stack of metal 8 and metal 9), and the stubs are implemented on a lower metal layer (e.g., metal-7). Those of ordinary skill in the art will appreciate that the lower metal layer is closer to the semiconductor substrate than the upper metal layer.

As shown in fig. 3B, a plan view layout 120 of the RTWO segment 100 has been shown. The floor plan layout 120 includes a PVT tuning capacitor bank layout 121, a coarse tuning capacitor bank layout 122, a fine tuning capacitor bank layout 123, a regenerative amplifier layout 125, a TDC latch layout 127, a tap buffer layout 128, and a decoupling capacitor layout 129.

PVT tuning capacitor bank layout 121 corresponds to the boundaries of the active area (e.g., transistor layout and/or capacitor size) of PVT tuning capacitor bank 111, coarse tuning capacitor bank layout 122 corresponds to the boundaries of the active area of coarse tuning capacitor bank 112, and fine tuning capacitor bank layout 123 corresponds to the boundaries of the active area of fine tuning capacitor bank 113. Further, the tap buffer layout 128 corresponds to the boundary of the active area of the tap buffers 118a, 118b, and the TDC latch layout 127 corresponds to the boundary of the active area of the TDC latch 117. In addition, the regenerative amplifier topology 125 corresponds to the boundary of the active area of the inverters 116a, 116b, and the decoupling capacitor topology 129 corresponds to the boundary of the active area of the decoupling capacitor between the power supply and ground of the regenerative circuit 115.

In one embodiment, the RTWO segment 100 has a length S of less than about 25 μm_LAnd a width S of at least about 25 μm_W. In certain embodiments, the width of RTWO segment 100 is greater than the length, such that many segments can be distributed around the ring of the RTWO while maintaining a relatively short RTWO conductor loop length and correspondingly high oscillation frequency.

In one embodiment, the RTWO comprises at least 1 segment per 25 μm ring.

Although specific implementations of RTWO segment circuits and floor plans have been described above, the teachings herein are applicable to a variety of implementations of RTWO segments.

Segmented decoding example for rotary traveling wave oscillator

In certain configurations herein, a segmented decoding scheme is provided for RTWO frequency tuning codes to reduce decoding complexity. The segmented decoding scheme may use a combination of global decoding and local decoding to process the frequency tuning code. By using segmented decoding, many signal paths associated with frequency tuning codes may be reduced.

The RTWO can work with a large number of tuning capacitors, including tuning capacitors for PVT tuning, coarse tuning, and fine tuning (e.g., including fine integer and fine fractional tuning). In implementations that use multiple rings coupled to each other to reduce phase noise, the number of tuning capacitors may be further increased. A large number of tuning capacitors results in a large number of signal paths or wires.

In one example, a 4-ring RTWO includes 32 segments per ring, each segment including a 2-bit PVT tuned capacitor bank, a 3-bit coarse tuned capacitor bank, and a 5-bit fine tuned capacitor bank. In addition, each ring includes one instance of a fine fraction tuning capacitor bank having 5 bits. In this example, the PVT-tuned capacitor bank without segmented decoding uses 256 lines (2 bits x 32 segments x4 rings), the coarse-tuned capacitor bank uses 384 lines (3 bits x 32 segments x4 rings), the fine-integer-tuned capacitor bank operates using 640 lines (5 bits x 32 segments x4 rings), and the fine-fractional-tuned capacitor bank operates using 20 lines (5 bits x4 rings). Thus, the total number of wires in this example may be 256+384+640+ 20-1300 wires.

However, routing a large number of wires can result in routing congestion. Furthermore, these routes may result in the electrical environment being affected by potential coupling of the digital stray components to the RTWO. For example, a large number of wires may act as large antennas on a semiconductor chip. Furthermore, the flexibility and/or scalability of RTWO design may be limited. For example, such routing congestion may limit the maximum number of RTWO loops that can be coupled to each other to improve phase noise.

In certain configurations herein, the tuning capacitors across the RTWO segments are quantized such that the tuning capacitors of each RTWO segment can be controlled separately from the tuning capacitors of other segments. In addition, the global decoder processes the frequency tuning codes (e.g., PVT adjustment codes, coarse tuning codes, and/or fine integer adjustment codes) to generate input codes for the RTWO local decoder. In some implementations, thermometer decoding is performed locally for each segment by a local decoder. In a multi-loop implementation, the frequency tuning code may be routed to a global decoder associated with each RTWO loop.

By using a segmented decoding scheme, many metal routes or wires can be reduced.

For example, in the specific example above, 1300 lines are used for a 4-loop RTWO operating without segmented decoding. In contrast, the segmented decoding in this particular example may be used to provide PVT tuning of 7 bits (e.g., 3 thermometer bits per segment 32 segments 96 LSBs per segment)<2⁷) 8 bit coarse tuning (e.g., 224LSB of 32 bits per segment of 7 thermometer bits)<2⁸) And a 12-bit fine tuning integer (e.g., 3968LSB for 31-bit thermometer/32 segments/4 rings/segment)<2¹²). Thus, PVT tuning operates using 28 lines (7 bits by 4 rings),coarse tuning operates using 32 lines (8 bits by 4 rings) and fine tuning operates using 48 lines (12 bits by 4 rings). Thus, the total number in this example may be 28+32+48+ 20-128 lines, which is about an order of magnitude less than an embodiment without segmented decoding.

Fig. 4 illustrates one embodiment of an RTWO 400 with segmented decoding. In certain configurations herein, segmented decoding is provided to reduce the number of wires routed to the RTWO, e.g., the number of digital signal routes from the ADPLL core to the RTWO.

RTWO 400 includes differential transmission lines connected in a closed loop or ring. The differential transmission line comprises a first conductor 31, a second conductor 32 and a crossover 33. RTWO 400 also includes segment 100, which may be as previously described with respect to fig. 3B. In the illustrated embodiment, thirty-two instances of the segments 100 are positioned around a ring with eight segments on each side of the ring. As shown in fig. 10, 32 segments are labeled with an index ranging between 0 and 31.

RTWO 400 also includes global decoder system 401, local decoder system 402, digital routing bus 405, serial interface 406, and fine fraction tuning capacitor bank 410.

Although one particular RTWO implementation is shown, the teachings herein are applicable to RTWO implemented in a variety of ways, including but not limited to RTWO with different ring implementations, different segment implementations, and/or different decoder implementations.

Global decoder system 401 includes segment decoder system 403 and tuning decoder system 404. Global decoder system 401 may be implemented using digital logic circuitry, such as digital logic generated by digital synthesis. For example, the segment decoder system 403 and/or the tuning decoder system 404 may be described using a hardware description language (e.g., Verilog), which may be synthesized to generate a digital logic circuit. However, other implementations are possible. Although shown as being distributed by segment, one or more decoders may be configured to provide decoding to multiple segments. For example, one decoder per RTWO side may be used.

The tuning decoder system 404 is used to decode frequency tuning codes (e.g., PVT, coarse and/or fine integer tuning codes) to generate input codes to the local decoder system 402. The input code is processed by the local decoder system 402 to activate the appropriate tuning capacitors of the RTWO segment.

In the illustrated embodiment, the tuned decoder system 404 includes a Tuned Decoder (TD) for each segment 100. In addition, the local decoder system 402 includes a Local Decoder (LD) for each segment 100. In some implementations, the LD is used to convert a binary input code from a corresponding TD to a thermometer-coded output code for selecting a plurality of active tuning capacitors of a particular RTWO segment 100.

As shown in fig. 4, digital routing bus 405 surrounds the perimeter of RTWO 400. The digital routing bus 405 may be used to route a variety of input signals to the global decoder system 401.

For example, the global decoder system 401 of RTWO 400 has been annotated to illustrate an input signal 411 for frequency tuning 412 comprising PVT tuning codes (PVT _ code <6:0>), coarse tuning codes (coarse _ code <7:0>), fine integer adjustment codes (fine _ code <7:0>), and fine fractional adjustment codes (fine _ code <2:0 >). Although not shown in fig. 10 for clarity, RTWO 400 may receive one or more clock signals for indicating the timing of the tuning codes.

In the illustrated embodiment, the digital routing bus 405 provides PVT tuning codes, coarse tuning codes, and fine integer tuning codes to the tuning decoder system 404, which the tuning decoder system 404 processes to generate input codes to control the local decoder system 402. The local decoder system 402 processes the input codes to control the PVT tuning set, the coarse tuning set, and the fine integer tuning set of the RTWO segment 100.

As shown in FIG. 4, an example of a fine fractional tuning bank 410 is included in the RTWO 400 shown, and a differential fine tuning code (finefrac _ code <2:0>) is provided to the differential fine tuning bank 410 to control the differential fine tuning. Thus, in this example, the fine fraction tuning code bypasses the tuning decoder system 404. In some embodiments, an LD is included to decode the fine fraction tuning code to generate thermometer bits to control the fine fraction tuning bank 410.

Although one particular embodiment of frequency tuning code and decoding is shown, the teachings herein are applicable to a variety of embodiments.

Segment decoder system 403 includes a Segment Decoder (SD) for each segment 100. Segment decoder system 403 is used to decode data received via serial interface 406 to segment 100 of the RTWO.

As shown in FIG. 4, the serial interface 406 receives input signals 413 including a segment data signal (rtwo _ seg _ data <7:0>), a segment address signal (rtwo _ seg _ addr <4:0>), a write enable signal (rtwo _ wr _ en), a serial interface clock signal (rtwo _ sclk), and a read data signal (rtwo _ rd _ data <7:0 >). In some embodiments, the serial interface 406 is implemented as a local Serial Peripheral Interface (SPI).

In the illustrated embodiment, the digital routing bus 405 routes the input signal 413 to each SD of the segmented decoding system 403 for decoding.

It may be desirable for a segment of an RTWO, such as RTWO segment 100, to be configurable. To provide configurability, RTWO segment 100 may be written to or read from via serial interface 406.

The illustrated RTWO 400 includes a segment decoder system 401 that reduces the number of routes associated with communicating with RTWO segments 100. In some implementations, the segment decoder system 403 operates using local register mapping. The local register map is used to provide a bit address for each segment and to determine when the serial interface 406 is in communication with a particular one of the RTWO segments 100.

By including segment decoder system 401, the number of data and address bus bits associated with routing from serial interface 406 to RTWO segment 100 may be reduced.

For example, in one particular implementation, a 4-ring RTWO having 32 segments per ring includes a data bus that uses 8-bit operations common to 4 rings and an address bus that uses 5-bit operations common to 4 rings. In such an example, a 4-loop RTWO operates using 13-bit sum lines.

In contrast, a similar 4-ring RTWO implemented using a segment decoder system may include 2048 bits and lines (16 bits per segment x 32 segments x4 rings). Thus, by including a segment decoder system in this particular example, a reduction of over a hundred times can be achieved.

Figure 5 illustrates one embodiment of a tuned decoder for a multi-loop RTWO 600. Polycyclic RTWO600 includes southwest RTWO ring 601(R0), southeast RTWO ring 602(R1), northeast RTWO ring 603(R2), northwest RTWO ring 604 (R3). Although a configuration using four rectangular RTWO rings is shown, the teachings herein are applicable to embodiments using more or fewer rings and/or rings implemented in other shapes.

Although terms relating to the cardinal directions (north, south, east, west, northeast, northwest, southeast, southwest) are used in describing the multi-ring RTWO, those of ordinary skill in the art will appreciate that these terms are used herein for the understanding of the relative directions, and not to refer to the true directions. For example, the multi-ring RTWO600 is typically implemented at least partially on an Integrated Circuit (IC) or semiconductor die, and the orientation of the multi-ring RTWO600 changes as the IC changes position or angle. Similarly, terms related to top, bottom, left side, and right side are used to describe relative directions.

As shown in fig. 5, a PVT tuned decoder, a coarse tuned decoder, and a fine integer tuned decoder are provided around the sides of each RTWO ring 601-604.

With respect to northwest RTWO ring 604, north PVT decoder 614a, north coarse decoder 624a, and north fine integer decoder 634a are located on a first or top side. Further, a south PVT decoder 614b, a south coarse decoder 624b, and a south fine integer decoder 634b are located on a second or bottom side. Further, the west PVT decoder 614c, the west coarse decoder 624c, and the west fine integer decoder 634c are located on a third or left side. In addition, the east PVT decoder 614d, the east coarse decoder 624d, and the east fine integer decoder 634d are located on the fourth side or right side.

In addition, the orientation of the corresponding tuned decoder of the northeast RTWO loop 603 is line symmetric with respect to the northwest RTWO loop 604. For example, with respect to the northeast RTWO ring 603, a north PVT decoder 613a, a north coarse decoder 623a, and a north fine integer decoder 633a are located on the top side. Further, a south PVT decoder 613b, a south coarse decoder 623b, and a south fine integer decoder 633b are located at the bottom side. Further, a west PVT decoder 613c, a west coarse decoder 623c, and a west fine integer decoder 633c are located on the right side. In addition, the east PVT decoder 613d, the east coarse decoder 623d, and the east fine integer decoder 633d are located on the left side.

Furthermore, the orientation of the corresponding tuning decoder of the southwest RTWO ring 601 is line symmetric with respect to the northwest RTWO ring 604. For example, with respect to southwest RTWO ring 601, north PVT decoder 611a, north coarse decoder 621a, and north fine integer decoder 631a are located at the bottom side. Further, a south PVT decoder 611b, a south coarse decoder 621b, and a south fine integer decoder 631b are located on the top side. Also, the west PVT decoder 611c, the west coarse decoder 621c, and the west fine integer decoder 631c are located on the left side. In addition, the east PVT decoder 611d, the east coarse decoder 621d, and the east fine integer decoder 631d are located on the right side.

In addition, the orientation of the respective tuning decoders of southeast RTWO loop 602 is line symmetric with respect to southwest RTWO loop 601 and northeast RTWO loop 603. For example, with respect to southeast RTWO ring 602, north PVT decoder 612a, north coarse decoder 622a, and north fine integer decoder 632a are located at the bottom side. Further, a south PVT decoder 612b, a south coarse decoder 622b, and a south fine integer decoder 632b are located on the top side. Furthermore, west PVT decoder 612c, west coarse decoder 622c, and west fine integer decoder 632c are located on the right side. Further, the east PVT decoder 612d, the east coarse decoder 622d, and the east fine integer decoder 632d are located on the left side.

Implementing the tuned decoder of one RTWO-loop with line symmetry with respect to the tuned decoder of another RTWO-loop provides symmetry that reduces mismatch between the loops.

In the illustrated embodiment, a tuning decoder is placed on each side of the RTWO-loop. In addition, the tuning decoder controls the tuning capacitors of adjacent RTWO segments, which reduces the connections between the outputs of the tuning decoder and the RTWO segments. For example, in an implementation with 32 segments per RTWO ring, a north-tuned decoder provides decoding of the 8 corresponding segments of the RTWO ring. Thus, the route length is reduced. Thus, the illustrated tuning decoder may illustrate a set of TD blocks as depicted in fig. 4. However, other implementations are possible. For example, a separate TD block may be provided for each RTWO segment.

As shown in fig. 5, the PVT tuner decoder of RTWO rings 601-604 is represented by text labels PVT _ decoder _ normal, PVT _ decoder _ west, PVT _ decoder _ source, and PVT _ decoder _ east. The coarse adjustment decoder is represented by text labels coarse _ decoder _ normal, coarse _ decoder _ west, coarse _ decoder _ source, and coarse _ decoder _ east. In some embodiments, the PVT tuning decoder is substantially the same for each RTWO ring and segment, and the PVT tuning decoder operates using a common PVT tuning code. In addition, in some embodiments, the coarse tuning code is substantially the same for each RTWO ring and segment, and the coarse tuning code operates with a common coarse quantization code.

As shown in FIG. 5, the fine integer tuner decoder of the RTWO loop 601-604 represents the fine _ decoder _ r0_ normal, the fine _ decoder _ r0_ normal, the fine _ decoder _ r0_ normal, the fine _ decoder _ r0_ normal, the fine _ decoder _ r1_ normal, the fine _ decoder _ r1_ normal, the fine _ decoder _ r1_ normal, the fine _ decoder _ r1_ normal, the fine _ decoder _ r2_ normal, the fine _ decoder _ 2_ normal, the fine _ decoder _ r2_ normal, the fine _ decoder _ 2_ normal, the fine _ decoder 3_ normal, the fine _ decoder _ normal _ 3_ normal, the fine _ decoder 8536 _ normal, the fine _ decoder _ normal _ r _ normal _ 2_ normal, the fine _ decoder _ r0_ normal, the fine _ decoder _ r 638 _ normal, and the fine _ decoder 8536 _ normal _ 3_ normal.

In some implementations, the fine integer tuning decoder is implemented using substantially the same hardware (e.g., substantially the same Verilog), but operates with different rtwo _ location <3:0> values, and thus has different output values. Implementing the decoder in this manner enhances scalability and flexibility.

Although fig. 5 illustrates one embodiment of a tuned decoder for a multi-loop RTWO, the tuned decoder may be implemented in a variety of ways.

Dynamic element matching example for linearizing RTWO fine tuning gain

In certain configurations herein, a Dynamic Element Matching (DEM) scheme is provided to linearize the fine-tuned gain characteristics of the RTWO. For example, dynamic element matching may be used to break the periodicity of the fixed segment selection sequence used in the segment decoding scheme of RTWO. Reducing or eliminating the periodicity in the selection of segment sequences achieves mitigation of unwanted spurious frequency components. In contrast, selecting a fixed sequence of RTWO segments reduces spectral integrity by producing spurious frequency components.

For example, the wide frequency ramp may span the entire fine tuning code range. When a fixed segment selection sequence is used, the spurious component occurs at a frequency offset from the fundamental frequency. The frequency of the spurious component is based on the period of the fixed sequence of segment selections.

Table 1 below illustrates one example of a fixed sequence selection for one embodiment of the multi-ring RTWO600 of fig. 5. In table 1, W0, W1, W2 and W3 represent western-tuned decoders of RTWO rings R0, R1, R2 and R3, respectively. Similarly, S0, S1, S2 and S3 respectively represent south mediation coders of RTWO rings R0, R1, R2 and R3. Likewise, E0, E1, E2 and E3 represent east reconciled coders of RTWO rings R0, R1, R2 and R3, respectively. In addition, N0, N1, N2 and N3 represent north decoders of RTWO rings R0, R1, R2 and R3, respectively.

TABLE 1

As shown in the example in table 1, as the fineint _ code increases, the decoders activate or trigger in a particular order. The periodicity of the segment selection can result in a reduction in the spectral purity of the RTWO output clock phase.

In certain implementations herein, the RTWO decoding system is implemented with a dynamic element matching scheme to linearize the fixed sequence. In addition, the dynamic element matching scheme may increase the periodicity of the fixed sequence and/or remove the periodicity altogether.

Fig. 6A and 6B illustrate one implementation of dynamic element matching for segment selection for RTWO. The dynamic element matching scheme of fig. 6A and 6B illustrates one embodiment of dynamic element matching for the multi-ring RTWO600 of fig. 5. Thus, the illustrated embodiment of dynamic element matching is used in the context of sixteen tuned decoders, labeled decoder 0 through decoder 15, respectively.

However, the dynamic element matching scheme may be used with a variety of RTWO's, including but not limited to RTWO's that include more or fewer rings, different ring implementations, more or fewer segments, different segment implementations, more or fewer tuned decoders, and/or different implementations of tuned decoders.

As shown in fig. 6A and 6B, a sequence of 16 decoder cycles (in this example) is shown, with the sequence of selected decoders labeled first through sixteenth decoder selections 1001-1016, respectively. The decoder period indicates the selection of the decoder in response to the ramping up of the fine integer code received by the RTWO. As described above, in some applications, the wide frequency ramp may span the entire fine tuning code range.

Pointer 1000 is used to indicate the last tuned decoder that has been selected. Further, the next period pointer 1020 indicates the tuning decoder to be used at the beginning of the next decoder period (16 decoder periods in this example). As shown in the first decoder selection 1001, the next round pointer 1020 is located at a different decoder location than the pointer 1000 is located in the first decoder selection 1001. Implementing dynamic element matching in this way reduces the periodicity of decoder selection by preventing two consecutive 16 decoder cycles from starting at the same decoder location.

In the illustrated embodiment, pointer 1000 begins at decoder 0 at first decoder selection 1001. In some embodiments, if the pointer 1000 is never set, such as at power-up or reset of the chip, the pointer 1000 may be set to a particular starting value (e.g., decoder 0) or to a random or pseudo-random decoder location.

As shown in fig. 6A and 6B, the selected decoder changes when transitioning from one decoder selection to the next. For example, in the illustrated embodiment, the selected decoder in the next decoder selection begins after the decoder selected by the current decoder ends. Thus, in this embodiment, all previously selected decoders are turned off when transitioning to the next decoder selection.

For example, when transitioning from the first decoder select 1001 to the second decoder select 1002, decoder 0 is turned off and decoders 1-2 are turned on. In addition, when transitioning from the second decoder selection 1002 to the third decoder selection 1003, decoders 1-2 are turned off and decoders 3-5 are turned on. Further, when transitioning from the third decoder selection 1003 to the fourth decoder selection 1004, decoders 3-5 are turned off and decoders 6-9 are turned on. In addition, when transitioning from the fourth decoder select 1004 to the fifth decoder select 1005, decoders 6-9 are turned off and decoders 10-14 are turned on.

In the illustrated embodiment, the selected decoder is marked with a sequence of numbers starting at a start index of 0 and ending at an end index of 15. Further, when the end index is exceeded during decoder selection, the selected decoder wraps to include the start index. For example, when transitioning from the fifth decoder select 1005 to the sixth decoder select 1006, decoders 10-14 are turned off and decoders 15 and 0-4 are turned on.

As shown by the sixth through sixteenth decoder selections 1006-1016, the algorithm repeats until the sixteenth decoder selection 1016, where all sixteen decoders are selected.

The number of decoders selected may be selected according to the fine integer code. For example, in the present embodiment, mod (finite _ code,16) +1 can be calculated with distributed quantization across four rings. Further, in this example, the fineint _ code0 does not select any decoder. The result will therefore be a value between 1 and 16.

Depending on the current position of the pointer 1000, a certain number of decoders will be selected as a result from the current pointer position. In one example, pointer 1000 is located at decoder 5 and find _ code is 200 and mod (200,16) +1 is 9, the selected 9 decoders corresponding to decoders 6 through 14. The position of the pointer 1000 is then located at the decoder 14.

Fig. 7A and 7B illustrate another implementation of dynamic element matching for segment selection for RTWO. The implementation of dynamic element matching of fig. 7A and 7B is similar to the implementation of dynamic element matching of fig. 6A and 6B, except that the dynamic element matching of fig. 7A and 7B is implemented to only shut down one decoder when transitioning from one decoder selection to the next.

For example, when transitioning from the first decoder select 1101 to the second decoder select 1102, decoder 0 is turned off and decoders 1-2 are turned on. In addition, when transitioning from the second decoder select 1102 to the third decoder select 1103, decoder 1 is turned off, decoder 2 remains on, and decoders 3-4 are turned on. Further, when transitioning from the third decoder select 1103 to the fourth decoder select 1104, decoder 2 is turned off, decoders 3-4 remain on, and decoders 5-6 are turned on. In addition, when transitioning from the fourth decoder select 1104 to the fifth decoder select 1105, decoder 3 is turned off, decoders 4-6 remain on, and decoders 7-8 are turned on.

As shown by the sixth through sixteenth decoder selections 1106-1116, the algorithm repeats until the sixteenth decoder selection 1116, where all sixteen decoders are selected.

Additional details of the dynamic element matching of fig. 7A and 7B may be similar to those previously described.

The dynamic element matching scheme of fig. 6A and 6B and the dynamic element matching scheme of fig. 7A and 7B are rotational dynamic element matching schemes. In the example with 16 decoder selections, there are 256 activation possibilities (16 x 16) for the spin cycle. Although the rotational dynamic element matching scheme reduces the periodicity by increasing the period length of the fixed sequence, a degree of periodicity may still be preserved.

In certain embodiments, the segment decoder system is implemented to operate with random or pseudo-random dynamic element matching.

For example, in some embodiments, a pseudo-random binary sequence (PRBS) is used to change the selection sequence of the decoder. The PRBS may be generated in any suitable manner, for example using digital logic circuitry.

In one example, the PRBS changes the selection pointer every certain number of encodings, e.g., every 16 fine integer encodings, every 128 fine integer encodings, etc. This allows for longer rotation sequences to break the periodicity of the decoder selection.

In another example, dynamic element matching is used to randomize the sequence in which a particular tuned decoder selects a segment. Thus, rather than activating the tuning capacitors associated with a particular tuning decoder in a given order, the order of tuning capacitors controlled by a particular tuning decoder is dynamically selected. Thus, dynamic element matching may be used to break periodicity in the selection of tuning decoders (tuning decoder sequence) and/or break periodicity in tuning capacitors selected by tuning decoders (segment selection sequence).

Example of a transition control scheme for RTWO

Apparatus and methods are provided for addressing the effects of mismatch in the ON-OFF switching time of a controllable capacitor (also referred to herein as a varactor) of an RTWO. Controlling the number of varactor transitions that occur on each code may improve the performance of the RTWO, e.g., achieving a constant transition from the code when a data weighted DEM is applied to the decoder of the RTWO.

For example, in automotive radar applications, the frequency ramp is generated by a digital PLL with an RTWO (see, e.g., fig. 1). When DEM is enabled in an RTWO decoder, the number of varactor transitions is a function of the input code, and any mismatch in the ON-to-OFF (ON → OFF) and OFF-to-ON (OFF → ON) switching times of the varactors results in a frequency glitch that is proportional to the number of varactor switches, resulting in an input code. This results in a gain error that is a function of the input code and the corresponding spur in the baseband spectrum in the target application.

In certain embodiments herein, in addition to matching ON → OFF and OFF → ON switching times in the layout, the number of transitions relative to the code is ensured to be constant by creating virtual transitions using the spare set. For example, the number of virtual transitions follows the inverse of the number of transitions and the code, such that the total number of transitions remains constant.

By ensuring a constant number of transitions, performance is enhanced. For example, simulations show a 100-fold reduction in gain variation and 100ps on/off mismatch, while measurements show a 20dB reduction in the near-range spurs of the high-speed ramp in the baseband spectrum.

Figure 8A is a schematic diagram of one embodiment of an RTWO system 1150 including four coupled RTWO rings. Fig. 8B is a diagram of one example of a transition and fine input code for the RTWO system of fig. 8A.

In this example, 4 rings are provided, each ring having 4 sides, 8 segments per side, and 31 varactors per segment. In particular, RTWO system 1150 includes a Northwest (NW) RTWO ring 1141, a Northeast (NE) RTWO ring 1142, a Southwest (SW) RTWO ring 1143, and a Southeast (SE) RTWO ring 1144. In this example, each RTWO ring includes 4 edges, 8 segments per edge. Thus, RTWO system 1150 includes 128 segments (128 — 4x4x 8). Furthermore, each segment comprises 128 varactors, wherein the varactors of one segment are retained. Therefore, 3968 varactors (128 × 31 — 3968) are available for control. In addition, a 12-bit fine code maps to 3968 control lines. Furthermore, DEM is only applicable for segment selection of 7 LSB. Although RTWO having a specific number of rings, segments, and varactors are provided, the transition control scheme disclosed herein can be applied to a variety of RTWO.

As shown in fig. 8B, when the transition control is not provided, the number of transitions (0 → 1 and 1 → 0) depends on the code.

Fig. 8C is a diagram of one example of a switching time mismatch for the RTWO system 1150 of fig. 8A. The graph includes an upper graph of fine code values versus time and a bottom graph of frequency versus time.

With respect to the simulation of fig. 8C, a 100ps mismatch is added to the ON/OFF switching time of the varactor. DEM can cause frequency glitches whose magnitude is a function of the number of transitions. This can lead to code dependent gain errors.

Fig. 8D is a graph of an example of the gain error of the RTWO system of fig. 8A. The graph includes an upper graph of gain versus total code and a bottom graph of fine code versus total code for the frequency ramp.

With respect to fig. 8D, there is one step in gain per 64 codes due to unequal transition densities. For the first 64 codes, the glitch count increases as the code increases, and for the next 64 codes, the glitch count decreases as the code increases. Varactor gain mismatch is disabled and only the switching time mismatch is modeled in this example.

To overcome the problems of fig. 8A-8D, a transition controlled DEM may be used to match the number of transitions per code in accordance with the teachings herein.

For example, in the context of the RTWO system of fig. 8A, 2 of the 31 varactors in each segment (labeled var0 through var30, respectively) may be allocated for transition control. Thus, in this particular example, 128 segments per segment 2 for a total of 256 varactors may be used for transition control. Var29 (spare group 0) and Var30 (spare group 1) in each segment are reserved for transition control. Half of which are open at the beginning. The varactors from the spare bank are switched, according to the code, to provide 640 → 1 and 64 1 → 0 transitions in total. The same logic can be used to control both spare sets to save area.

Thus, in the example of code 2, (64-2)62 additional transitions may be obtained by switching 31Var29 plus 31Var 30. Further, in the example of code 3, (64-3) 61 additional transitions were obtained by alternately switching 30Var29 plus 30Var30 and 31Var29 plus 31Var30, so that a total of 61 transitions occurred on average. Further, in these examples, the standby groups are always just open 64Var29 and 64Var 30.

Thus, a constant total number of varactors turned on achieves a constant offset frequency of first order.

Although an example with a particular number of varactors, back-up varactors, and segments is provided, the teachings herein are applicable to RTWO implemented in a variety of ways.

Fig. 8E is a schematic diagram of a varactor circuit for RTWO segment 1220, according to one embodiment. RTWO segment 1220 includes segment decoder 1201, frequency controlled varactor 1202, and transition controlled varactor 1203. As shown in fig. 8E, a frequency-controlled varactor 1202 and a transition-controlled varactor 1203 are connected between differential transmission lines 1204a/1204b of the RTWO, respectively. Each varactor of the frequency controlled varactor 1202 and each varactor of the transition controlled varactor 1203 may be individually selected to control the capacitive load of the differential transmission line 1204a/1204 b.

As shown in fig. 8E, the segment decoder 1201 receives a COARSE frequency control signal (COARSE) and a FINE frequency control signal (FINE). In addition, segment decoder 1201 includes a frequency control decoder 1207 that controls frequency control varactor 1202 based on the coarse tuning code and the fine tuning code. Further, the segment decoder 1202 includes a transition control decoder 1208, which controls the transition control varactor 1203 based on the fine tuning code to compensate for a difference of the transition density of the frequency control decoder 1207 and the fine tuning code.

For example, in some embodiments, transition control decoder 1208 selects the number of state-transitioned transition control varactors 1203 based on the value of the fine tuning code. In particular, the transition control decoder 1208 selects a number of varactors selected from the transition control varactors 1203 to ensure that the sum of the number of transitions provided by the transition control decoder 1201 and the number of transitions provided by the frequency control decoder 1207 is constant for each value of the fine tuning code.

In some embodiments, the segment decoder 1201 is controlled by the clock signal CLK, and the transition control decoder 1208 updates the number of selected transition control varactors 1203 per cycle of the clock signal CLK. Furthermore, when the frequency tuning code is fixed at a given value (both the coarse tuning code and the fine tuning code are constant), the total number of varactors in the selected state is constant, but the particular selection of the transition control varactor 1203 changes each period of the clock signal CLK.

Thus, when dynamic element matching occurs at a fixed frequency tuning code, the transition control keeps the total number of varactors transitioning from 0 → 1 and from 1 → 0 from one clock cycle to the next constant. Thus, code dependent frequency errors are mitigated.

Fig. 9 is a diagram of one example of transition of the transition control DEM. As shown in the top view of fig. 9, the DEM has triangular shaped transitions and fine codes as discussed previously with respect to fig. 8B. Furthermore, as shown in the middle of FIG. 9, the spare set is implemented with inverted triangle transitions and fine code to compensate for the transitions of the main set for DEM. Thus, as shown in the bottom curve of FIG. 9, the total number of transitions is substantially constant with respect to the fine code.

Fig. 10 is an example of a standby group operation diagram of the transition control DEM. In this example, the OFF to ON transition is represented by an upward bold arrow, and the ON to OFF transition is represented by a downward bold arrow.

As shown in fig. 10, the number of varactors for the alternate set of transitions is a function of the input code and is selected such that the RTWO system is substantially constant over the total number of transitions for the fine code.

FIG. 11 is an example of a transition control group operation.

As shown in fig. 11, the varactor diodes for maintaining the transition density are also rotated using the DEM scheme. The triggered varactor diode is thus rotated (indicated by the thick arrow in the figure) in each clock cycle. Furthermore, in this example, the spare set always has exactly 64 varactors turned on. Furthermore, these transitions supplement the transitions from the main group DEM.

Fig. 12A is a diagram of one example of a switching time mismatch for an RTWO system with transition control. The graph includes an upper graph of fine code values versus time and a bottom graph of frequency versus time.

In the illustrated example, a 100ps mismatch is added to the on/off switching time of the varactor. The DEM plus transition control results in a constant transition. This results in code independent gain errors.

Fig. 12B is a graph of one example of gain error for an RTWO system with transition control.

As shown by a comparison of fig. 12B and fig. 8D, the gain step size for each 64 codes now disappears.

In particular, the transition density is constant and the error due to spur frequency is the same for all codes.

In this example, the varactor gain mismatch is disabled. Only the handover time mismatch is modeled.

Fig. 13A is a graph of another example of gain error for an RTWO system with transition control, where varactor gain mismatch is also modeled. The graph includes a top graph of gain error versus total code, a middle graph of amplified gain error versus total code, and a bottom graph of fine code versus total code for a frequency ramp.

The varactor gain mismatch is now modeled in this example. As shown in fig. 13A, there is a large glitch on the code 64. In addition, there is a slight difference in the gain of the lower and upper 64 codes.

Fig. 13B is a graph of another example of gain mismatch and transition control.

When the transition control is enabled, 128 varactors in the spare set conduct resulting in a frequency shift. This offset will change every clock cycle because different varactor diode pairs produce the offset to the DEM in the transition control. Furthermore, for code [6:0] — 64, there is no transition in the spare set, so the offset is constant, resulting in a glitch in the gain of this code.

In certain embodiments, modified transition control is provided herein to overcome the problems associated with fig. 13A and 13B, wherein varactor gain mismatch is also taken into account.

In a first aspect of modified transition control, the inventors have realized that the varactor gain span varies significantly compared to the variation within the segment. Therefore, by making the two spare groups opposite to each other, the spread of the offset frequency can be greatly reduced.

In a second aspect, non-zero spare set transitions on each code are ensured by having a larger number of total transitions, e.g., 66 instead of 64.

Fig. 14A is another example of an operation diagram for transition control of the spare group of the DEM. This figure corresponds to an example of modified transition control having 66 transitions instead of the 64 transitions discussed previously.

FIG. 14B is an exemplary graph of open loop gain in which switching time and gain mismatch are modeled.

In this example, the gain error per 64 codes is reduced from 3.2kHz to 30 Hz.

Fig. 15A is a graph simulating one example of a baseband diagram.

In fig. 15A, the transition control is disabled. The gain mismatch and the switching time mismatch are modeled.

Figure 15B is a diagram of another simulated baseband diagram example.

In fig. 15B, the transition control is enabled. The gain mismatch and the switching time mismatch are modeled.

Fig. 16 is a graph of measured baseband with and without transition control.

The mismatch in switching times in the varactor on/off path can cause periodic gain errors and degrade baseband performance.

By making the switching density independent of the code, the side lobe levels in the measurements are reduced by about 20 dB.

Applications of

Devices employing an RTWO that includes one or more of the above-described features can be implemented as various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, components of consumer electronics, electronic test equipment, radar systems, and the like. Examples of the electronic device may also include circuitry of an optical network or other communication network. Consumer electronics products may include, but are not limited to, automobiles, video cameras, still cameras, digital cameras, portable memory chips, washing machines, clothes dryers, washer/dryers, copiers, facsimile machines, scanners, multifunction peripherals, and the like. Further, the electronic devices may include unfinished products, including those used in industrial, medical, and automotive applications.

The foregoing description and claims may refer to elements or features as being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Also, unless expressly stated otherwise, "coupled" means that one element/feature is directly or indirectly coupled to another element/feature, and not necessarily mechanically. Thus, although the various schematic diagrams shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).

While the present invention has been described in terms of certain embodiments, other embodiments that are apparent to those of ordinary skill in the art, including embodiments that do not provide all of the features and advantages set forth herein, are also within the scope of the present invention. Furthermore, the various embodiments described above can be combined to provide further embodiments. Furthermore, certain features shown in the context of one embodiment may also be incorporated in other embodiments. Accordingly, the scope of the invention is to be defined only by reference to the following claims.